Same as last commit just run through the form tool (splits up large lib.rs files)

src/flexio/ctrl/mod.rs

@@ -0,0 +1,657 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CTRL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `FLEXEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FLEXENR {
+    #[doc = "FlexIO module is disabled."]
+    _0,
+    #[doc = "FlexIO module is enabled."]
+    _1,
+}
+impl FLEXENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FLEXENR::_0 => false,
+            FLEXENR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FLEXENR {
+        match value {
+            false => FLEXENR::_0,
+            true => FLEXENR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == FLEXENR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == FLEXENR::_1
+    }
+}
+#[doc = "Possible values of the field `SWRST`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SWRSTR {
+    #[doc = "Software reset is disabled"]
+    _0,
+    #[doc = "Software reset is enabled, all FlexIO registers except the Control Register are reset."]
+    _1,
+}
+impl SWRSTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            SWRSTR::_0 => false,
+            SWRSTR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> SWRSTR {
+        match value {
+            false => SWRSTR::_0,
+            true => SWRSTR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == SWRSTR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == SWRSTR::_1
+    }
+}
+#[doc = "Possible values of the field `FASTACC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FASTACCR {
+    #[doc = "Configures for normal register accesses to FlexIO"]
+    _0,
+    #[doc = "Configures for fast register accesses to FlexIO"]
+    _1,
+}
+impl FASTACCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FASTACCR::_0 => false,
+            FASTACCR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FASTACCR {
+        match value {
+            false => FASTACCR::_0,
+            true => FASTACCR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == FASTACCR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == FASTACCR::_1
+    }
+}
+#[doc = "Possible values of the field `DBGE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DBGER {
+    #[doc = "FlexIO is disabled in debug modes."]
+    _0,
+    #[doc = "FlexIO is enabled in debug modes"]
+    _1,
+}
+impl DBGER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            DBGER::_0 => false,
+            DBGER::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> DBGER {
+        match value {
+            false => DBGER::_0,
+            true => DBGER::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == DBGER::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == DBGER::_1
+    }
+}
+#[doc = "Possible values of the field `DOZEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DOZENR {
+    #[doc = "FlexIO enabled in Doze modes."]
+    _0,
+    #[doc = "FlexIO disabled in Doze modes."]
+    _1,
+}
+impl DOZENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            DOZENR::_0 => false,
+            DOZENR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> DOZENR {
+        match value {
+            false => DOZENR::_0,
+            true => DOZENR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == DOZENR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == DOZENR::_1
+    }
+}
+#[doc = "Values that can be written to the field `FLEXEN`"]
+pub enum FLEXENW {
+    #[doc = "FlexIO module is disabled."]
+    _0,
+    #[doc = "FlexIO module is enabled."]
+    _1,
+}
+impl FLEXENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            FLEXENW::_0 => false,
+            FLEXENW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FLEXENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FLEXENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: FLEXENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "FlexIO module is disabled."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(FLEXENW::_0)
+    }
+    #[doc = "FlexIO module is enabled."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(FLEXENW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SWRST`"]
+pub enum SWRSTW {
+    #[doc = "Software reset is disabled"]
+    _0,
+    #[doc = "Software reset is enabled, all FlexIO registers except the Control Register are reset."]
+    _1,
+}
+impl SWRSTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            SWRSTW::_0 => false,
+            SWRSTW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SWRSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SWRSTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SWRSTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Software reset is disabled"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(SWRSTW::_0)
+    }
+    #[doc = "Software reset is enabled, all FlexIO registers except the Control Register are reset."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(SWRSTW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `FASTACC`"]
+pub enum FASTACCW {
+    #[doc = "Configures for normal register accesses to FlexIO"]
+    _0,
+    #[doc = "Configures for fast register accesses to FlexIO"]
+    _1,
+}
+impl FASTACCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            FASTACCW::_0 => false,
+            FASTACCW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FASTACCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FASTACCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: FASTACCW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Configures for normal register accesses to FlexIO"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(FASTACCW::_0)
+    }
+    #[doc = "Configures for fast register accesses to FlexIO"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(FASTACCW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `DBGE`"]
+pub enum DBGEW {
+    #[doc = "FlexIO is disabled in debug modes."]
+    _0,
+    #[doc = "FlexIO is enabled in debug modes"]
+    _1,
+}
+impl DBGEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            DBGEW::_0 => false,
+            DBGEW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DBGEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DBGEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: DBGEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "FlexIO is disabled in debug modes."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(DBGEW::_0)
+    }
+    #[doc = "FlexIO is enabled in debug modes"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(DBGEW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 30;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `DOZEN`"]
+pub enum DOZENW {
+    #[doc = "FlexIO enabled in Doze modes."]
+    _0,
+    #[doc = "FlexIO disabled in Doze modes."]
+    _1,
+}
+impl DOZENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            DOZENW::_0 => false,
+            DOZENW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DOZENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DOZENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: DOZENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "FlexIO enabled in Doze modes."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(DOZENW::_0)
+    }
+    #[doc = "FlexIO disabled in Doze modes."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(DOZENW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 31;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - FlexIO Enable"]
+    #[inline]
+    pub fn flexen(&self) -> FLEXENR {
+        FLEXENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - Software Reset"]
+    #[inline]
+    pub fn swrst(&self) -> SWRSTR {
+        SWRSTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - Fast Access"]
+    #[inline]
+    pub fn fastacc(&self) -> FASTACCR {
+        FASTACCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 30 - Debug Enable"]
+    #[inline]
+    pub fn dbge(&self) -> DBGER {
+        DBGER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 30;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 31 - Doze Enable"]
+    #[inline]
+    pub fn dozen(&self) -> DOZENR {
+        DOZENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 31;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - FlexIO Enable"]
+    #[inline]
+    pub fn flexen(&mut self) -> _FLEXENW {
+        _FLEXENW { w: self }
+    }
+    #[doc = "Bit 1 - Software Reset"]
+    #[inline]
+    pub fn swrst(&mut self) -> _SWRSTW {
+        _SWRSTW { w: self }
+    }
+    #[doc = "Bit 2 - Fast Access"]
+    #[inline]
+    pub fn fastacc(&mut self) -> _FASTACCW {
+        _FASTACCW { w: self }
+    }
+    #[doc = "Bit 30 - Debug Enable"]
+    #[inline]
+    pub fn dbge(&mut self) -> _DBGEW {
+        _DBGEW { w: self }
+    }
+    #[doc = "Bit 31 - Doze Enable"]
+    #[inline]
+    pub fn dozen(&mut self) -> _DOZENW {
+        _DOZENW { w: self }
+    }
+}

src/flexio/mod.rs

@@ -0,0 +1,392 @@
+use vcell::VolatileCell;
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - Version ID Register"]
+    pub verid: VERID,
+    #[doc = "0x04 - Parameter Register"]
+    pub param: PARAM,
+    #[doc = "0x08 - FlexIO Control Register"]
+    pub ctrl: CTRL,
+    #[doc = "0x0c - Pin State Register"]
+    pub pin: PIN,
+    #[doc = "0x10 - Shifter Status Register"]
+    pub shiftstat: SHIFTSTAT,
+    #[doc = "0x14 - Shifter Error Register"]
+    pub shifterr: SHIFTERR,
+    #[doc = "0x18 - Timer Status Register"]
+    pub timstat: TIMSTAT,
+    _reserved0: [u8; 4usize],
+    #[doc = "0x20 - Shifter Status Interrupt Enable"]
+    pub shiftsien: SHIFTSIEN,
+    #[doc = "0x24 - Shifter Error Interrupt Enable"]
+    pub shifteien: SHIFTEIEN,
+    #[doc = "0x28 - Timer Interrupt Enable Register"]
+    pub timien: TIMIEN,
+    _reserved1: [u8; 4usize],
+    #[doc = "0x30 - Shifter Status DMA Enable"]
+    pub shiftsden: SHIFTSDEN,
+    _reserved2: [u8; 76usize],
+    #[doc = "0x80 - Shifter Control N Register"]
+    pub shiftctl0: SHIFTCTL0,
+    #[doc = "0x84 - Shifter Control N Register"]
+    pub shiftctl1: SHIFTCTL1,
+    #[doc = "0x88 - Shifter Control N Register"]
+    pub shiftctl2: SHIFTCTL2,
+    #[doc = "0x8c - Shifter Control N Register"]
+    pub shiftctl3: SHIFTCTL3,
+    _reserved3: [u8; 112usize],
+    #[doc = "0x100 - Shifter Configuration N Register"]
+    pub shiftcfg0: SHIFTCFG0,
+    #[doc = "0x104 - Shifter Configuration N Register"]
+    pub shiftcfg1: SHIFTCFG1,
+    #[doc = "0x108 - Shifter Configuration N Register"]
+    pub shiftcfg2: SHIFTCFG2,
+    #[doc = "0x10c - Shifter Configuration N Register"]
+    pub shiftcfg3: SHIFTCFG3,
+    _reserved4: [u8; 240usize],
+    #[doc = "0x200 - Shifter Buffer N Register"]
+    pub shiftbuf0: SHIFTBUF0,
+    #[doc = "0x204 - Shifter Buffer N Register"]
+    pub shiftbuf1: SHIFTBUF1,
+    #[doc = "0x208 - Shifter Buffer N Register"]
+    pub shiftbuf2: SHIFTBUF2,
+    #[doc = "0x20c - Shifter Buffer N Register"]
+    pub shiftbuf3: SHIFTBUF3,
+    _reserved5: [u8; 112usize],
+    #[doc = "0x280 - Shifter Buffer N Bit Swapped Register"]
+    pub shiftbufbis0: SHIFTBUFBIS0,
+    #[doc = "0x284 - Shifter Buffer N Bit Swapped Register"]
+    pub shiftbufbis1: SHIFTBUFBIS1,
+    #[doc = "0x288 - Shifter Buffer N Bit Swapped Register"]
+    pub shiftbufbis2: SHIFTBUFBIS2,
+    #[doc = "0x28c - Shifter Buffer N Bit Swapped Register"]
+    pub shiftbufbis3: SHIFTBUFBIS3,
+    _reserved6: [u8; 112usize],
+    #[doc = "0x300 - Shifter Buffer N Byte Swapped Register"]
+    pub shiftbufbys0: SHIFTBUFBYS0,
+    #[doc = "0x304 - Shifter Buffer N Byte Swapped Register"]
+    pub shiftbufbys1: SHIFTBUFBYS1,
+    #[doc = "0x308 - Shifter Buffer N Byte Swapped Register"]
+    pub shiftbufbys2: SHIFTBUFBYS2,
+    #[doc = "0x30c - Shifter Buffer N Byte Swapped Register"]
+    pub shiftbufbys3: SHIFTBUFBYS3,
+    _reserved7: [u8; 112usize],
+    #[doc = "0x380 - Shifter Buffer N Bit Byte Swapped Register"]
+    pub shiftbufbbs0: SHIFTBUFBBS0,
+    #[doc = "0x384 - Shifter Buffer N Bit Byte Swapped Register"]
+    pub shiftbufbbs1: SHIFTBUFBBS1,
+    #[doc = "0x388 - Shifter Buffer N Bit Byte Swapped Register"]
+    pub shiftbufbbs2: SHIFTBUFBBS2,
+    #[doc = "0x38c - Shifter Buffer N Bit Byte Swapped Register"]
+    pub shiftbufbbs3: SHIFTBUFBBS3,
+    _reserved8: [u8; 112usize],
+    #[doc = "0x400 - Timer Control N Register"]
+    pub timctl0: TIMCTL0,
+    #[doc = "0x404 - Timer Control N Register"]
+    pub timctl1: TIMCTL1,
+    #[doc = "0x408 - Timer Control N Register"]
+    pub timctl2: TIMCTL2,
+    #[doc = "0x40c - Timer Control N Register"]
+    pub timctl3: TIMCTL3,
+    _reserved9: [u8; 112usize],
+    #[doc = "0x480 - Timer Configuration N Register"]
+    pub timcfg0: TIMCFG0,
+    #[doc = "0x484 - Timer Configuration N Register"]
+    pub timcfg1: TIMCFG1,
+    #[doc = "0x488 - Timer Configuration N Register"]
+    pub timcfg2: TIMCFG2,
+    #[doc = "0x48c - Timer Configuration N Register"]
+    pub timcfg3: TIMCFG3,
+    _reserved10: [u8; 112usize],
+    #[doc = "0x500 - Timer Compare N Register"]
+    pub timcmp0: TIMCMP0,
+    #[doc = "0x504 - Timer Compare N Register"]
+    pub timcmp1: TIMCMP1,
+    #[doc = "0x508 - Timer Compare N Register"]
+    pub timcmp2: TIMCMP2,
+    #[doc = "0x50c - Timer Compare N Register"]
+    pub timcmp3: TIMCMP3,
+}
+#[doc = "Version ID Register"]
+pub struct VERID {
+    register: VolatileCell<u32>,
+}
+#[doc = "Version ID Register"]
+pub mod verid;
+#[doc = "Parameter Register"]
+pub struct PARAM {
+    register: VolatileCell<u32>,
+}
+#[doc = "Parameter Register"]
+pub mod param;
+#[doc = "FlexIO Control Register"]
+pub struct CTRL {
+    register: VolatileCell<u32>,
+}
+#[doc = "FlexIO Control Register"]
+pub mod ctrl;
+#[doc = "Pin State Register"]
+pub struct PIN {
+    register: VolatileCell<u32>,
+}
+#[doc = "Pin State Register"]
+pub mod pin;
+#[doc = "Shifter Status Register"]
+pub struct SHIFTSTAT {
+    register: VolatileCell<u32>,
+}
+#[doc = "Shifter Status Register"]
+pub mod shiftstat;
+#[doc = "Shifter Error Register"]
+pub struct SHIFTERR {
+    register: VolatileCell<u32>,
+}
+#[doc = "Shifter Error Register"]
+pub mod shifterr;
+#[doc = "Timer Status Register"]
+pub struct TIMSTAT {
+    register: VolatileCell<u32>,
+}
+#[doc = "Timer Status Register"]
+pub mod timstat;
+#[doc = "Shifter Status Interrupt Enable"]
+pub struct SHIFTSIEN {
+    register: VolatileCell<u32>,
+}
+#[doc = "Shifter Status Interrupt Enable"]
+pub mod shiftsien;
+#[doc = "Shifter Error Interrupt Enable"]
+pub struct SHIFTEIEN {
+    register: VolatileCell<u32>,
+}
+#[doc = "Shifter Error Interrupt Enable"]
+pub mod shifteien;
+#[doc = "Timer Interrupt Enable Register"]
+pub struct TIMIEN {
+    register: VolatileCell<u32>,
+}
+#[doc = "Timer Interrupt Enable Register"]
+pub mod timien;
+#[doc = "Shifter Status DMA Enable"]
+pub struct SHIFTSDEN {
+    register: VolatileCell<u32>,
+}
+#[doc = "Shifter Status DMA Enable"]
+pub mod shiftsden;
+#[doc = "Shifter Control N Register"]
+pub struct SHIFTCTL0 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Shifter Control N Register"]
+pub mod shiftctl0;
+#[doc = "Shifter Control N Register"]
+pub struct SHIFTCTL1 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Shifter Control N Register"]
+pub mod shiftctl1;
+#[doc = "Shifter Control N Register"]
+pub struct SHIFTCTL2 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Shifter Control N Register"]
+pub mod shiftctl2;
+#[doc = "Shifter Control N Register"]
+pub struct SHIFTCTL3 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Shifter Control N Register"]
+pub mod shiftctl3;
+#[doc = "Shifter Configuration N Register"]
+pub struct SHIFTCFG0 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Shifter Configuration N Register"]
+pub mod shiftcfg0;
+#[doc = "Shifter Configuration N Register"]
+pub struct SHIFTCFG1 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Shifter Configuration N Register"]
+pub mod shiftcfg1;
+#[doc = "Shifter Configuration N Register"]
+pub struct SHIFTCFG2 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Shifter Configuration N Register"]
+pub mod shiftcfg2;
+#[doc = "Shifter Configuration N Register"]
+pub struct SHIFTCFG3 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Shifter Configuration N Register"]
+pub mod shiftcfg3;
+#[doc = "Shifter Buffer N Register"]
+pub struct SHIFTBUF0 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Shifter Buffer N Register"]
+pub mod shiftbuf0;
+#[doc = "Shifter Buffer N Register"]
+pub struct SHIFTBUF1 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Shifter Buffer N Register"]
+pub mod shiftbuf1;
+#[doc = "Shifter Buffer N Register"]
+pub struct SHIFTBUF2 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Shifter Buffer N Register"]
+pub mod shiftbuf2;
+#[doc = "Shifter Buffer N Register"]
+pub struct SHIFTBUF3 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Shifter Buffer N Register"]
+pub mod shiftbuf3;
+#[doc = "Shifter Buffer N Bit Swapped Register"]
+pub struct SHIFTBUFBIS0 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Shifter Buffer N Bit Swapped Register"]
+pub mod shiftbufbis0;
+#[doc = "Shifter Buffer N Bit Swapped Register"]
+pub struct SHIFTBUFBIS1 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Shifter Buffer N Bit Swapped Register"]
+pub mod shiftbufbis1;
+#[doc = "Shifter Buffer N Bit Swapped Register"]
+pub struct SHIFTBUFBIS2 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Shifter Buffer N Bit Swapped Register"]
+pub mod shiftbufbis2;
+#[doc = "Shifter Buffer N Bit Swapped Register"]
+pub struct SHIFTBUFBIS3 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Shifter Buffer N Bit Swapped Register"]
+pub mod shiftbufbis3;
+#[doc = "Shifter Buffer N Byte Swapped Register"]
+pub struct SHIFTBUFBYS0 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Shifter Buffer N Byte Swapped Register"]
+pub mod shiftbufbys0;
+#[doc = "Shifter Buffer N Byte Swapped Register"]
+pub struct SHIFTBUFBYS1 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Shifter Buffer N Byte Swapped Register"]
+pub mod shiftbufbys1;
+#[doc = "Shifter Buffer N Byte Swapped Register"]
+pub struct SHIFTBUFBYS2 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Shifter Buffer N Byte Swapped Register"]
+pub mod shiftbufbys2;
+#[doc = "Shifter Buffer N Byte Swapped Register"]
+pub struct SHIFTBUFBYS3 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Shifter Buffer N Byte Swapped Register"]
+pub mod shiftbufbys3;
+#[doc = "Shifter Buffer N Bit Byte Swapped Register"]
+pub struct SHIFTBUFBBS0 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Shifter Buffer N Bit Byte Swapped Register"]
+pub mod shiftbufbbs0;
+#[doc = "Shifter Buffer N Bit Byte Swapped Register"]
+pub struct SHIFTBUFBBS1 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Shifter Buffer N Bit Byte Swapped Register"]
+pub mod shiftbufbbs1;
+#[doc = "Shifter Buffer N Bit Byte Swapped Register"]
+pub struct SHIFTBUFBBS2 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Shifter Buffer N Bit Byte Swapped Register"]
+pub mod shiftbufbbs2;
+#[doc = "Shifter Buffer N Bit Byte Swapped Register"]
+pub struct SHIFTBUFBBS3 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Shifter Buffer N Bit Byte Swapped Register"]
+pub mod shiftbufbbs3;
+#[doc = "Timer Control N Register"]
+pub struct TIMCTL0 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Timer Control N Register"]
+pub mod timctl0;
+#[doc = "Timer Control N Register"]
+pub struct TIMCTL1 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Timer Control N Register"]
+pub mod timctl1;
+#[doc = "Timer Control N Register"]
+pub struct TIMCTL2 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Timer Control N Register"]
+pub mod timctl2;
+#[doc = "Timer Control N Register"]
+pub struct TIMCTL3 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Timer Control N Register"]
+pub mod timctl3;
+#[doc = "Timer Configuration N Register"]
+pub struct TIMCFG0 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Timer Configuration N Register"]
+pub mod timcfg0;
+#[doc = "Timer Configuration N Register"]
+pub struct TIMCFG1 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Timer Configuration N Register"]
+pub mod timcfg1;
+#[doc = "Timer Configuration N Register"]
+pub struct TIMCFG2 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Timer Configuration N Register"]
+pub mod timcfg2;
+#[doc = "Timer Configuration N Register"]
+pub struct TIMCFG3 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Timer Configuration N Register"]
+pub mod timcfg3;
+#[doc = "Timer Compare N Register"]
+pub struct TIMCMP0 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Timer Compare N Register"]
+pub mod timcmp0;
+#[doc = "Timer Compare N Register"]
+pub struct TIMCMP1 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Timer Compare N Register"]
+pub mod timcmp1;
+#[doc = "Timer Compare N Register"]
+pub struct TIMCMP2 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Timer Compare N Register"]
+pub mod timcmp2;
+#[doc = "Timer Compare N Register"]
+pub struct TIMCMP3 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Timer Compare N Register"]
+pub mod timcmp3;

src/flexio/param/mod.rs

@@ -0,0 +1,102 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::PARAM {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SHIFTERR {
+    bits: u8,
+}
+impl SHIFTERR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TIMERR {
+    bits: u8,
+}
+impl TIMERR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PINR {
+    bits: u8,
+}
+impl PINR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TRIGGERR {
+    bits: u8,
+}
+impl TRIGGERR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Shifter Number"]
+    #[inline]
+    pub fn shifter(&self) -> SHIFTERR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        SHIFTERR { bits }
+    }
+    #[doc = "Bits 8:15 - Timer Number"]
+    #[inline]
+    pub fn timer(&self) -> TIMERR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        TIMERR { bits }
+    }
+    #[doc = "Bits 16:23 - Pin Number"]
+    #[inline]
+    pub fn pin(&self) -> PINR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        PINR { bits }
+    }
+    #[doc = "Bits 24:31 - Trigger Number"]
+    #[inline]
+    pub fn trigger(&self) -> TRIGGERR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 24;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        TRIGGERR { bits }
+    }
+}

src/flexio/pin/mod.rs

@@ -0,0 +1,39 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::PIN {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PDIR {
+    bits: u8,
+}
+impl PDIR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Pin Data Input"]
+    #[inline]
+    pub fn pdi(&self) -> PDIR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        PDIR { bits }
+    }
+}

src/flexio/shiftbuf0/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SHIFTBUF0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SHIFTBUFR {
+    bits: u32,
+}
+impl SHIFTBUFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SHIFTBUFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SHIFTBUFW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbuf(&self) -> SHIFTBUFR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        SHIFTBUFR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbuf(&mut self) -> _SHIFTBUFW {
+        _SHIFTBUFW { w: self }
+    }
+}

src/flexio/shiftbuf1/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SHIFTBUF1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SHIFTBUFR {
+    bits: u32,
+}
+impl SHIFTBUFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SHIFTBUFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SHIFTBUFW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbuf(&self) -> SHIFTBUFR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        SHIFTBUFR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbuf(&mut self) -> _SHIFTBUFW {
+        _SHIFTBUFW { w: self }
+    }
+}

src/flexio/shiftbuf2/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SHIFTBUF2 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SHIFTBUFR {
+    bits: u32,
+}
+impl SHIFTBUFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SHIFTBUFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SHIFTBUFW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbuf(&self) -> SHIFTBUFR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        SHIFTBUFR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbuf(&mut self) -> _SHIFTBUFW {
+        _SHIFTBUFW { w: self }
+    }
+}

src/flexio/shiftbuf3/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SHIFTBUF3 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SHIFTBUFR {
+    bits: u32,
+}
+impl SHIFTBUFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SHIFTBUFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SHIFTBUFW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbuf(&self) -> SHIFTBUFR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        SHIFTBUFR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbuf(&mut self) -> _SHIFTBUFW {
+        _SHIFTBUFW { w: self }
+    }
+}

src/flexio/shiftbufbbs0/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SHIFTBUFBBS0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SHIFTBUFBBSR {
+    bits: u32,
+}
+impl SHIFTBUFBBSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SHIFTBUFBBSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SHIFTBUFBBSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbufbbs(&self) -> SHIFTBUFBBSR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        SHIFTBUFBBSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbufbbs(&mut self) -> _SHIFTBUFBBSW {
+        _SHIFTBUFBBSW { w: self }
+    }
+}

src/flexio/shiftbufbbs1/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SHIFTBUFBBS1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SHIFTBUFBBSR {
+    bits: u32,
+}
+impl SHIFTBUFBBSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SHIFTBUFBBSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SHIFTBUFBBSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbufbbs(&self) -> SHIFTBUFBBSR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        SHIFTBUFBBSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbufbbs(&mut self) -> _SHIFTBUFBBSW {
+        _SHIFTBUFBBSW { w: self }
+    }
+}

src/flexio/shiftbufbbs2/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SHIFTBUFBBS2 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SHIFTBUFBBSR {
+    bits: u32,
+}
+impl SHIFTBUFBBSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SHIFTBUFBBSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SHIFTBUFBBSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbufbbs(&self) -> SHIFTBUFBBSR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        SHIFTBUFBBSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbufbbs(&mut self) -> _SHIFTBUFBBSW {
+        _SHIFTBUFBBSW { w: self }
+    }
+}

src/flexio/shiftbufbbs3/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SHIFTBUFBBS3 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SHIFTBUFBBSR {
+    bits: u32,
+}
+impl SHIFTBUFBBSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SHIFTBUFBBSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SHIFTBUFBBSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbufbbs(&self) -> SHIFTBUFBBSR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        SHIFTBUFBBSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbufbbs(&mut self) -> _SHIFTBUFBBSW {
+        _SHIFTBUFBBSW { w: self }
+    }
+}

src/flexio/shiftbufbis0/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SHIFTBUFBIS0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SHIFTBUFBISR {
+    bits: u32,
+}
+impl SHIFTBUFBISR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SHIFTBUFBISW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SHIFTBUFBISW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbufbis(&self) -> SHIFTBUFBISR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        SHIFTBUFBISR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbufbis(&mut self) -> _SHIFTBUFBISW {
+        _SHIFTBUFBISW { w: self }
+    }
+}

src/flexio/shiftbufbis1/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SHIFTBUFBIS1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SHIFTBUFBISR {
+    bits: u32,
+}
+impl SHIFTBUFBISR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SHIFTBUFBISW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SHIFTBUFBISW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbufbis(&self) -> SHIFTBUFBISR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        SHIFTBUFBISR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbufbis(&mut self) -> _SHIFTBUFBISW {
+        _SHIFTBUFBISW { w: self }
+    }
+}

src/flexio/shiftbufbis2/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SHIFTBUFBIS2 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SHIFTBUFBISR {
+    bits: u32,
+}
+impl SHIFTBUFBISR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SHIFTBUFBISW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SHIFTBUFBISW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbufbis(&self) -> SHIFTBUFBISR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        SHIFTBUFBISR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbufbis(&mut self) -> _SHIFTBUFBISW {
+        _SHIFTBUFBISW { w: self }
+    }
+}

src/flexio/shiftbufbis3/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SHIFTBUFBIS3 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SHIFTBUFBISR {
+    bits: u32,
+}
+impl SHIFTBUFBISR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SHIFTBUFBISW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SHIFTBUFBISW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbufbis(&self) -> SHIFTBUFBISR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        SHIFTBUFBISR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbufbis(&mut self) -> _SHIFTBUFBISW {
+        _SHIFTBUFBISW { w: self }
+    }
+}

src/flexio/shiftbufbys0/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SHIFTBUFBYS0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SHIFTBUFBYSR {
+    bits: u32,
+}
+impl SHIFTBUFBYSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SHIFTBUFBYSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SHIFTBUFBYSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbufbys(&self) -> SHIFTBUFBYSR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        SHIFTBUFBYSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbufbys(&mut self) -> _SHIFTBUFBYSW {
+        _SHIFTBUFBYSW { w: self }
+    }
+}

src/flexio/shiftbufbys1/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SHIFTBUFBYS1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SHIFTBUFBYSR {
+    bits: u32,
+}
+impl SHIFTBUFBYSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SHIFTBUFBYSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SHIFTBUFBYSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbufbys(&self) -> SHIFTBUFBYSR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        SHIFTBUFBYSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbufbys(&mut self) -> _SHIFTBUFBYSW {
+        _SHIFTBUFBYSW { w: self }
+    }
+}

src/flexio/shiftbufbys2/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SHIFTBUFBYS2 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SHIFTBUFBYSR {
+    bits: u32,
+}
+impl SHIFTBUFBYSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SHIFTBUFBYSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SHIFTBUFBYSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbufbys(&self) -> SHIFTBUFBYSR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        SHIFTBUFBYSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbufbys(&mut self) -> _SHIFTBUFBYSW {
+        _SHIFTBUFBYSW { w: self }
+    }
+}

src/flexio/shiftbufbys3/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SHIFTBUFBYS3 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SHIFTBUFBYSR {
+    bits: u32,
+}
+impl SHIFTBUFBYSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SHIFTBUFBYSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SHIFTBUFBYSW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbufbys(&self) -> SHIFTBUFBYSR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        SHIFTBUFBYSR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Shift Buffer"]
+    #[inline]
+    pub fn shiftbufbys(&mut self) -> _SHIFTBUFBYSW {
+        _SHIFTBUFBYSW { w: self }
+    }
+}

src/flexio/shiftcfg0/mod.rs

@@ -0,0 +1,453 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SHIFTCFG0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `SSTART`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SSTARTR {
+    #[doc = "Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable"]
+    _0,
+    #[doc = "Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift"]
+    _1,
+    #[doc = "Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0"]
+    _10,
+    #[doc = "Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1"]
+    _11,
+}
+impl SSTARTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            SSTARTR::_0 => 0,
+            SSTARTR::_1 => 1,
+            SSTARTR::_10 => 2,
+            SSTARTR::_11 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> SSTARTR {
+        match value {
+            0 => SSTARTR::_0,
+            1 => SSTARTR::_1,
+            2 => SSTARTR::_10,
+            3 => SSTARTR::_11,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == SSTARTR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == SSTARTR::_1
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == SSTARTR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == SSTARTR::_11
+    }
+}
+#[doc = "Possible values of the field `SSTOP`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SSTOPR {
+    #[doc = "Stop bit disabled for transmitter/receiver/match store"]
+    _0,
+    #[doc = "Reserved for transmitter/receiver/match store"]
+    _1,
+    #[doc = "Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0"]
+    _10,
+    #[doc = "Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1"]
+    _11,
+}
+impl SSTOPR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            SSTOPR::_0 => 0,
+            SSTOPR::_1 => 1,
+            SSTOPR::_10 => 2,
+            SSTOPR::_11 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> SSTOPR {
+        match value {
+            0 => SSTOPR::_0,
+            1 => SSTOPR::_1,
+            2 => SSTOPR::_10,
+            3 => SSTOPR::_11,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == SSTOPR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == SSTOPR::_1
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == SSTOPR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == SSTOPR::_11
+    }
+}
+#[doc = "Possible values of the field `INSRC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum INSRCR {
+    #[doc = "Pin"]
+    _0,
+    #[doc = "Shifter N+1 Output"]
+    _1,
+}
+impl INSRCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            INSRCR::_0 => false,
+            INSRCR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> INSRCR {
+        match value {
+            false => INSRCR::_0,
+            true => INSRCR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == INSRCR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == INSRCR::_1
+    }
+}
+#[doc = "Values that can be written to the field `SSTART`"]
+pub enum SSTARTW {
+    #[doc = "Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable"]
+    _0,
+    #[doc = "Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift"]
+    _1,
+    #[doc = "Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0"]
+    _10,
+    #[doc = "Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1"]
+    _11,
+}
+impl SSTARTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            SSTARTW::_0 => 0,
+            SSTARTW::_1 => 1,
+            SSTARTW::_10 => 2,
+            SSTARTW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SSTARTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SSTARTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SSTARTW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(SSTARTW::_0)
+    }
+    #[doc = "Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(SSTARTW::_1)
+    }
+    #[doc = "Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0"]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(SSTARTW::_10)
+    }
+    #[doc = "Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1"]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(SSTARTW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SSTOP`"]
+pub enum SSTOPW {
+    #[doc = "Stop bit disabled for transmitter/receiver/match store"]
+    _0,
+    #[doc = "Reserved for transmitter/receiver/match store"]
+    _1,
+    #[doc = "Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0"]
+    _10,
+    #[doc = "Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1"]
+    _11,
+}
+impl SSTOPW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            SSTOPW::_0 => 0,
+            SSTOPW::_1 => 1,
+            SSTOPW::_10 => 2,
+            SSTOPW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SSTOPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SSTOPW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SSTOPW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Stop bit disabled for transmitter/receiver/match store"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(SSTOPW::_0)
+    }
+    #[doc = "Reserved for transmitter/receiver/match store"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(SSTOPW::_1)
+    }
+    #[doc = "Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0"]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(SSTOPW::_10)
+    }
+    #[doc = "Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1"]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(SSTOPW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `INSRC`"]
+pub enum INSRCW {
+    #[doc = "Pin"]
+    _0,
+    #[doc = "Shifter N+1 Output"]
+    _1,
+}
+impl INSRCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            INSRCW::_0 => false,
+            INSRCW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _INSRCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _INSRCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: INSRCW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Pin"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(INSRCW::_0)
+    }
+    #[doc = "Shifter N+1 Output"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(INSRCW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:1 - Shifter Start bit"]
+    #[inline]
+    pub fn sstart(&self) -> SSTARTR {
+        SSTARTR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 4:5 - Shifter Stop bit"]
+    #[inline]
+    pub fn sstop(&self) -> SSTOPR {
+        SSTOPR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 8 - Input Source"]
+    #[inline]
+    pub fn insrc(&self) -> INSRCR {
+        INSRCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:1 - Shifter Start bit"]
+    #[inline]
+    pub fn sstart(&mut self) -> _SSTARTW {
+        _SSTARTW { w: self }
+    }
+    #[doc = "Bits 4:5 - Shifter Stop bit"]
+    #[inline]
+    pub fn sstop(&mut self) -> _SSTOPW {
+        _SSTOPW { w: self }
+    }
+    #[doc = "Bit 8 - Input Source"]
+    #[inline]
+    pub fn insrc(&mut self) -> _INSRCW {
+        _INSRCW { w: self }
+    }
+}

src/flexio/shiftcfg1/mod.rs

@@ -0,0 +1,453 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SHIFTCFG1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `SSTART`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SSTARTR {
+    #[doc = "Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable"]
+    _0,
+    #[doc = "Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift"]
+    _1,
+    #[doc = "Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0"]
+    _10,
+    #[doc = "Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1"]
+    _11,
+}
+impl SSTARTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            SSTARTR::_0 => 0,
+            SSTARTR::_1 => 1,
+            SSTARTR::_10 => 2,
+            SSTARTR::_11 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> SSTARTR {
+        match value {
+            0 => SSTARTR::_0,
+            1 => SSTARTR::_1,
+            2 => SSTARTR::_10,
+            3 => SSTARTR::_11,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == SSTARTR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == SSTARTR::_1
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == SSTARTR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == SSTARTR::_11
+    }
+}
+#[doc = "Possible values of the field `SSTOP`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SSTOPR {
+    #[doc = "Stop bit disabled for transmitter/receiver/match store"]
+    _0,
+    #[doc = "Reserved for transmitter/receiver/match store"]
+    _1,
+    #[doc = "Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0"]
+    _10,
+    #[doc = "Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1"]
+    _11,
+}
+impl SSTOPR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            SSTOPR::_0 => 0,
+            SSTOPR::_1 => 1,
+            SSTOPR::_10 => 2,
+            SSTOPR::_11 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> SSTOPR {
+        match value {
+            0 => SSTOPR::_0,
+            1 => SSTOPR::_1,
+            2 => SSTOPR::_10,
+            3 => SSTOPR::_11,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == SSTOPR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == SSTOPR::_1
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == SSTOPR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == SSTOPR::_11
+    }
+}
+#[doc = "Possible values of the field `INSRC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum INSRCR {
+    #[doc = "Pin"]
+    _0,
+    #[doc = "Shifter N+1 Output"]
+    _1,
+}
+impl INSRCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            INSRCR::_0 => false,
+            INSRCR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> INSRCR {
+        match value {
+            false => INSRCR::_0,
+            true => INSRCR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == INSRCR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == INSRCR::_1
+    }
+}
+#[doc = "Values that can be written to the field `SSTART`"]
+pub enum SSTARTW {
+    #[doc = "Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable"]
+    _0,
+    #[doc = "Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift"]
+    _1,
+    #[doc = "Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0"]
+    _10,
+    #[doc = "Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1"]
+    _11,
+}
+impl SSTARTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            SSTARTW::_0 => 0,
+            SSTARTW::_1 => 1,
+            SSTARTW::_10 => 2,
+            SSTARTW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SSTARTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SSTARTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SSTARTW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(SSTARTW::_0)
+    }
+    #[doc = "Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(SSTARTW::_1)
+    }
+    #[doc = "Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0"]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(SSTARTW::_10)
+    }
+    #[doc = "Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1"]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(SSTARTW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SSTOP`"]
+pub enum SSTOPW {
+    #[doc = "Stop bit disabled for transmitter/receiver/match store"]
+    _0,
+    #[doc = "Reserved for transmitter/receiver/match store"]
+    _1,
+    #[doc = "Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0"]
+    _10,
+    #[doc = "Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1"]
+    _11,
+}
+impl SSTOPW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            SSTOPW::_0 => 0,
+            SSTOPW::_1 => 1,
+            SSTOPW::_10 => 2,
+            SSTOPW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SSTOPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SSTOPW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SSTOPW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Stop bit disabled for transmitter/receiver/match store"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(SSTOPW::_0)
+    }
+    #[doc = "Reserved for transmitter/receiver/match store"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(SSTOPW::_1)
+    }
+    #[doc = "Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0"]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(SSTOPW::_10)
+    }
+    #[doc = "Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1"]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(SSTOPW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `INSRC`"]
+pub enum INSRCW {
+    #[doc = "Pin"]
+    _0,
+    #[doc = "Shifter N+1 Output"]
+    _1,
+}
+impl INSRCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            INSRCW::_0 => false,
+            INSRCW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _INSRCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _INSRCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: INSRCW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Pin"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(INSRCW::_0)
+    }
+    #[doc = "Shifter N+1 Output"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(INSRCW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:1 - Shifter Start bit"]
+    #[inline]
+    pub fn sstart(&self) -> SSTARTR {
+        SSTARTR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 4:5 - Shifter Stop bit"]
+    #[inline]
+    pub fn sstop(&self) -> SSTOPR {
+        SSTOPR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 8 - Input Source"]
+    #[inline]
+    pub fn insrc(&self) -> INSRCR {
+        INSRCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:1 - Shifter Start bit"]
+    #[inline]
+    pub fn sstart(&mut self) -> _SSTARTW {
+        _SSTARTW { w: self }
+    }
+    #[doc = "Bits 4:5 - Shifter Stop bit"]
+    #[inline]
+    pub fn sstop(&mut self) -> _SSTOPW {
+        _SSTOPW { w: self }
+    }
+    #[doc = "Bit 8 - Input Source"]
+    #[inline]
+    pub fn insrc(&mut self) -> _INSRCW {
+        _INSRCW { w: self }
+    }
+}

src/flexio/shiftcfg2/mod.rs

@@ -0,0 +1,453 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SHIFTCFG2 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `SSTART`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SSTARTR {
+    #[doc = "Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable"]
+    _0,
+    #[doc = "Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift"]
+    _1,
+    #[doc = "Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0"]
+    _10,
+    #[doc = "Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1"]
+    _11,
+}
+impl SSTARTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            SSTARTR::_0 => 0,
+            SSTARTR::_1 => 1,
+            SSTARTR::_10 => 2,
+            SSTARTR::_11 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> SSTARTR {
+        match value {
+            0 => SSTARTR::_0,
+            1 => SSTARTR::_1,
+            2 => SSTARTR::_10,
+            3 => SSTARTR::_11,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == SSTARTR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == SSTARTR::_1
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == SSTARTR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == SSTARTR::_11
+    }
+}
+#[doc = "Possible values of the field `SSTOP`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SSTOPR {
+    #[doc = "Stop bit disabled for transmitter/receiver/match store"]
+    _0,
+    #[doc = "Reserved for transmitter/receiver/match store"]
+    _1,
+    #[doc = "Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0"]
+    _10,
+    #[doc = "Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1"]
+    _11,
+}
+impl SSTOPR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            SSTOPR::_0 => 0,
+            SSTOPR::_1 => 1,
+            SSTOPR::_10 => 2,
+            SSTOPR::_11 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> SSTOPR {
+        match value {
+            0 => SSTOPR::_0,
+            1 => SSTOPR::_1,
+            2 => SSTOPR::_10,
+            3 => SSTOPR::_11,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == SSTOPR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == SSTOPR::_1
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == SSTOPR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == SSTOPR::_11
+    }
+}
+#[doc = "Possible values of the field `INSRC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum INSRCR {
+    #[doc = "Pin"]
+    _0,
+    #[doc = "Shifter N+1 Output"]
+    _1,
+}
+impl INSRCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            INSRCR::_0 => false,
+            INSRCR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> INSRCR {
+        match value {
+            false => INSRCR::_0,
+            true => INSRCR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == INSRCR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == INSRCR::_1
+    }
+}
+#[doc = "Values that can be written to the field `SSTART`"]
+pub enum SSTARTW {
+    #[doc = "Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable"]
+    _0,
+    #[doc = "Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift"]
+    _1,
+    #[doc = "Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0"]
+    _10,
+    #[doc = "Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1"]
+    _11,
+}
+impl SSTARTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            SSTARTW::_0 => 0,
+            SSTARTW::_1 => 1,
+            SSTARTW::_10 => 2,
+            SSTARTW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SSTARTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SSTARTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SSTARTW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(SSTARTW::_0)
+    }
+    #[doc = "Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(SSTARTW::_1)
+    }
+    #[doc = "Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0"]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(SSTARTW::_10)
+    }
+    #[doc = "Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1"]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(SSTARTW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SSTOP`"]
+pub enum SSTOPW {
+    #[doc = "Stop bit disabled for transmitter/receiver/match store"]
+    _0,
+    #[doc = "Reserved for transmitter/receiver/match store"]
+    _1,
+    #[doc = "Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0"]
+    _10,
+    #[doc = "Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1"]
+    _11,
+}
+impl SSTOPW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            SSTOPW::_0 => 0,
+            SSTOPW::_1 => 1,
+            SSTOPW::_10 => 2,
+            SSTOPW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SSTOPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SSTOPW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SSTOPW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Stop bit disabled for transmitter/receiver/match store"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(SSTOPW::_0)
+    }
+    #[doc = "Reserved for transmitter/receiver/match store"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(SSTOPW::_1)
+    }
+    #[doc = "Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0"]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(SSTOPW::_10)
+    }
+    #[doc = "Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1"]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(SSTOPW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `INSRC`"]
+pub enum INSRCW {
+    #[doc = "Pin"]
+    _0,
+    #[doc = "Shifter N+1 Output"]
+    _1,
+}
+impl INSRCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            INSRCW::_0 => false,
+            INSRCW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _INSRCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _INSRCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: INSRCW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Pin"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(INSRCW::_0)
+    }
+    #[doc = "Shifter N+1 Output"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(INSRCW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:1 - Shifter Start bit"]
+    #[inline]
+    pub fn sstart(&self) -> SSTARTR {
+        SSTARTR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 4:5 - Shifter Stop bit"]
+    #[inline]
+    pub fn sstop(&self) -> SSTOPR {
+        SSTOPR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 8 - Input Source"]
+    #[inline]
+    pub fn insrc(&self) -> INSRCR {
+        INSRCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:1 - Shifter Start bit"]
+    #[inline]
+    pub fn sstart(&mut self) -> _SSTARTW {
+        _SSTARTW { w: self }
+    }
+    #[doc = "Bits 4:5 - Shifter Stop bit"]
+    #[inline]
+    pub fn sstop(&mut self) -> _SSTOPW {
+        _SSTOPW { w: self }
+    }
+    #[doc = "Bit 8 - Input Source"]
+    #[inline]
+    pub fn insrc(&mut self) -> _INSRCW {
+        _INSRCW { w: self }
+    }
+}

src/flexio/shiftcfg3/mod.rs

@@ -0,0 +1,453 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SHIFTCFG3 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `SSTART`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SSTARTR {
+    #[doc = "Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable"]
+    _0,
+    #[doc = "Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift"]
+    _1,
+    #[doc = "Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0"]
+    _10,
+    #[doc = "Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1"]
+    _11,
+}
+impl SSTARTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            SSTARTR::_0 => 0,
+            SSTARTR::_1 => 1,
+            SSTARTR::_10 => 2,
+            SSTARTR::_11 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> SSTARTR {
+        match value {
+            0 => SSTARTR::_0,
+            1 => SSTARTR::_1,
+            2 => SSTARTR::_10,
+            3 => SSTARTR::_11,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == SSTARTR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == SSTARTR::_1
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == SSTARTR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == SSTARTR::_11
+    }
+}
+#[doc = "Possible values of the field `SSTOP`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SSTOPR {
+    #[doc = "Stop bit disabled for transmitter/receiver/match store"]
+    _0,
+    #[doc = "Reserved for transmitter/receiver/match store"]
+    _1,
+    #[doc = "Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0"]
+    _10,
+    #[doc = "Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1"]
+    _11,
+}
+impl SSTOPR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            SSTOPR::_0 => 0,
+            SSTOPR::_1 => 1,
+            SSTOPR::_10 => 2,
+            SSTOPR::_11 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> SSTOPR {
+        match value {
+            0 => SSTOPR::_0,
+            1 => SSTOPR::_1,
+            2 => SSTOPR::_10,
+            3 => SSTOPR::_11,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == SSTOPR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == SSTOPR::_1
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == SSTOPR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == SSTOPR::_11
+    }
+}
+#[doc = "Possible values of the field `INSRC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum INSRCR {
+    #[doc = "Pin"]
+    _0,
+    #[doc = "Shifter N+1 Output"]
+    _1,
+}
+impl INSRCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            INSRCR::_0 => false,
+            INSRCR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> INSRCR {
+        match value {
+            false => INSRCR::_0,
+            true => INSRCR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == INSRCR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == INSRCR::_1
+    }
+}
+#[doc = "Values that can be written to the field `SSTART`"]
+pub enum SSTARTW {
+    #[doc = "Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable"]
+    _0,
+    #[doc = "Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift"]
+    _1,
+    #[doc = "Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0"]
+    _10,
+    #[doc = "Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1"]
+    _11,
+}
+impl SSTARTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            SSTARTW::_0 => 0,
+            SSTARTW::_1 => 1,
+            SSTARTW::_10 => 2,
+            SSTARTW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SSTARTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SSTARTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SSTARTW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(SSTARTW::_0)
+    }
+    #[doc = "Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(SSTARTW::_1)
+    }
+    #[doc = "Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0"]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(SSTARTW::_10)
+    }
+    #[doc = "Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1"]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(SSTARTW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SSTOP`"]
+pub enum SSTOPW {
+    #[doc = "Stop bit disabled for transmitter/receiver/match store"]
+    _0,
+    #[doc = "Reserved for transmitter/receiver/match store"]
+    _1,
+    #[doc = "Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0"]
+    _10,
+    #[doc = "Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1"]
+    _11,
+}
+impl SSTOPW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            SSTOPW::_0 => 0,
+            SSTOPW::_1 => 1,
+            SSTOPW::_10 => 2,
+            SSTOPW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SSTOPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SSTOPW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SSTOPW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Stop bit disabled for transmitter/receiver/match store"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(SSTOPW::_0)
+    }
+    #[doc = "Reserved for transmitter/receiver/match store"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(SSTOPW::_1)
+    }
+    #[doc = "Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0"]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(SSTOPW::_10)
+    }
+    #[doc = "Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1"]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(SSTOPW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `INSRC`"]
+pub enum INSRCW {
+    #[doc = "Pin"]
+    _0,
+    #[doc = "Shifter N+1 Output"]
+    _1,
+}
+impl INSRCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            INSRCW::_0 => false,
+            INSRCW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _INSRCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _INSRCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: INSRCW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Pin"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(INSRCW::_0)
+    }
+    #[doc = "Shifter N+1 Output"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(INSRCW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:1 - Shifter Start bit"]
+    #[inline]
+    pub fn sstart(&self) -> SSTARTR {
+        SSTARTR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 4:5 - Shifter Stop bit"]
+    #[inline]
+    pub fn sstop(&self) -> SSTOPR {
+        SSTOPR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 8 - Input Source"]
+    #[inline]
+    pub fn insrc(&self) -> INSRCR {
+        INSRCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:1 - Shifter Start bit"]
+    #[inline]
+    pub fn sstart(&mut self) -> _SSTARTW {
+        _SSTARTW { w: self }
+    }
+    #[doc = "Bits 4:5 - Shifter Stop bit"]
+    #[inline]
+    pub fn sstop(&mut self) -> _SSTOPW {
+        _SSTOPW { w: self }
+    }
+    #[doc = "Bit 8 - Input Source"]
+    #[inline]
+    pub fn insrc(&mut self) -> _INSRCW {
+        _INSRCW { w: self }
+    }
+}

src/flexio/shiftctl0/mod.rs

@@ -0,0 +1,672 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SHIFTCTL0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `SMOD`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SMODR {
+    #[doc = "Disabled."]
+    _0,
+    #[doc = "Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer."]
+    _1,
+    #[doc = "Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer."]
+    _10,
+    #[doc = "Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer."]
+    _100,
+    #[doc = "Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents."]
+    _101,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl SMODR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            SMODR::_0 => 0,
+            SMODR::_1 => 1,
+            SMODR::_10 => 2,
+            SMODR::_100 => 4,
+            SMODR::_101 => 5,
+            SMODR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> SMODR {
+        match value {
+            0 => SMODR::_0,
+            1 => SMODR::_1,
+            2 => SMODR::_10,
+            4 => SMODR::_100,
+            5 => SMODR::_101,
+            i => SMODR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == SMODR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == SMODR::_1
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == SMODR::_10
+    }
+    #[doc = "Checks if the value of the field is `_100`"]
+    #[inline]
+    pub fn is_100(&self) -> bool {
+        *self == SMODR::_100
+    }
+    #[doc = "Checks if the value of the field is `_101`"]
+    #[inline]
+    pub fn is_101(&self) -> bool {
+        *self == SMODR::_101
+    }
+}
+#[doc = "Possible values of the field `PINPOL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PINPOLR {
+    #[doc = "Pin is active high"]
+    _0,
+    #[doc = "Pin is active low"]
+    _1,
+}
+impl PINPOLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            PINPOLR::_0 => false,
+            PINPOLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> PINPOLR {
+        match value {
+            false => PINPOLR::_0,
+            true => PINPOLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == PINPOLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == PINPOLR::_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PINSELR {
+    bits: u8,
+}
+impl PINSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `PINCFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PINCFGR {
+    #[doc = "Shifter pin output disabled"]
+    _0,
+    #[doc = "Shifter pin open drain or bidirectional output enable"]
+    _1,
+    #[doc = "Shifter pin bidirectional output data"]
+    _10,
+    #[doc = "Shifter pin output"]
+    _11,
+}
+impl PINCFGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            PINCFGR::_0 => 0,
+            PINCFGR::_1 => 1,
+            PINCFGR::_10 => 2,
+            PINCFGR::_11 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> PINCFGR {
+        match value {
+            0 => PINCFGR::_0,
+            1 => PINCFGR::_1,
+            2 => PINCFGR::_10,
+            3 => PINCFGR::_11,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == PINCFGR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == PINCFGR::_1
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == PINCFGR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == PINCFGR::_11
+    }
+}
+#[doc = "Possible values of the field `TIMPOL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TIMPOLR {
+    #[doc = "Shift on posedge of Shift clock"]
+    _0,
+    #[doc = "Shift on negedge of Shift clock"]
+    _1,
+}
+impl TIMPOLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TIMPOLR::_0 => false,
+            TIMPOLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TIMPOLR {
+        match value {
+            false => TIMPOLR::_0,
+            true => TIMPOLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TIMPOLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TIMPOLR::_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TIMSELR {
+    bits: u8,
+}
+impl TIMSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Values that can be written to the field `SMOD`"]
+pub enum SMODW {
+    #[doc = "Disabled."]
+    _0,
+    #[doc = "Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer."]
+    _1,
+    #[doc = "Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer."]
+    _10,
+    #[doc = "Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer."]
+    _100,
+    #[doc = "Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents."]
+    _101,
+}
+impl SMODW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            SMODW::_0 => 0,
+            SMODW::_1 => 1,
+            SMODW::_10 => 2,
+            SMODW::_100 => 4,
+            SMODW::_101 => 5,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SMODW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SMODW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SMODW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "Disabled."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(SMODW::_0)
+    }
+    #[doc = "Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(SMODW::_1)
+    }
+    #[doc = "Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer."]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(SMODW::_10)
+    }
+    #[doc = "Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer."]
+    #[inline]
+    pub fn _100(self) -> &'a mut W {
+        self.variant(SMODW::_100)
+    }
+    #[doc = "Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents."]
+    #[inline]
+    pub fn _101(self) -> &'a mut W {
+        self.variant(SMODW::_101)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PINPOL`"]
+pub enum PINPOLW {
+    #[doc = "Pin is active high"]
+    _0,
+    #[doc = "Pin is active low"]
+    _1,
+}
+impl PINPOLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            PINPOLW::_0 => false,
+            PINPOLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PINPOLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PINPOLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PINPOLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Pin is active high"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(PINPOLW::_0)
+    }
+    #[doc = "Pin is active low"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(PINPOLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PINSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PINSELW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PINCFG`"]
+pub enum PINCFGW {
+    #[doc = "Shifter pin output disabled"]
+    _0,
+    #[doc = "Shifter pin open drain or bidirectional output enable"]
+    _1,
+    #[doc = "Shifter pin bidirectional output data"]
+    _10,
+    #[doc = "Shifter pin output"]
+    _11,
+}
+impl PINCFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            PINCFGW::_0 => 0,
+            PINCFGW::_1 => 1,
+            PINCFGW::_10 => 2,
+            PINCFGW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PINCFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PINCFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PINCFGW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Shifter pin output disabled"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(PINCFGW::_0)
+    }
+    #[doc = "Shifter pin open drain or bidirectional output enable"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(PINCFGW::_1)
+    }
+    #[doc = "Shifter pin bidirectional output data"]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(PINCFGW::_10)
+    }
+    #[doc = "Shifter pin output"]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(PINCFGW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 16;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TIMPOL`"]
+pub enum TIMPOLW {
+    #[doc = "Shift on posedge of Shift clock"]
+    _0,
+    #[doc = "Shift on negedge of Shift clock"]
+    _1,
+}
+impl TIMPOLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TIMPOLW::_0 => false,
+            TIMPOLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TIMPOLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TIMPOLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TIMPOLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Shift on posedge of Shift clock"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TIMPOLW::_0)
+    }
+    #[doc = "Shift on negedge of Shift clock"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TIMPOLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 23;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TIMSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TIMSELW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 24;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:2 - Shifter Mode"]
+    #[inline]
+    pub fn smod(&self) -> SMODR {
+        SMODR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 7 - Shifter Pin Polarity"]
+    #[inline]
+    pub fn pinpol(&self) -> PINPOLR {
+        PINPOLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 8:10 - Shifter Pin Select"]
+    #[inline]
+    pub fn pinsel(&self) -> PINSELR {
+        let bits = {
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        PINSELR { bits }
+    }
+    #[doc = "Bits 16:17 - Shifter Pin Configuration"]
+    #[inline]
+    pub fn pincfg(&self) -> PINCFGR {
+        PINCFGR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 23 - Timer Polarity"]
+    #[inline]
+    pub fn timpol(&self) -> TIMPOLR {
+        TIMPOLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 23;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 24:25 - Timer Select"]
+    #[inline]
+    pub fn timsel(&self) -> TIMSELR {
+        let bits = {
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 24;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        TIMSELR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:2 - Shifter Mode"]
+    #[inline]
+    pub fn smod(&mut self) -> _SMODW {
+        _SMODW { w: self }
+    }
+    #[doc = "Bit 7 - Shifter Pin Polarity"]
+    #[inline]
+    pub fn pinpol(&mut self) -> _PINPOLW {
+        _PINPOLW { w: self }
+    }
+    #[doc = "Bits 8:10 - Shifter Pin Select"]
+    #[inline]
+    pub fn pinsel(&mut self) -> _PINSELW {
+        _PINSELW { w: self }
+    }
+    #[doc = "Bits 16:17 - Shifter Pin Configuration"]
+    #[inline]
+    pub fn pincfg(&mut self) -> _PINCFGW {
+        _PINCFGW { w: self }
+    }
+    #[doc = "Bit 23 - Timer Polarity"]
+    #[inline]
+    pub fn timpol(&mut self) -> _TIMPOLW {
+        _TIMPOLW { w: self }
+    }
+    #[doc = "Bits 24:25 - Timer Select"]
+    #[inline]
+    pub fn timsel(&mut self) -> _TIMSELW {
+        _TIMSELW { w: self }
+    }
+}

src/flexio/shiftctl1/mod.rs

@@ -0,0 +1,672 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SHIFTCTL1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `SMOD`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SMODR {
+    #[doc = "Disabled."]
+    _0,
+    #[doc = "Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer."]
+    _1,
+    #[doc = "Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer."]
+    _10,
+    #[doc = "Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer."]
+    _100,
+    #[doc = "Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents."]
+    _101,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl SMODR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            SMODR::_0 => 0,
+            SMODR::_1 => 1,
+            SMODR::_10 => 2,
+            SMODR::_100 => 4,
+            SMODR::_101 => 5,
+            SMODR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> SMODR {
+        match value {
+            0 => SMODR::_0,
+            1 => SMODR::_1,
+            2 => SMODR::_10,
+            4 => SMODR::_100,
+            5 => SMODR::_101,
+            i => SMODR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == SMODR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == SMODR::_1
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == SMODR::_10
+    }
+    #[doc = "Checks if the value of the field is `_100`"]
+    #[inline]
+    pub fn is_100(&self) -> bool {
+        *self == SMODR::_100
+    }
+    #[doc = "Checks if the value of the field is `_101`"]
+    #[inline]
+    pub fn is_101(&self) -> bool {
+        *self == SMODR::_101
+    }
+}
+#[doc = "Possible values of the field `PINPOL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PINPOLR {
+    #[doc = "Pin is active high"]
+    _0,
+    #[doc = "Pin is active low"]
+    _1,
+}
+impl PINPOLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            PINPOLR::_0 => false,
+            PINPOLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> PINPOLR {
+        match value {
+            false => PINPOLR::_0,
+            true => PINPOLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == PINPOLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == PINPOLR::_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PINSELR {
+    bits: u8,
+}
+impl PINSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `PINCFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PINCFGR {
+    #[doc = "Shifter pin output disabled"]
+    _0,
+    #[doc = "Shifter pin open drain or bidirectional output enable"]
+    _1,
+    #[doc = "Shifter pin bidirectional output data"]
+    _10,
+    #[doc = "Shifter pin output"]
+    _11,
+}
+impl PINCFGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            PINCFGR::_0 => 0,
+            PINCFGR::_1 => 1,
+            PINCFGR::_10 => 2,
+            PINCFGR::_11 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> PINCFGR {
+        match value {
+            0 => PINCFGR::_0,
+            1 => PINCFGR::_1,
+            2 => PINCFGR::_10,
+            3 => PINCFGR::_11,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == PINCFGR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == PINCFGR::_1
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == PINCFGR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == PINCFGR::_11
+    }
+}
+#[doc = "Possible values of the field `TIMPOL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TIMPOLR {
+    #[doc = "Shift on posedge of Shift clock"]
+    _0,
+    #[doc = "Shift on negedge of Shift clock"]
+    _1,
+}
+impl TIMPOLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TIMPOLR::_0 => false,
+            TIMPOLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TIMPOLR {
+        match value {
+            false => TIMPOLR::_0,
+            true => TIMPOLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TIMPOLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TIMPOLR::_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TIMSELR {
+    bits: u8,
+}
+impl TIMSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Values that can be written to the field `SMOD`"]
+pub enum SMODW {
+    #[doc = "Disabled."]
+    _0,
+    #[doc = "Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer."]
+    _1,
+    #[doc = "Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer."]
+    _10,
+    #[doc = "Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer."]
+    _100,
+    #[doc = "Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents."]
+    _101,
+}
+impl SMODW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            SMODW::_0 => 0,
+            SMODW::_1 => 1,
+            SMODW::_10 => 2,
+            SMODW::_100 => 4,
+            SMODW::_101 => 5,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SMODW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SMODW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SMODW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "Disabled."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(SMODW::_0)
+    }
+    #[doc = "Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(SMODW::_1)
+    }
+    #[doc = "Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer."]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(SMODW::_10)
+    }
+    #[doc = "Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer."]
+    #[inline]
+    pub fn _100(self) -> &'a mut W {
+        self.variant(SMODW::_100)
+    }
+    #[doc = "Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents."]
+    #[inline]
+    pub fn _101(self) -> &'a mut W {
+        self.variant(SMODW::_101)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PINPOL`"]
+pub enum PINPOLW {
+    #[doc = "Pin is active high"]
+    _0,
+    #[doc = "Pin is active low"]
+    _1,
+}
+impl PINPOLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            PINPOLW::_0 => false,
+            PINPOLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PINPOLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PINPOLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PINPOLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Pin is active high"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(PINPOLW::_0)
+    }
+    #[doc = "Pin is active low"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(PINPOLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PINSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PINSELW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PINCFG`"]
+pub enum PINCFGW {
+    #[doc = "Shifter pin output disabled"]
+    _0,
+    #[doc = "Shifter pin open drain or bidirectional output enable"]
+    _1,
+    #[doc = "Shifter pin bidirectional output data"]
+    _10,
+    #[doc = "Shifter pin output"]
+    _11,
+}
+impl PINCFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            PINCFGW::_0 => 0,
+            PINCFGW::_1 => 1,
+            PINCFGW::_10 => 2,
+            PINCFGW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PINCFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PINCFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PINCFGW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Shifter pin output disabled"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(PINCFGW::_0)
+    }
+    #[doc = "Shifter pin open drain or bidirectional output enable"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(PINCFGW::_1)
+    }
+    #[doc = "Shifter pin bidirectional output data"]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(PINCFGW::_10)
+    }
+    #[doc = "Shifter pin output"]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(PINCFGW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 16;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TIMPOL`"]
+pub enum TIMPOLW {
+    #[doc = "Shift on posedge of Shift clock"]
+    _0,
+    #[doc = "Shift on negedge of Shift clock"]
+    _1,
+}
+impl TIMPOLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TIMPOLW::_0 => false,
+            TIMPOLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TIMPOLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TIMPOLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TIMPOLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Shift on posedge of Shift clock"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TIMPOLW::_0)
+    }
+    #[doc = "Shift on negedge of Shift clock"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TIMPOLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 23;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TIMSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TIMSELW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 24;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:2 - Shifter Mode"]
+    #[inline]
+    pub fn smod(&self) -> SMODR {
+        SMODR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 7 - Shifter Pin Polarity"]
+    #[inline]
+    pub fn pinpol(&self) -> PINPOLR {
+        PINPOLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 8:10 - Shifter Pin Select"]
+    #[inline]
+    pub fn pinsel(&self) -> PINSELR {
+        let bits = {
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        PINSELR { bits }
+    }
+    #[doc = "Bits 16:17 - Shifter Pin Configuration"]
+    #[inline]
+    pub fn pincfg(&self) -> PINCFGR {
+        PINCFGR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 23 - Timer Polarity"]
+    #[inline]
+    pub fn timpol(&self) -> TIMPOLR {
+        TIMPOLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 23;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 24:25 - Timer Select"]
+    #[inline]
+    pub fn timsel(&self) -> TIMSELR {
+        let bits = {
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 24;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        TIMSELR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:2 - Shifter Mode"]
+    #[inline]
+    pub fn smod(&mut self) -> _SMODW {
+        _SMODW { w: self }
+    }
+    #[doc = "Bit 7 - Shifter Pin Polarity"]
+    #[inline]
+    pub fn pinpol(&mut self) -> _PINPOLW {
+        _PINPOLW { w: self }
+    }
+    #[doc = "Bits 8:10 - Shifter Pin Select"]
+    #[inline]
+    pub fn pinsel(&mut self) -> _PINSELW {
+        _PINSELW { w: self }
+    }
+    #[doc = "Bits 16:17 - Shifter Pin Configuration"]
+    #[inline]
+    pub fn pincfg(&mut self) -> _PINCFGW {
+        _PINCFGW { w: self }
+    }
+    #[doc = "Bit 23 - Timer Polarity"]
+    #[inline]
+    pub fn timpol(&mut self) -> _TIMPOLW {
+        _TIMPOLW { w: self }
+    }
+    #[doc = "Bits 24:25 - Timer Select"]
+    #[inline]
+    pub fn timsel(&mut self) -> _TIMSELW {
+        _TIMSELW { w: self }
+    }
+}

src/flexio/shiftctl2/mod.rs

@@ -0,0 +1,672 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SHIFTCTL2 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `SMOD`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SMODR {
+    #[doc = "Disabled."]
+    _0,
+    #[doc = "Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer."]
+    _1,
+    #[doc = "Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer."]
+    _10,
+    #[doc = "Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer."]
+    _100,
+    #[doc = "Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents."]
+    _101,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl SMODR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            SMODR::_0 => 0,
+            SMODR::_1 => 1,
+            SMODR::_10 => 2,
+            SMODR::_100 => 4,
+            SMODR::_101 => 5,
+            SMODR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> SMODR {
+        match value {
+            0 => SMODR::_0,
+            1 => SMODR::_1,
+            2 => SMODR::_10,
+            4 => SMODR::_100,
+            5 => SMODR::_101,
+            i => SMODR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == SMODR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == SMODR::_1
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == SMODR::_10
+    }
+    #[doc = "Checks if the value of the field is `_100`"]
+    #[inline]
+    pub fn is_100(&self) -> bool {
+        *self == SMODR::_100
+    }
+    #[doc = "Checks if the value of the field is `_101`"]
+    #[inline]
+    pub fn is_101(&self) -> bool {
+        *self == SMODR::_101
+    }
+}
+#[doc = "Possible values of the field `PINPOL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PINPOLR {
+    #[doc = "Pin is active high"]
+    _0,
+    #[doc = "Pin is active low"]
+    _1,
+}
+impl PINPOLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            PINPOLR::_0 => false,
+            PINPOLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> PINPOLR {
+        match value {
+            false => PINPOLR::_0,
+            true => PINPOLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == PINPOLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == PINPOLR::_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PINSELR {
+    bits: u8,
+}
+impl PINSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `PINCFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PINCFGR {
+    #[doc = "Shifter pin output disabled"]
+    _0,
+    #[doc = "Shifter pin open drain or bidirectional output enable"]
+    _1,
+    #[doc = "Shifter pin bidirectional output data"]
+    _10,
+    #[doc = "Shifter pin output"]
+    _11,
+}
+impl PINCFGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            PINCFGR::_0 => 0,
+            PINCFGR::_1 => 1,
+            PINCFGR::_10 => 2,
+            PINCFGR::_11 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> PINCFGR {
+        match value {
+            0 => PINCFGR::_0,
+            1 => PINCFGR::_1,
+            2 => PINCFGR::_10,
+            3 => PINCFGR::_11,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == PINCFGR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == PINCFGR::_1
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == PINCFGR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == PINCFGR::_11
+    }
+}
+#[doc = "Possible values of the field `TIMPOL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TIMPOLR {
+    #[doc = "Shift on posedge of Shift clock"]
+    _0,
+    #[doc = "Shift on negedge of Shift clock"]
+    _1,
+}
+impl TIMPOLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TIMPOLR::_0 => false,
+            TIMPOLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TIMPOLR {
+        match value {
+            false => TIMPOLR::_0,
+            true => TIMPOLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TIMPOLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TIMPOLR::_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TIMSELR {
+    bits: u8,
+}
+impl TIMSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Values that can be written to the field `SMOD`"]
+pub enum SMODW {
+    #[doc = "Disabled."]
+    _0,
+    #[doc = "Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer."]
+    _1,
+    #[doc = "Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer."]
+    _10,
+    #[doc = "Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer."]
+    _100,
+    #[doc = "Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents."]
+    _101,
+}
+impl SMODW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            SMODW::_0 => 0,
+            SMODW::_1 => 1,
+            SMODW::_10 => 2,
+            SMODW::_100 => 4,
+            SMODW::_101 => 5,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SMODW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SMODW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SMODW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "Disabled."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(SMODW::_0)
+    }
+    #[doc = "Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(SMODW::_1)
+    }
+    #[doc = "Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer."]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(SMODW::_10)
+    }
+    #[doc = "Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer."]
+    #[inline]
+    pub fn _100(self) -> &'a mut W {
+        self.variant(SMODW::_100)
+    }
+    #[doc = "Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents."]
+    #[inline]
+    pub fn _101(self) -> &'a mut W {
+        self.variant(SMODW::_101)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PINPOL`"]
+pub enum PINPOLW {
+    #[doc = "Pin is active high"]
+    _0,
+    #[doc = "Pin is active low"]
+    _1,
+}
+impl PINPOLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            PINPOLW::_0 => false,
+            PINPOLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PINPOLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PINPOLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PINPOLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Pin is active high"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(PINPOLW::_0)
+    }
+    #[doc = "Pin is active low"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(PINPOLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PINSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PINSELW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PINCFG`"]
+pub enum PINCFGW {
+    #[doc = "Shifter pin output disabled"]
+    _0,
+    #[doc = "Shifter pin open drain or bidirectional output enable"]
+    _1,
+    #[doc = "Shifter pin bidirectional output data"]
+    _10,
+    #[doc = "Shifter pin output"]
+    _11,
+}
+impl PINCFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            PINCFGW::_0 => 0,
+            PINCFGW::_1 => 1,
+            PINCFGW::_10 => 2,
+            PINCFGW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PINCFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PINCFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PINCFGW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Shifter pin output disabled"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(PINCFGW::_0)
+    }
+    #[doc = "Shifter pin open drain or bidirectional output enable"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(PINCFGW::_1)
+    }
+    #[doc = "Shifter pin bidirectional output data"]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(PINCFGW::_10)
+    }
+    #[doc = "Shifter pin output"]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(PINCFGW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 16;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TIMPOL`"]
+pub enum TIMPOLW {
+    #[doc = "Shift on posedge of Shift clock"]
+    _0,
+    #[doc = "Shift on negedge of Shift clock"]
+    _1,
+}
+impl TIMPOLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TIMPOLW::_0 => false,
+            TIMPOLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TIMPOLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TIMPOLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TIMPOLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Shift on posedge of Shift clock"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TIMPOLW::_0)
+    }
+    #[doc = "Shift on negedge of Shift clock"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TIMPOLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 23;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TIMSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TIMSELW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 24;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:2 - Shifter Mode"]
+    #[inline]
+    pub fn smod(&self) -> SMODR {
+        SMODR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 7 - Shifter Pin Polarity"]
+    #[inline]
+    pub fn pinpol(&self) -> PINPOLR {
+        PINPOLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 8:10 - Shifter Pin Select"]
+    #[inline]
+    pub fn pinsel(&self) -> PINSELR {
+        let bits = {
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        PINSELR { bits }
+    }
+    #[doc = "Bits 16:17 - Shifter Pin Configuration"]
+    #[inline]
+    pub fn pincfg(&self) -> PINCFGR {
+        PINCFGR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 23 - Timer Polarity"]
+    #[inline]
+    pub fn timpol(&self) -> TIMPOLR {
+        TIMPOLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 23;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 24:25 - Timer Select"]
+    #[inline]
+    pub fn timsel(&self) -> TIMSELR {
+        let bits = {
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 24;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        TIMSELR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:2 - Shifter Mode"]
+    #[inline]
+    pub fn smod(&mut self) -> _SMODW {
+        _SMODW { w: self }
+    }
+    #[doc = "Bit 7 - Shifter Pin Polarity"]
+    #[inline]
+    pub fn pinpol(&mut self) -> _PINPOLW {
+        _PINPOLW { w: self }
+    }
+    #[doc = "Bits 8:10 - Shifter Pin Select"]
+    #[inline]
+    pub fn pinsel(&mut self) -> _PINSELW {
+        _PINSELW { w: self }
+    }
+    #[doc = "Bits 16:17 - Shifter Pin Configuration"]
+    #[inline]
+    pub fn pincfg(&mut self) -> _PINCFGW {
+        _PINCFGW { w: self }
+    }
+    #[doc = "Bit 23 - Timer Polarity"]
+    #[inline]
+    pub fn timpol(&mut self) -> _TIMPOLW {
+        _TIMPOLW { w: self }
+    }
+    #[doc = "Bits 24:25 - Timer Select"]
+    #[inline]
+    pub fn timsel(&mut self) -> _TIMSELW {
+        _TIMSELW { w: self }
+    }
+}

src/flexio/shiftctl3/mod.rs

@@ -0,0 +1,672 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SHIFTCTL3 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `SMOD`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SMODR {
+    #[doc = "Disabled."]
+    _0,
+    #[doc = "Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer."]
+    _1,
+    #[doc = "Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer."]
+    _10,
+    #[doc = "Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer."]
+    _100,
+    #[doc = "Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents."]
+    _101,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl SMODR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            SMODR::_0 => 0,
+            SMODR::_1 => 1,
+            SMODR::_10 => 2,
+            SMODR::_100 => 4,
+            SMODR::_101 => 5,
+            SMODR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> SMODR {
+        match value {
+            0 => SMODR::_0,
+            1 => SMODR::_1,
+            2 => SMODR::_10,
+            4 => SMODR::_100,
+            5 => SMODR::_101,
+            i => SMODR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == SMODR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == SMODR::_1
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == SMODR::_10
+    }
+    #[doc = "Checks if the value of the field is `_100`"]
+    #[inline]
+    pub fn is_100(&self) -> bool {
+        *self == SMODR::_100
+    }
+    #[doc = "Checks if the value of the field is `_101`"]
+    #[inline]
+    pub fn is_101(&self) -> bool {
+        *self == SMODR::_101
+    }
+}
+#[doc = "Possible values of the field `PINPOL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PINPOLR {
+    #[doc = "Pin is active high"]
+    _0,
+    #[doc = "Pin is active low"]
+    _1,
+}
+impl PINPOLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            PINPOLR::_0 => false,
+            PINPOLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> PINPOLR {
+        match value {
+            false => PINPOLR::_0,
+            true => PINPOLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == PINPOLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == PINPOLR::_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PINSELR {
+    bits: u8,
+}
+impl PINSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `PINCFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PINCFGR {
+    #[doc = "Shifter pin output disabled"]
+    _0,
+    #[doc = "Shifter pin open drain or bidirectional output enable"]
+    _1,
+    #[doc = "Shifter pin bidirectional output data"]
+    _10,
+    #[doc = "Shifter pin output"]
+    _11,
+}
+impl PINCFGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            PINCFGR::_0 => 0,
+            PINCFGR::_1 => 1,
+            PINCFGR::_10 => 2,
+            PINCFGR::_11 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> PINCFGR {
+        match value {
+            0 => PINCFGR::_0,
+            1 => PINCFGR::_1,
+            2 => PINCFGR::_10,
+            3 => PINCFGR::_11,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == PINCFGR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == PINCFGR::_1
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == PINCFGR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == PINCFGR::_11
+    }
+}
+#[doc = "Possible values of the field `TIMPOL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TIMPOLR {
+    #[doc = "Shift on posedge of Shift clock"]
+    _0,
+    #[doc = "Shift on negedge of Shift clock"]
+    _1,
+}
+impl TIMPOLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TIMPOLR::_0 => false,
+            TIMPOLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TIMPOLR {
+        match value {
+            false => TIMPOLR::_0,
+            true => TIMPOLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TIMPOLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TIMPOLR::_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TIMSELR {
+    bits: u8,
+}
+impl TIMSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Values that can be written to the field `SMOD`"]
+pub enum SMODW {
+    #[doc = "Disabled."]
+    _0,
+    #[doc = "Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer."]
+    _1,
+    #[doc = "Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer."]
+    _10,
+    #[doc = "Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer."]
+    _100,
+    #[doc = "Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents."]
+    _101,
+}
+impl SMODW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            SMODW::_0 => 0,
+            SMODW::_1 => 1,
+            SMODW::_10 => 2,
+            SMODW::_100 => 4,
+            SMODW::_101 => 5,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SMODW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SMODW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SMODW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "Disabled."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(SMODW::_0)
+    }
+    #[doc = "Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(SMODW::_1)
+    }
+    #[doc = "Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer."]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(SMODW::_10)
+    }
+    #[doc = "Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer."]
+    #[inline]
+    pub fn _100(self) -> &'a mut W {
+        self.variant(SMODW::_100)
+    }
+    #[doc = "Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents."]
+    #[inline]
+    pub fn _101(self) -> &'a mut W {
+        self.variant(SMODW::_101)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PINPOL`"]
+pub enum PINPOLW {
+    #[doc = "Pin is active high"]
+    _0,
+    #[doc = "Pin is active low"]
+    _1,
+}
+impl PINPOLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            PINPOLW::_0 => false,
+            PINPOLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PINPOLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PINPOLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PINPOLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Pin is active high"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(PINPOLW::_0)
+    }
+    #[doc = "Pin is active low"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(PINPOLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PINSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PINSELW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PINCFG`"]
+pub enum PINCFGW {
+    #[doc = "Shifter pin output disabled"]
+    _0,
+    #[doc = "Shifter pin open drain or bidirectional output enable"]
+    _1,
+    #[doc = "Shifter pin bidirectional output data"]
+    _10,
+    #[doc = "Shifter pin output"]
+    _11,
+}
+impl PINCFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            PINCFGW::_0 => 0,
+            PINCFGW::_1 => 1,
+            PINCFGW::_10 => 2,
+            PINCFGW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PINCFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PINCFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PINCFGW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Shifter pin output disabled"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(PINCFGW::_0)
+    }
+    #[doc = "Shifter pin open drain or bidirectional output enable"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(PINCFGW::_1)
+    }
+    #[doc = "Shifter pin bidirectional output data"]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(PINCFGW::_10)
+    }
+    #[doc = "Shifter pin output"]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(PINCFGW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 16;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TIMPOL`"]
+pub enum TIMPOLW {
+    #[doc = "Shift on posedge of Shift clock"]
+    _0,
+    #[doc = "Shift on negedge of Shift clock"]
+    _1,
+}
+impl TIMPOLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TIMPOLW::_0 => false,
+            TIMPOLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TIMPOLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TIMPOLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TIMPOLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Shift on posedge of Shift clock"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TIMPOLW::_0)
+    }
+    #[doc = "Shift on negedge of Shift clock"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TIMPOLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 23;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TIMSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TIMSELW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 24;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:2 - Shifter Mode"]
+    #[inline]
+    pub fn smod(&self) -> SMODR {
+        SMODR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 7 - Shifter Pin Polarity"]
+    #[inline]
+    pub fn pinpol(&self) -> PINPOLR {
+        PINPOLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 8:10 - Shifter Pin Select"]
+    #[inline]
+    pub fn pinsel(&self) -> PINSELR {
+        let bits = {
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        PINSELR { bits }
+    }
+    #[doc = "Bits 16:17 - Shifter Pin Configuration"]
+    #[inline]
+    pub fn pincfg(&self) -> PINCFGR {
+        PINCFGR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 23 - Timer Polarity"]
+    #[inline]
+    pub fn timpol(&self) -> TIMPOLR {
+        TIMPOLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 23;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 24:25 - Timer Select"]
+    #[inline]
+    pub fn timsel(&self) -> TIMSELR {
+        let bits = {
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 24;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        TIMSELR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:2 - Shifter Mode"]
+    #[inline]
+    pub fn smod(&mut self) -> _SMODW {
+        _SMODW { w: self }
+    }
+    #[doc = "Bit 7 - Shifter Pin Polarity"]
+    #[inline]
+    pub fn pinpol(&mut self) -> _PINPOLW {
+        _PINPOLW { w: self }
+    }
+    #[doc = "Bits 8:10 - Shifter Pin Select"]
+    #[inline]
+    pub fn pinsel(&mut self) -> _PINSELW {
+        _PINSELW { w: self }
+    }
+    #[doc = "Bits 16:17 - Shifter Pin Configuration"]
+    #[inline]
+    pub fn pincfg(&mut self) -> _PINCFGW {
+        _PINCFGW { w: self }
+    }
+    #[doc = "Bit 23 - Timer Polarity"]
+    #[inline]
+    pub fn timpol(&mut self) -> _TIMPOLW {
+        _TIMPOLW { w: self }
+    }
+    #[doc = "Bits 24:25 - Timer Select"]
+    #[inline]
+    pub fn timsel(&mut self) -> _TIMSELW {
+        _TIMSELW { w: self }
+    }
+}

src/flexio/shifteien/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SHIFTEIEN {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SEIER {
+    bits: u8,
+}
+impl SEIER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SEIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SEIEW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:3 - Shifter Error Interrupt Enable"]
+    #[inline]
+    pub fn seie(&self) -> SEIER {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        SEIER { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:3 - Shifter Error Interrupt Enable"]
+    #[inline]
+    pub fn seie(&mut self) -> _SEIEW {
+        _SEIEW { w: self }
+    }
+}

src/flexio/shifterr/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SHIFTERR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SEFR {
+    bits: u8,
+}
+impl SEFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SEFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SEFW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:3 - Shifter Error Flags"]
+    #[inline]
+    pub fn sef(&self) -> SEFR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        SEFR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:3 - Shifter Error Flags"]
+    #[inline]
+    pub fn sef(&mut self) -> _SEFW {
+        _SEFW { w: self }
+    }
+}

src/flexio/shiftsden/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SHIFTSDEN {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SSDER {
+    bits: u8,
+}
+impl SSDER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SSDEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SSDEW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:3 - Shifter Status DMA Enable"]
+    #[inline]
+    pub fn ssde(&self) -> SSDER {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        SSDER { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:3 - Shifter Status DMA Enable"]
+    #[inline]
+    pub fn ssde(&mut self) -> _SSDEW {
+        _SSDEW { w: self }
+    }
+}

src/flexio/shiftsien/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SHIFTSIEN {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SSIER {
+    bits: u8,
+}
+impl SSIER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SSIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SSIEW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:3 - Shifter Status Interrupt Enable"]
+    #[inline]
+    pub fn ssie(&self) -> SSIER {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        SSIER { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:3 - Shifter Status Interrupt Enable"]
+    #[inline]
+    pub fn ssie(&mut self) -> _SSIEW {
+        _SSIEW { w: self }
+    }
+}

src/flexio/shiftstat/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SHIFTSTAT {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SSFR {
+    bits: u8,
+}
+impl SSFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SSFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SSFW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:3 - Shifter Status Flag"]
+    #[inline]
+    pub fn ssf(&self) -> SSFR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        SSFR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:3 - Shifter Status Flag"]
+    #[inline]
+    pub fn ssf(&mut self) -> _SSFW {
+        _SSFW { w: self }
+    }
+}

src/flexio/timcmp0/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::TIMCMP0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CMPR {
+    bits: u16,
+}
+impl CMPR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CMPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CMPW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Timer Compare Value"]
+    #[inline]
+    pub fn cmp(&self) -> CMPR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        CMPR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Timer Compare Value"]
+    #[inline]
+    pub fn cmp(&mut self) -> _CMPW {
+        _CMPW { w: self }
+    }
+}

src/flexio/timcmp1/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::TIMCMP1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CMPR {
+    bits: u16,
+}
+impl CMPR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CMPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CMPW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Timer Compare Value"]
+    #[inline]
+    pub fn cmp(&self) -> CMPR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        CMPR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Timer Compare Value"]
+    #[inline]
+    pub fn cmp(&mut self) -> _CMPW {
+        _CMPW { w: self }
+    }
+}

src/flexio/timcmp2/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::TIMCMP2 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CMPR {
+    bits: u16,
+}
+impl CMPR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CMPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CMPW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Timer Compare Value"]
+    #[inline]
+    pub fn cmp(&self) -> CMPR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        CMPR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Timer Compare Value"]
+    #[inline]
+    pub fn cmp(&mut self) -> _CMPW {
+        _CMPW { w: self }
+    }
+}

src/flexio/timcmp3/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::TIMCMP3 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CMPR {
+    bits: u16,
+}
+impl CMPR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CMPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CMPW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Timer Compare Value"]
+    #[inline]
+    pub fn cmp(&self) -> CMPR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        CMPR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Timer Compare Value"]
+    #[inline]
+    pub fn cmp(&mut self) -> _CMPW {
+        _CMPW { w: self }
+    }
+}

src/flexio/timctl0/mod.rs

@@ -0,0 +1,773 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::TIMCTL0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `TIMOD`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TIMODR {
+    #[doc = "Timer Disabled."]
+    _0,
+    #[doc = "Dual 8-bit counters baud/bit mode."]
+    _1,
+    #[doc = "Dual 8-bit counters PWM mode."]
+    _10,
+    #[doc = "Single 16-bit counter mode."]
+    _11,
+}
+impl TIMODR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            TIMODR::_0 => 0,
+            TIMODR::_1 => 1,
+            TIMODR::_10 => 2,
+            TIMODR::_11 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> TIMODR {
+        match value {
+            0 => TIMODR::_0,
+            1 => TIMODR::_1,
+            2 => TIMODR::_10,
+            3 => TIMODR::_11,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TIMODR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TIMODR::_1
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == TIMODR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == TIMODR::_11
+    }
+}
+#[doc = "Possible values of the field `PINPOL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PINPOLR {
+    #[doc = "Pin is active high"]
+    _0,
+    #[doc = "Pin is active low"]
+    _1,
+}
+impl PINPOLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            PINPOLR::_0 => false,
+            PINPOLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> PINPOLR {
+        match value {
+            false => PINPOLR::_0,
+            true => PINPOLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == PINPOLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == PINPOLR::_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PINSELR {
+    bits: u8,
+}
+impl PINSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `PINCFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PINCFGR {
+    #[doc = "Timer pin output disabled"]
+    _0,
+    #[doc = "Timer pin open drain or bidirectional output enable"]
+    _1,
+    #[doc = "Timer pin bidirectional output data"]
+    _10,
+    #[doc = "Timer pin output"]
+    _11,
+}
+impl PINCFGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            PINCFGR::_0 => 0,
+            PINCFGR::_1 => 1,
+            PINCFGR::_10 => 2,
+            PINCFGR::_11 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> PINCFGR {
+        match value {
+            0 => PINCFGR::_0,
+            1 => PINCFGR::_1,
+            2 => PINCFGR::_10,
+            3 => PINCFGR::_11,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == PINCFGR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == PINCFGR::_1
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == PINCFGR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == PINCFGR::_11
+    }
+}
+#[doc = "Possible values of the field `TRGSRC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TRGSRCR {
+    #[doc = "External trigger selected"]
+    _0,
+    #[doc = "Internal trigger selected"]
+    _1,
+}
+impl TRGSRCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TRGSRCR::_0 => false,
+            TRGSRCR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TRGSRCR {
+        match value {
+            false => TRGSRCR::_0,
+            true => TRGSRCR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TRGSRCR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TRGSRCR::_1
+    }
+}
+#[doc = "Possible values of the field `TRGPOL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TRGPOLR {
+    #[doc = "Trigger active high"]
+    _0,
+    #[doc = "Trigger active low"]
+    _1,
+}
+impl TRGPOLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TRGPOLR::_0 => false,
+            TRGPOLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TRGPOLR {
+        match value {
+            false => TRGPOLR::_0,
+            true => TRGPOLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TRGPOLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TRGPOLR::_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TRGSELR {
+    bits: u8,
+}
+impl TRGSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Values that can be written to the field `TIMOD`"]
+pub enum TIMODW {
+    #[doc = "Timer Disabled."]
+    _0,
+    #[doc = "Dual 8-bit counters baud/bit mode."]
+    _1,
+    #[doc = "Dual 8-bit counters PWM mode."]
+    _10,
+    #[doc = "Single 16-bit counter mode."]
+    _11,
+}
+impl TIMODW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            TIMODW::_0 => 0,
+            TIMODW::_1 => 1,
+            TIMODW::_10 => 2,
+            TIMODW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TIMODW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TIMODW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TIMODW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Timer Disabled."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TIMODW::_0)
+    }
+    #[doc = "Dual 8-bit counters baud/bit mode."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TIMODW::_1)
+    }
+    #[doc = "Dual 8-bit counters PWM mode."]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(TIMODW::_10)
+    }
+    #[doc = "Single 16-bit counter mode."]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(TIMODW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PINPOL`"]
+pub enum PINPOLW {
+    #[doc = "Pin is active high"]
+    _0,
+    #[doc = "Pin is active low"]
+    _1,
+}
+impl PINPOLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            PINPOLW::_0 => false,
+            PINPOLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PINPOLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PINPOLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PINPOLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Pin is active high"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(PINPOLW::_0)
+    }
+    #[doc = "Pin is active low"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(PINPOLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PINSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PINSELW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PINCFG`"]
+pub enum PINCFGW {
+    #[doc = "Timer pin output disabled"]
+    _0,
+    #[doc = "Timer pin open drain or bidirectional output enable"]
+    _1,
+    #[doc = "Timer pin bidirectional output data"]
+    _10,
+    #[doc = "Timer pin output"]
+    _11,
+}
+impl PINCFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            PINCFGW::_0 => 0,
+            PINCFGW::_1 => 1,
+            PINCFGW::_10 => 2,
+            PINCFGW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PINCFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PINCFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PINCFGW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Timer pin output disabled"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(PINCFGW::_0)
+    }
+    #[doc = "Timer pin open drain or bidirectional output enable"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(PINCFGW::_1)
+    }
+    #[doc = "Timer pin bidirectional output data"]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(PINCFGW::_10)
+    }
+    #[doc = "Timer pin output"]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(PINCFGW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 16;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TRGSRC`"]
+pub enum TRGSRCW {
+    #[doc = "External trigger selected"]
+    _0,
+    #[doc = "Internal trigger selected"]
+    _1,
+}
+impl TRGSRCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TRGSRCW::_0 => false,
+            TRGSRCW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TRGSRCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TRGSRCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TRGSRCW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "External trigger selected"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TRGSRCW::_0)
+    }
+    #[doc = "Internal trigger selected"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TRGSRCW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 22;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TRGPOL`"]
+pub enum TRGPOLW {
+    #[doc = "Trigger active high"]
+    _0,
+    #[doc = "Trigger active low"]
+    _1,
+}
+impl TRGPOLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TRGPOLW::_0 => false,
+            TRGPOLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TRGPOLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TRGPOLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TRGPOLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Trigger active high"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TRGPOLW::_0)
+    }
+    #[doc = "Trigger active low"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TRGPOLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 23;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TRGSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TRGSELW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 24;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:1 - Timer Mode"]
+    #[inline]
+    pub fn timod(&self) -> TIMODR {
+        TIMODR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 7 - Timer Pin Polarity"]
+    #[inline]
+    pub fn pinpol(&self) -> PINPOLR {
+        PINPOLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 8:10 - Timer Pin Select"]
+    #[inline]
+    pub fn pinsel(&self) -> PINSELR {
+        let bits = {
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        PINSELR { bits }
+    }
+    #[doc = "Bits 16:17 - Timer Pin Configuration"]
+    #[inline]
+    pub fn pincfg(&self) -> PINCFGR {
+        PINCFGR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 22 - Trigger Source"]
+    #[inline]
+    pub fn trgsrc(&self) -> TRGSRCR {
+        TRGSRCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 22;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 23 - Trigger Polarity"]
+    #[inline]
+    pub fn trgpol(&self) -> TRGPOLR {
+        TRGPOLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 23;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 24:27 - Trigger Select"]
+    #[inline]
+    pub fn trgsel(&self) -> TRGSELR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 24;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        TRGSELR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:1 - Timer Mode"]
+    #[inline]
+    pub fn timod(&mut self) -> _TIMODW {
+        _TIMODW { w: self }
+    }
+    #[doc = "Bit 7 - Timer Pin Polarity"]
+    #[inline]
+    pub fn pinpol(&mut self) -> _PINPOLW {
+        _PINPOLW { w: self }
+    }
+    #[doc = "Bits 8:10 - Timer Pin Select"]
+    #[inline]
+    pub fn pinsel(&mut self) -> _PINSELW {
+        _PINSELW { w: self }
+    }
+    #[doc = "Bits 16:17 - Timer Pin Configuration"]
+    #[inline]
+    pub fn pincfg(&mut self) -> _PINCFGW {
+        _PINCFGW { w: self }
+    }
+    #[doc = "Bit 22 - Trigger Source"]
+    #[inline]
+    pub fn trgsrc(&mut self) -> _TRGSRCW {
+        _TRGSRCW { w: self }
+    }
+    #[doc = "Bit 23 - Trigger Polarity"]
+    #[inline]
+    pub fn trgpol(&mut self) -> _TRGPOLW {
+        _TRGPOLW { w: self }
+    }
+    #[doc = "Bits 24:27 - Trigger Select"]
+    #[inline]
+    pub fn trgsel(&mut self) -> _TRGSELW {
+        _TRGSELW { w: self }
+    }
+}

src/flexio/timctl1/mod.rs

@@ -0,0 +1,773 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::TIMCTL1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `TIMOD`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TIMODR {
+    #[doc = "Timer Disabled."]
+    _0,
+    #[doc = "Dual 8-bit counters baud/bit mode."]
+    _1,
+    #[doc = "Dual 8-bit counters PWM mode."]
+    _10,
+    #[doc = "Single 16-bit counter mode."]
+    _11,
+}
+impl TIMODR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            TIMODR::_0 => 0,
+            TIMODR::_1 => 1,
+            TIMODR::_10 => 2,
+            TIMODR::_11 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> TIMODR {
+        match value {
+            0 => TIMODR::_0,
+            1 => TIMODR::_1,
+            2 => TIMODR::_10,
+            3 => TIMODR::_11,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TIMODR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TIMODR::_1
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == TIMODR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == TIMODR::_11
+    }
+}
+#[doc = "Possible values of the field `PINPOL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PINPOLR {
+    #[doc = "Pin is active high"]
+    _0,
+    #[doc = "Pin is active low"]
+    _1,
+}
+impl PINPOLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            PINPOLR::_0 => false,
+            PINPOLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> PINPOLR {
+        match value {
+            false => PINPOLR::_0,
+            true => PINPOLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == PINPOLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == PINPOLR::_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PINSELR {
+    bits: u8,
+}
+impl PINSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `PINCFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PINCFGR {
+    #[doc = "Timer pin output disabled"]
+    _0,
+    #[doc = "Timer pin open drain or bidirectional output enable"]
+    _1,
+    #[doc = "Timer pin bidirectional output data"]
+    _10,
+    #[doc = "Timer pin output"]
+    _11,
+}
+impl PINCFGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            PINCFGR::_0 => 0,
+            PINCFGR::_1 => 1,
+            PINCFGR::_10 => 2,
+            PINCFGR::_11 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> PINCFGR {
+        match value {
+            0 => PINCFGR::_0,
+            1 => PINCFGR::_1,
+            2 => PINCFGR::_10,
+            3 => PINCFGR::_11,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == PINCFGR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == PINCFGR::_1
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == PINCFGR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == PINCFGR::_11
+    }
+}
+#[doc = "Possible values of the field `TRGSRC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TRGSRCR {
+    #[doc = "External trigger selected"]
+    _0,
+    #[doc = "Internal trigger selected"]
+    _1,
+}
+impl TRGSRCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TRGSRCR::_0 => false,
+            TRGSRCR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TRGSRCR {
+        match value {
+            false => TRGSRCR::_0,
+            true => TRGSRCR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TRGSRCR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TRGSRCR::_1
+    }
+}
+#[doc = "Possible values of the field `TRGPOL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TRGPOLR {
+    #[doc = "Trigger active high"]
+    _0,
+    #[doc = "Trigger active low"]
+    _1,
+}
+impl TRGPOLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TRGPOLR::_0 => false,
+            TRGPOLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TRGPOLR {
+        match value {
+            false => TRGPOLR::_0,
+            true => TRGPOLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TRGPOLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TRGPOLR::_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TRGSELR {
+    bits: u8,
+}
+impl TRGSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Values that can be written to the field `TIMOD`"]
+pub enum TIMODW {
+    #[doc = "Timer Disabled."]
+    _0,
+    #[doc = "Dual 8-bit counters baud/bit mode."]
+    _1,
+    #[doc = "Dual 8-bit counters PWM mode."]
+    _10,
+    #[doc = "Single 16-bit counter mode."]
+    _11,
+}
+impl TIMODW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            TIMODW::_0 => 0,
+            TIMODW::_1 => 1,
+            TIMODW::_10 => 2,
+            TIMODW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TIMODW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TIMODW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TIMODW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Timer Disabled."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TIMODW::_0)
+    }
+    #[doc = "Dual 8-bit counters baud/bit mode."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TIMODW::_1)
+    }
+    #[doc = "Dual 8-bit counters PWM mode."]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(TIMODW::_10)
+    }
+    #[doc = "Single 16-bit counter mode."]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(TIMODW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PINPOL`"]
+pub enum PINPOLW {
+    #[doc = "Pin is active high"]
+    _0,
+    #[doc = "Pin is active low"]
+    _1,
+}
+impl PINPOLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            PINPOLW::_0 => false,
+            PINPOLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PINPOLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PINPOLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PINPOLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Pin is active high"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(PINPOLW::_0)
+    }
+    #[doc = "Pin is active low"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(PINPOLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PINSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PINSELW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PINCFG`"]
+pub enum PINCFGW {
+    #[doc = "Timer pin output disabled"]
+    _0,
+    #[doc = "Timer pin open drain or bidirectional output enable"]
+    _1,
+    #[doc = "Timer pin bidirectional output data"]
+    _10,
+    #[doc = "Timer pin output"]
+    _11,
+}
+impl PINCFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            PINCFGW::_0 => 0,
+            PINCFGW::_1 => 1,
+            PINCFGW::_10 => 2,
+            PINCFGW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PINCFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PINCFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PINCFGW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Timer pin output disabled"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(PINCFGW::_0)
+    }
+    #[doc = "Timer pin open drain or bidirectional output enable"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(PINCFGW::_1)
+    }
+    #[doc = "Timer pin bidirectional output data"]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(PINCFGW::_10)
+    }
+    #[doc = "Timer pin output"]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(PINCFGW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 16;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TRGSRC`"]
+pub enum TRGSRCW {
+    #[doc = "External trigger selected"]
+    _0,
+    #[doc = "Internal trigger selected"]
+    _1,
+}
+impl TRGSRCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TRGSRCW::_0 => false,
+            TRGSRCW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TRGSRCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TRGSRCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TRGSRCW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "External trigger selected"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TRGSRCW::_0)
+    }
+    #[doc = "Internal trigger selected"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TRGSRCW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 22;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TRGPOL`"]
+pub enum TRGPOLW {
+    #[doc = "Trigger active high"]
+    _0,
+    #[doc = "Trigger active low"]
+    _1,
+}
+impl TRGPOLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TRGPOLW::_0 => false,
+            TRGPOLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TRGPOLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TRGPOLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TRGPOLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Trigger active high"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TRGPOLW::_0)
+    }
+    #[doc = "Trigger active low"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TRGPOLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 23;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TRGSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TRGSELW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 24;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:1 - Timer Mode"]
+    #[inline]
+    pub fn timod(&self) -> TIMODR {
+        TIMODR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 7 - Timer Pin Polarity"]
+    #[inline]
+    pub fn pinpol(&self) -> PINPOLR {
+        PINPOLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 8:10 - Timer Pin Select"]
+    #[inline]
+    pub fn pinsel(&self) -> PINSELR {
+        let bits = {
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        PINSELR { bits }
+    }
+    #[doc = "Bits 16:17 - Timer Pin Configuration"]
+    #[inline]
+    pub fn pincfg(&self) -> PINCFGR {
+        PINCFGR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 22 - Trigger Source"]
+    #[inline]
+    pub fn trgsrc(&self) -> TRGSRCR {
+        TRGSRCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 22;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 23 - Trigger Polarity"]
+    #[inline]
+    pub fn trgpol(&self) -> TRGPOLR {
+        TRGPOLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 23;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 24:27 - Trigger Select"]
+    #[inline]
+    pub fn trgsel(&self) -> TRGSELR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 24;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        TRGSELR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:1 - Timer Mode"]
+    #[inline]
+    pub fn timod(&mut self) -> _TIMODW {
+        _TIMODW { w: self }
+    }
+    #[doc = "Bit 7 - Timer Pin Polarity"]
+    #[inline]
+    pub fn pinpol(&mut self) -> _PINPOLW {
+        _PINPOLW { w: self }
+    }
+    #[doc = "Bits 8:10 - Timer Pin Select"]
+    #[inline]
+    pub fn pinsel(&mut self) -> _PINSELW {
+        _PINSELW { w: self }
+    }
+    #[doc = "Bits 16:17 - Timer Pin Configuration"]
+    #[inline]
+    pub fn pincfg(&mut self) -> _PINCFGW {
+        _PINCFGW { w: self }
+    }
+    #[doc = "Bit 22 - Trigger Source"]
+    #[inline]
+    pub fn trgsrc(&mut self) -> _TRGSRCW {
+        _TRGSRCW { w: self }
+    }
+    #[doc = "Bit 23 - Trigger Polarity"]
+    #[inline]
+    pub fn trgpol(&mut self) -> _TRGPOLW {
+        _TRGPOLW { w: self }
+    }
+    #[doc = "Bits 24:27 - Trigger Select"]
+    #[inline]
+    pub fn trgsel(&mut self) -> _TRGSELW {
+        _TRGSELW { w: self }
+    }
+}

src/flexio/timctl2/mod.rs

@@ -0,0 +1,773 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::TIMCTL2 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `TIMOD`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TIMODR {
+    #[doc = "Timer Disabled."]
+    _0,
+    #[doc = "Dual 8-bit counters baud/bit mode."]
+    _1,
+    #[doc = "Dual 8-bit counters PWM mode."]
+    _10,
+    #[doc = "Single 16-bit counter mode."]
+    _11,
+}
+impl TIMODR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            TIMODR::_0 => 0,
+            TIMODR::_1 => 1,
+            TIMODR::_10 => 2,
+            TIMODR::_11 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> TIMODR {
+        match value {
+            0 => TIMODR::_0,
+            1 => TIMODR::_1,
+            2 => TIMODR::_10,
+            3 => TIMODR::_11,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TIMODR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TIMODR::_1
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == TIMODR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == TIMODR::_11
+    }
+}
+#[doc = "Possible values of the field `PINPOL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PINPOLR {
+    #[doc = "Pin is active high"]
+    _0,
+    #[doc = "Pin is active low"]
+    _1,
+}
+impl PINPOLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            PINPOLR::_0 => false,
+            PINPOLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> PINPOLR {
+        match value {
+            false => PINPOLR::_0,
+            true => PINPOLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == PINPOLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == PINPOLR::_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PINSELR {
+    bits: u8,
+}
+impl PINSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `PINCFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PINCFGR {
+    #[doc = "Timer pin output disabled"]
+    _0,
+    #[doc = "Timer pin open drain or bidirectional output enable"]
+    _1,
+    #[doc = "Timer pin bidirectional output data"]
+    _10,
+    #[doc = "Timer pin output"]
+    _11,
+}
+impl PINCFGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            PINCFGR::_0 => 0,
+            PINCFGR::_1 => 1,
+            PINCFGR::_10 => 2,
+            PINCFGR::_11 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> PINCFGR {
+        match value {
+            0 => PINCFGR::_0,
+            1 => PINCFGR::_1,
+            2 => PINCFGR::_10,
+            3 => PINCFGR::_11,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == PINCFGR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == PINCFGR::_1
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == PINCFGR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == PINCFGR::_11
+    }
+}
+#[doc = "Possible values of the field `TRGSRC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TRGSRCR {
+    #[doc = "External trigger selected"]
+    _0,
+    #[doc = "Internal trigger selected"]
+    _1,
+}
+impl TRGSRCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TRGSRCR::_0 => false,
+            TRGSRCR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TRGSRCR {
+        match value {
+            false => TRGSRCR::_0,
+            true => TRGSRCR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TRGSRCR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TRGSRCR::_1
+    }
+}
+#[doc = "Possible values of the field `TRGPOL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TRGPOLR {
+    #[doc = "Trigger active high"]
+    _0,
+    #[doc = "Trigger active low"]
+    _1,
+}
+impl TRGPOLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TRGPOLR::_0 => false,
+            TRGPOLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TRGPOLR {
+        match value {
+            false => TRGPOLR::_0,
+            true => TRGPOLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TRGPOLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TRGPOLR::_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TRGSELR {
+    bits: u8,
+}
+impl TRGSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Values that can be written to the field `TIMOD`"]
+pub enum TIMODW {
+    #[doc = "Timer Disabled."]
+    _0,
+    #[doc = "Dual 8-bit counters baud/bit mode."]
+    _1,
+    #[doc = "Dual 8-bit counters PWM mode."]
+    _10,
+    #[doc = "Single 16-bit counter mode."]
+    _11,
+}
+impl TIMODW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            TIMODW::_0 => 0,
+            TIMODW::_1 => 1,
+            TIMODW::_10 => 2,
+            TIMODW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TIMODW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TIMODW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TIMODW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Timer Disabled."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TIMODW::_0)
+    }
+    #[doc = "Dual 8-bit counters baud/bit mode."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TIMODW::_1)
+    }
+    #[doc = "Dual 8-bit counters PWM mode."]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(TIMODW::_10)
+    }
+    #[doc = "Single 16-bit counter mode."]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(TIMODW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PINPOL`"]
+pub enum PINPOLW {
+    #[doc = "Pin is active high"]
+    _0,
+    #[doc = "Pin is active low"]
+    _1,
+}
+impl PINPOLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            PINPOLW::_0 => false,
+            PINPOLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PINPOLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PINPOLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PINPOLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Pin is active high"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(PINPOLW::_0)
+    }
+    #[doc = "Pin is active low"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(PINPOLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PINSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PINSELW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PINCFG`"]
+pub enum PINCFGW {
+    #[doc = "Timer pin output disabled"]
+    _0,
+    #[doc = "Timer pin open drain or bidirectional output enable"]
+    _1,
+    #[doc = "Timer pin bidirectional output data"]
+    _10,
+    #[doc = "Timer pin output"]
+    _11,
+}
+impl PINCFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            PINCFGW::_0 => 0,
+            PINCFGW::_1 => 1,
+            PINCFGW::_10 => 2,
+            PINCFGW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PINCFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PINCFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PINCFGW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Timer pin output disabled"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(PINCFGW::_0)
+    }
+    #[doc = "Timer pin open drain or bidirectional output enable"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(PINCFGW::_1)
+    }
+    #[doc = "Timer pin bidirectional output data"]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(PINCFGW::_10)
+    }
+    #[doc = "Timer pin output"]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(PINCFGW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 16;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TRGSRC`"]
+pub enum TRGSRCW {
+    #[doc = "External trigger selected"]
+    _0,
+    #[doc = "Internal trigger selected"]
+    _1,
+}
+impl TRGSRCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TRGSRCW::_0 => false,
+            TRGSRCW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TRGSRCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TRGSRCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TRGSRCW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "External trigger selected"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TRGSRCW::_0)
+    }
+    #[doc = "Internal trigger selected"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TRGSRCW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 22;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TRGPOL`"]
+pub enum TRGPOLW {
+    #[doc = "Trigger active high"]
+    _0,
+    #[doc = "Trigger active low"]
+    _1,
+}
+impl TRGPOLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TRGPOLW::_0 => false,
+            TRGPOLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TRGPOLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TRGPOLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TRGPOLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Trigger active high"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TRGPOLW::_0)
+    }
+    #[doc = "Trigger active low"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TRGPOLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 23;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TRGSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TRGSELW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 24;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:1 - Timer Mode"]
+    #[inline]
+    pub fn timod(&self) -> TIMODR {
+        TIMODR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 7 - Timer Pin Polarity"]
+    #[inline]
+    pub fn pinpol(&self) -> PINPOLR {
+        PINPOLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 8:10 - Timer Pin Select"]
+    #[inline]
+    pub fn pinsel(&self) -> PINSELR {
+        let bits = {
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        PINSELR { bits }
+    }
+    #[doc = "Bits 16:17 - Timer Pin Configuration"]
+    #[inline]
+    pub fn pincfg(&self) -> PINCFGR {
+        PINCFGR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 22 - Trigger Source"]
+    #[inline]
+    pub fn trgsrc(&self) -> TRGSRCR {
+        TRGSRCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 22;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 23 - Trigger Polarity"]
+    #[inline]
+    pub fn trgpol(&self) -> TRGPOLR {
+        TRGPOLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 23;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 24:27 - Trigger Select"]
+    #[inline]
+    pub fn trgsel(&self) -> TRGSELR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 24;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        TRGSELR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:1 - Timer Mode"]
+    #[inline]
+    pub fn timod(&mut self) -> _TIMODW {
+        _TIMODW { w: self }
+    }
+    #[doc = "Bit 7 - Timer Pin Polarity"]
+    #[inline]
+    pub fn pinpol(&mut self) -> _PINPOLW {
+        _PINPOLW { w: self }
+    }
+    #[doc = "Bits 8:10 - Timer Pin Select"]
+    #[inline]
+    pub fn pinsel(&mut self) -> _PINSELW {
+        _PINSELW { w: self }
+    }
+    #[doc = "Bits 16:17 - Timer Pin Configuration"]
+    #[inline]
+    pub fn pincfg(&mut self) -> _PINCFGW {
+        _PINCFGW { w: self }
+    }
+    #[doc = "Bit 22 - Trigger Source"]
+    #[inline]
+    pub fn trgsrc(&mut self) -> _TRGSRCW {
+        _TRGSRCW { w: self }
+    }
+    #[doc = "Bit 23 - Trigger Polarity"]
+    #[inline]
+    pub fn trgpol(&mut self) -> _TRGPOLW {
+        _TRGPOLW { w: self }
+    }
+    #[doc = "Bits 24:27 - Trigger Select"]
+    #[inline]
+    pub fn trgsel(&mut self) -> _TRGSELW {
+        _TRGSELW { w: self }
+    }
+}

src/flexio/timctl3/mod.rs

@@ -0,0 +1,773 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::TIMCTL3 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `TIMOD`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TIMODR {
+    #[doc = "Timer Disabled."]
+    _0,
+    #[doc = "Dual 8-bit counters baud/bit mode."]
+    _1,
+    #[doc = "Dual 8-bit counters PWM mode."]
+    _10,
+    #[doc = "Single 16-bit counter mode."]
+    _11,
+}
+impl TIMODR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            TIMODR::_0 => 0,
+            TIMODR::_1 => 1,
+            TIMODR::_10 => 2,
+            TIMODR::_11 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> TIMODR {
+        match value {
+            0 => TIMODR::_0,
+            1 => TIMODR::_1,
+            2 => TIMODR::_10,
+            3 => TIMODR::_11,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TIMODR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TIMODR::_1
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == TIMODR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == TIMODR::_11
+    }
+}
+#[doc = "Possible values of the field `PINPOL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PINPOLR {
+    #[doc = "Pin is active high"]
+    _0,
+    #[doc = "Pin is active low"]
+    _1,
+}
+impl PINPOLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            PINPOLR::_0 => false,
+            PINPOLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> PINPOLR {
+        match value {
+            false => PINPOLR::_0,
+            true => PINPOLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == PINPOLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == PINPOLR::_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct PINSELR {
+    bits: u8,
+}
+impl PINSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `PINCFG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PINCFGR {
+    #[doc = "Timer pin output disabled"]
+    _0,
+    #[doc = "Timer pin open drain or bidirectional output enable"]
+    _1,
+    #[doc = "Timer pin bidirectional output data"]
+    _10,
+    #[doc = "Timer pin output"]
+    _11,
+}
+impl PINCFGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            PINCFGR::_0 => 0,
+            PINCFGR::_1 => 1,
+            PINCFGR::_10 => 2,
+            PINCFGR::_11 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> PINCFGR {
+        match value {
+            0 => PINCFGR::_0,
+            1 => PINCFGR::_1,
+            2 => PINCFGR::_10,
+            3 => PINCFGR::_11,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == PINCFGR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == PINCFGR::_1
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == PINCFGR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == PINCFGR::_11
+    }
+}
+#[doc = "Possible values of the field `TRGSRC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TRGSRCR {
+    #[doc = "External trigger selected"]
+    _0,
+    #[doc = "Internal trigger selected"]
+    _1,
+}
+impl TRGSRCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TRGSRCR::_0 => false,
+            TRGSRCR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TRGSRCR {
+        match value {
+            false => TRGSRCR::_0,
+            true => TRGSRCR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TRGSRCR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TRGSRCR::_1
+    }
+}
+#[doc = "Possible values of the field `TRGPOL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TRGPOLR {
+    #[doc = "Trigger active high"]
+    _0,
+    #[doc = "Trigger active low"]
+    _1,
+}
+impl TRGPOLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TRGPOLR::_0 => false,
+            TRGPOLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TRGPOLR {
+        match value {
+            false => TRGPOLR::_0,
+            true => TRGPOLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TRGPOLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TRGPOLR::_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TRGSELR {
+    bits: u8,
+}
+impl TRGSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Values that can be written to the field `TIMOD`"]
+pub enum TIMODW {
+    #[doc = "Timer Disabled."]
+    _0,
+    #[doc = "Dual 8-bit counters baud/bit mode."]
+    _1,
+    #[doc = "Dual 8-bit counters PWM mode."]
+    _10,
+    #[doc = "Single 16-bit counter mode."]
+    _11,
+}
+impl TIMODW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            TIMODW::_0 => 0,
+            TIMODW::_1 => 1,
+            TIMODW::_10 => 2,
+            TIMODW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TIMODW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TIMODW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TIMODW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Timer Disabled."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TIMODW::_0)
+    }
+    #[doc = "Dual 8-bit counters baud/bit mode."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TIMODW::_1)
+    }
+    #[doc = "Dual 8-bit counters PWM mode."]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(TIMODW::_10)
+    }
+    #[doc = "Single 16-bit counter mode."]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(TIMODW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PINPOL`"]
+pub enum PINPOLW {
+    #[doc = "Pin is active high"]
+    _0,
+    #[doc = "Pin is active low"]
+    _1,
+}
+impl PINPOLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            PINPOLW::_0 => false,
+            PINPOLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PINPOLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PINPOLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PINPOLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Pin is active high"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(PINPOLW::_0)
+    }
+    #[doc = "Pin is active low"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(PINPOLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PINSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PINSELW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PINCFG`"]
+pub enum PINCFGW {
+    #[doc = "Timer pin output disabled"]
+    _0,
+    #[doc = "Timer pin open drain or bidirectional output enable"]
+    _1,
+    #[doc = "Timer pin bidirectional output data"]
+    _10,
+    #[doc = "Timer pin output"]
+    _11,
+}
+impl PINCFGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            PINCFGW::_0 => 0,
+            PINCFGW::_1 => 1,
+            PINCFGW::_10 => 2,
+            PINCFGW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PINCFGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PINCFGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PINCFGW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Timer pin output disabled"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(PINCFGW::_0)
+    }
+    #[doc = "Timer pin open drain or bidirectional output enable"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(PINCFGW::_1)
+    }
+    #[doc = "Timer pin bidirectional output data"]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(PINCFGW::_10)
+    }
+    #[doc = "Timer pin output"]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(PINCFGW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 16;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TRGSRC`"]
+pub enum TRGSRCW {
+    #[doc = "External trigger selected"]
+    _0,
+    #[doc = "Internal trigger selected"]
+    _1,
+}
+impl TRGSRCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TRGSRCW::_0 => false,
+            TRGSRCW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TRGSRCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TRGSRCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TRGSRCW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "External trigger selected"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TRGSRCW::_0)
+    }
+    #[doc = "Internal trigger selected"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TRGSRCW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 22;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TRGPOL`"]
+pub enum TRGPOLW {
+    #[doc = "Trigger active high"]
+    _0,
+    #[doc = "Trigger active low"]
+    _1,
+}
+impl TRGPOLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TRGPOLW::_0 => false,
+            TRGPOLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TRGPOLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TRGPOLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TRGPOLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Trigger active high"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TRGPOLW::_0)
+    }
+    #[doc = "Trigger active low"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TRGPOLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 23;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TRGSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TRGSELW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 24;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:1 - Timer Mode"]
+    #[inline]
+    pub fn timod(&self) -> TIMODR {
+        TIMODR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 7 - Timer Pin Polarity"]
+    #[inline]
+    pub fn pinpol(&self) -> PINPOLR {
+        PINPOLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 8:10 - Timer Pin Select"]
+    #[inline]
+    pub fn pinsel(&self) -> PINSELR {
+        let bits = {
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        PINSELR { bits }
+    }
+    #[doc = "Bits 16:17 - Timer Pin Configuration"]
+    #[inline]
+    pub fn pincfg(&self) -> PINCFGR {
+        PINCFGR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 22 - Trigger Source"]
+    #[inline]
+    pub fn trgsrc(&self) -> TRGSRCR {
+        TRGSRCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 22;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 23 - Trigger Polarity"]
+    #[inline]
+    pub fn trgpol(&self) -> TRGPOLR {
+        TRGPOLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 23;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 24:27 - Trigger Select"]
+    #[inline]
+    pub fn trgsel(&self) -> TRGSELR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 24;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        TRGSELR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:1 - Timer Mode"]
+    #[inline]
+    pub fn timod(&mut self) -> _TIMODW {
+        _TIMODW { w: self }
+    }
+    #[doc = "Bit 7 - Timer Pin Polarity"]
+    #[inline]
+    pub fn pinpol(&mut self) -> _PINPOLW {
+        _PINPOLW { w: self }
+    }
+    #[doc = "Bits 8:10 - Timer Pin Select"]
+    #[inline]
+    pub fn pinsel(&mut self) -> _PINSELW {
+        _PINSELW { w: self }
+    }
+    #[doc = "Bits 16:17 - Timer Pin Configuration"]
+    #[inline]
+    pub fn pincfg(&mut self) -> _PINCFGW {
+        _PINCFGW { w: self }
+    }
+    #[doc = "Bit 22 - Trigger Source"]
+    #[inline]
+    pub fn trgsrc(&mut self) -> _TRGSRCW {
+        _TRGSRCW { w: self }
+    }
+    #[doc = "Bit 23 - Trigger Polarity"]
+    #[inline]
+    pub fn trgpol(&mut self) -> _TRGPOLW {
+        _TRGPOLW { w: self }
+    }
+    #[doc = "Bits 24:27 - Trigger Select"]
+    #[inline]
+    pub fn trgsel(&mut self) -> _TRGSELW {
+        _TRGSELW { w: self }
+    }
+}

src/flexio/timien/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::TIMIEN {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TEIER {
+    bits: u8,
+}
+impl TEIER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TEIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TEIEW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:3 - Timer Status Interrupt Enable"]
+    #[inline]
+    pub fn teie(&self) -> TEIER {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        TEIER { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:3 - Timer Status Interrupt Enable"]
+    #[inline]
+    pub fn teie(&mut self) -> _TEIEW {
+        _TEIEW { w: self }
+    }
+}

src/flexio/timstat/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::TIMSTAT {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TSFR {
+    bits: u8,
+}
+impl TSFR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TSFW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TSFW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:3 - Timer Status Flags"]
+    #[inline]
+    pub fn tsf(&self) -> TSFR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        TSFR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:3 - Timer Status Flags"]
+    #[inline]
+    pub fn tsf(&mut self) -> _TSFW {
+        _TSFW { w: self }
+    }
+}

src/flexio/verid/mod.rs

@@ -0,0 +1,110 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::VERID {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+}
+#[doc = "Possible values of the field `FEATURE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FEATURER {
+    #[doc = "Standard features implemented."]
+    _0000000000000000,
+    #[doc = "Supports state, logic and parallel modes."]
+    _0000000000000001,
+    #[doc = r" Reserved"]
+    _Reserved(u16),
+}
+impl FEATURER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        match *self {
+            FEATURER::_0000000000000000 => 0,
+            FEATURER::_0000000000000001 => 1,
+            FEATURER::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u16) -> FEATURER {
+        match value {
+            0 => FEATURER::_0000000000000000,
+            1 => FEATURER::_0000000000000001,
+            i => FEATURER::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0000000000000000`"]
+    #[inline]
+    pub fn is_0000000000000000(&self) -> bool {
+        *self == FEATURER::_0000000000000000
+    }
+    #[doc = "Checks if the value of the field is `_0000000000000001`"]
+    #[inline]
+    pub fn is_0000000000000001(&self) -> bool {
+        *self == FEATURER::_0000000000000001
+    }
+}
+#[doc = r" Value of the field"]
+pub struct MINORR {
+    bits: u8,
+}
+impl MINORR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct MAJORR {
+    bits: u8,
+}
+impl MAJORR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Feature Specification Number"]
+    #[inline]
+    pub fn feature(&self) -> FEATURER {
+        FEATURER::_from({
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        })
+    }
+    #[doc = "Bits 16:23 - Minor Version Number"]
+    #[inline]
+    pub fn minor(&self) -> MINORR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        MINORR { bits }
+    }
+    #[doc = "Bits 24:31 - Major Version Number"]
+    #[inline]
+    pub fn major(&self) -> MAJORR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 24;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        MAJORR { bits }
+    }
+}