774 lines
19 KiB
Rust
774 lines
19 KiB
Rust
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#[doc = r" Value read from the register"]
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pub struct R {
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bits: u32,
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}
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#[doc = r" Value to write to the register"]
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pub struct W {
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bits: u32,
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}
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impl super::TIMCTL0 {
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#[doc = r" Modifies the contents of the register"]
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#[inline]
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pub fn modify<F>(&self, f: F)
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where
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for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
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{
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let bits = self.register.get();
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let r = R { bits: bits };
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let mut w = W { bits: bits };
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f(&r, &mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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pub fn write<F>(&self, f: F)
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where
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F: FnOnce(&mut W) -> &mut W,
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{
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let mut w = W::reset_value();
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f(&mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Writes the reset value to the register"]
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#[inline]
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pub fn reset(&self) {
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self.write(|w| w)
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}
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}
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#[doc = "Possible values of the field `TIMOD`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum TIMODR {
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#[doc = "Timer Disabled."]
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_0,
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#[doc = "Dual 8-bit counters baud/bit mode."]
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_1,
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#[doc = "Dual 8-bit counters PWM mode."]
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_10,
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#[doc = "Single 16-bit counter mode."]
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_11,
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}
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impl TIMODR {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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match *self {
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TIMODR::_0 => 0,
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TIMODR::_1 => 1,
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TIMODR::_10 => 2,
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TIMODR::_11 => 3,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: u8) -> TIMODR {
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match value {
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0 => TIMODR::_0,
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1 => TIMODR::_1,
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2 => TIMODR::_10,
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3 => TIMODR::_11,
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_ => unreachable!(),
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == TIMODR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == TIMODR::_1
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}
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#[doc = "Checks if the value of the field is `_10`"]
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#[inline]
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pub fn is_10(&self) -> bool {
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*self == TIMODR::_10
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}
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#[doc = "Checks if the value of the field is `_11`"]
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#[inline]
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pub fn is_11(&self) -> bool {
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*self == TIMODR::_11
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}
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}
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#[doc = "Possible values of the field `PINPOL`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum PINPOLR {
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#[doc = "Pin is active high"]
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_0,
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#[doc = "Pin is active low"]
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_1,
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}
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impl PINPOLR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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PINPOLR::_0 => false,
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PINPOLR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> PINPOLR {
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match value {
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false => PINPOLR::_0,
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true => PINPOLR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == PINPOLR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == PINPOLR::_1
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}
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}
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#[doc = r" Value of the field"]
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pub struct PINSELR {
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bits: u8,
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}
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impl PINSELR {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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self.bits
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}
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}
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#[doc = "Possible values of the field `PINCFG`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum PINCFGR {
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#[doc = "Timer pin output disabled"]
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_0,
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#[doc = "Timer pin open drain or bidirectional output enable"]
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_1,
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#[doc = "Timer pin bidirectional output data"]
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_10,
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#[doc = "Timer pin output"]
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_11,
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}
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impl PINCFGR {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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match *self {
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PINCFGR::_0 => 0,
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PINCFGR::_1 => 1,
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PINCFGR::_10 => 2,
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PINCFGR::_11 => 3,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: u8) -> PINCFGR {
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match value {
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0 => PINCFGR::_0,
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1 => PINCFGR::_1,
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2 => PINCFGR::_10,
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3 => PINCFGR::_11,
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_ => unreachable!(),
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == PINCFGR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == PINCFGR::_1
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}
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#[doc = "Checks if the value of the field is `_10`"]
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#[inline]
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pub fn is_10(&self) -> bool {
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*self == PINCFGR::_10
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}
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#[doc = "Checks if the value of the field is `_11`"]
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#[inline]
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pub fn is_11(&self) -> bool {
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*self == PINCFGR::_11
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}
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}
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#[doc = "Possible values of the field `TRGSRC`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum TRGSRCR {
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#[doc = "External trigger selected"]
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_0,
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#[doc = "Internal trigger selected"]
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_1,
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}
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impl TRGSRCR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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TRGSRCR::_0 => false,
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TRGSRCR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> TRGSRCR {
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match value {
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false => TRGSRCR::_0,
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true => TRGSRCR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == TRGSRCR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == TRGSRCR::_1
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}
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}
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#[doc = "Possible values of the field `TRGPOL`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum TRGPOLR {
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#[doc = "Trigger active high"]
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_0,
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#[doc = "Trigger active low"]
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_1,
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}
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impl TRGPOLR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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TRGPOLR::_0 => false,
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TRGPOLR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> TRGPOLR {
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match value {
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false => TRGPOLR::_0,
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true => TRGPOLR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == TRGPOLR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == TRGPOLR::_1
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}
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}
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#[doc = r" Value of the field"]
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pub struct TRGSELR {
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bits: u8,
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}
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impl TRGSELR {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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self.bits
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}
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}
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#[doc = "Values that can be written to the field `TIMOD`"]
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pub enum TIMODW {
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#[doc = "Timer Disabled."]
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_0,
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#[doc = "Dual 8-bit counters baud/bit mode."]
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_1,
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#[doc = "Dual 8-bit counters PWM mode."]
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_10,
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#[doc = "Single 16-bit counter mode."]
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_11,
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}
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impl TIMODW {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> u8 {
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match *self {
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TIMODW::_0 => 0,
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TIMODW::_1 => 1,
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TIMODW::_10 => 2,
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TIMODW::_11 => 3,
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}
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}
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}
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#[doc = r" Proxy"]
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||
|
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pub struct _TIMODW<'a> {
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w: &'a mut W,
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}
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impl<'a> _TIMODW<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: TIMODW) -> &'a mut W {
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{
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self.bits(variant._bits())
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}
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}
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#[doc = "Timer Disabled."]
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#[inline]
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pub fn _0(self) -> &'a mut W {
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self.variant(TIMODW::_0)
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}
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#[doc = "Dual 8-bit counters baud/bit mode."]
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#[inline]
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pub fn _1(self) -> &'a mut W {
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self.variant(TIMODW::_1)
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}
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|
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#[doc = "Dual 8-bit counters PWM mode."]
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#[inline]
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||
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pub fn _10(self) -> &'a mut W {
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self.variant(TIMODW::_10)
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}
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|
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#[doc = "Single 16-bit counter mode."]
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||
|
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#[inline]
|
||
|
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pub fn _11(self) -> &'a mut W {
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||
|
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self.variant(TIMODW::_11)
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||
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}
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||
|
|
#[doc = r" Writes raw bits to the field"]
|
||
|
|
#[inline]
|
||
|
|
pub fn bits(self, value: u8) -> &'a mut W {
|
||
|
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const MASK: u8 = 3;
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||
|
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const OFFSET: u8 = 0;
|
||
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
||
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||
|
|
self.w
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#[doc = "Values that can be written to the field `PINPOL`"]
|
||
|
|
pub enum PINPOLW {
|
||
|
|
#[doc = "Pin is active high"]
|
||
|
|
_0,
|
||
|
|
#[doc = "Pin is active low"]
|
||
|
|
_1,
|
||
|
|
}
|
||
|
|
impl PINPOLW {
|
||
|
|
#[allow(missing_docs)]
|
||
|
|
#[doc(hidden)]
|
||
|
|
#[inline]
|
||
|
|
pub fn _bits(&self) -> bool {
|
||
|
|
match *self {
|
||
|
|
PINPOLW::_0 => false,
|
||
|
|
PINPOLW::_1 => true,
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#[doc = r" Proxy"]
|
||
|
|
pub struct _PINPOLW<'a> {
|
||
|
|
w: &'a mut W,
|
||
|
|
}
|
||
|
|
impl<'a> _PINPOLW<'a> {
|
||
|
|
#[doc = r" Writes `variant` to the field"]
|
||
|
|
#[inline]
|
||
|
|
pub fn variant(self, variant: PINPOLW) -> &'a mut W {
|
||
|
|
{
|
||
|
|
self.bit(variant._bits())
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#[doc = "Pin is active high"]
|
||
|
|
#[inline]
|
||
|
|
pub fn _0(self) -> &'a mut W {
|
||
|
|
self.variant(PINPOLW::_0)
|
||
|
|
}
|
||
|
|
#[doc = "Pin is active low"]
|
||
|
|
#[inline]
|
||
|
|
pub fn _1(self) -> &'a mut W {
|
||
|
|
self.variant(PINPOLW::_1)
|
||
|
|
}
|
||
|
|
#[doc = r" Sets the field bit"]
|
||
|
|
pub fn set_bit(self) -> &'a mut W {
|
||
|
|
self.bit(true)
|
||
|
|
}
|
||
|
|
#[doc = r" Clears the field bit"]
|
||
|
|
pub fn clear_bit(self) -> &'a mut W {
|
||
|
|
self.bit(false)
|
||
|
|
}
|
||
|
|
#[doc = r" Writes raw bits to the field"]
|
||
|
|
#[inline]
|
||
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
||
|
|
const MASK: bool = true;
|
||
|
|
const OFFSET: u8 = 7;
|
||
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
||
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||
|
|
self.w
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#[doc = r" Proxy"]
|
||
|
|
pub struct _PINSELW<'a> {
|
||
|
|
w: &'a mut W,
|
||
|
|
}
|
||
|
|
impl<'a> _PINSELW<'a> {
|
||
|
|
#[doc = r" Writes raw bits to the field"]
|
||
|
|
#[inline]
|
||
|
|
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||
|
|
const MASK: u8 = 7;
|
||
|
|
const OFFSET: u8 = 8;
|
||
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
||
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||
|
|
self.w
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#[doc = "Values that can be written to the field `PINCFG`"]
|
||
|
|
pub enum PINCFGW {
|
||
|
|
#[doc = "Timer pin output disabled"]
|
||
|
|
_0,
|
||
|
|
#[doc = "Timer pin open drain or bidirectional output enable"]
|
||
|
|
_1,
|
||
|
|
#[doc = "Timer pin bidirectional output data"]
|
||
|
|
_10,
|
||
|
|
#[doc = "Timer pin output"]
|
||
|
|
_11,
|
||
|
|
}
|
||
|
|
impl PINCFGW {
|
||
|
|
#[allow(missing_docs)]
|
||
|
|
#[doc(hidden)]
|
||
|
|
#[inline]
|
||
|
|
pub fn _bits(&self) -> u8 {
|
||
|
|
match *self {
|
||
|
|
PINCFGW::_0 => 0,
|
||
|
|
PINCFGW::_1 => 1,
|
||
|
|
PINCFGW::_10 => 2,
|
||
|
|
PINCFGW::_11 => 3,
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#[doc = r" Proxy"]
|
||
|
|
pub struct _PINCFGW<'a> {
|
||
|
|
w: &'a mut W,
|
||
|
|
}
|
||
|
|
impl<'a> _PINCFGW<'a> {
|
||
|
|
#[doc = r" Writes `variant` to the field"]
|
||
|
|
#[inline]
|
||
|
|
pub fn variant(self, variant: PINCFGW) -> &'a mut W {
|
||
|
|
{
|
||
|
|
self.bits(variant._bits())
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#[doc = "Timer pin output disabled"]
|
||
|
|
#[inline]
|
||
|
|
pub fn _0(self) -> &'a mut W {
|
||
|
|
self.variant(PINCFGW::_0)
|
||
|
|
}
|
||
|
|
#[doc = "Timer pin open drain or bidirectional output enable"]
|
||
|
|
#[inline]
|
||
|
|
pub fn _1(self) -> &'a mut W {
|
||
|
|
self.variant(PINCFGW::_1)
|
||
|
|
}
|
||
|
|
#[doc = "Timer pin bidirectional output data"]
|
||
|
|
#[inline]
|
||
|
|
pub fn _10(self) -> &'a mut W {
|
||
|
|
self.variant(PINCFGW::_10)
|
||
|
|
}
|
||
|
|
#[doc = "Timer pin output"]
|
||
|
|
#[inline]
|
||
|
|
pub fn _11(self) -> &'a mut W {
|
||
|
|
self.variant(PINCFGW::_11)
|
||
|
|
}
|
||
|
|
#[doc = r" Writes raw bits to the field"]
|
||
|
|
#[inline]
|
||
|
|
pub fn bits(self, value: u8) -> &'a mut W {
|
||
|
|
const MASK: u8 = 3;
|
||
|
|
const OFFSET: u8 = 16;
|
||
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
||
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||
|
|
self.w
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#[doc = "Values that can be written to the field `TRGSRC`"]
|
||
|
|
pub enum TRGSRCW {
|
||
|
|
#[doc = "External trigger selected"]
|
||
|
|
_0,
|
||
|
|
#[doc = "Internal trigger selected"]
|
||
|
|
_1,
|
||
|
|
}
|
||
|
|
impl TRGSRCW {
|
||
|
|
#[allow(missing_docs)]
|
||
|
|
#[doc(hidden)]
|
||
|
|
#[inline]
|
||
|
|
pub fn _bits(&self) -> bool {
|
||
|
|
match *self {
|
||
|
|
TRGSRCW::_0 => false,
|
||
|
|
TRGSRCW::_1 => true,
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#[doc = r" Proxy"]
|
||
|
|
pub struct _TRGSRCW<'a> {
|
||
|
|
w: &'a mut W,
|
||
|
|
}
|
||
|
|
impl<'a> _TRGSRCW<'a> {
|
||
|
|
#[doc = r" Writes `variant` to the field"]
|
||
|
|
#[inline]
|
||
|
|
pub fn variant(self, variant: TRGSRCW) -> &'a mut W {
|
||
|
|
{
|
||
|
|
self.bit(variant._bits())
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#[doc = "External trigger selected"]
|
||
|
|
#[inline]
|
||
|
|
pub fn _0(self) -> &'a mut W {
|
||
|
|
self.variant(TRGSRCW::_0)
|
||
|
|
}
|
||
|
|
#[doc = "Internal trigger selected"]
|
||
|
|
#[inline]
|
||
|
|
pub fn _1(self) -> &'a mut W {
|
||
|
|
self.variant(TRGSRCW::_1)
|
||
|
|
}
|
||
|
|
#[doc = r" Sets the field bit"]
|
||
|
|
pub fn set_bit(self) -> &'a mut W {
|
||
|
|
self.bit(true)
|
||
|
|
}
|
||
|
|
#[doc = r" Clears the field bit"]
|
||
|
|
pub fn clear_bit(self) -> &'a mut W {
|
||
|
|
self.bit(false)
|
||
|
|
}
|
||
|
|
#[doc = r" Writes raw bits to the field"]
|
||
|
|
#[inline]
|
||
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
||
|
|
const MASK: bool = true;
|
||
|
|
const OFFSET: u8 = 22;
|
||
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
||
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||
|
|
self.w
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#[doc = "Values that can be written to the field `TRGPOL`"]
|
||
|
|
pub enum TRGPOLW {
|
||
|
|
#[doc = "Trigger active high"]
|
||
|
|
_0,
|
||
|
|
#[doc = "Trigger active low"]
|
||
|
|
_1,
|
||
|
|
}
|
||
|
|
impl TRGPOLW {
|
||
|
|
#[allow(missing_docs)]
|
||
|
|
#[doc(hidden)]
|
||
|
|
#[inline]
|
||
|
|
pub fn _bits(&self) -> bool {
|
||
|
|
match *self {
|
||
|
|
TRGPOLW::_0 => false,
|
||
|
|
TRGPOLW::_1 => true,
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#[doc = r" Proxy"]
|
||
|
|
pub struct _TRGPOLW<'a> {
|
||
|
|
w: &'a mut W,
|
||
|
|
}
|
||
|
|
impl<'a> _TRGPOLW<'a> {
|
||
|
|
#[doc = r" Writes `variant` to the field"]
|
||
|
|
#[inline]
|
||
|
|
pub fn variant(self, variant: TRGPOLW) -> &'a mut W {
|
||
|
|
{
|
||
|
|
self.bit(variant._bits())
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#[doc = "Trigger active high"]
|
||
|
|
#[inline]
|
||
|
|
pub fn _0(self) -> &'a mut W {
|
||
|
|
self.variant(TRGPOLW::_0)
|
||
|
|
}
|
||
|
|
#[doc = "Trigger active low"]
|
||
|
|
#[inline]
|
||
|
|
pub fn _1(self) -> &'a mut W {
|
||
|
|
self.variant(TRGPOLW::_1)
|
||
|
|
}
|
||
|
|
#[doc = r" Sets the field bit"]
|
||
|
|
pub fn set_bit(self) -> &'a mut W {
|
||
|
|
self.bit(true)
|
||
|
|
}
|
||
|
|
#[doc = r" Clears the field bit"]
|
||
|
|
pub fn clear_bit(self) -> &'a mut W {
|
||
|
|
self.bit(false)
|
||
|
|
}
|
||
|
|
#[doc = r" Writes raw bits to the field"]
|
||
|
|
#[inline]
|
||
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
||
|
|
const MASK: bool = true;
|
||
|
|
const OFFSET: u8 = 23;
|
||
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
||
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||
|
|
self.w
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#[doc = r" Proxy"]
|
||
|
|
pub struct _TRGSELW<'a> {
|
||
|
|
w: &'a mut W,
|
||
|
|
}
|
||
|
|
impl<'a> _TRGSELW<'a> {
|
||
|
|
#[doc = r" Writes raw bits to the field"]
|
||
|
|
#[inline]
|
||
|
|
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||
|
|
const MASK: u8 = 15;
|
||
|
|
const OFFSET: u8 = 24;
|
||
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
||
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||
|
|
self.w
|
||
|
|
}
|
||
|
|
}
|
||
|
|
impl R {
|
||
|
|
#[doc = r" Value of the register as raw bits"]
|
||
|
|
#[inline]
|
||
|
|
pub fn bits(&self) -> u32 {
|
||
|
|
self.bits
|
||
|
|
}
|
||
|
|
#[doc = "Bits 0:1 - Timer Mode"]
|
||
|
|
#[inline]
|
||
|
|
pub fn timod(&self) -> TIMODR {
|
||
|
|
TIMODR::_from({
|
||
|
|
const MASK: u8 = 3;
|
||
|
|
const OFFSET: u8 = 0;
|
||
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
||
|
|
})
|
||
|
|
}
|
||
|
|
#[doc = "Bit 7 - Timer Pin Polarity"]
|
||
|
|
#[inline]
|
||
|
|
pub fn pinpol(&self) -> PINPOLR {
|
||
|
|
PINPOLR::_from({
|
||
|
|
const MASK: bool = true;
|
||
|
|
const OFFSET: u8 = 7;
|
||
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
||
|
|
})
|
||
|
|
}
|
||
|
|
#[doc = "Bits 8:10 - Timer Pin Select"]
|
||
|
|
#[inline]
|
||
|
|
pub fn pinsel(&self) -> PINSELR {
|
||
|
|
let bits = {
|
||
|
|
const MASK: u8 = 7;
|
||
|
|
const OFFSET: u8 = 8;
|
||
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
||
|
|
};
|
||
|
|
PINSELR { bits }
|
||
|
|
}
|
||
|
|
#[doc = "Bits 16:17 - Timer Pin Configuration"]
|
||
|
|
#[inline]
|
||
|
|
pub fn pincfg(&self) -> PINCFGR {
|
||
|
|
PINCFGR::_from({
|
||
|
|
const MASK: u8 = 3;
|
||
|
|
const OFFSET: u8 = 16;
|
||
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
||
|
|
})
|
||
|
|
}
|
||
|
|
#[doc = "Bit 22 - Trigger Source"]
|
||
|
|
#[inline]
|
||
|
|
pub fn trgsrc(&self) -> TRGSRCR {
|
||
|
|
TRGSRCR::_from({
|
||
|
|
const MASK: bool = true;
|
||
|
|
const OFFSET: u8 = 22;
|
||
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
||
|
|
})
|
||
|
|
}
|
||
|
|
#[doc = "Bit 23 - Trigger Polarity"]
|
||
|
|
#[inline]
|
||
|
|
pub fn trgpol(&self) -> TRGPOLR {
|
||
|
|
TRGPOLR::_from({
|
||
|
|
const MASK: bool = true;
|
||
|
|
const OFFSET: u8 = 23;
|
||
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
||
|
|
})
|
||
|
|
}
|
||
|
|
#[doc = "Bits 24:27 - Trigger Select"]
|
||
|
|
#[inline]
|
||
|
|
pub fn trgsel(&self) -> TRGSELR {
|
||
|
|
let bits = {
|
||
|
|
const MASK: u8 = 15;
|
||
|
|
const OFFSET: u8 = 24;
|
||
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
||
|
|
};
|
||
|
|
TRGSELR { bits }
|
||
|
|
}
|
||
|
|
}
|
||
|
|
impl W {
|
||
|
|
#[doc = r" Reset value of the register"]
|
||
|
|
#[inline]
|
||
|
|
pub fn reset_value() -> W {
|
||
|
|
W { bits: 0 }
|
||
|
|
}
|
||
|
|
#[doc = r" Writes raw bits to the register"]
|
||
|
|
#[inline]
|
||
|
|
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||
|
|
self.bits = bits;
|
||
|
|
self
|
||
|
|
}
|
||
|
|
#[doc = "Bits 0:1 - Timer Mode"]
|
||
|
|
#[inline]
|
||
|
|
pub fn timod(&mut self) -> _TIMODW {
|
||
|
|
_TIMODW { w: self }
|
||
|
|
}
|
||
|
|
#[doc = "Bit 7 - Timer Pin Polarity"]
|
||
|
|
#[inline]
|
||
|
|
pub fn pinpol(&mut self) -> _PINPOLW {
|
||
|
|
_PINPOLW { w: self }
|
||
|
|
}
|
||
|
|
#[doc = "Bits 8:10 - Timer Pin Select"]
|
||
|
|
#[inline]
|
||
|
|
pub fn pinsel(&mut self) -> _PINSELW {
|
||
|
|
_PINSELW { w: self }
|
||
|
|
}
|
||
|
|
#[doc = "Bits 16:17 - Timer Pin Configuration"]
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||
|
|
#[inline]
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||
|
|
pub fn pincfg(&mut self) -> _PINCFGW {
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||
|
|
_PINCFGW { w: self }
|
||
|
|
}
|
||
|
|
#[doc = "Bit 22 - Trigger Source"]
|
||
|
|
#[inline]
|
||
|
|
pub fn trgsrc(&mut self) -> _TRGSRCW {
|
||
|
|
_TRGSRCW { w: self }
|
||
|
|
}
|
||
|
|
#[doc = "Bit 23 - Trigger Polarity"]
|
||
|
|
#[inline]
|
||
|
|
pub fn trgpol(&mut self) -> _TRGPOLW {
|
||
|
|
_TRGPOLW { w: self }
|
||
|
|
}
|
||
|
|
#[doc = "Bits 24:27 - Trigger Select"]
|
||
|
|
#[inline]
|
||
|
|
pub fn trgsel(&mut self) -> _TRGSELW {
|
||
|
|
_TRGSELW { w: self }
|
||
|
|
}
|
||
|
|
}
|