276 lines
19 KiB
C#
276 lines
19 KiB
C#
//
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// Copyright (c) 2010-2023 Antmicro
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// Copyright (c) 2011-2015 Realtime Embedded
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//
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// This file is licensed under the MIT License.
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// Full license text is available in 'licenses/MIT.txt'.
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//
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using System;
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using Antmicro.Renode.Peripherals.Bus;
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using Antmicro.Renode.Core;
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using Antmicro.Renode.Peripherals;
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using Antmicro.Renode.Utilities;
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using Antmicro.Renode.Logging;
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using System.Collections.Generic;
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using Antmicro.Renode.Core.Structure.Registers;
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namespace Antmicro.Renode.Peripherals.Miscellaneous
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{
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public class ESP32S3_EXTMEM : IBytePeripheral, IDoubleWordPeripheral, IKnownSize
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{
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public ESP32S3_EXTMEM(Machine machine)
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{
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var registersMap = new Dictionary<long, DoubleWordRegister>
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{
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{(long)Registers.DCACHE_CTRL, new DoubleWordRegister(this)
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// NOTE: This appears to be inverted logic, i.e. `false` means `enable`
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.WithFlag(0, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => dCacheEnabled, writeCallback: (_, val) => dCacheEnabled = !val, name: "DCACHE_ENABLE") // The bit is used to activate the data cache. 0: disable, 1: enable
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.WithFlag(1, FieldMode.Read | FieldMode.Write, name: "DCACHE_SIZE_MODE") // The bit is used to configure cache memory size.0: 32KB, 1: 64KB
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.WithValueField(2, 2, FieldMode.Read | FieldMode.Write, name: "DCACHE_BLOCKSIZE_MODE") // The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2: 64 bytes
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},
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{(long)Registers.DCACHE_CTRL1, new DoubleWordRegister(this)
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.WithFlag(0, FieldMode.Read | FieldMode.Write, name: "DCACHE_SHUT_CORE0_BUS") // The bit is used to disable core0 dbus, 0: enable, 1: disable
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.WithFlag(1, FieldMode.Read | FieldMode.Write, name: "DCACHE_SHUT_CORE1_BUS") // The bit is used to disable core1 dbus, 0: enable, 1: disable
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},
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{(long)Registers.DCACHE_SYNC_CTRL, new DoubleWordRegister(this)
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.WithFlag(0, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => false, name: "DCACHE_INVALIDATE_ENA") // The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.
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.WithFlag(1, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => false, name: "DCACHE_WRITEBACK_ENA") // The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done.
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.WithFlag(2, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => false, name: "DCACHE_CLEAN_ENA") // The bit is used to enable clean operation. It will be cleared by hardware after clean operation done.
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.WithFlag(3, FieldMode.Read, valueProviderCallback: (_) => true, name: "DCACHE_SYNC_DONE") // The bit is used to indicate clean/writeback/invalidate operation is finished.
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},
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{(long)Registers.DCACHE_SYNC_ADDR, new DoubleWordRegister(this)
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.WithValueField(0, 32, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => 0, name: "DCACHE_SYNC_ADDR") // The bits are used to configure the start virtual address for clean operations. It should be combined with DCACHE_SYNC_SIZE_REG.
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},
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{(long)Registers.DCACHE_SYNC_SIZE, new DoubleWordRegister(this)
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.WithValueField(0, 32, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => 0, name: "DCACHE_SYNC_SIZE") // The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG.
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},
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{(long)Registers.DCACHE_PRELOAD_CTRL, new DoubleWordRegister(this)
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.WithFlag(0, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => false, name: "DCACHE_PRELOAD_ENA") // The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.
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.WithFlag(1, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => true, name: "DCACHE_PRELOAD_DONE") // The bit is used to indicate preload operation is finished.
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.WithFlag(2, FieldMode.Read | FieldMode.Write, name: "DCACHE_PRELOAD_ORDER") // The bit is used to configure the direction of preload operation. 1: descending, 0: ascending.
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},
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{(long)Registers.DCACHE_AUTOLOAD_CTRL, new DoubleWordRegister(this)
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.WithFlag(0, FieldMode.Read | FieldMode.Write, name: "DCACHE_AUTOLOAD_SCT0_ENA") // The bits are used to enable the first section for autoload operation.
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.WithFlag(1, FieldMode.Read | FieldMode.Write, name: "DCACHE_AUTOLOAD_SCT1_ENA") // The bits are used to enable the second section for autoload operation.
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.WithFlag(2, FieldMode.Read | FieldMode.Write, name: "DCACHE_AUTOLOAD_ENA") // The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable, 0: disable.
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.WithFlag(3, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => true, name: "DCACHE_AUTOLOAD_DONE") // The bit is used to indicate autoload operation is finished.
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.WithFlag(4, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => false, name: "DCACHE_AUTOLOAD_ORDER") // The bits are used to configure the direction of autoload. 1: descending, 0: ascending.
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.WithValueField(5, 2, FieldMode.Read | FieldMode.Write, name: "DCACHE_AUTOLOAD_RQST") // The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.
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.WithValueField(7, 2, FieldMode.Read | FieldMode.Write, name: "DCACHE_AUTOLOAD_SIZE") // The bits are used to configure the numbers of the cache block for the issuing autoload operation.
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.WithFlag(9, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => false, name: "DCACHE_AUTOLOAD_BUFFER_CLEAR") // The bit is used to clear autoload buffer in dcache.
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},
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{(long)Registers.CACHE_ILG_INT_CLR, new DoubleWordRegister(this)
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.WithFlag(0, FieldMode.Read | FieldMode.Write, name: "ICACHE_SYNC_OP_FAULT_INT_CLR") // The bit is used to clear interrupt by sync configurations fault.
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.WithFlag(1, FieldMode.Read | FieldMode.Write, name: "ICACHE_PRELOAD_OP_FAULT_INT_CLR") // The bit is used to clear interrupt by preload configurations fault.
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.WithFlag(2, FieldMode.Read | FieldMode.Write, name: "DCACHE_SYNC_OP_FAULT_INT_CLR") // The bit is used to clear interrupt by sync configurations fault.
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.WithFlag(3, FieldMode.Read | FieldMode.Write, name: "DCACHE_PRELOAD_OP_FAULT_INT_CLR") // The bit is used to clear interrupt by preload configurations fault.
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.WithFlag(4, FieldMode.Read | FieldMode.Write, name: "DCACHE_WRITE_FLASH_INT_CLR") // The bit is used to clear interrupt by dcache trying to write flash.
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.WithFlag(5, FieldMode.Read | FieldMode.Write, name: "MMU_ENTRY_FAULT_INT_CLR") // The bit is used to clear interrupt by mmu entry fault.
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.WithFlag(6, FieldMode.Read | FieldMode.Write, name: "DCACHE_OCCUPY_EXC_INT_CLR") // The bit is used to clear interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.
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.WithFlag(7, FieldMode.Read | FieldMode.Write, name: "IBUS_CNT_OVF_INT_CLR") // The bit is used to clear interrupt by ibus counter overflow.
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.WithFlag(8, FieldMode.Read | FieldMode.Write, name: "DBUS_CNT_OVF_INT_CLR") // The bit is used to clear interrupt by dbus counter overflow.
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},
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{(long)Registers.CACHE_WRAP_AROUND_CTRL, new DoubleWordRegister(this)
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.WithFlag(0, FieldMode.Read | FieldMode.Write, name: "CACHE_FLASH_WRAP_AROUND") // The bit is used to enable wrap around mode when read data from flash.
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.WithFlag(1, FieldMode.Read | FieldMode.Write, name: "CACHE_SRAM_RD_WRAP_AROUND") // The bit is used to enable wrap around mode when read data from spiram.
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},
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{(long)Registers.CACHE_MMU_OWNER, new DoubleWordRegister(this)
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.WithValueField(7, 2, FieldMode.Read | FieldMode.Write, name: "CACHE_MMU_OWNER") // The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, bit2: dma, bit3: reserved.
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},
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{(long)Registers.DCACHE_FREEZE, new DoubleWordRegister(this)
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.WithFlag(0, FieldMode.Read | FieldMode.Write, name: "ENA") // The bit is used to enable dcache freeze mode
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.WithFlag(1, FieldMode.Read | FieldMode.Write, name: "MODE") // The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss
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.WithFlag(2, FieldMode.Read, valueProviderCallback: (_) => true, name: "DONE") // The bit is used to indicate dcache freeze success
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},
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{(long)Registers.ICACHE_FREEZE, new DoubleWordRegister(this)
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.WithFlag(0, FieldMode.Read | FieldMode.Write, name: "ENA") // The bit is used to enable icache freeze mode
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.WithFlag(1, FieldMode.Read | FieldMode.Write, name: "MODE") // The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss
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.WithFlag(2, FieldMode.Read, valueProviderCallback: (_) => true, name: "DONE") // The bit is used to indicate icache freeze success
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},
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// 0x60: ******* Description ***********
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{(long)Registers.ICACHE_CTRL, new DoubleWordRegister(this)
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// NOTE: This appears to be inverted logic, i.e. `false` means `enable`
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.WithFlag(0, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => iCacheEnabled, writeCallback: (_, val) => iCacheEnabled = !val, name: "ICACHE_ENABLE") // The bit is used to activate the data cache. 0: disable, 1: enable
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.WithFlag(1, FieldMode.Read | FieldMode.Write, name: "ICACHE_WAY_MODE") // The bit is used to configure cache way mode.0: 4-way, 1: 8-way
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.WithFlag(2, FieldMode.Read | FieldMode.Write, name: "ICACHE_SIZE_MODE") // The bit is used to configure cache memory size.0: 16KB, 1: 32KB
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.WithFlag(3, FieldMode.Read | FieldMode.Write, name: "ICACHE_BLOCKSIZE_MODE") // The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes
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},
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// 0x88: ******* Description ***********
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{(long)Registers.ICACHE_SYNC_CTRL, new DoubleWordRegister(this)
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.WithFlag(0, FieldMode.Read | FieldMode.Write, name: "ICACHE_INVALIDATE_ENA") // The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.
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.WithFlag(1, FieldMode.Read, valueProviderCallback: (_) => true, name: "ICACHE_SYNC_DONE") // The bit is used to indicate invalidate operation is finished.
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},
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// 0x94: ******* Description ***********
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{(long)Registers.ICACHE_PRELOAD_CTRL, new DoubleWordRegister(this)
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.WithFlag(0, FieldMode.Read | FieldMode.Write, name: "ICACHE_PRELOAD_ENA") // The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.
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.WithFlag(1, FieldMode.Read, valueProviderCallback: (_) => true, name: "ICACHE_PRELOAD_DONE") // The bit is used to indicate preload operation is finished.
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.WithFlag(2, FieldMode.Read | FieldMode.Write, name: "ICACHE_PRELOAD_ORDER") // The bit is used to configure the direction of preload operation. 1: descending, 0: ascending.
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},
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// 0xa0: ******* Description ***********
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{(long)Registers.ICACHE_AUTOLOAD_CTRL, new DoubleWordRegister(this)
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.WithFlag(0, FieldMode.Read | FieldMode.Write, name: "ICACHE_AUTOLOAD_SCT0_ENA") // The bits are used to enable the first section for autoload operation.
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.WithFlag(1, FieldMode.Read | FieldMode.Write, name: "ICACHE_AUTOLOAD_SCT1_ENA") // The bits are used to enable the second section for autoload operation.
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.WithFlag(2, FieldMode.Read | FieldMode.Write, name: "ICACHE_AUTOLOAD_ENA") // The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable.
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.WithFlag(3, FieldMode.Read, valueProviderCallback: (_) => true, name: "ICACHE_AUTOLOAD_DONE") // The bit is used to indicate autoload operation is finished.
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.WithFlag(4, FieldMode.Read | FieldMode.Write, name: "ICACHE_AUTOLOAD_ORDER") // The bits are used to configure the direction of autoload. 1: descending, 0: ascending.
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.WithValueField(5, 2, FieldMode.Read | FieldMode.Write, name: "ICACHE_AUTOLOAD_RQST") // The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.
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.WithValueField(7, 2, FieldMode.Read | FieldMode.Write, name: "ICACHE_AUTOLOAD_SIZE") // The bits are used to configure the numbers of the cache block for the issuing autoload operation.
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.WithFlag(9, FieldMode.Read | FieldMode.Write, name: "ICACHE_AUTOLOAD_BUFFER_CLEAR") // The bit is used to clear autoload buffer in icache.
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},
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// 0x130: ******* Description ***********
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{(long)Registers.CACHE_STATE, new DoubleWordRegister(this)
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.WithValueField(0, 12, FieldMode.Read, valueProviderCallback: (_) => {if (iCacheEnabled) return 1; else return 0;}, name: "ICACHE_STATE") // The bit is used to indicate whether icache main fsm is in idle state or not. 1: in idle state, 0: not in idle state
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.WithValueField(12, 12, FieldMode.Read, valueProviderCallback: (_) => {if (dCacheEnabled) return 1; else return 0;}, name: "DCACHE_STATE") // The bit is used to indicate whether dcache main fsm is in idle state or not. 1: in idle state, 0: not in idle state
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},
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};
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registers = new DoubleWordRegisterCollection(this, registersMap);
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}
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public uint ReadDoubleWord(long offset)
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{
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return registers.Read(offset);
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}
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public byte ReadByte(long offset)
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{
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if (offset % 4 != 0)
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{
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// in the current configuration, only the lowest byte
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// contains a meaningful data
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return 0;
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}
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return (byte)ReadDoubleWord(offset);
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}
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public void Reset()
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{
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// base.Reset();
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registers.Reset();
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// UpdateInterrupts();
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}
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public void WriteDoubleWord(long offset, uint value)
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{
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registers.Write(offset, value);
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}
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public void WriteByte(long offset, byte value)
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{
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if (offset % 4 != 0)
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{
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// in the current configuration, only the lowest byte
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// contains a meaningful data
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return;
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}
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WriteDoubleWord(offset, value);
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}
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public long Size => 0x17C;
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private readonly DoubleWordRegisterCollection registers;
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public bool iCacheEnabled;
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public bool dCacheEnabled;
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private enum Registers : long
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{
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DCACHE_CTRL = 0x0,
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DCACHE_CTRL1 = 0x4,
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DCACHE_TAG_POWER_CTRL = 0x8,
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DCACHE_PRELOCK_CTRL = 0xc,
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DCACHE_PRELOCK_SCT0_ADDR = 0x10,
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DCACHE_PRELOCK_SCT1_ADDR = 0x14,
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DCACHE_PRELOCK_SCT_SIZE = 0x18,
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DCACHE_LOCK_CTRL = 0x1c,
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DCACHE_LOCK_ADDR = 0x20,
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DCACHE_LOCK_SIZE = 0x24,
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DCACHE_SYNC_CTRL = 0x28,
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DCACHE_SYNC_ADDR = 0x2c,
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DCACHE_SYNC_SIZE = 0x30,
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DCACHE_OCCUPY_CTRL = 0x34,
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DCACHE_OCCUPY_ADDR = 0x38,
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DCACHE_OCCUPY_SIZE = 0x3c,
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DCACHE_PRELOAD_CTRL = 0x40,
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DCACHE_PRELOAD_ADDR = 0x44,
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DCACHE_PRELOAD_SIZE = 0x48,
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DCACHE_AUTOLOAD_CTRL = 0x4c,
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DCACHE_AUTOLOAD_SCT0_ADDR = 0x50,
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DCACHE_AUTOLOAD_SCT0_SIZE = 0x54,
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DCACHE_AUTOLOAD_SCT1_ADDR = 0x58,
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DCACHE_AUTOLOAD_SCT1_SIZE = 0x5c,
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ICACHE_CTRL = 0x60,
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ICACHE_CTRL1 = 0x64,
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ICACHE_TAG_POWER_CTRL = 0x68,
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ICACHE_PRELOCK_CTRL = 0x6c,
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ICACHE_PRELOCK_SCT0_ADDR = 0x70,
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ICACHE_PRELOCK_SCT1_ADDR = 0x74,
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ICACHE_PRELOCK_SCT_SIZE = 0x78,
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ICACHE_LOCK_CTRL = 0x7c,
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ICACHE_LOCK_ADDR = 0x80,
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ICACHE_LOCK_SIZE = 0x84,
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ICACHE_SYNC_CTRL = 0x88,
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ICACHE_SYNC_ADDR = 0x8c,
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ICACHE_SYNC_SIZE = 0x90,
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ICACHE_PRELOAD_CTRL = 0x94,
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ICACHE_PRELOAD_ADDR = 0x98,
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ICACHE_PRELOAD_SIZE = 0x9c,
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ICACHE_AUTOLOAD_CTRL = 0xa0,
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ICACHE_AUTOLOAD_SCT0_ADDR = 0xa4,
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ICACHE_AUTOLOAD_SCT0_SIZE = 0xa8,
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ICACHE_AUTOLOAD_SCT1_ADDR = 0xac,
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ICACHE_AUTOLOAD_SCT1_SIZE = 0xb0,
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IBUS_TO_FLASH_START_VADDR = 0xb4,
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IBUS_TO_FLASH_END_VADDR = 0xb8,
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DBUS_TO_FLASH_START_VADDR = 0xbc,
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DBUS_TO_FLASH_END_VADDR = 0xc0,
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CACHE_ACS_CNT_CLR = 0xc4,
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IBUS_ACS_MISS_CNT = 0xc8,
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IBUS_ACS_CNT = 0xcc,
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DBUS_ACS_FLASH_MISS_CNT = 0xd0,
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DBUS_ACS_SPIRAM_MISS_CNT = 0xd4,
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DBUS_ACS_CNT = 0xd8,
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CACHE_ILG_INT_ENA = 0xdc,
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CACHE_ILG_INT_CLR = 0xe0,
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CACHE_ILG_INT_ST = 0xe4,
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CORE0_ACS_CACHE_INT_ENA = 0xe8,
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CORE0_ACS_CACHE_INT_CLR = 0xec,
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CORE0_ACS_CACHE_INT_ST = 0xf0,
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CORE1_ACS_CACHE_INT_ENA = 0xf4,
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CORE1_ACS_CACHE_INT_CLR = 0xf8,
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CORE1_ACS_CACHE_INT_ST = 0xfc,
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CORE0_DBUS_REJECT_ST = 0x100,
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CORE0_DBUS_REJECT_VADDR = 0x104,
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CORE0_IBUS_REJECT_ST = 0x108,
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CORE0_IBUS_REJECT_VADDR = 0x10c,
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CORE1_DBUS_REJECT_ST = 0x110,
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CORE1_DBUS_REJECT_VADDR = 0x114,
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CORE1_IBUS_REJECT_ST = 0x118,
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CORE1_IBUS_REJECT_VADDR = 0x11c,
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CACHE_MMU_FAULT_CONTENT = 0x120,
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CACHE_MMU_FAULT_VADDR = 0x124,
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CACHE_WRAP_AROUND_CTRL = 0x128,
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CACHE_MMU_POWER_CTRL = 0x12c,
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CACHE_STATE = 0x130,
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CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE = 0x134,
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CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON = 0x138,
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CACHE_BRIDGE_ARBITER_CTRL = 0x13c,
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CACHE_PRELOAD_INT_CTRL = 0x140,
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CACHE_SYNC_INT_CTRL = 0x144,
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CACHE_MMU_OWNER = 0x148,
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CACHE_CONF_MISC = 0x14c,
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DCACHE_FREEZE = 0x150,
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ICACHE_FREEZE = 0x154,
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ICACHE_ATOMIC_OPERATE_ENA = 0x158,
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DCACHE_ATOMIC_OPERATE_ENA = 0x15c,
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CACHE_REQUEST = 0x160,
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CLOCK_GATE = 0x164,
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CACHE_TAG_OBJECT_CTRL = 0x180,
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CACHE_TAG_WAY_OBJECT = 0x184,
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CACHE_VADDR = 0x188,
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CACHE_TAG_CONTENT = 0x18c,
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DATE = 0x3fc,
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}
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}
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}
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