801 lines
24 KiB
C
801 lines
24 KiB
C
//--------------------------------------------------------------------------------
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// Auto-generated by Migen (bc90344) & LiteX (3a72688b) on 2019-05-26 18:13:05
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//--------------------------------------------------------------------------------
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#ifndef __GENERATED_CSR_H
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#define __GENERATED_CSR_H
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#include <stdint.h>
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#ifdef CSR_ACCESSORS_DEFINED
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extern void csr_writeb(uint8_t value, unsigned long addr);
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extern uint8_t csr_readb(unsigned long addr);
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extern void csr_writew(uint16_t value, unsigned long addr);
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extern uint16_t csr_readw(unsigned long addr);
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extern void csr_writel(uint32_t value, unsigned long addr);
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extern uint32_t csr_readl(unsigned long addr);
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#else /* ! CSR_ACCESSORS_DEFINED */
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#include <hw/common.h>
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#endif /* ! CSR_ACCESSORS_DEFINED */
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/* ctrl */
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#define CSR_CTRL_BASE 0xe0000000L
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#define CSR_CTRL_RESET_ADDR 0xe0000000L
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#define CSR_CTRL_RESET_SIZE 1
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static inline unsigned char ctrl_reset_read(void) {
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unsigned char r = csr_readl(0xe0000000L);
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return r;
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}
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static inline void ctrl_reset_write(unsigned char value) {
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csr_writel(value, 0xe0000000L);
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}
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#define CSR_CTRL_SCRATCH_ADDR 0xe0000004L
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#define CSR_CTRL_SCRATCH_SIZE 4
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static inline unsigned int ctrl_scratch_read(void) {
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unsigned int r = csr_readl(0xe0000004L);
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r <<= 8;
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r |= csr_readl(0xe0000008L);
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r <<= 8;
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r |= csr_readl(0xe000000cL);
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r <<= 8;
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r |= csr_readl(0xe0000010L);
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return r;
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}
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static inline void ctrl_scratch_write(unsigned int value) {
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csr_writel(value >> 24, 0xe0000004L);
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csr_writel(value >> 16, 0xe0000008L);
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csr_writel(value >> 8, 0xe000000cL);
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csr_writel(value, 0xe0000010L);
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}
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#define CSR_CTRL_BUS_ERRORS_ADDR 0xe0000014L
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#define CSR_CTRL_BUS_ERRORS_SIZE 4
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static inline unsigned int ctrl_bus_errors_read(void) {
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unsigned int r = csr_readl(0xe0000014L);
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r <<= 8;
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r |= csr_readl(0xe0000018L);
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r <<= 8;
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r |= csr_readl(0xe000001cL);
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r <<= 8;
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r |= csr_readl(0xe0000020L);
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return r;
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}
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/* picorvspi */
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#define CSR_PICORVSPI_BASE 0xe0005000L
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#define CSR_PICORVSPI_CFG1_ADDR 0xe0005000L
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#define CSR_PICORVSPI_CFG1_SIZE 1
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static inline unsigned char picorvspi_cfg1_read(void) {
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unsigned char r = csr_readl(0xe0005000L);
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return r;
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}
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static inline void picorvspi_cfg1_write(unsigned char value) {
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csr_writel(value, 0xe0005000L);
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}
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#define CSR_PICORVSPI_CFG2_ADDR 0xe0005004L
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#define CSR_PICORVSPI_CFG2_SIZE 1
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static inline unsigned char picorvspi_cfg2_read(void) {
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unsigned char r = csr_readl(0xe0005004L);
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return r;
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}
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static inline void picorvspi_cfg2_write(unsigned char value) {
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csr_writel(value, 0xe0005004L);
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}
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#define CSR_PICORVSPI_CFG3_ADDR 0xe0005008L
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#define CSR_PICORVSPI_CFG3_SIZE 1
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static inline unsigned char picorvspi_cfg3_read(void) {
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unsigned char r = csr_readl(0xe0005008L);
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return r;
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}
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static inline void picorvspi_cfg3_write(unsigned char value) {
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csr_writel(value, 0xe0005008L);
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}
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#define CSR_PICORVSPI_CFG4_ADDR 0xe000500cL
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#define CSR_PICORVSPI_CFG4_SIZE 1
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static inline unsigned char picorvspi_cfg4_read(void) {
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unsigned char r = csr_readl(0xe000500cL);
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return r;
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}
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static inline void picorvspi_cfg4_write(unsigned char value) {
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csr_writel(value, 0xe000500cL);
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}
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#define CSR_PICORVSPI_STAT1_ADDR 0xe0005010L
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#define CSR_PICORVSPI_STAT1_SIZE 1
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static inline unsigned char picorvspi_stat1_read(void) {
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unsigned char r = csr_readl(0xe0005010L);
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return r;
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}
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#define CSR_PICORVSPI_STAT2_ADDR 0xe0005014L
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#define CSR_PICORVSPI_STAT2_SIZE 1
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static inline unsigned char picorvspi_stat2_read(void) {
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unsigned char r = csr_readl(0xe0005014L);
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return r;
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}
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#define CSR_PICORVSPI_STAT3_ADDR 0xe0005018L
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#define CSR_PICORVSPI_STAT3_SIZE 1
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static inline unsigned char picorvspi_stat3_read(void) {
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unsigned char r = csr_readl(0xe0005018L);
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return r;
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}
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#define CSR_PICORVSPI_STAT4_ADDR 0xe000501cL
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#define CSR_PICORVSPI_STAT4_SIZE 1
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static inline unsigned char picorvspi_stat4_read(void) {
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unsigned char r = csr_readl(0xe000501cL);
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return r;
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}
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/* reboot */
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#define CSR_REBOOT_BASE 0xe0006000L
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#define CSR_REBOOT_CTRL_ADDR 0xe0006000L
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#define CSR_REBOOT_CTRL_SIZE 1
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static inline unsigned char reboot_ctrl_read(void) {
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unsigned char r = csr_readl(0xe0006000L);
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return r;
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}
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static inline void reboot_ctrl_write(unsigned char value) {
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csr_writel(value, 0xe0006000L);
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}
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#define CSR_REBOOT_ADDR_ADDR 0xe0006004L
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#define CSR_REBOOT_ADDR_SIZE 4
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static inline unsigned int reboot_addr_read(void) {
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unsigned int r = csr_readl(0xe0006004L);
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r <<= 8;
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r |= csr_readl(0xe0006008L);
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r <<= 8;
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r |= csr_readl(0xe000600cL);
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r <<= 8;
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r |= csr_readl(0xe0006010L);
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return r;
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}
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static inline void reboot_addr_write(unsigned int value) {
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csr_writel(value >> 24, 0xe0006004L);
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csr_writel(value >> 16, 0xe0006008L);
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csr_writel(value >> 8, 0xe000600cL);
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csr_writel(value, 0xe0006010L);
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}
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/* rgb */
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#define CSR_RGB_BASE 0xe0006800L
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#define CSR_RGB_DAT_ADDR 0xe0006800L
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#define CSR_RGB_DAT_SIZE 1
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static inline unsigned char rgb_dat_read(void) {
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unsigned char r = csr_readl(0xe0006800L);
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return r;
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}
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static inline void rgb_dat_write(unsigned char value) {
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csr_writel(value, 0xe0006800L);
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}
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#define CSR_RGB_ADDR_ADDR 0xe0006804L
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#define CSR_RGB_ADDR_SIZE 1
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static inline unsigned char rgb_addr_read(void) {
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unsigned char r = csr_readl(0xe0006804L);
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return r;
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}
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static inline void rgb_addr_write(unsigned char value) {
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csr_writel(value, 0xe0006804L);
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}
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#define CSR_RGB_CTRL_ADDR 0xe0006808L
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#define CSR_RGB_CTRL_SIZE 1
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static inline unsigned char rgb_ctrl_read(void) {
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unsigned char r = csr_readl(0xe0006808L);
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return r;
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}
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static inline void rgb_ctrl_write(unsigned char value) {
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csr_writel(value, 0xe0006808L);
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}
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#define CSR_RGB_BYPASS_ADDR 0xe000680cL
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#define CSR_RGB_BYPASS_SIZE 1
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static inline unsigned char rgb_bypass_read(void) {
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unsigned char r = csr_readl(0xe000680cL);
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return r;
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}
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static inline void rgb_bypass_write(unsigned char value) {
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csr_writel(value, 0xe000680cL);
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}
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#define CSR_RGB_PULSE_ADDR 0xe0006810L
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#define CSR_RGB_PULSE_SIZE 3
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static inline unsigned int rgb_pulse_read(void) {
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unsigned int r = csr_readl(0xe0006810L);
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r <<= 8;
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r |= csr_readl(0xe0006814L);
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r <<= 8;
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r |= csr_readl(0xe0006818L);
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return r;
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}
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static inline void rgb_pulse_write(unsigned int value) {
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csr_writel(value >> 16, 0xe0006810L);
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csr_writel(value >> 8, 0xe0006814L);
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csr_writel(value, 0xe0006818L);
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}
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#define CSR_RGB_DUTY_ADDR 0xe000681cL
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#define CSR_RGB_DUTY_SIZE 3
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static inline unsigned int rgb_duty_read(void) {
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unsigned int r = csr_readl(0xe000681cL);
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r <<= 8;
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r |= csr_readl(0xe0006820L);
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r <<= 8;
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r |= csr_readl(0xe0006824L);
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return r;
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}
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static inline void rgb_duty_write(unsigned int value) {
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csr_writel(value >> 16, 0xe000681cL);
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csr_writel(value >> 8, 0xe0006820L);
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csr_writel(value, 0xe0006824L);
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}
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#define CSR_RGB_SENT_PULSES_ADDR 0xe0006828L
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#define CSR_RGB_SENT_PULSES_SIZE 4
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static inline unsigned int rgb_sent_pulses_read(void) {
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unsigned int r = csr_readl(0xe0006828L);
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r <<= 8;
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r |= csr_readl(0xe000682cL);
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r <<= 8;
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r |= csr_readl(0xe0006830L);
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r <<= 8;
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r |= csr_readl(0xe0006834L);
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return r;
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}
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#define CSR_RGB_DETECTED_PULSES_ADDR 0xe0006838L
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#define CSR_RGB_DETECTED_PULSES_SIZE 4
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static inline unsigned int rgb_detected_pulses_read(void) {
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unsigned int r = csr_readl(0xe0006838L);
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r <<= 8;
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r |= csr_readl(0xe000683cL);
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r <<= 8;
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r |= csr_readl(0xe0006840L);
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r <<= 8;
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r |= csr_readl(0xe0006844L);
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return r;
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}
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/* timer0 */
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#define CSR_TIMER0_BASE 0xe0002800L
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#define CSR_TIMER0_LOAD_ADDR 0xe0002800L
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#define CSR_TIMER0_LOAD_SIZE 4
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static inline unsigned int timer0_load_read(void) {
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unsigned int r = csr_readl(0xe0002800L);
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r <<= 8;
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r |= csr_readl(0xe0002804L);
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r <<= 8;
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r |= csr_readl(0xe0002808L);
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r <<= 8;
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r |= csr_readl(0xe000280cL);
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return r;
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}
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static inline void timer0_load_write(unsigned int value) {
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csr_writel(value >> 24, 0xe0002800L);
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csr_writel(value >> 16, 0xe0002804L);
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csr_writel(value >> 8, 0xe0002808L);
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csr_writel(value, 0xe000280cL);
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}
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#define CSR_TIMER0_RELOAD_ADDR 0xe0002810L
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#define CSR_TIMER0_RELOAD_SIZE 4
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static inline unsigned int timer0_reload_read(void) {
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unsigned int r = csr_readl(0xe0002810L);
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r <<= 8;
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r |= csr_readl(0xe0002814L);
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r <<= 8;
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r |= csr_readl(0xe0002818L);
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r <<= 8;
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r |= csr_readl(0xe000281cL);
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return r;
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}
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static inline void timer0_reload_write(unsigned int value) {
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csr_writel(value >> 24, 0xe0002810L);
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csr_writel(value >> 16, 0xe0002814L);
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csr_writel(value >> 8, 0xe0002818L);
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csr_writel(value, 0xe000281cL);
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}
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#define CSR_TIMER0_EN_ADDR 0xe0002820L
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#define CSR_TIMER0_EN_SIZE 1
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static inline unsigned char timer0_en_read(void) {
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unsigned char r = csr_readl(0xe0002820L);
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return r;
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}
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static inline void timer0_en_write(unsigned char value) {
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csr_writel(value, 0xe0002820L);
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}
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#define CSR_TIMER0_UPDATE_VALUE_ADDR 0xe0002824L
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#define CSR_TIMER0_UPDATE_VALUE_SIZE 1
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static inline unsigned char timer0_update_value_read(void) {
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unsigned char r = csr_readl(0xe0002824L);
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return r;
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}
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static inline void timer0_update_value_write(unsigned char value) {
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csr_writel(value, 0xe0002824L);
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}
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#define CSR_TIMER0_VALUE_ADDR 0xe0002828L
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#define CSR_TIMER0_VALUE_SIZE 4
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static inline unsigned int timer0_value_read(void) {
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unsigned int r = csr_readl(0xe0002828L);
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r <<= 8;
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r |= csr_readl(0xe000282cL);
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r <<= 8;
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r |= csr_readl(0xe0002830L);
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r <<= 8;
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r |= csr_readl(0xe0002834L);
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return r;
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}
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#define CSR_TIMER0_EV_STATUS_ADDR 0xe0002838L
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#define CSR_TIMER0_EV_STATUS_SIZE 1
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static inline unsigned char timer0_ev_status_read(void) {
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unsigned char r = csr_readl(0xe0002838L);
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return r;
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}
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static inline void timer0_ev_status_write(unsigned char value) {
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csr_writel(value, 0xe0002838L);
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}
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#define CSR_TIMER0_EV_PENDING_ADDR 0xe000283cL
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#define CSR_TIMER0_EV_PENDING_SIZE 1
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static inline unsigned char timer0_ev_pending_read(void) {
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unsigned char r = csr_readl(0xe000283cL);
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return r;
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}
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static inline void timer0_ev_pending_write(unsigned char value) {
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csr_writel(value, 0xe000283cL);
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}
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#define CSR_TIMER0_EV_ENABLE_ADDR 0xe0002840L
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#define CSR_TIMER0_EV_ENABLE_SIZE 1
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static inline unsigned char timer0_ev_enable_read(void) {
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unsigned char r = csr_readl(0xe0002840L);
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return r;
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}
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static inline void timer0_ev_enable_write(unsigned char value) {
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csr_writel(value, 0xe0002840L);
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}
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/* touch */
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#define CSR_TOUCH_BASE 0xe0005800L
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#define CSR_TOUCH_O_ADDR 0xe0005800L
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#define CSR_TOUCH_O_SIZE 1
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static inline unsigned char touch_o_read(void) {
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unsigned char r = csr_readl(0xe0005800L);
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return r;
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}
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static inline void touch_o_write(unsigned char value) {
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csr_writel(value, 0xe0005800L);
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}
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#define CSR_TOUCH_OE_ADDR 0xe0005804L
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#define CSR_TOUCH_OE_SIZE 1
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static inline unsigned char touch_oe_read(void) {
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unsigned char r = csr_readl(0xe0005804L);
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return r;
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}
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static inline void touch_oe_write(unsigned char value) {
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csr_writel(value, 0xe0005804L);
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}
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#define CSR_TOUCH_I_ADDR 0xe0005808L
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#define CSR_TOUCH_I_SIZE 1
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static inline unsigned char touch_i_read(void) {
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unsigned char r = csr_readl(0xe0005808L);
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return r;
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}
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/* usb */
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#define CSR_USB_BASE 0xe0004800L
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#define CSR_USB_PULLUP_OUT_ADDR 0xe0004800L
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#define CSR_USB_PULLUP_OUT_SIZE 1
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static inline unsigned char usb_pullup_out_read(void) {
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unsigned char r = csr_readl(0xe0004800L);
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return r;
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}
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static inline void usb_pullup_out_write(unsigned char value) {
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csr_writel(value, 0xe0004800L);
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}
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#define CSR_USB_EP_0_OUT_EV_STATUS_ADDR 0xe0004804L
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#define CSR_USB_EP_0_OUT_EV_STATUS_SIZE 1
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static inline unsigned char usb_ep_0_out_ev_status_read(void) {
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unsigned char r = csr_readl(0xe0004804L);
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return r;
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}
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static inline void usb_ep_0_out_ev_status_write(unsigned char value) {
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csr_writel(value, 0xe0004804L);
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}
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#define CSR_USB_EP_0_OUT_EV_PENDING_ADDR 0xe0004808L
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#define CSR_USB_EP_0_OUT_EV_PENDING_SIZE 1
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static inline unsigned char usb_ep_0_out_ev_pending_read(void) {
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unsigned char r = csr_readl(0xe0004808L);
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return r;
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}
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static inline void usb_ep_0_out_ev_pending_write(unsigned char value) {
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csr_writel(value, 0xe0004808L);
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}
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#define CSR_USB_EP_0_OUT_EV_ENABLE_ADDR 0xe000480cL
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#define CSR_USB_EP_0_OUT_EV_ENABLE_SIZE 1
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static inline unsigned char usb_ep_0_out_ev_enable_read(void) {
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unsigned char r = csr_readl(0xe000480cL);
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return r;
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}
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static inline void usb_ep_0_out_ev_enable_write(unsigned char value) {
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csr_writel(value, 0xe000480cL);
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}
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#define CSR_USB_EP_0_OUT_LAST_TOK_ADDR 0xe0004810L
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#define CSR_USB_EP_0_OUT_LAST_TOK_SIZE 1
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static inline unsigned char usb_ep_0_out_last_tok_read(void) {
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unsigned char r = csr_readl(0xe0004810L);
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return r;
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}
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#define CSR_USB_EP_0_OUT_RESPOND_ADDR 0xe0004814L
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#define CSR_USB_EP_0_OUT_RESPOND_SIZE 1
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static inline unsigned char usb_ep_0_out_respond_read(void) {
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unsigned char r = csr_readl(0xe0004814L);
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return r;
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}
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static inline void usb_ep_0_out_respond_write(unsigned char value) {
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csr_writel(value, 0xe0004814L);
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}
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#define CSR_USB_EP_0_OUT_DTB_ADDR 0xe0004818L
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#define CSR_USB_EP_0_OUT_DTB_SIZE 1
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static inline unsigned char usb_ep_0_out_dtb_read(void) {
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unsigned char r = csr_readl(0xe0004818L);
|
|
return r;
|
|
}
|
|
static inline void usb_ep_0_out_dtb_write(unsigned char value) {
|
|
csr_writel(value, 0xe0004818L);
|
|
}
|
|
#define CSR_USB_EP_0_OUT_OBUF_HEAD_ADDR 0xe000481cL
|
|
#define CSR_USB_EP_0_OUT_OBUF_HEAD_SIZE 1
|
|
static inline unsigned char usb_ep_0_out_obuf_head_read(void) {
|
|
unsigned char r = csr_readl(0xe000481cL);
|
|
return r;
|
|
}
|
|
static inline void usb_ep_0_out_obuf_head_write(unsigned char value) {
|
|
csr_writel(value, 0xe000481cL);
|
|
}
|
|
#define CSR_USB_EP_0_OUT_OBUF_EMPTY_ADDR 0xe0004820L
|
|
#define CSR_USB_EP_0_OUT_OBUF_EMPTY_SIZE 1
|
|
static inline unsigned char usb_ep_0_out_obuf_empty_read(void) {
|
|
unsigned char r = csr_readl(0xe0004820L);
|
|
return r;
|
|
}
|
|
#define CSR_USB_EP_0_IN_EV_STATUS_ADDR 0xe0004824L
|
|
#define CSR_USB_EP_0_IN_EV_STATUS_SIZE 1
|
|
static inline unsigned char usb_ep_0_in_ev_status_read(void) {
|
|
unsigned char r = csr_readl(0xe0004824L);
|
|
return r;
|
|
}
|
|
static inline void usb_ep_0_in_ev_status_write(unsigned char value) {
|
|
csr_writel(value, 0xe0004824L);
|
|
}
|
|
#define CSR_USB_EP_0_IN_EV_PENDING_ADDR 0xe0004828L
|
|
#define CSR_USB_EP_0_IN_EV_PENDING_SIZE 1
|
|
static inline unsigned char usb_ep_0_in_ev_pending_read(void) {
|
|
unsigned char r = csr_readl(0xe0004828L);
|
|
return r;
|
|
}
|
|
static inline void usb_ep_0_in_ev_pending_write(unsigned char value) {
|
|
csr_writel(value, 0xe0004828L);
|
|
}
|
|
#define CSR_USB_EP_0_IN_EV_ENABLE_ADDR 0xe000482cL
|
|
#define CSR_USB_EP_0_IN_EV_ENABLE_SIZE 1
|
|
static inline unsigned char usb_ep_0_in_ev_enable_read(void) {
|
|
unsigned char r = csr_readl(0xe000482cL);
|
|
return r;
|
|
}
|
|
static inline void usb_ep_0_in_ev_enable_write(unsigned char value) {
|
|
csr_writel(value, 0xe000482cL);
|
|
}
|
|
#define CSR_USB_EP_0_IN_LAST_TOK_ADDR 0xe0004830L
|
|
#define CSR_USB_EP_0_IN_LAST_TOK_SIZE 1
|
|
static inline unsigned char usb_ep_0_in_last_tok_read(void) {
|
|
unsigned char r = csr_readl(0xe0004830L);
|
|
return r;
|
|
}
|
|
#define CSR_USB_EP_0_IN_RESPOND_ADDR 0xe0004834L
|
|
#define CSR_USB_EP_0_IN_RESPOND_SIZE 1
|
|
static inline unsigned char usb_ep_0_in_respond_read(void) {
|
|
unsigned char r = csr_readl(0xe0004834L);
|
|
return r;
|
|
}
|
|
static inline void usb_ep_0_in_respond_write(unsigned char value) {
|
|
csr_writel(value, 0xe0004834L);
|
|
}
|
|
#define CSR_USB_EP_0_IN_DTB_ADDR 0xe0004838L
|
|
#define CSR_USB_EP_0_IN_DTB_SIZE 1
|
|
static inline unsigned char usb_ep_0_in_dtb_read(void) {
|
|
unsigned char r = csr_readl(0xe0004838L);
|
|
return r;
|
|
}
|
|
static inline void usb_ep_0_in_dtb_write(unsigned char value) {
|
|
csr_writel(value, 0xe0004838L);
|
|
}
|
|
#define CSR_USB_EP_0_IN_IBUF_HEAD_ADDR 0xe000483cL
|
|
#define CSR_USB_EP_0_IN_IBUF_HEAD_SIZE 1
|
|
static inline unsigned char usb_ep_0_in_ibuf_head_read(void) {
|
|
unsigned char r = csr_readl(0xe000483cL);
|
|
return r;
|
|
}
|
|
static inline void usb_ep_0_in_ibuf_head_write(unsigned char value) {
|
|
csr_writel(value, 0xe000483cL);
|
|
}
|
|
#define CSR_USB_EP_0_IN_IBUF_EMPTY_ADDR 0xe0004840L
|
|
#define CSR_USB_EP_0_IN_IBUF_EMPTY_SIZE 1
|
|
static inline unsigned char usb_ep_0_in_ibuf_empty_read(void) {
|
|
unsigned char r = csr_readl(0xe0004840L);
|
|
return r;
|
|
}
|
|
#define CSR_USB_EP_1_IN_EV_STATUS_ADDR 0xe0004844L
|
|
#define CSR_USB_EP_1_IN_EV_STATUS_SIZE 1
|
|
static inline unsigned char usb_ep_1_in_ev_status_read(void) {
|
|
unsigned char r = csr_readl(0xe0004844L);
|
|
return r;
|
|
}
|
|
static inline void usb_ep_1_in_ev_status_write(unsigned char value) {
|
|
csr_writel(value, 0xe0004844L);
|
|
}
|
|
#define CSR_USB_EP_1_IN_EV_PENDING_ADDR 0xe0004848L
|
|
#define CSR_USB_EP_1_IN_EV_PENDING_SIZE 1
|
|
static inline unsigned char usb_ep_1_in_ev_pending_read(void) {
|
|
unsigned char r = csr_readl(0xe0004848L);
|
|
return r;
|
|
}
|
|
static inline void usb_ep_1_in_ev_pending_write(unsigned char value) {
|
|
csr_writel(value, 0xe0004848L);
|
|
}
|
|
#define CSR_USB_EP_1_IN_EV_ENABLE_ADDR 0xe000484cL
|
|
#define CSR_USB_EP_1_IN_EV_ENABLE_SIZE 1
|
|
static inline unsigned char usb_ep_1_in_ev_enable_read(void) {
|
|
unsigned char r = csr_readl(0xe000484cL);
|
|
return r;
|
|
}
|
|
static inline void usb_ep_1_in_ev_enable_write(unsigned char value) {
|
|
csr_writel(value, 0xe000484cL);
|
|
}
|
|
#define CSR_USB_EP_1_IN_LAST_TOK_ADDR 0xe0004850L
|
|
#define CSR_USB_EP_1_IN_LAST_TOK_SIZE 1
|
|
static inline unsigned char usb_ep_1_in_last_tok_read(void) {
|
|
unsigned char r = csr_readl(0xe0004850L);
|
|
return r;
|
|
}
|
|
#define CSR_USB_EP_1_IN_RESPOND_ADDR 0xe0004854L
|
|
#define CSR_USB_EP_1_IN_RESPOND_SIZE 1
|
|
static inline unsigned char usb_ep_1_in_respond_read(void) {
|
|
unsigned char r = csr_readl(0xe0004854L);
|
|
return r;
|
|
}
|
|
static inline void usb_ep_1_in_respond_write(unsigned char value) {
|
|
csr_writel(value, 0xe0004854L);
|
|
}
|
|
#define CSR_USB_EP_1_IN_DTB_ADDR 0xe0004858L
|
|
#define CSR_USB_EP_1_IN_DTB_SIZE 1
|
|
static inline unsigned char usb_ep_1_in_dtb_read(void) {
|
|
unsigned char r = csr_readl(0xe0004858L);
|
|
return r;
|
|
}
|
|
static inline void usb_ep_1_in_dtb_write(unsigned char value) {
|
|
csr_writel(value, 0xe0004858L);
|
|
}
|
|
#define CSR_USB_EP_1_IN_IBUF_HEAD_ADDR 0xe000485cL
|
|
#define CSR_USB_EP_1_IN_IBUF_HEAD_SIZE 1
|
|
static inline unsigned char usb_ep_1_in_ibuf_head_read(void) {
|
|
unsigned char r = csr_readl(0xe000485cL);
|
|
return r;
|
|
}
|
|
static inline void usb_ep_1_in_ibuf_head_write(unsigned char value) {
|
|
csr_writel(value, 0xe000485cL);
|
|
}
|
|
#define CSR_USB_EP_1_IN_IBUF_EMPTY_ADDR 0xe0004860L
|
|
#define CSR_USB_EP_1_IN_IBUF_EMPTY_SIZE 1
|
|
static inline unsigned char usb_ep_1_in_ibuf_empty_read(void) {
|
|
unsigned char r = csr_readl(0xe0004860L);
|
|
return r;
|
|
}
|
|
#define CSR_USB_EP_2_OUT_EV_STATUS_ADDR 0xe0004864L
|
|
#define CSR_USB_EP_2_OUT_EV_STATUS_SIZE 1
|
|
static inline unsigned char usb_ep_2_out_ev_status_read(void) {
|
|
unsigned char r = csr_readl(0xe0004864L);
|
|
return r;
|
|
}
|
|
static inline void usb_ep_2_out_ev_status_write(unsigned char value) {
|
|
csr_writel(value, 0xe0004864L);
|
|
}
|
|
#define CSR_USB_EP_2_OUT_EV_PENDING_ADDR 0xe0004868L
|
|
#define CSR_USB_EP_2_OUT_EV_PENDING_SIZE 1
|
|
static inline unsigned char usb_ep_2_out_ev_pending_read(void) {
|
|
unsigned char r = csr_readl(0xe0004868L);
|
|
return r;
|
|
}
|
|
static inline void usb_ep_2_out_ev_pending_write(unsigned char value) {
|
|
csr_writel(value, 0xe0004868L);
|
|
}
|
|
#define CSR_USB_EP_2_OUT_EV_ENABLE_ADDR 0xe000486cL
|
|
#define CSR_USB_EP_2_OUT_EV_ENABLE_SIZE 1
|
|
static inline unsigned char usb_ep_2_out_ev_enable_read(void) {
|
|
unsigned char r = csr_readl(0xe000486cL);
|
|
return r;
|
|
}
|
|
static inline void usb_ep_2_out_ev_enable_write(unsigned char value) {
|
|
csr_writel(value, 0xe000486cL);
|
|
}
|
|
#define CSR_USB_EP_2_OUT_LAST_TOK_ADDR 0xe0004870L
|
|
#define CSR_USB_EP_2_OUT_LAST_TOK_SIZE 1
|
|
static inline unsigned char usb_ep_2_out_last_tok_read(void) {
|
|
unsigned char r = csr_readl(0xe0004870L);
|
|
return r;
|
|
}
|
|
#define CSR_USB_EP_2_OUT_RESPOND_ADDR 0xe0004874L
|
|
#define CSR_USB_EP_2_OUT_RESPOND_SIZE 1
|
|
static inline unsigned char usb_ep_2_out_respond_read(void) {
|
|
unsigned char r = csr_readl(0xe0004874L);
|
|
return r;
|
|
}
|
|
static inline void usb_ep_2_out_respond_write(unsigned char value) {
|
|
csr_writel(value, 0xe0004874L);
|
|
}
|
|
#define CSR_USB_EP_2_OUT_DTB_ADDR 0xe0004878L
|
|
#define CSR_USB_EP_2_OUT_DTB_SIZE 1
|
|
static inline unsigned char usb_ep_2_out_dtb_read(void) {
|
|
unsigned char r = csr_readl(0xe0004878L);
|
|
return r;
|
|
}
|
|
static inline void usb_ep_2_out_dtb_write(unsigned char value) {
|
|
csr_writel(value, 0xe0004878L);
|
|
}
|
|
#define CSR_USB_EP_2_OUT_OBUF_HEAD_ADDR 0xe000487cL
|
|
#define CSR_USB_EP_2_OUT_OBUF_HEAD_SIZE 1
|
|
static inline unsigned char usb_ep_2_out_obuf_head_read(void) {
|
|
unsigned char r = csr_readl(0xe000487cL);
|
|
return r;
|
|
}
|
|
static inline void usb_ep_2_out_obuf_head_write(unsigned char value) {
|
|
csr_writel(value, 0xe000487cL);
|
|
}
|
|
#define CSR_USB_EP_2_OUT_OBUF_EMPTY_ADDR 0xe0004880L
|
|
#define CSR_USB_EP_2_OUT_OBUF_EMPTY_SIZE 1
|
|
static inline unsigned char usb_ep_2_out_obuf_empty_read(void) {
|
|
unsigned char r = csr_readl(0xe0004880L);
|
|
return r;
|
|
}
|
|
#define CSR_USB_EP_2_IN_EV_STATUS_ADDR 0xe0004884L
|
|
#define CSR_USB_EP_2_IN_EV_STATUS_SIZE 1
|
|
static inline unsigned char usb_ep_2_in_ev_status_read(void) {
|
|
unsigned char r = csr_readl(0xe0004884L);
|
|
return r;
|
|
}
|
|
static inline void usb_ep_2_in_ev_status_write(unsigned char value) {
|
|
csr_writel(value, 0xe0004884L);
|
|
}
|
|
#define CSR_USB_EP_2_IN_EV_PENDING_ADDR 0xe0004888L
|
|
#define CSR_USB_EP_2_IN_EV_PENDING_SIZE 1
|
|
static inline unsigned char usb_ep_2_in_ev_pending_read(void) {
|
|
unsigned char r = csr_readl(0xe0004888L);
|
|
return r;
|
|
}
|
|
static inline void usb_ep_2_in_ev_pending_write(unsigned char value) {
|
|
csr_writel(value, 0xe0004888L);
|
|
}
|
|
#define CSR_USB_EP_2_IN_EV_ENABLE_ADDR 0xe000488cL
|
|
#define CSR_USB_EP_2_IN_EV_ENABLE_SIZE 1
|
|
static inline unsigned char usb_ep_2_in_ev_enable_read(void) {
|
|
unsigned char r = csr_readl(0xe000488cL);
|
|
return r;
|
|
}
|
|
static inline void usb_ep_2_in_ev_enable_write(unsigned char value) {
|
|
csr_writel(value, 0xe000488cL);
|
|
}
|
|
#define CSR_USB_EP_2_IN_LAST_TOK_ADDR 0xe0004890L
|
|
#define CSR_USB_EP_2_IN_LAST_TOK_SIZE 1
|
|
static inline unsigned char usb_ep_2_in_last_tok_read(void) {
|
|
unsigned char r = csr_readl(0xe0004890L);
|
|
return r;
|
|
}
|
|
#define CSR_USB_EP_2_IN_RESPOND_ADDR 0xe0004894L
|
|
#define CSR_USB_EP_2_IN_RESPOND_SIZE 1
|
|
static inline unsigned char usb_ep_2_in_respond_read(void) {
|
|
unsigned char r = csr_readl(0xe0004894L);
|
|
return r;
|
|
}
|
|
static inline void usb_ep_2_in_respond_write(unsigned char value) {
|
|
csr_writel(value, 0xe0004894L);
|
|
}
|
|
#define CSR_USB_EP_2_IN_DTB_ADDR 0xe0004898L
|
|
#define CSR_USB_EP_2_IN_DTB_SIZE 1
|
|
static inline unsigned char usb_ep_2_in_dtb_read(void) {
|
|
unsigned char r = csr_readl(0xe0004898L);
|
|
return r;
|
|
}
|
|
static inline void usb_ep_2_in_dtb_write(unsigned char value) {
|
|
csr_writel(value, 0xe0004898L);
|
|
}
|
|
#define CSR_USB_EP_2_IN_IBUF_HEAD_ADDR 0xe000489cL
|
|
#define CSR_USB_EP_2_IN_IBUF_HEAD_SIZE 1
|
|
static inline unsigned char usb_ep_2_in_ibuf_head_read(void) {
|
|
unsigned char r = csr_readl(0xe000489cL);
|
|
return r;
|
|
}
|
|
static inline void usb_ep_2_in_ibuf_head_write(unsigned char value) {
|
|
csr_writel(value, 0xe000489cL);
|
|
}
|
|
#define CSR_USB_EP_2_IN_IBUF_EMPTY_ADDR 0xe00048a0L
|
|
#define CSR_USB_EP_2_IN_IBUF_EMPTY_SIZE 1
|
|
static inline unsigned char usb_ep_2_in_ibuf_empty_read(void) {
|
|
unsigned char r = csr_readl(0xe00048a0L);
|
|
return r;
|
|
}
|
|
|
|
/* version */
|
|
#define CSR_VERSION_BASE 0xe0007000L
|
|
#define CSR_VERSION_MAJOR_ADDR 0xe0007000L
|
|
#define CSR_VERSION_MAJOR_SIZE 1
|
|
static inline unsigned char version_major_read(void) {
|
|
unsigned char r = csr_readl(0xe0007000L);
|
|
return r;
|
|
}
|
|
#define CSR_VERSION_MINOR_ADDR 0xe0007004L
|
|
#define CSR_VERSION_MINOR_SIZE 1
|
|
static inline unsigned char version_minor_read(void) {
|
|
unsigned char r = csr_readl(0xe0007004L);
|
|
return r;
|
|
}
|
|
#define CSR_VERSION_REVISION_ADDR 0xe0007008L
|
|
#define CSR_VERSION_REVISION_SIZE 1
|
|
static inline unsigned char version_revision_read(void) {
|
|
unsigned char r = csr_readl(0xe0007008L);
|
|
return r;
|
|
}
|
|
#define CSR_VERSION_GITREV_ADDR 0xe000700cL
|
|
#define CSR_VERSION_GITREV_SIZE 4
|
|
static inline unsigned int version_gitrev_read(void) {
|
|
unsigned int r = csr_readl(0xe000700cL);
|
|
r <<= 8;
|
|
r |= csr_readl(0xe0007010L);
|
|
r <<= 8;
|
|
r |= csr_readl(0xe0007014L);
|
|
r <<= 8;
|
|
r |= csr_readl(0xe0007018L);
|
|
return r;
|
|
}
|
|
#define CSR_VERSION_GITEXTRA_ADDR 0xe000701cL
|
|
#define CSR_VERSION_GITEXTRA_SIZE 2
|
|
static inline unsigned short int version_gitextra_read(void) {
|
|
unsigned short int r = csr_readl(0xe000701cL);
|
|
r <<= 8;
|
|
r |= csr_readl(0xe0007020L);
|
|
return r;
|
|
}
|
|
#define CSR_VERSION_DIRTY_ADDR 0xe0007024L
|
|
#define CSR_VERSION_DIRTY_SIZE 1
|
|
static inline unsigned char version_dirty_read(void) {
|
|
unsigned char r = csr_readl(0xe0007024L);
|
|
return r;
|
|
}
|
|
|
|
/* constants */
|
|
#define TIMER0_INTERRUPT 0
|
|
static inline int timer0_interrupt_read(void) {
|
|
return 0;
|
|
}
|
|
#define USB_INTERRUPT 3
|
|
static inline int usb_interrupt_read(void) {
|
|
return 3;
|
|
}
|
|
#define CSR_DATA_WIDTH 8
|
|
static inline int csr_data_width_read(void) {
|
|
return 8;
|
|
}
|
|
#define SYSTEM_CLOCK_FREQUENCY 12000000
|
|
static inline int system_clock_frequency_read(void) {
|
|
return 12000000;
|
|
}
|
|
#define ROM_DISABLE 1
|
|
static inline int rom_disable_read(void) {
|
|
return 1;
|
|
}
|
|
#define CONFIG_CLOCK_FREQUENCY 12000000
|
|
static inline int config_clock_frequency_read(void) {
|
|
return 12000000;
|
|
}
|
|
#define CONFIG_CPU_RESET_ADDR 0
|
|
static inline int config_cpu_reset_addr_read(void) {
|
|
return 0;
|
|
}
|
|
#define CONFIG_CPU_TYPE "VEXRISCV"
|
|
static inline const char * config_cpu_type_read(void) {
|
|
return "VEXRISCV";
|
|
}
|
|
#define CONFIG_CPU_VARIANT "VEXRISCV"
|
|
static inline const char * config_cpu_variant_read(void) {
|
|
return "VEXRISCV";
|
|
}
|
|
#define CONFIG_CSR_DATA_WIDTH 8
|
|
static inline int config_csr_data_width_read(void) {
|
|
return 8;
|
|
}
|
|
|
|
#endif
|