xobs/fomu-factory-test
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sw: tester: adjust tester time to 900us/1ms

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This is in-line with the datasheet.

Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross 2019-05-26 18:20:39 +08:00
parent 165cf24bc7
commit 2a3c5d352e
3 changed files with 9 additions and 4 deletions
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2
hw/factory-bitstream.py
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@ -899,7 +899,7 @@ class BaseSoC(SoCCore):
# and the "-dffe_min_ce_use 4" flag prevents Yosys from generating a
# Clock Enable signal for a LUT that has fewer than 4 flip-flops.
# This increases density, and lets us use the FPGA more efficiently.
platform.toolchain.nextpnr_yosys_template[2] += " -relut -dffe_min_ce_use 5"
platform.toolchain.nextpnr_yosys_template[2] += " -relut -dffe_min_ce_use 4"
if use_dsp:
platform.toolchain.nextpnr_yosys_template[2] += " -dsp"

2
sw/include/fomu/csr.h
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@ -1,5 +1,5 @@
//--------------------------------------------------------------------------------
// Auto-generated by Migen (bc90344) & LiteX (3a72688b) on 2019-05-23 14:16:56
// Auto-generated by Migen (bc90344) & LiteX (3a72688b) on 2019-05-26 18:13:05
//--------------------------------------------------------------------------------
#ifndef __GENERATED_CSR_H
#define __GENERATED_CSR_H

9
sw/src/tester.c
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@ -137,8 +137,13 @@ static uint32_t test_one_color(int color)
rgb_bypass_write(1 << color);
rgb_mode_off();
rgb_duty_write(SYSTEM_CLOCK_FREQUENCY / 10000 * 1);
rgb_pulse_write(SYSTEM_CLOCK_FREQUENCY / 1000 * 1);
// Amount of time it's off (900 us)
rgb_duty_write(SYSTEM_CLOCK_FREQUENCY / 10000 * 9);
// Total amount of time for one pulse (1000 us or 1 ms)
rgb_pulse_write(SYSTEM_CLOCK_FREQUENCY / 10000 * 10);
put_string("RGB");
put_char(color_names[color]);
put_string(": ");