xobs/fomu-factory-test
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sw: tester: adjust tester time to 900us/1ms

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This is in-line with the datasheet.

Signed-off-by: Sean Cross <sean@xobs.io>
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Sean Cross
2019-05-26 18:20:39 +08:00
parent 165cf24bc7
commit 2a3c5d352e
3 changed files with 9 additions and 4 deletions
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hw/factory-bitstream.py
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@@ -899,7 +899,7 @@ class BaseSoC(SoCCore):
# and the "-dffe_min_ce_use 4" flag prevents Yosys from generating a
# Clock Enable signal for a LUT that has fewer than 4 flip-flops.
# This increases density, and lets us use the FPGA more efficiently.
platform.toolchain.nextpnr_yosys_template[2] += " -relut -dffe_min_ce_use 5"
platform.toolchain.nextpnr_yosys_template[2] += " -relut -dffe_min_ce_use 4"
if use_dsp:
platform.toolchain.nextpnr_yosys_template[2] += " -dsp"