f3d779787b
hw: foboot-bitstream: add reset to usb_48
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This is required to meet timing.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-20 13:11:45 +08:00
b09333f023
hw: add spi and new vexriscv to foboot
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This is the beginning of having SPI.
Also add a new two-stage pipeline.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-20 11:25:09 +08:00
2d7c7794f5
hw: foboot-bitstream: remove debug pins, use epfifo
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Remove the debug pins to let timing close.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 21:06:37 +08:00
0c6e444789
hw: foboot-bitstream: add -relut and friends to nextpnr
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Shrink the resulting gate count by adding -relut and adjusting the
number of luts that a CE signal can use.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 21:05:51 +08:00
8aed600cd6
hw: foboot-bitstream: specify additional clock domain constraints
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Specify all the clock domain constraints for every possible signal, to
work around the fact that nextpnr currently will pick one and ignore the
rest.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 21:05:12 +08:00
6638801886
hw: foboot-bitstream: remove clk48_in signal
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It's unused.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 21:04:19 +08:00
8fb6b5977b
hw: foboot-bitstream: remove unused clk48 net
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We only use the raw and usb48 nets.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-10 20:53:58 +08:00
d603113b6f
foboot-bitstream: send clk48 through shifter, then through pll
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-08 20:47:42 +08:00
3df59a866d
metastable fix: wip
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Trying to figure out what's causing this problem.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-03-05 20:28:54 +08:00
8fe27d9371
Add 'hw/' from commit 'd812378c4d61f7c957ac4bcba15a8344fb7fb458'
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git-subtree-dir: hw
git-subtree-mainline: e4af98b4aad812378c4d
2019-03-05 09:05:50 +08:00
