it builds! what more do you want?
Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
347
include/generated/csr.h
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347
include/generated/csr.h
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#ifndef __GENERATED_CSR_H
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#define __GENERATED_CSR_H
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#include <stdint.h>
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#ifdef CSR_ACCESSORS_DEFINED
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extern void csr_writeb(uint8_t value, uint32_t addr);
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extern uint8_t csr_readb(uint32_t addr);
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extern void csr_writew(uint16_t value, uint32_t addr);
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extern uint16_t csr_readw(uint32_t addr);
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extern void csr_writel(uint32_t value, uint32_t addr);
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extern uint32_t csr_readl(uint32_t addr);
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#else /* ! CSR_ACCESSORS_DEFINED */
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#include <hw/common.h>
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#endif /* ! CSR_ACCESSORS_DEFINED */
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/* spiflash */
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#define CSR_SPIFLASH_BASE 0xe0004800
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#define CSR_SPIFLASH_BITBANG_ADDR 0xe0004800
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#define CSR_SPIFLASH_BITBANG_SIZE 1
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static inline unsigned char spiflash_bitbang_read(void) {
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unsigned char r = csr_readl(0xe0004800);
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return r;
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}
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static inline void spiflash_bitbang_write(unsigned char value) {
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csr_writel(value, 0xe0004800);
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}
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#define CSR_SPIFLASH_MISO_ADDR 0xe0004804
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#define CSR_SPIFLASH_MISO_SIZE 1
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static inline unsigned char spiflash_miso_read(void) {
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unsigned char r = csr_readl(0xe0004804);
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return r;
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}
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#define CSR_SPIFLASH_BITBANG_EN_ADDR 0xe0004808
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#define CSR_SPIFLASH_BITBANG_EN_SIZE 1
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static inline unsigned char spiflash_bitbang_en_read(void) {
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unsigned char r = csr_readl(0xe0004808);
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return r;
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}
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static inline void spiflash_bitbang_en_write(unsigned char value) {
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csr_writel(value, 0xe0004808);
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}
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/* timer0 */
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#define CSR_TIMER0_BASE 0xe0002800
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#define CSR_TIMER0_LOAD_ADDR 0xe0002800
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#define CSR_TIMER0_LOAD_SIZE 4
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static inline unsigned int timer0_load_read(void) {
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unsigned int r = csr_readl(0xe0002800);
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r <<= 8;
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r |= csr_readl(0xe0002804);
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r <<= 8;
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r |= csr_readl(0xe0002808);
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r <<= 8;
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r |= csr_readl(0xe000280c);
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return r;
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}
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static inline void timer0_load_write(unsigned int value) {
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csr_writel(value >> 24, 0xe0002800);
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csr_writel(value >> 16, 0xe0002804);
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csr_writel(value >> 8, 0xe0002808);
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csr_writel(value, 0xe000280c);
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}
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#define CSR_TIMER0_RELOAD_ADDR 0xe0002810
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#define CSR_TIMER0_RELOAD_SIZE 4
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static inline unsigned int timer0_reload_read(void) {
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unsigned int r = csr_readl(0xe0002810);
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r <<= 8;
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r |= csr_readl(0xe0002814);
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r <<= 8;
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r |= csr_readl(0xe0002818);
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r <<= 8;
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r |= csr_readl(0xe000281c);
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return r;
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}
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static inline void timer0_reload_write(unsigned int value) {
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csr_writel(value >> 24, 0xe0002810);
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csr_writel(value >> 16, 0xe0002814);
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csr_writel(value >> 8, 0xe0002818);
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csr_writel(value, 0xe000281c);
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}
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#define CSR_TIMER0_EN_ADDR 0xe0002820
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#define CSR_TIMER0_EN_SIZE 1
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static inline unsigned char timer0_en_read(void) {
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unsigned char r = csr_readl(0xe0002820);
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return r;
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}
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static inline void timer0_en_write(unsigned char value) {
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csr_writel(value, 0xe0002820);
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}
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#define CSR_TIMER0_UPDATE_VALUE_ADDR 0xe0002824
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#define CSR_TIMER0_UPDATE_VALUE_SIZE 1
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static inline unsigned char timer0_update_value_read(void) {
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unsigned char r = csr_readl(0xe0002824);
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return r;
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}
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static inline void timer0_update_value_write(unsigned char value) {
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csr_writel(value, 0xe0002824);
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}
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#define CSR_TIMER0_VALUE_ADDR 0xe0002828
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#define CSR_TIMER0_VALUE_SIZE 4
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static inline unsigned int timer0_value_read(void) {
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unsigned int r = csr_readl(0xe0002828);
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r <<= 8;
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r |= csr_readl(0xe000282c);
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r <<= 8;
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r |= csr_readl(0xe0002830);
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r <<= 8;
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r |= csr_readl(0xe0002834);
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return r;
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}
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#define CSR_TIMER0_EV_STATUS_ADDR 0xe0002838
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#define CSR_TIMER0_EV_STATUS_SIZE 1
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static inline unsigned char timer0_ev_status_read(void) {
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unsigned char r = csr_readl(0xe0002838);
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return r;
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}
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static inline void timer0_ev_status_write(unsigned char value) {
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csr_writel(value, 0xe0002838);
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}
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#define CSR_TIMER0_EV_PENDING_ADDR 0xe000283c
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#define CSR_TIMER0_EV_PENDING_SIZE 1
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static inline unsigned char timer0_ev_pending_read(void) {
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unsigned char r = csr_readl(0xe000283c);
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return r;
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}
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static inline void timer0_ev_pending_write(unsigned char value) {
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csr_writel(value, 0xe000283c);
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}
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#define CSR_TIMER0_EV_ENABLE_ADDR 0xe0002840
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#define CSR_TIMER0_EV_ENABLE_SIZE 1
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static inline unsigned char timer0_ev_enable_read(void) {
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unsigned char r = csr_readl(0xe0002840);
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return r;
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}
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static inline void timer0_ev_enable_write(unsigned char value) {
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csr_writel(value, 0xe0002840);
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}
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/* uart */
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#define CSR_UART_BASE 0xe0001800
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#define CSR_UART_RXTX_ADDR 0xe0001800
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#define CSR_UART_RXTX_SIZE 1
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static inline unsigned char uart_rxtx_read(void) {
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unsigned char r = csr_readl(0xe0001800);
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return r;
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}
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static inline void uart_rxtx_write(unsigned char value) {
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csr_writel(value, 0xe0001800);
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}
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#define CSR_UART_TXFULL_ADDR 0xe0001804
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#define CSR_UART_TXFULL_SIZE 1
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static inline unsigned char uart_txfull_read(void) {
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unsigned char r = csr_readl(0xe0001804);
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return r;
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}
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#define CSR_UART_RXEMPTY_ADDR 0xe0001808
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#define CSR_UART_RXEMPTY_SIZE 1
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static inline unsigned char uart_rxempty_read(void) {
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unsigned char r = csr_readl(0xe0001808);
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return r;
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}
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#define CSR_UART_EV_STATUS_ADDR 0xe000180c
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#define CSR_UART_EV_STATUS_SIZE 1
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static inline unsigned char uart_ev_status_read(void) {
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unsigned char r = csr_readl(0xe000180c);
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return r;
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}
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static inline void uart_ev_status_write(unsigned char value) {
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csr_writel(value, 0xe000180c);
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}
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#define CSR_UART_EV_PENDING_ADDR 0xe0001810
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#define CSR_UART_EV_PENDING_SIZE 1
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static inline unsigned char uart_ev_pending_read(void) {
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unsigned char r = csr_readl(0xe0001810);
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return r;
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}
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static inline void uart_ev_pending_write(unsigned char value) {
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csr_writel(value, 0xe0001810);
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}
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#define CSR_UART_EV_ENABLE_ADDR 0xe0001814
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#define CSR_UART_EV_ENABLE_SIZE 1
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static inline unsigned char uart_ev_enable_read(void) {
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unsigned char r = csr_readl(0xe0001814);
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return r;
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}
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static inline void uart_ev_enable_write(unsigned char value) {
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csr_writel(value, 0xe0001814);
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}
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/* uart_phy */
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#define CSR_UART_PHY_BASE 0xe0001000
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#define CSR_UART_PHY_TUNING_WORD_ADDR 0xe0001000
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#define CSR_UART_PHY_TUNING_WORD_SIZE 4
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static inline unsigned int uart_phy_tuning_word_read(void) {
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unsigned int r = csr_readl(0xe0001000);
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r <<= 8;
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r |= csr_readl(0xe0001004);
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r <<= 8;
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r |= csr_readl(0xe0001008);
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r <<= 8;
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r |= csr_readl(0xe000100c);
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return r;
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}
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static inline void uart_phy_tuning_word_write(unsigned int value) {
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csr_writel(value >> 24, 0xe0001000);
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csr_writel(value >> 16, 0xe0001004);
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csr_writel(value >> 8, 0xe0001008);
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csr_writel(value, 0xe000100c);
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}
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/* usb */
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#define CSR_USB_BASE 0xe0005000
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#define CSR_USB_OBUF_HEAD_ADDR 0xe0005000
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#define CSR_USB_OBUF_HEAD_SIZE 1
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static inline unsigned char usb_obuf_head_read(void) {
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unsigned char r = csr_readl(0xe0005000);
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return r;
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}
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static inline void usb_obuf_head_write(unsigned char value) {
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csr_writel(value, 0xe0005000);
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}
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#define CSR_USB_OBUF_EMPTY_ADDR 0xe0005004
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#define CSR_USB_OBUF_EMPTY_SIZE 1
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static inline unsigned char usb_obuf_empty_read(void) {
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unsigned char r = csr_readl(0xe0005004);
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return r;
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}
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#define CSR_USB_ARM_ADDR 0xe0005008
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#define CSR_USB_ARM_SIZE 1
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static inline unsigned char usb_arm_read(void) {
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unsigned char r = csr_readl(0xe0005008);
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return r;
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}
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static inline void usb_arm_write(unsigned char value) {
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csr_writel(value, 0xe0005008);
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}
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#define CSR_USB_IBUF_HEAD_ADDR 0xe000500c
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#define CSR_USB_IBUF_HEAD_SIZE 1
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static inline unsigned char usb_ibuf_head_read(void) {
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unsigned char r = csr_readl(0xe000500c);
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return r;
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}
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static inline void usb_ibuf_head_write(unsigned char value) {
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csr_writel(value, 0xe000500c);
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}
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#define CSR_USB_IBUF_EMPTY_ADDR 0xe0005010
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#define CSR_USB_IBUF_EMPTY_SIZE 1
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static inline unsigned char usb_ibuf_empty_read(void) {
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unsigned char r = csr_readl(0xe0005010);
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return r;
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}
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#define CSR_USB_PULLUP_OUT_ADDR 0xe0005014
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#define CSR_USB_PULLUP_OUT_SIZE 1
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static inline unsigned char usb_pullup_out_read(void) {
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unsigned char r = csr_readl(0xe0005014);
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return r;
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}
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static inline void usb_pullup_out_write(unsigned char value) {
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csr_writel(value, 0xe0005014);
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}
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#define CSR_USB_EV_STATUS_ADDR 0xe0005018
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#define CSR_USB_EV_STATUS_SIZE 1
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static inline unsigned char usb_ev_status_read(void) {
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unsigned char r = csr_readl(0xe0005018);
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return r;
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}
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static inline void usb_ev_status_write(unsigned char value) {
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csr_writel(value, 0xe0005018);
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}
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#define CSR_USB_EV_PENDING_ADDR 0xe000501c
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#define CSR_USB_EV_PENDING_SIZE 1
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static inline unsigned char usb_ev_pending_read(void) {
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unsigned char r = csr_readl(0xe000501c);
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return r;
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}
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static inline void usb_ev_pending_write(unsigned char value) {
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csr_writel(value, 0xe000501c);
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}
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#define CSR_USB_EV_ENABLE_ADDR 0xe0005020
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#define CSR_USB_EV_ENABLE_SIZE 1
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static inline unsigned char usb_ev_enable_read(void) {
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unsigned char r = csr_readl(0xe0005020);
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return r;
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}
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static inline void usb_ev_enable_write(unsigned char value) {
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csr_writel(value, 0xe0005020);
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}
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#define CSR_IDENTIFIER_MEM_BASE 0xe0002000
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/* constants */
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#define NMI_INTERRUPT 0
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static inline int nmi_interrupt_read(void) {
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return 0;
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}
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#define TIMER0_INTERRUPT 1
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static inline int timer0_interrupt_read(void) {
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return 1;
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}
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#define UART_INTERRUPT 2
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static inline int uart_interrupt_read(void) {
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return 2;
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}
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#define USB_INTERRUPT 3
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static inline int usb_interrupt_read(void) {
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return 3;
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}
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#define CSR_DATA_WIDTH 8
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static inline int csr_data_width_read(void) {
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return 8;
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}
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#define SYSTEM_CLOCK_FREQUENCY 12000000
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static inline int system_clock_frequency_read(void) {
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return 12000000;
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}
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#define SPIFLASH_PAGE_SIZE 256
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static inline int spiflash_page_size_read(void) {
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return 256;
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}
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#define SPIFLASH_SECTOR_SIZE 65536
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static inline int spiflash_sector_size_read(void) {
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return 65536;
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}
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#define ROM_DISABLE 1
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static inline int rom_disable_read(void) {
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return 1;
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}
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#define CONFIG_CLOCK_FREQUENCY 12000000
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static inline int config_clock_frequency_read(void) {
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return 12000000;
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}
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#define CONFIG_CPU_RESET_ADDR 0
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static inline int config_cpu_reset_addr_read(void) {
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return 0;
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}
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#define CONFIG_CPU_TYPE "VEXRISCV"
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static inline const char * config_cpu_type_read(void) {
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return "VEXRISCV";
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}
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#define CONFIG_CPU_VARIANT "VEXRISCV"
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static inline const char * config_cpu_variant_read(void) {
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return "VEXRISCV";
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}
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#define CONFIG_CSR_DATA_WIDTH 8
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static inline int config_csr_data_width_read(void) {
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return 8;
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}
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#endif
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13
include/generated/mem.h
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13
include/generated/mem.h
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@ -0,0 +1,13 @@
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#ifndef __GENERATED_MEM_H
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#define __GENERATED_MEM_H
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#define SPIFLASH_BASE 0x20000000
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#define SPIFLASH_SIZE 0x00200000
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#define SRAM_BASE 0x10000000
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#define SRAM_SIZE 0x00020000
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#define ROM_BASE 0x00000000
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#define ROM_SIZE 0x00002000
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#endif
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Block a user