xobs/foboot-bitstream
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

lxbuildenv: fix generation of initial python

Browse Source 
It still doesn't work (owing to some bit rot), but it's better now.

Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross
2019-02-18 10:48:57 +08:00
parent 68694294e1
commit f9eeee3ff7
1 changed files with 9 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
lxbuildenv.py
View File

@@ -178,6 +178,9 @@ def check_yosys(args):
def check_arachne(args): def check_arachne(args):
return check_cmd(args, "arachne-pnr") return check_cmd(args, "arachne-pnr")
def check_icestorm(args):
return check_cmd(args, "icepack") and check_cmd(args, "nextpnr-ice40")
dependency_checkers = { dependency_checkers = {
'python': check_python_version, 'python': check_python_version,
'vivado': check_vivado, 'vivado': check_vivado,
@@ -185,6 +188,7 @@ dependency_checkers = {
'riscv': check_riscv, 'riscv': check_riscv,
'yosys': check_yosys, 'yosys': check_yosys,
'arachne-pnr': check_arachne, 'arachne-pnr': check_arachne,
'icestorm': check_icestorm,
} }
# Validate that the required dependencies (Vivado, compilers, etc.) # Validate that the required dependencies (Vivado, compilers, etc.)
@@ -361,7 +365,11 @@ import lxbuildenv
#pylint:disable=E1101 #pylint:disable=E1101
from migen import * from migen import *
from litex.build.generic_platform import * from litex.build.xilinx import VivadoProgrammer, XilinxPlatform
from litex.build.generic_platform import Pins, IOStandard
from litex.soc.integration import SoCSDRAM
from litex.soc.integration.builder import Builder
from litex.soc.integration.soc_core import csr_map_update
_io = [ _io = [
("clk50", 0, Pins("J19"), IOStandard("LVCMOS33")), ("clk50", 0, Pins("J19"), IOStandard("LVCMOS33")),