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@ -82,14 +82,29 @@ class _CRG(Module):
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]
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class RandomFirmwareROM(wishbone.SRAM):
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"""
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Seed the random data with a fixed number, so different bitstreams
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can all share firmware.
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"""
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def __init__(self, size, seed=2373):
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import random
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# Seed the random data with a fixed number, so different bitstreams
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# can all share firmware.
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random.seed(seed)
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def xorshift32(x):
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x = x ^ (x << 13) & 0xffffffff
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x = x ^ (x >> 17) & 0xffffffff
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x = x ^ (x << 5) & 0xffffffff
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return x & 0xffffffff
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def get_rand(x):
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out = 0
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for i in range(32):
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x = xorshift32(x)
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if (x & 1) == 1:
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out = out | (1 << i)
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return out & 0xffffffff
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data = []
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seed = 1
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for d in range(int(size / 4)):
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data.append(random.getrandbits(32))
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seed = get_rand(seed)
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data.append(seed)
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print("Firmware {} bytes of random data".format(size))
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wishbone.SRAM.__init__(self, size, read_only=True, init=data)
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