logic: add example of synthesis

Signed-off-by: Sean Cross <sean@xobs.io>

index.html

@@ -110,17 +110,19 @@
 				</section>
 				<section>
 					<h2>Digital logic overview (Today)</h2>
+					<div class="r-hstack">
 						<pre data-id="code-animation"><code class="hljs verilog" data-trim data-line-numbers>
-						module inverter(input clk, input [15:0] A, output [15:0] X);
-							reg [15:0] R;
-							assign X = R;
-							always @(posedge clk)
-							begin
-								R <= ~A;
-							end
+						module and_four(input A, input B,
+													  input C, input D,
+													  output X);
+							assign X = A & B & C & D;
 						endmodule
 					</code></pre>
-					<img data-src="img/gf180mcu_fd_sc_mcu7t5v0__inv_16.layout.png">
+						<div class="r-vstack">
+							<img data-src="img/boolean-4.png">
+							<img data-src="img/boolean-1.png">
+						</div>
+					</div>
 				</section>
 
 				<section>