diff --git a/img/boolean-1.png b/img/boolean-1.png new file mode 100644 index 0000000..b5bb77e Binary files /dev/null and b/img/boolean-1.png differ diff --git a/img/boolean-4.png b/img/boolean-4.png new file mode 100644 index 0000000..cf8ab70 Binary files /dev/null and b/img/boolean-4.png differ diff --git a/index.html b/index.html index 8df2333..30954a0 100644 --- a/index.html +++ b/index.html @@ -9,7 +9,7 @@ - + @@ -17,9 +17,9 @@
- +

The State of Open Silicon

@@ -110,17 +110,19 @@

Digital logic overview (Today)

-

-						module inverter(input clk, input [15:0] A, output [15:0] X);
-							reg [15:0] R;
-							assign X = R;
-							always @(posedge clk)
-							begin
-								R <= ~A;
-							end
+					
+

+						module and_four(input A, input B,
+													  input C, input D,
+													  output X);
+							assign X = A & B & C & D;
 						endmodule
 					
- +
+ + +
+
@@ -381,97 +383,97 @@
- - - - - - + + + + +