verilog: use a wider example and include an img

Browse Source

Signed-off-by: Sean Cross <sean@xobs.io>

...

This commit is contained in:

Sean Cross

2019-06-18 16:06:09 -07:00

parent 9901b83844

commit 03aab024d6

2 changed files with 12 additions and 11 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download Patch File Download Diff File Expand all files Collapse all files

BIN

img/verilog-synthesis.png Normal file

Binary file not shown.

Side by Side After Width:  |  Height:  |  Size: 14 KiB