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What is an FPGA?


-							module DFF (output reg Q, input C, D, R);
-								always @(posedge C)
-								if (~R) begin
-									Q <= 1'b0;
-								end else begin
-									Q <= D;
-								end
-							endmodule						  
-						
+ module example (output reg [0:5] Q, input C); + reg [0:8] counter; + always @(posedge C) + begin + counter <= counter + 1'b1; + Q = counter[7] ^ counter[5] | counter<<2; + end + endmodule + + Verilog Synthesis
@@ -172,10 +173,10 @@
  • 5280 4-input LUTs (LC)
  • 16 kilobytes BRAM
  • 128 kilobytes "SPRAM"
  • -
  • Current-limited 3-channel LED
  • +
  • Current-limited 3-channel LED driver
  • 2x I2C and 2x SPI
  • 8 16-bit DSP units
  • -
  • Warmboot capability
  • +
  • Warmboot capability