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platform: first working irq test

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This now has interrupts working.

Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross
2019-12-19 12:17:38 +08:00
parent 607a91f06e
commit 74fb4b855e
2 changed files with 12 additions and 10 deletions
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1
boot.resc
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@@ -1,6 +1,7 @@
using sysbus using sysbus
mach create mach create
machine LoadPlatformDescription @platonic.repl machine LoadPlatformDescription @platonic.repl
sysbus LoadELF @../kernel/target/riscv32i-unknown-none-elf/debug/xous-kernel
machine StartGdbServer 3333 machine StartGdbServer 3333

17
platonic.repl
View File

@@ -1,7 +1,13 @@
cpu: CPU.VexRiscv @ sysbus
timeProvider: cpu_timer
cpuType: "rv32imac"
privilegeArchitecture: PrivilegeArchitecture.Priv1_10
uart: UART.LiteX_UART @ { uart: UART.LiteX_UART @ {
sysbus 0x60001800; sysbus 0x60001800;
sysbus 0xE0001800 // shadow sysbus 0xE0001800 // shadow
} }
-> cpu@2
rom: Memory.MappedMemory @ { rom: Memory.MappedMemory @ {
sysbus 0x00000000; sysbus 0x00000000;
@@ -10,15 +16,10 @@ rom: Memory.MappedMemory @ {
size: 0x00002000 size: 0x00002000
sram: Memory.MappedMemory @ { sram: Memory.MappedMemory @ {
sysbus 0x10000000; sysbus 0x40000000;
sysbus 0x90000000 // shadow sysbus 0xc0000000 // shadow
} }
size: 0x00020000 size: 16777216
cpu: CPU.VexRiscv @ sysbus
timeProvider: cpu_timer
cpuType: "rv32ima"
privilegeArchitecture: PrivilegeArchitecture.Priv1_10
cpu_timer: Timers.LiteX_CPUTimer @ sysbus 0xf0000800 cpu_timer: Timers.LiteX_CPUTimer @ sysbus 0xf0000800
frequency: 66000000 frequency: 66000000