90 lines
1.9 KiB
Rust
90 lines
1.9 KiB
Rust
use core::fmt::{Error, Write};
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#[macro_export]
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macro_rules! print
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{
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($($args:tt)+) => ({
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use core::fmt::Write;
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let _ = write!(crate::debug::DEFAULT_UART, $($args)+);
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});
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}
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#[macro_export]
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macro_rules! println
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{
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() => ({
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print!("\r\n")
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});
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($fmt:expr) => ({
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print!(concat!($fmt, "\r\n"))
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});
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($fmt:expr, $($args:tt)+) => ({
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print!(concat!($fmt, "\r\n"), $($args)+)
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});
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}
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pub struct Uart {
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base: *mut usize,
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}
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pub const DEFAULT_UART: Uart = Uart {
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base: 0xE000_1800 as *mut usize,
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};
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impl Uart {
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// pub fn new(base_addr: usize) -> Uart {
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// Uart {
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// base: base_addr as *mut usize,
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// }
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// }
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pub fn enable_rx(self) {
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unsafe {
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self.base
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.add(5)
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.write_volatile(self.base.add(5).read_volatile() | 2)
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};
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}
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pub fn putc(&self, c: u8) {
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unsafe {
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// Wait until TXFULL is `0`
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while self.base.add(1).read_volatile() != 0 {
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()
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}
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self.base.add(0).write_volatile(c as usize)
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};
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}
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pub fn getc(&self) -> Option<u8> {
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unsafe {
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// If EV_PENDING_RX is 1, return the pending character.
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// Otherwise, return None.
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match self.base.add(4).read_volatile() & 2 {
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0 => None,
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ack => {
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let c = Some(self.base.add(0).read_volatile() as u8);
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self.base.add(4).write_volatile(ack);
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c
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}
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}
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}
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}
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}
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pub fn irq(irq_number: usize) {
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println!(
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"Interrupt {}: Key pressed: {}",
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irq_number,
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DEFAULT_UART.getc().unwrap() as char
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);
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}
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impl Write for Uart {
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fn write_str(&mut self, s: &str) -> Result<(), Error> {
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for c in s.bytes() {
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self.putc(c);
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}
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Ok(())
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}
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}
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