111 lines
2.3 KiB
Rust
111 lines
2.3 KiB
Rust
//! satp register
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#[cfg(riscv)]
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use bit_field::BitField;
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/// satp register
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#[derive(Clone, Copy, Debug)]
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pub struct Satp {
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bits: usize,
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}
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impl Satp {
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/// Returns the contents of the register as raw bits
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#[inline]
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pub fn bits(&self) -> usize {
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self.bits
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}
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/// Current address-translation scheme
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#[inline]
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#[cfg(riscv32)]
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pub fn mode(&self) -> Mode {
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match self.bits.get_bit(31) {
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false => Mode::Bare,
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true => Mode::Sv32,
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}
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}
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/// Current address-translation scheme
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#[inline]
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#[cfg(riscv64)]
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pub fn mode(&self) -> Mode {
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match self.bits.get_bits(60..64) {
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0 => Mode::Bare,
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8 => Mode::Sv39,
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9 => Mode::Sv48,
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10 => Mode::Sv57,
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11 => Mode::Sv64,
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_ => unreachable!(),
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}
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}
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/// Address space identifier
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#[inline]
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#[cfg(riscv32)]
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pub fn asid(&self) -> usize {
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self.bits.get_bits(22..31)
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}
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/// Address space identifier
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#[inline]
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#[cfg(riscv64)]
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pub fn asid(&self) -> usize {
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self.bits.get_bits(44..60)
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}
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/// Physical page number
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#[inline]
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#[cfg(riscv32)]
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pub fn ppn(&self) -> usize {
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self.bits.get_bits(0..22)
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}
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/// Physical page number
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#[inline]
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#[cfg(riscv64)]
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pub fn ppn(&self) -> usize {
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self.bits.get_bits(0..44)
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}
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}
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#[cfg(riscv32)]
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#[derive(Clone, Copy, Debug, Eq, PartialEq)]
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pub enum Mode {
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Bare = 0,
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Sv32 = 1,
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}
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#[cfg(riscv64)]
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#[derive(Clone, Copy, Debug, Eq, PartialEq)]
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pub enum Mode {
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Bare = 0,
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Sv39 = 8,
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Sv48 = 9,
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Sv57 = 10,
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Sv64 = 11,
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}
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read_csr_as!(Satp, 0x180, __read_satp);
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write_csr!(0x180, __write_satp);
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#[inline]
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#[cfg(riscv32)]
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pub unsafe fn set(mode: Mode, asid: usize, ppn: usize) {
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let mut bits = 0usize;
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bits.set_bits(31..32, mode as usize);
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bits.set_bits(22..31, asid);
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bits.set_bits(0..22, ppn);
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_write(bits);
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}
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#[inline]
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#[cfg(riscv64)]
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pub unsafe fn set(mode: Mode, asid: usize, ppn: usize) {
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let mut bits = 0usize;
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bits.set_bits(60..64, mode as usize);
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bits.set_bits(44..60, asid);
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bits.set_bits(0..44, ppn);
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_write(bits);
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}
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