140 lines
3.6 KiB
Rust
140 lines
3.6 KiB
Rust
//! mcause register
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/// mcause register
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#[derive(Clone, Copy, Debug)]
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pub struct Mcause {
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bits: usize,
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}
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/// Trap Cause
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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pub enum Trap {
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Interrupt(Interrupt),
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Exception(Exception),
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}
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/// Interrupt
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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pub enum Interrupt {
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UserSoft,
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SupervisorSoft,
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MachineSoft,
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UserTimer,
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SupervisorTimer,
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MachineTimer,
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UserExternal,
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SupervisorExternal,
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MachineExternal,
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Unknown,
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}
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/// Exception
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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pub enum Exception {
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InstructionMisaligned,
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InstructionFault,
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IllegalInstruction,
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Breakpoint,
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LoadMisaligned,
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LoadFault,
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StoreMisaligned,
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StoreFault,
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UserEnvCall,
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SupervisorEnvCall,
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MachineEnvCall,
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InstructionPageFault,
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LoadPageFault,
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StorePageFault,
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Unknown,
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}
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impl Interrupt {
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pub fn from(nr: usize) -> Self {
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match nr {
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0 => Interrupt::UserSoft,
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1 => Interrupt::SupervisorSoft,
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3 => Interrupt::MachineSoft,
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4 => Interrupt::UserTimer,
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5 => Interrupt::SupervisorTimer,
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7 => Interrupt::MachineTimer,
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8 => Interrupt::UserExternal,
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9 => Interrupt::SupervisorExternal,
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11 => Interrupt::MachineExternal,
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_ => Interrupt::Unknown,
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}
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}
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}
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impl Exception {
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pub fn from(nr: usize) -> Self {
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match nr {
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0 => Exception::InstructionMisaligned,
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1 => Exception::InstructionFault,
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2 => Exception::IllegalInstruction,
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3 => Exception::Breakpoint,
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4 => Exception::LoadMisaligned,
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5 => Exception::LoadFault,
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6 => Exception::StoreMisaligned,
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7 => Exception::StoreFault,
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8 => Exception::UserEnvCall,
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9 => Exception::SupervisorEnvCall,
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11 => Exception::MachineEnvCall,
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12 => Exception::InstructionPageFault,
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13 => Exception::LoadPageFault,
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15 => Exception::StorePageFault,
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_ => Exception::Unknown,
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}
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}
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}
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impl Mcause {
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/// Returns the contents of the register as raw bits
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#[inline]
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pub fn bits(&self) -> usize {
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self.bits
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}
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/// Returns the code field
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pub fn code(&self) -> usize {
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match () {
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#[cfg(target_pointer_width = "32")]
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() => self.bits & !(1 << 31),
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#[cfg(target_pointer_width = "64")]
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() => self.bits & !(1 << 63),
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#[cfg(target_pointer_width = "128")]
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() => self.bits & !(1 << 127),
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}
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}
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/// Trap Cause
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#[inline]
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pub fn cause(&self) -> Trap {
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if self.is_interrupt() {
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Trap::Interrupt(Interrupt::from(self.code()))
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} else {
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Trap::Exception(Exception::from(self.code()))
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}
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}
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/// Is trap cause an interrupt.
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#[inline]
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pub fn is_interrupt(&self) -> bool {
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match () {
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#[cfg(target_pointer_width = "32")]
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() => self.bits & (1 << 31) == 1 << 31,
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#[cfg(target_pointer_width = "64")]
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() => self.bits & (1 << 63) == 1 << 63,
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#[cfg(target_pointer_width = "128")]
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() => self.bits & (1 << 127) == 1 << 127,
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}
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}
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/// Is trap cause an exception.
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#[inline]
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pub fn is_exception(&self) -> bool {
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!self.is_interrupt()
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}
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}
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read_csr_as!(Mcause, 0x342, __read_mcause);
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