irq commit: this large commit gets interrupts working

Signed-off-by: Sean Cross <sean@xobs.io>

xous-riscv/asm.S

@@ -315,3 +315,10 @@ RW(0x7A3, tdata3)   // Third Debug/Trace trigger data register
 RW(0x7B0, dcsr)     // Debug control and status register
 RW(0x7B1, dpc)      // Debug PC
 RW(0x7B2, dscratch) // Debug scratch register
+
+// VexRiscv custom registers
+RW(0xBC0, vmim)     // Machine IRQ Mask
+RW(0xFC0, vmip)     // Machine IRQ Pending
+RW(0x9C0, vsim)     // Supervisor IRQ Mask
+RW(0xDC0, vsip)     // Supervisor IRQ Pending
+RW(0xCC0, vdci)     // DCache Info

xous-riscv/src/register/mod.rs

@@ -107,3 +107,10 @@ pub use self::mhpmeventx::*;
 
 
 // TODO: Debug Mode Registers
+
+// VexRiscv registers
+pub mod vmim;
+pub mod vmip;
+pub mod vsim;
+pub mod vsip;
+pub mod vdci;

xous-riscv/src/register/vdci.rs

@@ -0,0 +1,4 @@
+//! uscratch register
+
+read_csr_as_usize!(0xCC0, __read_vdci);
+write_csr_as_usize!(0xCC0, __write_vdci);

xous-riscv/src/register/vmim.rs

@@ -0,0 +1,4 @@
+//! uscratch register
+
+read_csr_as_usize!(0xBC0, __read_vmim);
+write_csr_as_usize!(0xBC0, __write_vmim);

xous-riscv/src/register/vmip.rs

@@ -0,0 +1,4 @@
+//! uscratch register
+
+read_csr_as_usize!(0xFC0, __read_vmip);
+write_csr_as_usize!(0xFC0, __write_vmip);

xous-riscv/src/register/vsim.rs

@@ -0,0 +1,4 @@
+//! uscratch register
+
+read_csr_as_usize!(0x9C0, __read_vsim);
+write_csr_as_usize!(0x9C0, __write_vsim);

xous-riscv/src/register/vsip.rs

@@ -0,0 +1,4 @@
+//! uscratch register
+
+read_csr_as_usize!(0xDC0, __read_vsip);
+write_csr_as_usize!(0xDC0, __write_vsip);