Sean Cross
30b7610996
We have spare pins, so run more debug wires. Many of these will probably get cut when doing the PCB layout. Signed-off-by: Sean Cross <sean@xobs.io> |
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FPGA-DS-02008-1-5-iCE40-UltraPlus-Family-Data-Sheet.pdf | ||
FPGA-iCE40UP 5k Pinout.xlsx | ||
FPGA-PackageDiagrams.pdf | ||
FPGA-TN-1074-PCBLayoutRecommendationsforBGAPackages.pdf | ||
FPGA-TN-1251-iCE40sysCLOCKPLLDesignandUsageGuide.pdf | ||
FPGA-TN-1252-iCE40HardwareChecklist.pdf | ||
FPGA-TN-1288-ICE40LEDDriverUsageGuide.pdf | ||
FPGA-TN-02001-3-1-iCE40-Programming-Configuration.pdf | ||
FPGA-TN--2008-iCE40OscillatorUsageGuide.pdf | ||
LDO-lp5907.pdf | ||
LDO-MIC550x-300mA-Single-Output-LDO-in-Small-Packages-DS20006006A.pdf | ||
LED-5ds-uhd1110-fka.pdf | ||
OSC-MEMS-20005625B.pdf | ||
SPI-w25q128jv_dtr revc 03272018 plus.pdf | ||
tomu-fpga-evt1.pdf | ||
XTAL-ECS-2520MV.pdf |