212 lines
6.7 KiB
C
212 lines
6.7 KiB
C
/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved.
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*
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* The information contained herein is property of Nordic Semiconductor ASA.
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* Terms and conditions of usage are described in detail in NORDIC
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* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
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*
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* Licensees are granted free, non-transferable use of the information. NO
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* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
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* the file.
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*
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*/
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/**@file
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*
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* @defgroup app_util_platform Utility Functions and Definitions (Platform)
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* @{
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* @ingroup app_common
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*
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* @brief Various types and definitions available to all applications when using SoftDevice.
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*/
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#ifndef APP_UTIL_PLATFORM_H__
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#define APP_UTIL_PLATFORM_H__
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#include <stdint.h>
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#include "compiler_abstraction.h"
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#include "nrf.h"
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#ifdef SOFTDEVICE_PRESENT
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#include "nrf_soc.h"
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#include "nrf_nvic.h"
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#endif
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#include "nrf_assert.h"
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#include "app_error.h"
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#if defined(NRF51)
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#define _PRIO_SD_HIGH 0
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#define _PRIO_APP_HIGH 1
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#define _PRIO_APP_MID 1
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#define _PRIO_SD_LOW 2
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#define _PRIO_APP_LOW 3
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#define _PRIO_APP_LOWEST 3
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#define _PRIO_THREAD 4
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#elif defined(NRF52)
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#define _PRIO_SD_HIGH 0
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#define _PRIO_SD_MID 1
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#define _PRIO_APP_HIGH 2
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#define _PRIO_APP_MID 3
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#define _PRIO_SD_LOW 4
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#define _PRIO_SD_LOWEST 5
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#define _PRIO_APP_LOW 6
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#define _PRIO_APP_LOWEST 7
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#define _PRIO_THREAD 15
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#else
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#error "No platform defined"
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#endif
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/**@brief The interrupt priorities available to the application while the SoftDevice is active. */
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typedef enum
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{
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#ifdef SOFTDEVICE_PRESENT
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APP_IRQ_PRIORITY_HIGHEST = _PRIO_SD_HIGH,
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#else
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APP_IRQ_PRIORITY_HIGHEST = _PRIO_APP_HIGH,
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#endif
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APP_IRQ_PRIORITY_HIGH = _PRIO_APP_HIGH,
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#ifndef SOFTDEVICE_PRESENT
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APP_IRQ_PRIORITY_MID = _PRIO_SD_LOW,
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#else
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APP_IRQ_PRIORITY_MID = _PRIO_APP_MID,
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#endif
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APP_IRQ_PRIORITY_LOW = _PRIO_APP_LOW,
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APP_IRQ_PRIORITY_LOWEST = _PRIO_APP_LOWEST,
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APP_IRQ_PRIORITY_THREAD = _PRIO_THREAD /**< "Interrupt level" when running in Thread Mode. */
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} app_irq_priority_t;
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/*@brief The privilege levels available to applications in Thread Mode */
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typedef enum
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{
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APP_LEVEL_UNPRIVILEGED,
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APP_LEVEL_PRIVILEGED
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} app_level_t;
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/**@cond NO_DOXYGEN */
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#define EXTERNAL_INT_VECTOR_OFFSET 16
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/**@endcond */
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#define PACKED(TYPE) __packed TYPE
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void app_util_critical_region_enter (uint8_t *p_nested);
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void app_util_critical_region_exit (uint8_t nested);
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/**@brief Macro for entering a critical region.
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*
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* @note Due to implementation details, there must exist one and only one call to
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* CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located
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* in the same scope.
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*/
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#ifdef SOFTDEVICE_PRESENT
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#define CRITICAL_REGION_ENTER() \
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{ \
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uint8_t __CR_NESTED = 0; \
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app_util_critical_region_enter(&__CR_NESTED);
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#else
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#define CRITICAL_REGION_ENTER() app_util_critical_region_enter(NULL)
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#endif
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/**@brief Macro for leaving a critical region.
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*
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* @note Due to implementation details, there must exist one and only one call to
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* CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located
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* in the same scope.
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*/
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#ifdef SOFTDEVICE_PRESENT
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#define CRITICAL_REGION_EXIT() \
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app_util_critical_region_exit(__CR_NESTED); \
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}
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#else
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#define CRITICAL_REGION_EXIT() app_util_critical_region_exit(0)
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#endif
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/* Workaround for Keil 4 */
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#ifndef IPSR_ISR_Msk
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#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
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#endif
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/**@brief Macro to enable anonymous unions from a certain point in the code.
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*/
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#if defined(__CC_ARM)
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#define ANON_UNIONS_ENABLE _Pragma("push") \
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_Pragma("anon_unions")
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#elif defined(__ICCARM__)
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#define ANON_UNIONS_ENABLE _Pragma("language=extended")
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#else
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#define ANON_UNIONS_ENABLE
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// No action will be taken.
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// For GCC anonymous unions are enabled by default.
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#endif
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/**@brief Macro to disable anonymous unions from a certain point in the code.
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* @note Call only after first calling @ref ANON_UNIONS_ENABLE.
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*/
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#if defined(__CC_ARM)
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#define ANON_UNIONS_DISABLE _Pragma("pop")
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#elif defined(__ICCARM__)
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#define ANON_UNIONS_DISABLE
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// for IAR leave anonymous unions enabled
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#else
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#define ANON_UNIONS_DISABLE
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// No action will be taken.
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// For GCC anonymous unions are enabled by default.
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#endif
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/* Workaround for Keil 4 */
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#ifndef CONTROL_nPRIV_Msk
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#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
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#endif
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/**@brief Function for finding the current interrupt level.
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*
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* @return Current interrupt level.
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* @retval APP_IRQ_PRIORITY_HIGH We are running in Application High interrupt level.
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* @retval APP_IRQ_PRIORITY_LOW We are running in Application Low interrupt level.
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* @retval APP_IRQ_PRIORITY_THREAD We are running in Thread Mode.
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*/
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static __INLINE uint8_t current_int_priority_get(void)
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{
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uint32_t isr_vector_num = __get_IPSR() & IPSR_ISR_Msk ;
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if (isr_vector_num > 0)
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{
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int32_t irq_type = ((int32_t)isr_vector_num - EXTERNAL_INT_VECTOR_OFFSET);
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return (NVIC_GetPriority((IRQn_Type)irq_type) & 0xFF);
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}
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else
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{
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return APP_IRQ_PRIORITY_THREAD;
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}
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}
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/**@brief Function for finding out the current privilege level.
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*
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* @return Current privilege level.
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* @retval APP_LEVEL_UNPRIVILEGED We are running in unprivileged level.
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* @retval APP_LEVEL_PRIVILEGED We are running in privileged level.
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*/
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static __INLINE uint8_t privilege_level_get(void)
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{
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#if defined(NRF51)
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/* the Cortex-M0 has no concept of privilege */
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return APP_LEVEL_PRIVILEGED;
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#elif defined(NRF52)
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uint32_t isr_vector_num = __get_IPSR() & IPSR_ISR_Msk ;
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if (0 == isr_vector_num)
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{
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/* Thread Mode, check nPRIV */
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int32_t control = __get_CONTROL();
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return control & CONTROL_nPRIV_Msk ? APP_LEVEL_UNPRIVILEGED : APP_LEVEL_PRIVILEGED;
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}
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else
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{
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/* Handler Mode, always privileged */
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return APP_LEVEL_PRIVILEGED;
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}
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#endif
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}
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#endif // APP_UTIL_PLATFORM_H__
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/** @} */
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