257 lines
10 KiB
C
257 lines
10 KiB
C
/*
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Copyright (c) 2009-2017 ARM Limited. All rights reserved.
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SPDX-License-Identifier: Apache-2.0
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Licensed under the Apache License, Version 2.0 (the License); you may
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not use this file except in compliance with the License.
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You may obtain a copy of the License at
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www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an AS IS BASIS, WITHOUT
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WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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NOTICE: This file has been modified by Nordic Semiconductor ASA.
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*/
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/* NOTE: Template files (including this one) are application specific and therefore expected to
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be copied into the application project folder prior to its use! */
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#include <stdint.h>
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#include <stdbool.h>
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#include "nrf.h"
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#include "system_nrf52840.h"
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/*lint ++flb "Enter library region" */
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#define __SYSTEM_CLOCK_64M (64000000UL)
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static bool errata_36(void);
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static bool errata_66(void);
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static bool errata_98(void);
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static bool errata_103(void);
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static bool errata_115(void);
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static bool errata_120(void);
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static bool errata_136(void);
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#if defined ( __CC_ARM )
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uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
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#elif defined ( __ICCARM__ )
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__root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M;
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#elif defined ( __GNUC__ )
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uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
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#endif
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void SystemCoreClockUpdate(void)
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{
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SystemCoreClock = __SYSTEM_CLOCK_64M;
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}
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void SystemInit(void)
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{
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/* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
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Specification to see which one). */
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#if defined (ENABLE_SWO)
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CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
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NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
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NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
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#endif
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/* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
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Specification to see which ones). */
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#if defined (ENABLE_TRACE)
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CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
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NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos;
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NRF_P0->PIN_CNF[7] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
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NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
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NRF_P0->PIN_CNF[12] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
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NRF_P0->PIN_CNF[11] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
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NRF_P1->PIN_CNF[9] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
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#endif
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/* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
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for your device located at https://infocenter.nordicsemi.com/ */
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if (errata_36()){
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NRF_CLOCK->EVENTS_DONE = 0;
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NRF_CLOCK->EVENTS_CTTO = 0;
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NRF_CLOCK->CTIV = 0;
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}
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/* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
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for your device located at https://infocenter.nordicsemi.com/ */
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if (errata_66()){
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NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
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NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
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NRF_TEMP->A2 = NRF_FICR->TEMP.A2;
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NRF_TEMP->A3 = NRF_FICR->TEMP.A3;
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NRF_TEMP->A4 = NRF_FICR->TEMP.A4;
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NRF_TEMP->A5 = NRF_FICR->TEMP.A5;
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NRF_TEMP->B0 = NRF_FICR->TEMP.B0;
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NRF_TEMP->B1 = NRF_FICR->TEMP.B1;
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NRF_TEMP->B2 = NRF_FICR->TEMP.B2;
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NRF_TEMP->B3 = NRF_FICR->TEMP.B3;
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NRF_TEMP->B4 = NRF_FICR->TEMP.B4;
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NRF_TEMP->B5 = NRF_FICR->TEMP.B5;
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NRF_TEMP->T0 = NRF_FICR->TEMP.T0;
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NRF_TEMP->T1 = NRF_FICR->TEMP.T1;
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NRF_TEMP->T2 = NRF_FICR->TEMP.T2;
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NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
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NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
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}
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/* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document
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for your device located at https://infocenter.nordicsemi.com/ */
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if (errata_98()){
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*(volatile uint32_t *)0x4000568Cul = 0x00038148ul;
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}
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/* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document
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for your device located at https://infocenter.nordicsemi.com/ */
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if (errata_103()){
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NRF_CCM->MAXPACKETSIZE = 0xFBul;
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}
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/* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
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for your device located at https://infocenter.nordicsemi.com/ */
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if (errata_115()){
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*(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F);
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}
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/* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document
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for your device located at https://infocenter.nordicsemi.com/ */
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if (errata_120()){
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*(volatile uint32_t *)0x40029640ul = 0x200ul;
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}
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/* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
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for your device located at https://infocenter.nordicsemi.com/ */
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if (errata_136()){
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if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
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NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk;
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}
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}
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/* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
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* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
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* operations are not used in your code. */
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#if (__FPU_USED == 1)
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SCB->CPACR |= (3UL << 20) | (3UL << 22);
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__DSB();
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__ISB();
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#endif
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/* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
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two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
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normal GPIOs. */
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#if defined (CONFIG_NFCT_PINS_AS_GPIOS)
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if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
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NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
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while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
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NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
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while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
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NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
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while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
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NVIC_SystemReset();
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}
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#endif
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/* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
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defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
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reserved for PinReset and not available as normal GPIO. */
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#if defined (CONFIG_GPIO_AS_PINRESET)
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if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
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((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
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NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
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while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
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NRF_UICR->PSELRESET[0] = 18;
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while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
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NRF_UICR->PSELRESET[1] = 18;
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while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
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NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
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while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
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NVIC_SystemReset();
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}
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#endif
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SystemCoreClockUpdate();
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}
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static bool errata_36(void)
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{
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if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
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return true;
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}
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return false;
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}
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static bool errata_66(void)
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{
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if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
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return true;
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}
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return false;
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}
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static bool errata_98(void)
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{
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if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
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return true;
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}
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return false;
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}
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static bool errata_103(void)
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{
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if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
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return true;
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}
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return false;
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}
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static bool errata_115(void)
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{
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if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
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return true;
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}
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return false;
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}
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static bool errata_120(void)
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{
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if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
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return true;
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}
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return false;
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}
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static bool errata_136(void)
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{
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if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
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return true;
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}
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return false;
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}
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/*lint --flb "Leave library region" */
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