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@ -106,7 +106,7 @@ enum { BLE_CONN_CFG_HIGH_BANDWIDTH = 1 };
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// Adafruit for factory reset
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#define APPDATA_ADDR_START (BOOTLOADER_REGION_START-DFU_APP_DATA_RESERVED)
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STATIC_ASSERT( APPDATA_ADDR_START == 0x6D000);
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STATIC_ASSERT( APPDATA_ADDR_START == 0xED000);
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void adafruit_factory_reset(void);
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volatile bool _freset_erased_complete = false;
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@ -104,7 +104,6 @@ C_SOURCE_FILES += $(SDK_PATH)/libraries/hci/hci_transport.c
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C_SOURCE_FILES += $(SDK_PATH)/libraries/util/nrf_assert.c
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C_SOURCE_FILES += $(SDK_PATH)/libraries/uart/app_uart.c
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C_SOURCE_FILES += $(SDK_PATH)/drivers_nrf/delay/nrf_delay.c
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C_SOURCE_FILES += $(SDK_PATH)/drivers_nrf/common/nrf_drv_common.c
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C_SOURCE_FILES += $(SDK_PATH)/drivers_nrf/uart/nrf_drv_uart.c
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@ -115,7 +114,7 @@ C_SOURCE_FILES += $(SDK_PATH)/ble/ble_services/ble_dfu/ble_dfu.c
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C_SOURCE_FILES += $(SDK_PATH)/ble/ble_services/ble_dis/ble_dis.c
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C_SOURCE_FILES += $(SDK_PATH)/drivers_nrf/pstorage/pstorage_raw.c
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C_SOURCE_FILES += $(SDK_PATH)/toolchain/system_nrf52.c
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C_SOURCE_FILES += $(SDK_PATH)/toolchain/system_nrf52840.c
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C_SOURCE_FILES += ../../softdevice/common/softdevice_handler/softdevice_handler.c
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C_SOURCE_FILES += ../../softdevice/common/softdevice_handler/softdevice_handler_appsh.c
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@ -125,7 +124,7 @@ C_SOURCE_FILES += ../../softdevice/common/softdevice_handler/softdevice_handler_
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#******************************************************************************
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# Assembly Files
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#******************************************************************************
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ASM_SOURCE_FILES = $(SDK_PATH)/toolchain/gcc/gcc_startup_nrf52.S
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ASM_SOURCE_FILES = $(SDK_PATH)/toolchain/gcc/gcc_startup_nrf52840.S
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#******************************************************************************
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# INCLUDE PATH
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@ -1,464 +0,0 @@
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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
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*
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* The information contained herein is property of Nordic Semiconductor ASA.
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* Terms and conditions of usage are described in detail in NORDIC
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* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
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*
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* Licensees are granted free, non-transferable use of the information. NO
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* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
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* the file.
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*
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*/
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#ifndef NRF_DRV_CONFIG_H
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#define NRF_DRV_CONFIG_H
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/**
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* Provide a non-zero value here in applications that need to use several
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* peripherals with the same ID that are sharing certain resources
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* (for example, SPI0 and TWI0). Obviously, such peripherals cannot be used
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* simultaneously. Therefore, this definition allows to initialize the driver
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* for another peripheral from a given group only after the previously used one
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* is uninitialized. Normally, this is not possible, because interrupt handlers
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* are implemented in individual drivers.
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* This functionality requires a more complicated interrupt handling and driver
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* initialization, hence it is not always desirable to use it.
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*/
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#define PERIPHERAL_RESOURCE_SHARING_ENABLED 0
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/* CLOCK */
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#define CLOCK_ENABLED 0
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#if (CLOCK_ENABLED == 1)
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#define CLOCK_CONFIG_XTAL_FREQ NRF_CLOCK_XTALFREQ_Default
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#define CLOCK_CONFIG_LF_SRC NRF_CLOCK_LFCLK_Xtal
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#define CLOCK_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#endif
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/* GPIOTE */
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#define GPIOTE_ENABLED 0
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#if (GPIOTE_ENABLED == 1)
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#define GPIOTE_CONFIG_USE_SWI_EGU false
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#define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1
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#endif
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/* TIMER */
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#define TIMER0_ENABLED 0
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#if (TIMER0_ENABLED == 1)
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#define TIMER0_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
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#define TIMER0_CONFIG_MODE TIMER_MODE_MODE_Timer
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#define TIMER0_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_32Bit
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#define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define TIMER0_INSTANCE_INDEX 0
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#endif
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#define TIMER1_ENABLED 0
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#if (TIMER1_ENABLED == 1)
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#define TIMER1_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
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#define TIMER1_CONFIG_MODE TIMER_MODE_MODE_Timer
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#define TIMER1_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
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#define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define TIMER1_INSTANCE_INDEX (TIMER0_ENABLED)
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#endif
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#define TIMER2_ENABLED 0
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#if (TIMER2_ENABLED == 1)
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#define TIMER2_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
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#define TIMER2_CONFIG_MODE TIMER_MODE_MODE_Timer
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#define TIMER2_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
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#define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define TIMER2_INSTANCE_INDEX (TIMER1_ENABLED+TIMER0_ENABLED)
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#endif
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#define TIMER3_ENABLED 0
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#if (TIMER3_ENABLED == 1)
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#define TIMER3_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
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#define TIMER3_CONFIG_MODE TIMER_MODE_MODE_Timer
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#define TIMER3_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
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#define TIMER3_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define TIMER3_INSTANCE_INDEX (TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
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#endif
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#define TIMER4_ENABLED 0
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#if (TIMER4_ENABLED == 1)
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#define TIMER4_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
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#define TIMER4_CONFIG_MODE TIMER_MODE_MODE_Timer
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#define TIMER4_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
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#define TIMER4_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define TIMER4_INSTANCE_INDEX (TIMER3_ENABLED+TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
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#endif
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#define TIMER_COUNT (TIMER0_ENABLED + TIMER1_ENABLED + TIMER2_ENABLED + TIMER3_ENABLED + TIMER4_ENABLED)
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/* RTC */
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#define RTC0_ENABLED 0
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#if (RTC0_ENABLED == 1)
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#define RTC0_CONFIG_FREQUENCY 32678
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#define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define RTC0_CONFIG_RELIABLE false
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#define RTC0_INSTANCE_INDEX 0
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#endif
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#define RTC1_ENABLED 0
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#if (RTC1_ENABLED == 1)
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#define RTC1_CONFIG_FREQUENCY 32768
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#define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define RTC1_CONFIG_RELIABLE false
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#define RTC1_INSTANCE_INDEX (RTC0_ENABLED)
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#endif
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#define RTC2_ENABLED 0
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#if (RTC2_ENABLED == 1)
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#define RTC2_CONFIG_FREQUENCY 32768
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#define RTC2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define RTC2_CONFIG_RELIABLE false
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#define RTC2_INSTANCE_INDEX (RTC0_ENABLED+RTC1_ENABLED)
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#endif
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#define RTC_COUNT (RTC0_ENABLED+RTC1_ENABLED+RTC2_ENABLED)
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#define NRF_MAXIMUM_LATENCY_US 2000
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/* RNG */
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#define RNG_ENABLED 0
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#if (RNG_ENABLED == 1)
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#define RNG_CONFIG_ERROR_CORRECTION true
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#define RNG_CONFIG_POOL_SIZE 8
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#define RNG_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#endif
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/* PWM */
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#define PWM0_ENABLED 0
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#if (PWM0_ENABLED == 1)
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#define PWM0_CONFIG_OUT0_PIN 2
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#define PWM0_CONFIG_OUT1_PIN 3
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#define PWM0_CONFIG_OUT2_PIN 4
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#define PWM0_CONFIG_OUT3_PIN 5
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#define PWM0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define PWM0_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
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#define PWM0_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
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#define PWM0_CONFIG_TOP_VALUE 1000
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#define PWM0_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
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#define PWM0_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
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#define PWM0_INSTANCE_INDEX 0
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#endif
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#define PWM1_ENABLED 0
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#if (PWM1_ENABLED == 1)
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#define PWM1_CONFIG_OUT0_PIN 2
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#define PWM1_CONFIG_OUT1_PIN 3
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#define PWM1_CONFIG_OUT2_PIN 4
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#define PWM1_CONFIG_OUT3_PIN 5
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#define PWM1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define PWM1_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
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#define PWM1_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
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#define PWM1_CONFIG_TOP_VALUE 1000
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#define PWM1_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
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#define PWM1_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
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#define PWM1_INSTANCE_INDEX (PWM0_ENABLED)
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#endif
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#define PWM2_ENABLED 0
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#if (PWM2_ENABLED == 1)
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#define PWM2_CONFIG_OUT0_PIN 2
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#define PWM2_CONFIG_OUT1_PIN 3
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#define PWM2_CONFIG_OUT2_PIN 4
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#define PWM2_CONFIG_OUT3_PIN 5
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#define PWM2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define PWM2_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
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#define PWM2_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
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#define PWM2_CONFIG_TOP_VALUE 1000
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#define PWM2_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
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#define PWM2_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
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#define PWM2_INSTANCE_INDEX (PWM0_ENABLED + PWM1_ENABLED)
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#endif
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#define PWM_COUNT (PWM0_ENABLED + PWM1_ENABLED + PWM2_ENABLED)
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/* SPI */
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#define SPI0_ENABLED 0
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#if (SPI0_ENABLED == 1)
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#define SPI0_USE_EASY_DMA 0
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#define SPI0_CONFIG_SCK_PIN 2
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#define SPI0_CONFIG_MOSI_PIN 3
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#define SPI0_CONFIG_MISO_PIN 4
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#define SPI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define SPI0_INSTANCE_INDEX 0
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#endif
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#define SPI1_ENABLED 0
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#if (SPI1_ENABLED == 1)
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#define SPI1_USE_EASY_DMA 0
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#define SPI1_CONFIG_SCK_PIN 2
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#define SPI1_CONFIG_MOSI_PIN 3
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#define SPI1_CONFIG_MISO_PIN 4
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#define SPI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define SPI1_INSTANCE_INDEX (SPI0_ENABLED)
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#endif
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#define SPI2_ENABLED 0
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#if (SPI2_ENABLED == 1)
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#define SPI2_USE_EASY_DMA 0
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#define SPI2_CONFIG_SCK_PIN 2
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#define SPI2_CONFIG_MOSI_PIN 3
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#define SPI2_CONFIG_MISO_PIN 4
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#define SPI2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define SPI2_INSTANCE_INDEX (SPI0_ENABLED + SPI1_ENABLED)
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#endif
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#define SPI_COUNT (SPI0_ENABLED + SPI1_ENABLED + SPI2_ENABLED)
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/* SPIS */
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#define SPIS0_ENABLED 0
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#if (SPIS0_ENABLED == 1)
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#define SPIS0_CONFIG_SCK_PIN 2
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#define SPIS0_CONFIG_MOSI_PIN 3
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#define SPIS0_CONFIG_MISO_PIN 4
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#define SPIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define SPIS0_INSTANCE_INDEX 0
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#endif
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#define SPIS1_ENABLED 0
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#if (SPIS1_ENABLED == 1)
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#define SPIS1_CONFIG_SCK_PIN 2
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#define SPIS1_CONFIG_MOSI_PIN 3
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#define SPIS1_CONFIG_MISO_PIN 4
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#define SPIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
|
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|
||||
#define SPIS1_INSTANCE_INDEX SPIS0_ENABLED
|
||||
#endif
|
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|
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#define SPIS2_ENABLED 0
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|
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#if (SPIS2_ENABLED == 1)
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#define SPIS2_CONFIG_SCK_PIN 2
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#define SPIS2_CONFIG_MOSI_PIN 3
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#define SPIS2_CONFIG_MISO_PIN 4
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#define SPIS2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
|
||||
|
||||
#define SPIS2_INSTANCE_INDEX (SPIS0_ENABLED + SPIS1_ENABLED)
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#endif
|
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|
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#define SPIS_COUNT (SPIS0_ENABLED + SPIS1_ENABLED + SPIS2_ENABLED)
|
||||
|
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/* UART */
|
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#define UART0_ENABLED 1
|
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|
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#if (UART0_ENABLED == 1)
|
||||
#define UART0_CONFIG_HWFC NRF_UART_HWFC_DISABLED
|
||||
#define UART0_CONFIG_PARITY NRF_UART_PARITY_EXCLUDED
|
||||
#define UART0_CONFIG_BAUDRATE NRF_UART_BAUDRATE_115200
|
||||
#define UART0_CONFIG_PSEL_TXD 6
|
||||
#define UART0_CONFIG_PSEL_RXD 8
|
||||
#define UART0_CONFIG_PSEL_CTS 7
|
||||
#define UART0_CONFIG_PSEL_RTS 5
|
||||
#define UART0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
|
||||
#ifdef NRF52
|
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#define UART0_CONFIG_USE_EASY_DMA false
|
||||
//Compile time flag
|
||||
#define UART_EASY_DMA_SUPPORT 1
|
||||
#define UART_LEGACY_SUPPORT 1
|
||||
#endif //NRF52
|
||||
#endif
|
||||
|
||||
#define TWI0_ENABLED 0
|
||||
|
||||
#if (TWI0_ENABLED == 1)
|
||||
#define TWI0_USE_EASY_DMA 0
|
||||
|
||||
#define TWI0_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
|
||||
#define TWI0_CONFIG_SCL 0
|
||||
#define TWI0_CONFIG_SDA 1
|
||||
#define TWI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
|
||||
|
||||
#define TWI0_INSTANCE_INDEX 0
|
||||
#endif
|
||||
|
||||
#define TWI1_ENABLED 0
|
||||
|
||||
#if (TWI1_ENABLED == 1)
|
||||
#define TWI1_USE_EASY_DMA 0
|
||||
|
||||
#define TWI1_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
|
||||
#define TWI1_CONFIG_SCL 0
|
||||
#define TWI1_CONFIG_SDA 1
|
||||
#define TWI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
|
||||
|
||||
#define TWI1_INSTANCE_INDEX (TWI0_ENABLED)
|
||||
#endif
|
||||
|
||||
#define TWI_COUNT (TWI0_ENABLED + TWI1_ENABLED)
|
||||
|
||||
/* TWIS */
|
||||
#define TWIS0_ENABLED 0
|
||||
|
||||
#if (TWIS0_ENABLED == 1)
|
||||
#define TWIS0_CONFIG_ADDR0 0
|
||||
#define TWIS0_CONFIG_ADDR1 0 /* 0: Disabled */
|
||||
#define TWIS0_CONFIG_SCL 0
|
||||
#define TWIS0_CONFIG_SDA 1
|
||||
#define TWIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
|
||||
|
||||
#define TWIS0_INSTANCE_INDEX 0
|
||||
#endif
|
||||
|
||||
#define TWIS1_ENABLED 0
|
||||
|
||||
#if (TWIS1_ENABLED == 1)
|
||||
#define TWIS1_CONFIG_ADDR0 0
|
||||
#define TWIS1_CONFIG_ADDR1 0 /* 0: Disabled */
|
||||
#define TWIS1_CONFIG_SCL 0
|
||||
#define TWIS1_CONFIG_SDA 1
|
||||
#define TWIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
|
||||
|
||||
#define TWIS1_INSTANCE_INDEX (TWIS0_ENABLED)
|
||||
#endif
|
||||
|
||||
#define TWIS_COUNT (TWIS0_ENABLED + TWIS1_ENABLED)
|
||||
/* For more documentation see nrf_drv_twis.h file */
|
||||
#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
|
||||
/* For more documentation see nrf_drv_twis.h file */
|
||||
#define TWIS_NO_SYNC_MODE 0
|
||||
|
||||
/* QDEC */
|
||||
#define QDEC_ENABLED 0
|
||||
|
||||
#if (QDEC_ENABLED == 1)
|
||||
#define QDEC_CONFIG_REPORTPER NRF_QDEC_REPORTPER_10
|
||||
#define QDEC_CONFIG_SAMPLEPER NRF_QDEC_SAMPLEPER_16384us
|
||||
#define QDEC_CONFIG_PIO_A 1
|
||||
#define QDEC_CONFIG_PIO_B 2
|
||||
#define QDEC_CONFIG_PIO_LED 3
|
||||
#define QDEC_CONFIG_LEDPRE 511
|
||||
#define QDEC_CONFIG_LEDPOL NRF_QDEC_LEPOL_ACTIVE_HIGH
|
||||
#define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
|
||||
#define QDEC_CONFIG_DBFEN false
|
||||
#define QDEC_CONFIG_SAMPLE_INTEN false
|
||||
#endif
|
||||
|
||||
/* ADC */
|
||||
#define ADC_ENABLED 0
|
||||
|
||||
#if (ADC_ENABLED == 1)
|
||||
#define ADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
|
||||
#endif
|
||||
|
||||
|
||||
/* SAADC */
|
||||
#define SAADC_ENABLED 0
|
||||
|
||||
#if (SAADC_ENABLED == 1)
|
||||
#define SAADC_CONFIG_RESOLUTION NRF_SAADC_RESOLUTION_10BIT
|
||||
#define SAADC_CONFIG_OVERSAMPLE NRF_SAADC_OVERSAMPLE_DISABLED
|
||||
#define SAADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
|
||||
#endif
|
||||
|
||||
/* PDM */
|
||||
#define PDM_ENABLED 0
|
||||
|
||||
#if (PDM_ENABLED == 1)
|
||||
#define PDM_CONFIG_MODE NRF_PDM_MODE_MONO
|
||||
#define PDM_CONFIG_EDGE NRF_PDM_EDGE_LEFTFALLING
|
||||
#define PDM_CONFIG_CLOCK_FREQ NRF_PDM_FREQ_1032K
|
||||
#define PDM_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
|
||||
#endif
|
||||
|
||||
/* COMP */
|
||||
#define COMP_ENABLED 0
|
||||
|
||||
#if (COMP_ENABLED == 1)
|
||||
#define COMP_CONFIG_REF NRF_COMP_REF_Int1V8
|
||||
#define COMP_CONFIG_MAIN_MODE NRF_COMP_MAIN_MODE_SE
|
||||
#define COMP_CONFIG_SPEED_MODE NRF_COMP_SP_MODE_High
|
||||
#define COMP_CONFIG_HYST NRF_COMP_HYST_NoHyst
|
||||
#define COMP_CONFIG_ISOURCE NRF_COMP_ISOURCE_Off
|
||||
#define COMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
|
||||
#define COMP_CONFIG_INPUT NRF_COMP_INPUT_0
|
||||
#endif
|
||||
|
||||
/* LPCOMP */
|
||||
#define LPCOMP_ENABLED 0
|
||||
|
||||
#if (LPCOMP_ENABLED == 1)
|
||||
#define LPCOMP_CONFIG_REFERENCE NRF_LPCOMP_REF_SUPPLY_4_8
|
||||
#define LPCOMP_CONFIG_DETECTION NRF_LPCOMP_DETECT_DOWN
|
||||
#define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
|
||||
#define LPCOMP_CONFIG_INPUT NRF_LPCOMP_INPUT_0
|
||||
#endif
|
||||
|
||||
/* WDT */
|
||||
#define WDT_ENABLED 0
|
||||
|
||||
#if (WDT_ENABLED == 1)
|
||||
#define WDT_CONFIG_BEHAVIOUR NRF_WDT_BEHAVIOUR_RUN_SLEEP
|
||||
#define WDT_CONFIG_RELOAD_VALUE 2000
|
||||
#define WDT_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
|
||||
#endif
|
||||
|
||||
/* SWI EGU */
|
||||
#ifdef NRF52
|
||||
#define EGU_ENABLED 0
|
||||
#endif
|
||||
|
||||
/* I2S */
|
||||
#define I2S_ENABLED 0
|
||||
|
||||
#if (I2S_ENABLED == 1)
|
||||
#define I2S_CONFIG_SCK_PIN 22
|
||||
#define I2S_CONFIG_LRCK_PIN 23
|
||||
#define I2S_CONFIG_MCK_PIN NRF_DRV_I2S_PIN_NOT_USED
|
||||
#define I2S_CONFIG_SDOUT_PIN 24
|
||||
#define I2S_CONFIG_SDIN_PIN 25
|
||||
#define I2S_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
|
||||
#define I2S_CONFIG_MASTER NRF_I2S_MODE_MASTER
|
||||
#define I2S_CONFIG_FORMAT NRF_I2S_FORMAT_I2S
|
||||
#define I2S_CONFIG_ALIGN NRF_I2S_ALIGN_LEFT
|
||||
#define I2S_CONFIG_SWIDTH NRF_I2S_SWIDTH_16BIT
|
||||
#define I2S_CONFIG_CHANNELS NRF_I2S_CHANNELS_STEREO
|
||||
#define I2S_CONFIG_MCK_SETUP NRF_I2S_MCK_32MDIV8
|
||||
#define I2S_CONFIG_RATIO NRF_I2S_RATIO_256X
|
||||
#endif
|
||||
|
||||
#include "nrf_drv_config_validation.h"
|
||||
|
||||
#endif // NRF_DRV_CONFIG_H
|
||||
1529
src/sdk_config.h
1529
src/sdk_config.h
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user