2205 lines
304 KiB
Plaintext
2205 lines
304 KiB
Plaintext
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/----------------------------------------------------------------------------\
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| yosys -- Yosys Open SYnthesis Suite |
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| Copyright (C) 2012 - 2018 Clifford Wolf <clifford@clifford.at> |
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| Permission to use, copy, modify, and/or distribute this software for any |
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| purpose with or without fee is hereby granted, provided that the above |
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| copyright notice and this permission notice appear in all copies. |
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| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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\----------------------------------------------------------------------------/
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Yosys 0.8+ (git sha1 UNKNOWN, x86_64-w64-mingw32-g++ 7.3-posix -O3 -DNDEBUG)
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-- Parsing `memtest.v' using frontend `verilog' --
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1. Executing Verilog-2005 frontend.
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Parsing Verilog input from `memtest.v' to AST representation.
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Generating RTLIL representation for module `\memtest'.
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Warning: wire '\led_r' is assigned in a block at memtest.v:63.
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memtest.v:16: Warning: Identifier `\random_rom_dat_r' is implicitly declared.
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memtest.v:23: Warning: Identifier `\clk' is implicitly declared.
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Successfully finished Verilog frontend.
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-- Running command `synth_ice40 -top memtest -json .build/memtest.json' --
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2. Executing SYNTH_ICE40 pass.
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2.1. Executing Verilog-2005 frontend.
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Parsing Verilog input from `D:\Software\Icestorm\bin\../share/yosys/ice40/cells_sim.v' to AST representation.
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Generating RTLIL representation for module `\SB_IO'.
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Generating RTLIL representation for module `\SB_GB_IO'.
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Generating RTLIL representation for module `\SB_GB'.
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Generating RTLIL representation for module `\SB_LUT4'.
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Generating RTLIL representation for module `\SB_CARRY'.
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Generating RTLIL representation for module `\SB_DFF'.
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Generating RTLIL representation for module `\SB_DFFE'.
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Generating RTLIL representation for module `\SB_DFFSR'.
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Generating RTLIL representation for module `\SB_DFFR'.
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Generating RTLIL representation for module `\SB_DFFSS'.
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Generating RTLIL representation for module `\SB_DFFS'.
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Generating RTLIL representation for module `\SB_DFFESR'.
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Generating RTLIL representation for module `\SB_DFFER'.
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Generating RTLIL representation for module `\SB_DFFESS'.
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Generating RTLIL representation for module `\SB_DFFES'.
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Generating RTLIL representation for module `\SB_DFFN'.
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Generating RTLIL representation for module `\SB_DFFNE'.
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Generating RTLIL representation for module `\SB_DFFNSR'.
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Generating RTLIL representation for module `\SB_DFFNR'.
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Generating RTLIL representation for module `\SB_DFFNSS'.
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Generating RTLIL representation for module `\SB_DFFNS'.
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Generating RTLIL representation for module `\SB_DFFNESR'.
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Generating RTLIL representation for module `\SB_DFFNER'.
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Generating RTLIL representation for module `\SB_DFFNESS'.
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Generating RTLIL representation for module `\SB_DFFNES'.
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Generating RTLIL representation for module `\SB_RAM40_4K'.
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Generating RTLIL representation for module `\SB_RAM40_4KNR'.
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Generating RTLIL representation for module `\SB_RAM40_4KNW'.
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Generating RTLIL representation for module `\SB_RAM40_4KNRNW'.
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Generating RTLIL representation for module `\ICESTORM_LC'.
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Generating RTLIL representation for module `\SB_PLL40_CORE'.
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Generating RTLIL representation for module `\SB_PLL40_PAD'.
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Generating RTLIL representation for module `\SB_PLL40_2_PAD'.
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Generating RTLIL representation for module `\SB_PLL40_2F_CORE'.
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Generating RTLIL representation for module `\SB_PLL40_2F_PAD'.
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Generating RTLIL representation for module `\SB_WARMBOOT'.
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Generating RTLIL representation for module `\SB_MAC16'.
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Generating RTLIL representation for module `\SB_SPRAM256KA'.
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Generating RTLIL representation for module `\SB_HFOSC'.
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Generating RTLIL representation for module `\SB_LFOSC'.
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Generating RTLIL representation for module `\SB_RGBA_DRV'.
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Generating RTLIL representation for module `\SB_I2C'.
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Generating RTLIL representation for module `\SB_SPI'.
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Generating RTLIL representation for module `\SB_LEDDA_IP'.
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Generating RTLIL representation for module `\SB_FILTER_50NS'.
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Generating RTLIL representation for module `\SB_IO_I3C'.
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Generating RTLIL representation for module `\SB_IO_OD'.
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Successfully finished Verilog frontend.
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2.2. Executing HIERARCHY pass (managing design hierarchy).
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2.2.1. Analyzing design hierarchy..
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Top module: \memtest
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2.2.2. Analyzing design hierarchy..
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Top module: \memtest
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Removed 0 unused modules.
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2.3. Executing PROC pass (convert processes to netlists).
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2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Removing empty process `memtest.$proc$memtest.v:25$132'.
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Cleaned up 0 empty switches.
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2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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Removed a total of 0 dead cases.
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2.3.3. Executing PROC_INIT pass (extract init attributes).
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2.3.4. Executing PROC_ARST pass (detect async resets in processes).
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2.3.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
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Creating decoders for process `\memtest.$proc$memtest.v:29$34'.
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1/34: $0\led_r[0:0]
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2/34: $0$mem2bits$\mem$memtest.v:63$32[31:0]$66
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3/34: $0$mem2bits$\mem$memtest.v:62$31[31:0]$65
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4/34: $0$mem2bits$\mem$memtest.v:61$30[31:0]$64
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5/34: $0$mem2bits$\mem$memtest.v:60$29[31:0]$63
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6/34: $0$mem2bits$\mem$memtest.v:59$28[31:0]$62
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7/34: $0$mem2bits$\mem$memtest.v:58$27[31:0]$61
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8/34: $0$mem2bits$\mem$memtest.v:57$26[31:0]$60
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9/34: $0$mem2bits$\mem$memtest.v:56$25[31:0]$59
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10/34: $0$mem2bits$\mem$memtest.v:55$24[31:0]$58
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11/34: $0$mem2bits$\mem$memtest.v:54$23[31:0]$57
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12/34: $0$mem2bits$\mem$memtest.v:53$22[31:0]$56
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13/34: $0$mem2bits$\mem$memtest.v:52$21[31:0]$55
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14/34: $0$mem2bits$\mem$memtest.v:51$20[31:0]$54
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15/34: $0$mem2bits$\mem$memtest.v:50$19[31:0]$53
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16/34: $0$mem2bits$\mem$memtest.v:49$18[31:0]$52
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17/34: $0$mem2bits$\mem$memtest.v:48$17[31:0]$51
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18/34: $0$mem2bits$\mem$memtest.v:47$16[31:0]$50
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19/34: $0$mem2bits$\mem$memtest.v:46$15[31:0]$49
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20/34: $0$mem2bits$\mem$memtest.v:45$14[31:0]$48
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21/34: $0$mem2bits$\mem$memtest.v:44$13[31:0]$47
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22/34: $0$mem2bits$\mem$memtest.v:43$12[31:0]$46
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23/34: $0$mem2bits$\mem$memtest.v:42$11[31:0]$45
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24/34: $0$mem2bits$\mem$memtest.v:41$10[31:0]$44
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25/34: $0$mem2bits$\mem$memtest.v:40$9[31:0]$43
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26/34: $0$mem2bits$\mem$memtest.v:39$8[31:0]$42
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27/34: $0$mem2bits$\mem$memtest.v:38$7[31:0]$41
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28/34: $0$mem2bits$\mem$memtest.v:37$6[31:0]$40
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29/34: $0$mem2bits$\mem$memtest.v:36$5[31:0]$39
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30/34: $0$mem2bits$\mem$memtest.v:35$4[31:0]$38
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31/34: $0$mem2bits$\mem$memtest.v:34$3[31:0]$37
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32/34: $0$mem2bits$\mem$memtest.v:33$2[31:0]$36
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33/34: $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
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34/34: $0\memadr[10:0]
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2.3.6. Executing PROC_DLATCH pass (convert process syncs to latches).
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2.3.7. Executing PROC_DFF pass (convert process syncs to FFs).
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Creating register for signal `\memtest.\led_r' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$133' with positive edge clock.
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Creating register for signal `\memtest.\memadr' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$134' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:32$1' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$135' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:33$2' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$136' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:34$3' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$137' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:35$4' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$138' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:36$5' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$139' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:37$6' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$140' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:38$7' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$141' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:39$8' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$142' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:40$9' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$143' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:41$10' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$144' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:42$11' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$145' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:43$12' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$146' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:44$13' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$147' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:45$14' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$148' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:46$15' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$149' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:47$16' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$150' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:48$17' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$151' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:49$18' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$152' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:50$19' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$153' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:51$20' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$154' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:52$21' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$155' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:53$22' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$156' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:54$23' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$157' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:55$24' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$158' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:56$25' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$159' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:57$26' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$160' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:58$27' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$161' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:59$28' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$162' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:60$29' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$163' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:61$30' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$164' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:62$31' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$165' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:63$32' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$166' with positive edge clock.
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2.3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Removing empty process `memtest.$proc$memtest.v:29$34'.
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Cleaned up 0 empty switches.
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2.4. Executing FLATTEN pass (flatten design).
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No more expansions possible.
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2.5. Executing TRIBUF pass.
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2.6. Executing DEMINOUT pass (demote inout ports to input or output).
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2.7. Executing SYNTH pass.
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2.7.1. Executing PROC pass (convert processes to netlists).
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2.7.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Cleaned up 0 empty switches.
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2.7.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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Removed a total of 0 dead cases.
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2.7.1.3. Executing PROC_INIT pass (extract init attributes).
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2.7.1.4. Executing PROC_ARST pass (detect async resets in processes).
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2.7.1.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
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2.7.1.6. Executing PROC_DLATCH pass (convert process syncs to latches).
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2.7.1.7. Executing PROC_DFF pass (convert process syncs to FFs).
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2.7.1.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Cleaned up 0 empty switches.
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2.7.2. Executing OPT_EXPR pass (perform const folding).
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2.7.3. Executing OPT_CLEAN pass (remove unused cells and wires).
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Finding unused cells or wires in module \memtest..
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removing unused `$memrd' cell `$memrd$\mem$memtest.v:16$33'.
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removing unused `$dff' cell `$procdff$135'.
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removing unused `$dff' cell `$procdff$136'.
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removing unused `$dff' cell `$procdff$137'.
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removing unused `$dff' cell `$procdff$138'.
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removing unused `$dff' cell `$procdff$139'.
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removing unused `$dff' cell `$procdff$140'.
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removing unused `$dff' cell `$procdff$141'.
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removing unused `$dff' cell `$procdff$142'.
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removing unused `$dff' cell `$procdff$143'.
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removing unused `$dff' cell `$procdff$144'.
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removing unused `$dff' cell `$procdff$145'.
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removing unused `$dff' cell `$procdff$146'.
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removing unused `$dff' cell `$procdff$147'.
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removing unused `$dff' cell `$procdff$148'.
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removing unused `$dff' cell `$procdff$149'.
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removing unused `$dff' cell `$procdff$150'.
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removing unused `$dff' cell `$procdff$151'.
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removing unused `$dff' cell `$procdff$152'.
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removing unused `$dff' cell `$procdff$153'.
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removing unused `$dff' cell `$procdff$154'.
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removing unused `$dff' cell `$procdff$155'.
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removing unused `$dff' cell `$procdff$156'.
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removing unused `$dff' cell `$procdff$157'.
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removing unused `$dff' cell `$procdff$158'.
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removing unused `$dff' cell `$procdff$159'.
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removing unused `$dff' cell `$procdff$160'.
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removing unused `$dff' cell `$procdff$161'.
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removing unused `$dff' cell `$procdff$162'.
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removing unused `$dff' cell `$procdff$163'.
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removing unused `$dff' cell `$procdff$164'.
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removing unused `$dff' cell `$procdff$165'.
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removing unused `$dff' cell `$procdff$166'.
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removing unused non-port wire \random_rom_dat_r.
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removed 67 unused temporary wires.
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Removed 33 unused cells and 67 unused wires.
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2.7.4. Executing CHECK pass (checking for obvious problems).
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checking module memtest..
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Warning: Wire memtest.\pmod_4 is used but has no driver.
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Warning: Wire memtest.\pmod_3 is used but has no driver.
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Warning: Wire memtest.\pmod_2 is used but has no driver.
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Warning: Wire memtest.\pmod_1 is used but has no driver.
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Warning: Wire memtest.\led_g is used but has no driver.
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Warning: Wire memtest.\led_b is used but has no driver.
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found and reported 6 problems.
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2.7.5. Executing OPT pass (performing simple optimizations).
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2.7.5.1. Executing OPT_EXPR pass (perform const folding).
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2.7.5.2. Executing OPT_MERGE pass (detect identical cells).
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Finding identical cells in module `\memtest'.
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Cell `$memrd$\mem$memtest.v:33$69' is identical to cell `$memrd$\mem$memtest.v:32$68'.
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Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:33$2[31:0]$36 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
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Removing $memrd cell `$memrd$\mem$memtest.v:33$69' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:34$70' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:34$3[31:0]$37 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:34$70' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:35$71' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:35$4[31:0]$38 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:35$71' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:36$72' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:36$5[31:0]$39 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:36$72' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:37$73' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:37$6[31:0]$40 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:37$73' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:38$74' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:38$7[31:0]$41 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:38$74' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:39$75' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:39$8[31:0]$42 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:39$75' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:40$76' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:40$9[31:0]$43 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:40$76' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:41$77' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:41$10[31:0]$44 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:41$77' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:42$78' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:42$11[31:0]$45 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:42$78' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:43$79' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:43$12[31:0]$46 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:43$79' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:44$80' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:44$13[31:0]$47 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:44$80' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:45$81' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:45$14[31:0]$48 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:45$81' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:46$82' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:46$15[31:0]$49 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:46$82' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:47$83' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:47$16[31:0]$50 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:47$83' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:48$84' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:48$17[31:0]$51 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:48$84' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:49$85' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:49$18[31:0]$52 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:49$85' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:50$86' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:50$19[31:0]$53 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:50$86' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:51$87' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:51$20[31:0]$54 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:51$87' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:52$88' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:52$21[31:0]$55 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:52$88' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:53$89' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:53$22[31:0]$56 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:53$89' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:54$90' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:54$23[31:0]$57 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:54$90' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:55$91' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:55$24[31:0]$58 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:55$91' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:56$92' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:56$25[31:0]$59 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:56$92' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:57$93' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:57$26[31:0]$60 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:57$93' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:58$94' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:58$27[31:0]$61 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:58$94' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:59$95' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:59$28[31:0]$62 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:59$95' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:60$96' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:60$29[31:0]$63 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:60$96' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:61$97' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:61$30[31:0]$64 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:61$97' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:62$98' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:62$31[31:0]$65 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:62$98' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:63$99' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:63$32[31:0]$66 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:63$99' from module `\memtest'.
|
|
Removed a total of 31 cells.
|
|
|
|
2.7.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \memtest..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
2.7.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \memtest.
|
|
Performed a total of 0 changes.
|
|
|
|
2.7.5.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.7.5.6. Executing OPT_RMDFF pass (remove dff with constant values).
|
|
|
|
2.7.5.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
removed 31 unused temporary wires.
|
|
Removed 33 unused cells and 98 unused wires.
|
|
|
|
2.7.5.8. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
2.7.5.9. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.7.6. Executing WREDUCE pass (reducing word size of cells).
|
|
Removed top 21 address bits (of 32) from memory init port memtest.$meminit$\mem$memtest.v:26$131 (mem).
|
|
Removed top 31 bits (of 32) from port B of cell memtest.$add$memtest.v:30$67 ($add).
|
|
Removed top 21 bits (of 32) from port Y of cell memtest.$add$memtest.v:30$67 ($add).
|
|
|
|
2.7.7. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.7.7.1. Executing Verilog-2005 frontend.
|
|
Parsing Verilog input from `D:\Software\Icestorm\bin\../share/yosys/cmp2lut.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_lut_cmp_'.
|
|
Successfully finished Verilog frontend.
|
|
No more expansions possible.
|
|
|
|
2.7.8. Executing ALUMACC pass (create $alu and $macc cells).
|
|
Extracting $alu and $macc cells in module memtest:
|
|
creating $macc model for $add$memtest.v:30$67 ($add).
|
|
creating $alu model for $macc $add$memtest.v:30$67.
|
|
creating $alu cell for $add$memtest.v:30$67: $auto$alumacc.cc:474:replace_alu$167
|
|
created 1 $alu and 0 $macc cells.
|
|
|
|
2.7.9. Executing SHARE pass (SAT-based resource sharing).
|
|
|
|
2.7.10. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.7.10.1. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
2.7.10.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.7.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \memtest..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
2.7.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \memtest.
|
|
Performed a total of 0 changes.
|
|
|
|
2.7.10.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.7.10.6. Executing OPT_RMDFF pass (remove dff with constant values).
|
|
|
|
2.7.10.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
removed 1 unused temporary wires.
|
|
Removed 33 unused cells and 99 unused wires.
|
|
|
|
2.7.10.8. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
2.7.10.9. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.7.11. Executing FSM pass (extract and optimize FSM).
|
|
|
|
2.7.11.1. Executing FSM_DETECT pass (finding FSMs in design).
|
|
|
|
2.7.11.2. Executing FSM_EXTRACT pass (extracting FSM from design).
|
|
|
|
2.7.11.3. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
|
|
2.7.11.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
Removed 33 unused cells and 99 unused wires.
|
|
|
|
2.7.11.5. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
|
|
2.7.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
|
|
|
|
2.7.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
|
|
|
|
2.7.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
|
|
|
|
2.7.12. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.7.12.1. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
2.7.12.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.7.12.3. Executing OPT_RMDFF pass (remove dff with constant values).
|
|
|
|
2.7.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
Removed 33 unused cells and 99 unused wires.
|
|
|
|
2.7.12.5. Finished fast OPT passes.
|
|
|
|
2.7.13. Executing MEMORY pass.
|
|
|
|
2.7.13.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
|
|
Checking cell `$memrd$\mem$memtest.v:32$68' in module `\memtest': merged address $dff to cell.
|
|
|
|
2.7.13.2. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
Removed 33 unused cells and 99 unused wires.
|
|
|
|
2.7.13.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
|
|
|
|
2.7.13.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
Removed 33 unused cells and 99 unused wires.
|
|
|
|
2.7.13.5. Executing MEMORY_COLLECT pass (generating $mem cells).
|
|
Collecting $memrd, $memwr and $meminit for memory `\mem' in module `\memtest':
|
|
$meminit$\mem$memtest.v:26$131 ($meminit)
|
|
$memrd$\mem$memtest.v:32$68 ($memrd)
|
|
|
|
2.7.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
Removed 33 unused cells and 99 unused wires.
|
|
|
|
2.8. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).
|
|
Processing memtest.mem:
|
|
Properties: ports=1 bits=65536 rports=1 wports=0 dbits=32 abits=11 words=2048
|
|
Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1):
|
|
Bram geometry: abits=8 dbits=16 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted.
|
|
Mapping to bram type $__ICE40_RAM4K_M0 (variant 1):
|
|
Read port #0 is in clock domain \clk.
|
|
Mapped to bram port A1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1):
|
|
Bram geometry: abits=9 dbits=8 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted.
|
|
Mapping to bram type $__ICE40_RAM4K_M123 (variant 1):
|
|
Read port #0 is in clock domain \clk.
|
|
Mapped to bram port A1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2):
|
|
Bram geometry: abits=10 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted.
|
|
Mapping to bram type $__ICE40_RAM4K_M123 (variant 2):
|
|
Read port #0 is in clock domain \clk.
|
|
Mapped to bram port A1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3):
|
|
Bram geometry: abits=11 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted.
|
|
Mapping to bram type $__ICE40_RAM4K_M123 (variant 3):
|
|
Read port #0 is in clock domain \clk.
|
|
Mapped to bram port A1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Selecting best of 4 rules:
|
|
Efficiency for rule 2.3: efficiency=100, cells=16, acells=1
|
|
Efficiency for rule 2.2: efficiency=100, cells=16, acells=2
|
|
Efficiency for rule 2.1: efficiency=100, cells=16, acells=4
|
|
Efficiency for rule 1.1: efficiency=100, cells=16, acells=8
|
|
Selected rule 2.3 with efficiency 100.
|
|
Mapping to bram type $__ICE40_RAM4K_M123 (variant 3):
|
|
Read port #0 is in clock domain \clk.
|
|
Mapped to bram port A1.1.
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <0 0 0>: mem.0.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <1 0 0>: mem.1.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <2 0 0>: mem.2.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <3 0 0>: mem.3.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <4 0 0>: mem.4.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <5 0 0>: mem.5.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <6 0 0>: mem.6.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <7 0 0>: mem.7.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <8 0 0>: mem.8.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <9 0 0>: mem.9.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <10 0 0>: mem.10.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <11 0 0>: mem.11.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <12 0 0>: mem.12.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <13 0 0>: mem.13.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <14 0 0>: mem.14.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <15 0 0>: mem.15.0.0
|
|
|
|
2.9. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.9.1. Executing Verilog-2005 frontend.
|
|
Parsing Verilog input from `D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$__ICE40_RAM4K'.
|
|
Generating RTLIL representation for module `\$__ICE40_RAM4K_M0'.
|
|
Generating RTLIL representation for module `\$__ICE40_RAM4K_M123'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.9.2. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K_M123'.
|
|
Parameter \CFG_ABITS = 11
|
|
Parameter \CFG_DBITS = 2
|
|
Parameter \CLKPOL2 = 1
|
|
Parameter \INIT = 4096'1001101101111010010101010110010010010110011110001111101000110111010100110100010011111010100101011001000011010111000001111101000110001001011001110010110111100100110001000010010110100100010110011100101001011100100110011110001011001011001011100110001101111000001111011000100011100011101011100010110010001110011011101101111101010111110100010110101011100010001110111011000100010000011101010100011001111010000100011101101101101111000010101010011111001001000001000010110110010100010100011001011110011101011111111101111100111110101101011000000000000100010110011011011100010110110101100111001011111101011010101100101011010011011101100110011001011110010011010101011011001000000011010000110011110110010101010110000010101010100001011001010001110111010111010111000010101111001110010100100100101011011110110010000010110011000100010110101011100111000010100011100110011100011110000100000010011010110101001110100001110011001111001001011011101010011010000011001101110100011110110000010110111010100100111010010110101010010001100111011001011110000010000000100000011011010101100000110000000100101010110110001110100111101011011000100101000100100111000010110010010100011110001100001011000110101011000111010001101100111101000001100011000001001001010011111100101111000000101110010100110001100110011100101100100110101100110010001000010011011001011101111101001010100001111011010010010110101110011011000010101100011100111111001100000111100010101011110111000111101101101010110010011010011001110100110111010101000110001111111100100001000000100101011110000001011110110111011101001111010000100111100101100010001101001101100001100010100011010100011100011100111101101101000000001100011110000110011101100111111000000000001101001011100011100101001111000011100100111101010101000011100000110000111001100010010000100101100100001101100000000000011101100000001011101001111101100001111011010100101001110010111010011001010010001111010011110100111000111000101010001011100011001010100000100001010100111111110011100000111110010110000010111000000100100110100001111011101001001001000011011101001100011001011011000000110100100110101001110010110100101001101100110010011010001111000001110001011110110001001010111111111110110100110011010100111110010111110110101110111110110010100100101111000001011101000001010000100011111110101010101100001111110111000011001000000011000011100001100000111001010001101000010010010011100011010011101111010100101010111101011010010000011001000101111101101000101001000011010000000110011000011000010111101011101111011011000111011000001011001000001000100011101011110000101101101001100010010101000101011011001010000001010011011111110010111001010111010101100001110010010011100011111111101001110110100001011110100111011000000011111000001011001011110011100111011110101110000100000010100111001100000001000110010100100101101101101101000011001110010000011001001110011101010001011000110100010011101011100111000000001010100111100101101100101100011001001000101010000110010010001110011100111101001111110110010000101000101100011011010110101011001001000001000001001100011111010100001100010011101010010010101100110110010001100000111111111111100000001001001000000010001001011101110010001101110000111011011110110100011000001011110010100110010000001010000100110110011100010011010000011001110010011100010101011111010011010001101111001101101110100100110011001110000101011100110111110110100010010110100011010110101001100010000101011000000011100110111010111110111101100011010110101001101000100011111011100110000110010111001111001010110000011011101001100001010010111110110010111011000011011101000101100000111000010011001110101101111111000111111100100000000101111010100010110101101001001100100010010110100010000100001110100101011110100011001010110110101001100011111100101111010010111111100011100011001110110100011010111100001011111111101011011100010001110001111101000000111000101011010110111101001011101110001111110100001100001110001101101111101101110011110011010010111010000100011000101000011101010010001010101010110010110110110110110110001010100100111110101000110111101011110011000000001011000000111111010111010101110110100110011010010000110011
|
|
Generating RTLIL representation for module `$paramod$f34e4fc64748f57bac4a16b7abe1ff9627c0d713\$__ICE40_RAM4K_M123'.
|
|
|
|
2.9.3. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.0.0.0 using $paramod$f34e4fc64748f57bac4a16b7abe1ff9627c0d713\$__ICE40_RAM4K_M123.
|
|
|
|
2.9.4. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K_M123'.
|
|
Parameter \CFG_ABITS = 11
|
|
Parameter \CFG_DBITS = 2
|
|
Parameter \CLKPOL2 = 1
|
|
Parameter \INIT = 4096'1100111011001110000100101100101011010110011000110001110111000101111100101100011010011100100101101101001011101110100101011110111111101100001010010001000010011100001010100101001111011101001000011010001011111110000000101111011101110101011011110110011000011111111011100010001001000101100110100001001100110101011111001111010001101010101011100010111111100100100100101000110100101110100011101101010110011011101011111010001110110111100011011110110010110100001010000001010011101110001000111001111101000001101100000111110011001001111111010010111111010110010010110010001111111001011000000000110110001001010100010001110001000110101101101010111100111010110111100100110010110101010000111000011010110111110110011010000011100000111000000100101101011111110110110111000000001000000100001000000010101010110101101000111101101001100000110001110110010001110100001001111100111111000000101001101001101100111100011001100110000100100100110110010000001001001110111010001010000101111111110101010110110110100001111110100101101110010101000010010010001101011110110000010010000101001001100110111110111111011001101111001011000111011101010111110100011011110001001101000100101111100100000111111101101110110111110000000111100100011110001000001100000110100110010011000111110111000100111101100100000000101001010111010001011100110001000010000010011001111000011010001111001010101110111000101011001001010111001110101110101110100100111001101011101111111110011000100110101000111000111010100011010011100010100100010001000111110001111000110010100111111100011110000011111100000101001110110111011010111011111101011100010110101000000001101010100010010000010111011001011110000110001011011100000001010110101110010111101110110111110101111001000111100110011100100010110000111011110001101000111001111110000010001100011100101001111110111110111001010111100110001010010011001010110010011111001010000010111110000000110101101101111010110010000000011001110010101000001000101110110000101011111001000011101000110111001010001110110101100110111110111100001111100001111101111001110010100001010110001111110110100111100110000100000011110111101001000111100000011111111110011001110011000100001001010111110111011000110011111100011111001111100110011100001101101011111010011101101001001101000111111011101111010011010100101111000000011011101110110000100010010101010110101111001100111101101101010001011110111111100101100010011101100100011000010101000101101010100001010010000010010100100000011111100100101110110011101111010100101110101110111100010010000101110100100110110000000110110011010110101100100011001011001010011001010010111110100110111010111100010011001010010111101100101011001100100100101001110111111110000101111110101010101011010011000101001100110011010011111001010010110011011001001000111101100010011000110011111000111101101100010111101111111101101010000000111011011011101000111100110000111110000111100010110101001110101010001000110000110010011010110111101010111001001100010110101100100010010101110111101101111000110101000110110110010011000001101101011101010110010001001110101101100111111011000010011010101101100001010000001000101011001010111010001001101010001000111001101111111100110110001000110101010001010010110000111110000100111100111110101000001101010001111010111001000011101100010011100000101110000101100000111110010100101101100101011010000110101111101000110011000101011100010101011111011010000101111111010100011101101110110101110111101111111111011101110010101010111010110010000100110011111011010110110001111101011000000010101000011110101101110101111011001011101111110111110011100100000011011011001110011001010000000111000110100010111010100010000001101011011110010011111111010110000111100011110000010111110010000111101001010110100101110110100100001100001011100101100111110100001000100001000000100111000111001101010110101001000101010100011110100010110111101110010110111000111001001001001001110000001010100110100110111111101001101010011000001011110111100111111001001001010111011100110000011010000100111101110011010010110110001000100010011001110011101100001010110010101100010101011101111111110010100010101010110011100000111001001111100110100011111100101011
|
|
Generating RTLIL representation for module `$paramod$d29ea10a8c2254f5db658036dae08160f73747d3\$__ICE40_RAM4K_M123'.
|
|
|
|
2.9.5. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.1.0.0 using $paramod$d29ea10a8c2254f5db658036dae08160f73747d3\$__ICE40_RAM4K_M123.
|
|
|
|
2.9.6. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K_M123'.
|
|
Parameter \CFG_ABITS = 11
|
|
Parameter \CFG_DBITS = 2
|
|
Parameter \CLKPOL2 = 1
|
|
Parameter \INIT = 4096'1001101111011111111111000011010010001110111100100110000110010101000110001101100001100110100011100111111100100101010000011011110101110010001111101010000111001101011100010100000100000001011010000001000001110010001011010011010010100011000100000111110010010010001001110111111100101110100110011011101000010010111010101110100001011001110110011110010110001101011101000110011011000100110110110000101010011110110110111011001010101110000111001110000000110001000100100100000001100011101011011001011000111101010110010000111101101111001000101111111001101001001011010010001111111000111110010010100000111111100111011110010000001011010100100111101010101100000011010110110011111000100111100010100001111001000010000001101010011110101101101100111001000100010001011001001111111101010010010111001100010010010010011100111000011110001100000000101111110001000100101111000101010110011100111100110100001010010110011011000010110110111010001011000100111010111010110111010100011100101010100100011101000101111110101100110110111100001100001000010001001110001100001000010010110101110101011010001101101011100011000110010010101111000001011110110001110010100101000101110000101001111001100001110110110010011011010111110110111111111001111101100000100101000110100001101100010000111010100111111111111111101111101001101010001101001001111101110111000100011011000000010011011110000001011011110101111010110010011101000100001101001011110111101101100111111101101000101000010000001101101001010011001001011011101001101000111100100110100101001101100001110001111000101010000110100000101000001100010001011010011100000111110110111000001110011001101001101110101001010100101001101011100010000010111010010010001100000001101110101110001001000010100001010110001101100011100011110000100111100101111010010100000101111001011000110101100001100111100001110110101010000111111000111010001100100000100110001001101010110101100001011111011011101110011000110101110101111110111011011111000110111111100100111010111100100001110110010001011011010100000011111011110001110100111101100001101010100011110110100101001010010001011111001101101100111001010110100001001001100111011010111001111010110111011101100011100001100011101101011000010001100010010110011101110100011000101000011011101000011011000000110000001011000000011110111010110000011001111100001110001000100000000110111010100101110100011000000100101100111000101010100100011111000000110110100101011000011001111101110010010000110001110110111100010010001100010101101011010011011100000111111100100111011101000000111110111101011111111001010010011010001011101011110010110000110111000101001010010001100101000110111110110100011010111000110101001000011001001001000000001100011010100110001001001011110011101111100110010100010111000011110111100100111100110011001011111101011001000110010101011100100011101001101011001001011011010111000011100110111101000101001111000101101001101110101101000010100010010010100110110010110101000000010100001000011001010011110100010111110100110111110001101111011001010010111111111110010011011111010110010101001010001100101110001010001101010001111110101100010100100100110100011100110010011110001010100001000101001010010101100110100001001110010101000001000101110110000010011110010011110110101010100100101111100010011010100111000101010001110000111000111001101001101000001010100100001000111011111011100100011011011010010001011010101011010010010011001001110001011110011001010100011101101010110100000000011011001100001001111111011110100111001101011000111001000000110110001110110011101010111110011000011001011010011011000100100001111110110111010000111000011011001000110110110010101101100101101100111001011001100010110110101100000100000110100001010011000011100101111000111100100111001110001011111010010010010010001010010101100001001000111001001001000010000110010101011001010111110100110101010101110101010010100111110011010011110111111110110110010001010011001100011001110010110000011000100100110001100000111100011010111101001010010001101100101010010111011010011111010000010110111001110001001000111111001000101110001110100000010111011010100101011110001111010001001000011011011110101100100011000001000000001001
|
|
Generating RTLIL representation for module `$paramod$54b8ee85936b5b862f32ccf0024a595c36a339b2\$__ICE40_RAM4K_M123'.
|
|
|
|
2.9.7. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.2.0.0 using $paramod$54b8ee85936b5b862f32ccf0024a595c36a339b2\$__ICE40_RAM4K_M123.
|
|
|
|
2.9.8. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K_M123'.
|
|
Parameter \CFG_ABITS = 11
|
|
Parameter \CFG_DBITS = 2
|
|
Parameter \CLKPOL2 = 1
|
|
Parameter \INIT = 4096'1100000101110100111101010000011011110001011010011011001001001110101110110100011111011110001001001011101011100100000111111010111000110011001000101011101110001101110101110101000000111000000101011101101010101110001000110011000010000011011101010001101110011110011000101011100000001001000110011100000100110000111100111111001111100001110011000110111010011010001101110100110000110011101101100111111110011100010011011011100110111011011000101101010001101001011110100101010111111011110111111110011110111110000011101010110101010101110111000101001010110000100010101010000000011101110110010001001011000101100010101100011010111100110010000101100101111000010011010010011010000001011111011110110101100100001001000100111010111010010001010010111001111000000111101111101111100000100100110010011001011011110111010001101111100001000101100111010010111100000101111000111101101011101000110111011111110100010010000110000110010000100010011111111110110110110111011011111000110110000000101011011000000011110110011110000110000100110001010111011001010100111101010100011011001100110100110101010111100101101010100001000110011100001011011100101011110111000101000010110101101000100111101010010110110000011000101101011001001011101101100001100010111100011000001100110110101011010001010001001010000000111010101011000010111111110100110001101010000001100110111101110101111101010110100110111110001000111110110101111010111011110011111100011011111100111101010101001010001101010111010010111100011001010100110101111110101011101010100101101010010001010010111000010100000101010100111111110011111001010100101011101010001110111100110010011111010001010011000010111000010011111000000111001101011101100111100100111101010101100111001001110100001111111011000101010001101111110001111110111101111101110111010011110101100110010010010000010100101110110001000000011110100100001001101111100001011100111001111010100100000011110001111011111110001000010111011101111000001110010100101110111011011001010010111101001000011100110010111101001101110000010000000101111011101100110010001001011101110010011000101110100010011011100000111011110111111010000100101001001001101100000111101001010110001101011100111010011001001010001111111011000111011110101111100110010010101011101100101000001011011111111000011001111100011001010011100110100011010010011011011100000111100001100010001100100111011111010010001111111101101000101111011100001101010001110011101010011110100111101100111001010001101010110101010111010100100101101011100101011000100101000100010001101000001011001101111111100010010011110101010110000110100000110110101000000111100010000101101100101000011110111100111110010111101100001101110111010111001111001101101001110101100100001101101111010001110010111101110010100111100001010101000110010110010000001110000101100110110110000101011001000111011001111010110110010010000111011100000101110111100100110100001101110001100111101011100010101111010110110100111010111011101000010001111110100111101001011010001011101100101001010111110110101000111101010101110000111011101001010010011110010000010010101001101010101011011001010101001000101100111111101101100011011100101010110001100110101100001110100011110010101001111110010111011101101010111100000011111110110011011000110101000101100100011001011000101110101000100000011010111100011011011111010101101111000011100011101100010100111001010100011000101010111001101011011000100111101110111100010011000000010010110110011000001100101001101111111010111011000110001010010111001101111011100001001110001111010110100110011100000100001001111010100000100001100101110010110000100111100101110000101110001001110000101001110000110100001100111110111010100110110010010101100011111011000011000110101001010111001001100110000000001100010000101001010010110101011010000110001001111001000110100100001100101100000011100011011001101001101100011010111000111110001010001001000011101110110001010110011100001001001101110111111111100010000111000111010100110000111101100100100011001001101011100001100101110110010101110110010100000010001111001101011001101000000100111000110001011001010011010100001100100101001000111011110111010011001011010010110101010100011001100000
|
|
Generating RTLIL representation for module `$paramod$70b913e53302824162354964047ff9a7c4f55ae7\$__ICE40_RAM4K_M123'.
|
|
|
|
2.9.9. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.3.0.0 using $paramod$70b913e53302824162354964047ff9a7c4f55ae7\$__ICE40_RAM4K_M123.
|
|
|
|
2.9.10. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K_M123'.
|
|
Parameter \CFG_ABITS = 11
|
|
Parameter \CFG_DBITS = 2
|
|
Parameter \CLKPOL2 = 1
|
|
Parameter \INIT = 4096'1101010011000000100101001010100111111011100101111111011101001101011010100001000111000111110110000000000111000010010110100100001000111001000000101111111111000011011011110110111000011010011101010101100010011001010110011001011010000011000111010010111001101011100000011001100100111010101101001110110001111101010011101000110000011100000101100111010011110000000001101110011110011101000010111011110101110000111111011101101010000111011101010100100101101001101011011001100111000000001111010011000100100000001001100100010000111100011000111000011111010111000111101101100101000000011100111101100101111000100101110000101010100011011110001010000110100111101001101001011000000100111011111001011010011101100100010111111110000110010110010000010001111011010110101101011111010101111110111010101101110101010110100010101001100000011001011001001111001111101100011000011101111011000100111001111010111001110011011111101100011011100101101001001011101011010001101001100000111010101010111111011010000100010011100111010101101000000011101010011011111111011011010010111100111010001110111111000100000011110110101010010100101100001010011001000011000010010001001000111000110010111111111001011100111011010010011011100011010011101001000001110010100101011100000110011010001100011011001110110111110001010000110110100100100111110111011010001110111010010011100011010100110111111011110100101010101010000100001010010111111011100111101011011000101011100110001011001110101001011000011000110110011000000001001000001111101010011111011001111001000010010011101010100100000111100001100110001110111010010100100011000001011011011010011100100101100110111101001101101000011101000011010000111011101100011111001110001110100000010010011011110101011111110011100011000010101010000001011101011000011011101000001011001001011101111101000011110101000101000100111100111011111011101011100101110100010110100001010101111001101111111110111110001100111000100000110001101101011000100000001010111110000110110010011110110010000110001110111100011110111100111010110110011101111001000100011101101000110101011111110111000011011101001100110000001110111001100110100111110101100101101101011011010100000111100111011011110001010101101000010111010101101111100111100001100010111001011000110101111111111110010110001111011000110101000000010011110111000101110110110011010111101011011010011001110101010010110110110100100011101011101001101101011011000111001000001000010001000011110000100100111001000101000011011100000101011110010000111001000010000010000011100100111001111100101100010011011111010110001001110111011011000010111100000001001001110001111101011001101100000100100111100001010010010010011010111011111111110100111110010100100101101011010001111110110100100010011001110011101101100111000010010001110011111111000011100100101110111111101011100100000010010111001011010100100001110011110110001010101010100100111011011010011110111100000010000110000001111010000101001011010001110110101011010110010000110011000110001111111111010111001101101001111000111001100010001011101000000101100000111001101110110100011101001111101011001001011001001010001101010010000000011111110101011001011101111100100101011100111100001010001100110011011101101010111111110100101000000100011011101000110101101100011100101100101100101110000000100011001011101001110101011001111110100011100000000111000001100100100110000100011001101100010101101001000011000001000110111010100110010011000111110010111101010110011110000010100110110100111111010110101111101111101111100110010000000100110000001000001011111101011011100110010100011001101101110110111100101111111111000110110100101011011010101110000101001000101011100011010011010110001101001001011100100000010111101010011100000111010010110000010111111001001111011111011101000010110010111010000110001110010000010010110101111000010010011001011110111100001101100101001000011100010011000101011011110100010101010111000000011011001100101101101011001111001011001000100011101110111110010000110100101101011101000111101010010100000000101111101000011000111001110011100001100000100000111000010010100100011111111111010001100111000101000011111010001100001000101010011100101011110101001001
|
|
Generating RTLIL representation for module `$paramod$80133ed0e502a2cbc0fb9f4f4723ae90ee3bd1b8\$__ICE40_RAM4K_M123'.
|
|
|
|
2.9.11. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.4.0.0 using $paramod$80133ed0e502a2cbc0fb9f4f4723ae90ee3bd1b8\$__ICE40_RAM4K_M123.
|
|
|
|
2.9.12. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K_M123'.
|
|
Parameter \CFG_ABITS = 11
|
|
Parameter \CFG_DBITS = 2
|
|
Parameter \CLKPOL2 = 1
|
|
Parameter \INIT = 4096'1001101010001110001111000111011011000110010101000101111011101010111011100111100000001110101011110100010110100111011100111010010010111011010111010111001110001000010000100100001010111010100100011011010100101010010110100101011010101101011010010010001111111101000100110010001011000111101011001100000111111011001010101110010100100011011110010110001010011011001011010111101011110010100010110000100011010110011111011110000110110000100110110010101110101000011011111000100000111001110101100001110010101000001010010010010011011011110011010000000100110100110111110111011100110010001100101111001101101100100101010011000100101011100100111100010111101110111001110101001000010100001110011001010010101001000011001110001111101001010011111011101101000010000010110111101110100100101000100001100001000100101000000100011100111000100000001001000000101101101101100000010000011001000110101110011101010010001101001100110110100110111001010001101101011000000110110011000001011101011110111111011011011011011100110111110010101100100100101110111010110011100000011110101010110001001001101011010001000111001101111001010000100001111011101111110011101011110001101011011101110010001010100100011001101110001110111000101011101111101010001100101100100100111101111110111111011010011110101001010000100011011111000001010011101101001100100011100110001100010010110011000010010110000100011101101000101001001101010101010010100101111011111000101000001000000010100001110000100011011010101100001000001101001100111101010010010111000001110111111010000001100100010101010111111100110101000101101000101010111100100110010111101111101111101000011100111001001111010010111101111111001110101100100111001000011011000111100010101001110011011101101100000001010000101010111101101111111011011101010011011111000000011000001001100101010101011110101011111011101011110001001111001110110001111010101001100011111100101011111111110100000100100111000110100111000000111010001110001001110101001000010100110000110010001010101111010110011101000011011001100100100110100111111110000000010100100001100100000101110011101000011101000000111001001011100011011111001111010000100101101011000110000001001111010101011111010011001100011100001100011001010000001001100000101011111111110110100010001010010010101101011001000010100010011001010010010110110000110001011011001000010001111000110111000101111001001000101101111000100111101111000011001100101110001101100110101001000100110000001011101111011001110101110111100111010101110101000000001000100010011010110000001010101011000100101101011100011110101000011010101100101011111010110010011001011010010010010111110111000010110100010100010010011010001111011011010100100100000011010100000001110010010111000101101011111111111000001000100001000101101001000100100011100011010100000000100100000101001001011001100010101011000111100001011000011111101111010110010111010010101001000001001010100100001111111010011100100111101001110011011100101010110010111000011011100110000101011010101100001101010001100000010101111100000111100111110010111011101010000000011001111010011011101111101111011100110110100110011001000110110101101101000001000110111110000100100000011101101001110001010000101001001110011000001111001010010111101001110101100000000110111010110010101111000100010100111100011010001011111101011010010100110110000001010000111100110111101001011110011010000101001100101101000111101101111000010010110111110010101010011111111001001000010101000100111111001111100110101010001111110100101111111000110100110011000111100011001011011111011100111010001000011101010000111110110000110111010111110111011110001010100001110001100110110010011101100011101111001000001011010110111101010111111011011110010111000110100111100101101111010100100010100111000110100000001111110101101000101001101101010101110000010001000110011111010010111110110001101110000011101000010000111001001010110101100011010111101010110000101001001001000101010010011100111101011001011010011011111101111001000101010001110100111010001100101111110000000100111110111100111010101110100001010100101110111100001111111100011110110111101011101100100011110101010101000110111000001110111000000000010001000000010111
|
|
Generating RTLIL representation for module `$paramod$f97a514d2b440ef4e918056000ac32a28b520f0d\$__ICE40_RAM4K_M123'.
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|
|
|
2.9.13. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.5.0.0 using $paramod$f97a514d2b440ef4e918056000ac32a28b520f0d\$__ICE40_RAM4K_M123.
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|
|
|
2.9.14. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K_M123'.
|
|
Parameter \CFG_ABITS = 11
|
|
Parameter \CFG_DBITS = 2
|
|
Parameter \CLKPOL2 = 1
|
|
Parameter \INIT = 4096'1111101110010101111110011001111101100100101111010000101110111010011010011011111100100111011101111000011111010010110110111101011010000100100010011010100001000011010100100101001101110101111010100111010001100011111100010111110100110110100011111101000111001010100101100111010110011000111010001001011110010000000110100011010000011011100010011100110011010011100000011001101010010010110000100001000110010111100001101000011100001101110110010000000111001001100110101110000101010001010001001010011111000010000011100110010011111110011110000101110100111000001100111011110000100110000001001101111010011111000101101110010010100001010110111100001001011011110110111100010010000010101110000111101010110011101001100010011010010100110001010110010010010010101110000111100101110111001010010111001010110111010000111111100100000011110110101011000011011000011010001000110111010111010000011011001101111110010010011100101110000010011010010010011111100100001100000010111101001011010110101001111010101111111100101011101100110100101000101110110100110010001000011101011110101101111001000010011110000101101111111100100011110001011110101110101011110011100101010101101011000011110101001000010100101110000000010011110001101001100010011011010100001100101010100011001001100111010111101011100110100111001010100111010011111101001111000011111100101110001010111011010101001101111011010111000100110110111001111000101100001001100010101111101110010010010110001110000011001000000010010100110100110010101110110100000100111101101110001100111110001110011011111011000011101011010100110000101010010111001011011001101101111000101111010110100011000011010010001101010100111011001011010001010001100101110010111010100000111000000100001001001000010000011110000100110111101110101011100001101110010100001101110010100010111111111100101010000111110110011111110101100010111010110100011100001110000100110001001111111110111011010000000101101000010001100000010010101100010101111101000110101010000011101100011010010011101001011110001111011111010110101110100011110000101011011110111010010110001001111100110101001011101011111100000101111110110010100101010100011011100111100010000000111111011010100001100101001110010100101011011010001111100011011000110001010011000011101000100001100011100001000111101110111010001000101000100110000001101011101011111110000000000011101101111010110101000010000111111001111001101100101101010111111110100001100111110111100011100110011011010000001111110001100001110001010011101010000011110000001011111110001111101111111101001010010110000101101010110100010011110000110100100101000001000010010011001010000100111001110111001100111100001110001111101011011111101010001011000001001010100101100111010010010110111010011110011011001101100010100000111110000011000011001010000000101100110001010101110001110111000000011010010110111011000110100010110100000000010001000111001011110100111100100100000000100100110000011101010001110111110011110001010111011101101101000101110010100010110100101110110100111011100010101111010010110110011011100101110101011000100101100101101000000001100111100100010010011111011000010010111010011110101010111111011110100100101111101001000101101101010010000010001010110101001111100100010101010000101000110010010001011011010100010110110011100101101001110101101111101111100010101100010111101011101011010010000111100000110111000010001111011001011010101011010000101100101100001010100101011100010110110101011001110000000100000010010100101110000111110001111001101100110101110100100001001010111011101111110001110001000010000110101000110111101000100110100001000001111001101000000101101010100101100000011011111000000110100101000001111111000100110110111111111110110001101110010101010100111011100100000010110010011011010001100100110111110111110101110101001100010001001011011000110000100001100111011100100000001011010010111110101000110000001111010100100110111101001000101010000010000110001100000000010000010101100111110010101101111101000101010001111011001001111011011011101010111110111000100111110110001001001001100111010111010110101111001001101101111100111101111000100101110101011000110010111010111100111100011111111100010001100100010000
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Generating RTLIL representation for module `$paramod$a1c7297c5d07698b21ac139a98895b267b24d56b\$__ICE40_RAM4K_M123'.
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|
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2.9.15. Continuing TECHMAP pass.
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|
Mapping memtest.mem.6.0.0 using $paramod$a1c7297c5d07698b21ac139a98895b267b24d56b\$__ICE40_RAM4K_M123.
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2.9.16. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K_M123'.
|
|
Parameter \CFG_ABITS = 11
|
|
Parameter \CFG_DBITS = 2
|
|
Parameter \CLKPOL2 = 1
|
|
Parameter \INIT = 4096'1100111011001111011001111101110101111001101001101100001101000110100000101000100100010111000110011001101110000010100101000000100000011010101011101111001000111100100110001110111111110111001011010011111011000011001001111110110100011001110010001010100110000100101011011001011110011111101101011100001110100100000010101011000111101010111011111111100000000001100100111010000001111101101110111100010111011101101010010010010011100110010101111001100011011000100010100011101010010000100001001001011110001001000000001010011110010001000100000000010010001111111011000111101011100100100111110001011010101100010000011100011011000000101011101110000011010110101101100111011101000101111010011110100111011010101001001110001101000011000011110010011011001011101100001011010101011101010011100011111100100110100001011110110110001101111001011101101010010100100110000100101100010001001100110011011010100000110100101100100101000010000110001010010010001101110001110000110000111111011111110000110101010100010111111111000110010101110111000000110100110000011111100000010100001001000101011111100011100001011001000000110101001001010100100010000011111001010111100110111011101101110111111111001110110111001010101011010111000001101100010000110111101011010011101110101101011000111011000101000100111011011011110101111110000011111111110111101011010100110000110010101000110101111101011101010010000011000100111001011111000111111010111100001000001001100011111100010110100110001111111111011111110010101110100100011001010010001110000000100000011101001011110000000001100100000100011101111100000110101010111100001010001000101010111011110110100000101110101100000110000011000011001111011100000100011110110010110100011000101110000011010011010001111111011011100101101101010101110100110100100100111110010100011110111010001010101010100110110111011011011001110100110110010000100010001100000000001010100001001000111011000110010100100101011000011101101000001100010010000111101000100111100000101000100101010111011110110101011100110010011010111100000100010001000011110010011000010011100000010010010001110000110000011111100100011111001011000010010011000101001111110001000100110111100000011100001111001100000000100011110000100111000101110110110010111001111100110000011111111000001000001001110001011100110000101000110101000010100100000100000001101111100100001101111111100101011100111010111100111100100101110101101110100001001001111110011110110001101011101001100011010011010010000011101010111111101011000110011000010010010101001001100011011011101111000010100111101111110111110001100000001011111100111100100000010110101100111001101010110110101001011110011110011100111111010000001010100011100111101110010000000100110010010101000110001000110010111110111000000001011110011111101011111001110000110101001100001111001010110000101000111110110101111100110000100011111111000000100001111100001010100000001000101000000110100100001000101110101101010111010111010000010010010101001101011110001000000101001100101011101100111000100110000000001100100111100001000011100001100011100000010101001110000001111101100010101000010010100011111011000111010101101010100111001001111101101100001010101110100110001110111111000001011100100101101101000010101100111001110101001110001111011010011011011011110100101010110011011111101000000000000011000010000000111100110010101000000100111110101101001110111101001001100100111000100100001001110011110011111101011111000001100011100111000011101011000000000010111110110001111011101100000111100010100100010100001011111000010110001000100101100001100001111100100111101011011001010111000010110110011100100100101011011100000000001011111111000101110001010101011100110000000101110100010101010111110111000100010010000000111110101011110101010010111110111100001100000000110001101101110110000100100111101011000110100111000110001000001111100001110000101111100001000010001010111010100000100011111000011110101110001111011010111000011101001101011101011100110000000100100011111111111111100100101110100100011000000011111001100111001100010100010101011010011011010000000110001101101000001101100101001101101010010101110001000001010010111110011000010011111011110100001001
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Generating RTLIL representation for module `$paramod$c02feb6cffe46223ae1ed3b34a9ebbbf5b325211\$__ICE40_RAM4K_M123'.
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2.9.17. Continuing TECHMAP pass.
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|
Mapping memtest.mem.15.0.0 using $paramod$c02feb6cffe46223ae1ed3b34a9ebbbf5b325211\$__ICE40_RAM4K_M123.
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2.9.18. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K_M123'.
|
|
Parameter \CFG_ABITS = 11
|
|
Parameter \CFG_DBITS = 2
|
|
Parameter \CLKPOL2 = 1
|
|
Parameter \INIT = 4096'1100001011101001000101010001011011110001011100000100010110111110000010110011011000001001110111000001100000011100000011000011100101110111101001010010100010101100010000000101101110001101111010111110101101101010111001001000100011001111101001111111111111100111110011111110010011101000000100110011101101010010101100001010110111001110111101101111001111010000110010111110000111110111011001010110101110000010100001001001001001011010001000110101100000010010010111111000011011000010110000100001010000101101010101100101011101100001001001111100010000001100001000011110101100100111111101001001111110011101010100100110001010011101110100001000101101100001110100100110110001100001101101000111101100001110010110101110111000000011100001101110101111101111110100100110001000110101001101111111001011010000011110100100100011011101011000000000110011001100101001010111110101101110101011010100111001001100100110000010000111001110100001001000001010100100111100100011011110001010000110000000000101100010111110010001010000001111011000100110111010011100011001101111010100100111100100101010000000101010101000110110100100111010111011101110110010000010110001010000101000110011010000011101000010100101011000101100001111011111111000100001110010111100110000100001010101110011100101000000001101000000100000110100000010100100011000111001111101101000011001010111110110001001000001100010011000010011010110000001101001001000001111010101101101100101101011011001111011001110001011011100010111000010000000110110000010110011011101011011110111110110011011010000000111101010011000110011000110110000000111101010001001101100110010111101111000100111000010100010000011010010001100001110100100010010011110001100001010111011010011111100101010001100110011111100000011110011110101011100011010110101010011011001000101000101100110001100101111101101101111011011011000001110000001001110011011000001101001101011110001010011110111010011001110011111011101011111111011001100011110111000011100011001010110011011000011011100000110010100000110110111000110111100101001111101010011100010101000010111001110011111010010010101001001000001110010011000101110111010000100100001010011110000100110111110100001100000100000111110110110100111100011100001111000101111000100100001100011101111101011010100101100011101110110000101111000110100011001101101010000001010000111010000100100000100111110111100100010000000000101011110010110010101001011010011010000001111000010100110101101111001001001011110100000111111110001110110111001101100110111101011110001000110101101100010010000111011011100011111001001001000100010100010100110100100001000000011110000000100110101001001100001110000110110100001011100000010010110110110011010110101101000100110001000100101110101000001100001011100101101010111111101000001010111110000101001100101001001110110010110111001100111111001110100111000011000011000110110111101011110100011010100011101011111111011010100000100101111001101001111101101000000100000110100101001101101111111110010001010011001111111110011011110001011010001101000100010011011110011110100001100110101101110010110101100000000111100011010100100011001111111000100001110011101100010100100000001111000110110100010110000001001011010011001000010001011011010100110010011010111001000101110110111111001010110010000101101010000001111011110010000111011001011111100000100011010000110110111010100001000101010111110111011100000101100011111100110011101011101011101111000011000111011001101010100010011001101011111101101110010111000111011111011011101100111111001000100010011000101110011100101100000101011101000010101000011000111101100011111011111000110011001110001100010111001001010110010000001101001111001001100110110101011011111100011110011011000111111111011110001001010111000011000110101010100011101001001100011010100000000110111101101001000001001101100110110011110100100001010001011010000101000011010011001010110000011110010000000010100011010001001111111110101011010110111101011000000110111101111100101110110100001111100001001101101000100000111001110110111011110011100000101011111001111100000010011110110001110000111001010000110000010011011010100001100101010111100011001111100010111101000100101011001
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Generating RTLIL representation for module `$paramod$7b8cb1da04fed3d66ce255399d919ce21f80702b\$__ICE40_RAM4K_M123'.
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2.9.19. Continuing TECHMAP pass.
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|
Mapping memtest.mem.14.0.0 using $paramod$7b8cb1da04fed3d66ce255399d919ce21f80702b\$__ICE40_RAM4K_M123.
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2.9.20. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K_M123'.
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Parameter \CFG_ABITS = 11
|
|
Parameter \CFG_DBITS = 2
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|
Parameter \CLKPOL2 = 1
|
|
Parameter \INIT = 4096'0111111010011100001001110101101111111110101100101110100001110000100011000110111000101011010000110011100110111001101001010101101001011010001101001001110100000101111100011100000011100001100101101011111111011011001101011011011000101100100001101000110100011101111101010100111010001000100011010100100000111111100101110000010000101111010100010011000101000001001000111101111110101001000111100011101001000000001010001010001000000010110001010011001110011010110001111010011001100000100111011001001011011110011000001011010010110111100010110110100101011000011010001001000011010011101001111001101001110010101000110001001101111100100100011000010001011000101000110010011011010101110000011111110111000100110111110000001111110100001011010110100111010011101110101101011111101010000000001110001101000010001001001011111110000100001100100001001011011000010011110011111011011000101000110110100100100111011010011110011110100001110001101000110000100000010100110111001110001100111100100000100001010100101010110111100001000111010100110101010000110101110101011010000110110010000100110111010111001000001111110010100100010111110100010011110010111111101100001000111010010001111001001101111100000000001010101010011001110111100011111011000101101100010011010011010110100110011000000100111110011110100001001011110010101101011010100010100100001111101100001000010100101010001010100001110001101111100110111010011110000110111110001010011101000101111001011100001000111001100110110011001101101001100101001110011001111111111100011100000001011010001010110000111001011101111000010010000111011110100111011011110100001111110111000000010010001101000110101000010011001010010100010101001001100110010011110101100100101100111010010010101100111010001111101010010101011000011111111101000110110110001100110111011110111111001011110011100001001110100010001001010101001000100011110100000001010111101110100110101000000000101000110100000101101000111100101010010010110100000001111110110101000011101100101000010100011001100011111110001000001010101000110000010111011101101111110110100110010100000000000010100000110010111111100000000001010011101010101111001000001100111010110000110000001011010000101010100111100100000111011110101111101110110110111111111000001001100110011100100011101101001010001001011111100010101110100110000011010000111110100101001110100001010010111010101011001001000100101100101100011100101011101000000011011011001011010110100101001011101110010010110110111100010101100010001000101010111011100100110000111110010010010000110010100000100100010110010010111011000101001111111000111000000110101110011011110010011110000100010101110100110010010101001001010000000100001111001101001111001111011111101101001010010101011100110010011101000000110110001100111111011001101111011010110111100001000111100111110000101010111110010011000110101100011010110010001000110011110011100110101001101111011000100010100100000110111100000010010010011010101011111001100001100100111101010111111100010000100000100011000001010100001101110100110010100000110010001010010111101110010100011110001101101111100010100101010110001101100000000100001011010100101001011110111001101010010110001110001001001101001110100101000110010101100100111111000010101101110001000111000001101110100001000111000010000011000111001010101100010101011010001000101000111101111001011010000001001010111101011110111111011100001000100110001000010101001000010110010011000000000100001001110000100010000111000000011010001110101010010110000011010010100011001110000101011100110011110000100111001101100101011000100001100001101110010101110011110000011011101101000010110011111000011111111111111010101100110111111100000000010001010111001111011110100100101010110110110010110001000111001001100000011100100110001011110100001010100111001110001111001101001001001101010111111000100110011000001000101010111010010110000000010111001000111010001010100111100101001101101111000010010000011011100111001010101001001011011101111100110010111000101000100100100100001100010100110000100001111110011111111100100000101000100010000110011000010111000011111100000101000010110010100101101101110010100101110011110101111010001011100001101101000101
|
|
Generating RTLIL representation for module `$paramod$8073cf2e09cf7860fd8803aa0caf58a2b7b19846\$__ICE40_RAM4K_M123'.
|
|
|
|
2.9.21. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.13.0.0 using $paramod$8073cf2e09cf7860fd8803aa0caf58a2b7b19846\$__ICE40_RAM4K_M123.
|
|
|
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2.9.22. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K_M123'.
|
|
Parameter \CFG_ABITS = 11
|
|
Parameter \CFG_DBITS = 2
|
|
Parameter \CLKPOL2 = 1
|
|
Parameter \INIT = 4096'0010111100001011100011001101110101000101000101101011110100110001010000010111111111000010010100111000110111110001001110101110100011001110010111011000001000001110011000010111101010100100110010100000111001100011110010111100001101110110100100110010011100101001111101010000101111010011010111111100000010100100101111011001100101001010111101111000110110100111111000101101101000111111100111001111111001110101011010010101010001010011011000011011010000010101101001001111011110010011100010000101000011110100110001011110101010101101001111101101100000101101001011100110100111001011001101011010111111010111101010101101100100110100100110100010010111110100111000010010011100111010101000110111011000011001011100001000001000100101011101100111010001001111101100000001000110100100000111001110011110001001100001100011001110001010101101000101000101100010100011011110111011101001000100011110010001111111101000101110010100010100010001110010000011001101010001001110010100011000011010111010100001101000111001011100011000010111010111100111011110010000010000100000010101110110100111000010100000111110000110111010010100110100111110001011001100000100001110101110000011000101101110111010011001101100101101101101000110100100001111000111100010010101011001100000001111101010000011011010111000001100010000111101110100011101000000100100000101100010110100110010000100001100010011111110000010111000000111100001001001000000001000000111000001110000100010010110000101010100011111011001101000101001100111100011011111110000101000011101101111110110001001011100100000001111101111000111111101100010001111101111101101110000010010001101111010011001101111101110000111011111100100111110100111011011010010101001000101011011000000010111111100100100110011001000101100111110110011110000000110011001100111001000100011111001111001111001101111110100110101110011100011010101101100001110011111110110101101000110000000001011111111010101101001100010011101111111001111010001011111000001100010011110110101101010101110001110111011001001100101110001110110011110100011001010111001010011100001000000000100000111000101001011110110010000001011101011110011101001101011111010000111000111110001001001111100011011101111011000101001001001000100010001100110110010101001100101011000000010010111100011110110001100011001100101110011001111101100100101001001101001110010001100100111101000010100011000101010100110011100111000100100111101101101010001110100011001111100001011011110011101100101001101100111011010010001111000001111011111110100000111000011100110111001011000110100011011010010010010010011111011001011111100011111110000100101110010101100100110001101001100011010101110000111000101010011010011110100010110000101111000011100101011100010010110101101000111011100010110011101001000000110111101010010001000011101100101111100001000010111011110110111011111000101011110110010111111100101001101100100001110101001110111010001001001000110001000100110001011100000101001010000101100101101011111001011001010111111000101111010010010111001001011110101110011011111010001011100110010011011011010001000111001000011001110111110010101100111110100101001011011000011111011000010000000100000011111110101000111100000100010001010011000001011101101101111100011011111000100110000111111100100110110110001101000011100110100100001000010010011001111100100001111100010001011000110011000001100010000110100111001100001001010111000001110100010001100011011001111011011001100000010100011100011111100011001110010011011100000001000101000111001011010110000000011110101100111101011000101100011101101110001110100001100101000011110000001011000000101011011010111110001110000000010000100001101100010101010101001110010110011111100101110100100101000101001101101011101000110110100100101011110100111000000110001110110011000001001011111010011010000011101000010000100110110110100011010101111000011101001111101111001010111110010101110111010101011100001010011010000011110000101011101100110000000110101011111010101001110110101101101000100010010100010000011100100000111100001101101010100000110101011010000100101011110011011111100010111011010100000110010001101001110000011000101000100101001110010000111111010001100010101111110
|
|
Generating RTLIL representation for module `$paramod$7601470b7257c750062785939abb2cd6c78f255e\$__ICE40_RAM4K_M123'.
|
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|
|
2.9.23. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.12.0.0 using $paramod$7601470b7257c750062785939abb2cd6c78f255e\$__ICE40_RAM4K_M123.
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|
|
|
2.9.24. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K_M123'.
|
|
Parameter \CFG_ABITS = 11
|
|
Parameter \CFG_DBITS = 2
|
|
Parameter \CLKPOL2 = 1
|
|
Parameter \INIT = 4096'1111100101001101000110010011111101000001011000010110001000010001111010110000001011110101001100000000111110011011001000011110111110101101011101110111011001000111000001111110011110010001010010101100000100100101111001010010010001001000000100111111001101011011001101111011100100001010110111100011001111011110110101010101111000100101000100110000100101010111100110011000010111010100001010010000111001101001111010000011010010000111011011111111010100110111101000100010000110011011000110101010001000000101000000010000111100111101100001100000101001000000101000000101101010001001011110000010011101001101010111010101011111011110111100011010101110100110101111010011001000011101011000100001110100001101110100100100101101110010111001110101110111000100100010010110010010100110001101111000000001110111000001010001101000001101100011101010011110100000001101011101111001010011011000010110011110110000100111101000111110001011000010010101000000111000000000000101000011010100111101010001001001111100001010010011110101101100001001100101100101110011101001011111011000101110001111010100000100110001101011000111101100100010110101000101101111000000101110101000110110100010010011111011000110000011010010111011110001011010011011110111011110011101000101110010110110001101110111110111110110101010101111000110000100101011111101001010100111101101111010001000101100111110001011001001110101110100110000110001101101101100010000100101101101000001111110100011100011110100110001111000011111101110001000101010000110101101000111001000110010110101011011100000100010100110011000001101111110011000000100110001110100101001011001010101101110101000111011001000010100101100101010001111001101010101000011011000011001011101110100001110001000110111001100100100111010100110001010001011010101111011010110110010100101001101011010101100100000101010100000011110100000000000011001111010101010111001011110000000101111111111111101100101110101011011111010001111101011101010111000001001111011010000110110010001001011101000111000101111010110110001101110110010011100101100011001111001110101011001110111101101001010000000100010100001001000001110001000000110110110101001011001000011010110001001111110111001011100001110101101110000110111111011001110101111101111010111001111101001110011010101001001111111111000111001100110110000100110001111111100100101010100000000011011010101101111111011111110100000011011111010001010001100011000100101110000100110100101111110101000111101110011011111100011010101101101110001111010101100000101100111110001011011111110001110000000011001100111000001101000010100111100100011000010110101110011100010100001101001101011010110101011101001010001111101111111011111111011110100100011010101110100011100101110101010011101010110010011101110000111110111001101000110000001000111111000101101001001101010001100011101001110100101101010011111011100011011001011000010000001000110110100001010100101010011111110011011010101111010011100111100101001001101111000011110000101001011100100100010100000110101000110000010101000001001110110111000001010110001010101111111111110010111001010011100011000000100001011100011000111111010000001001110001010110001100000010100111110111111000111101011001011000011001111111011111110011100011010000110110110100111011010100000010101101011100010001110000001000110010000101100011010011001010000001110110110100011011011000111110001011101000110101110010001100011110000001001101001011101010010000011100110110000101110100111111100011100110110111110000000111001011101010010011111011000010100110110011000100001111011110111111100111010001110011010110111100110111010100000001110011011000111010011100110111100001110101001000111011100101001110110010011110000000110110000110001101100101100010000000001110101010011001001110110001101011001000100100111110100001110000100111101111010011011000000010000011000010100001101000001111011100110110011101110001101010010110100111111010101000100101101011001011001011101011101000110110010101100111100100000101010111011111110011010101110000000001110010101111110110111111100101100000011000111100010100010100111011000111101011101100101010110011011011000001001101101100000101101111001110011001000111100001011
|
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Generating RTLIL representation for module `$paramod$ed9f319bde7ce6671112de05e5b97d1e60af8ddd\$__ICE40_RAM4K_M123'.
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|
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2.9.25. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.11.0.0 using $paramod$ed9f319bde7ce6671112de05e5b97d1e60af8ddd\$__ICE40_RAM4K_M123.
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2.9.26. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K_M123'.
|
|
Parameter \CFG_ABITS = 11
|
|
Parameter \CFG_DBITS = 2
|
|
Parameter \CLKPOL2 = 1
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|
Parameter \INIT = 4096'1101001001100010101100100000010110011110010111100101010000010001011101010101000111011000111100110100110101101001110101111000010011111010010110010001001001110111111010111110011100101111001110101110111111010110011101100000011011101100100100101111111110001111111111100010111001100111011011000101000001100101011010110110101111010100000101101000001110100000010111101001010110110000110010100011110010010110101010100101010110011110001110010101011100110111011101000010001000110000001110001101001101111101010110010110011011111110111000100100000110000011001010101100110101011101010101010111110101110001011011111110000110111000110000110011010101010000111001010101001010101010000011111100110111011111100100111111001011111110101100001100011100000010000101101001101110010111101101111100011001101011001001111110001110111011001000010011111011000010110001001101100001010010011000110100001000100100000110110100100101100010110111000011110110101100010101001100001111000001110000101000011010011110000000101111110011000010010000111101100100100001000010111101101010111101001001100001111001111110110111000000110010011001111110111110000110011110110111000110011100101000000010011010001001000000110101111001111100111101001111110001001101010101000110011010000101010111111011011110011111111111110111110111001011010000110100001000000100010011110011000111000101111101000001010011000010111100001001110100010010100010100110010101011000011111111000000000101011111010010101001100101010111101100101110101100011010011101001000001001011100101000111100100101010001010011100010010101101010101000100101010010101010101101010000111101000100100010101101001000010111100100011011101010001001000000010011010111000101011011011111110010101110010010100000001011010101101000111001101101100101000010111111010111011011110111110011111001100000011100010100010001101011101110000000001111000101110011101010010011000001011101011011001100000001000010010101000100010001001101111000111001011000101110001001111011000001110101110111001011000101110011110101101011101001000000001110010011011001100100011000101001101101011001110000010010011101011110110011100101101110101111100110001100010101110001010101111111011111101001000001010011111011110100010000010010010110000001001010101101011101101100001101000010100100101110100110011110100111001101001100111110110001110110001101001001100011000111100000001111110110000101001101111010100101001111111101101110110101111110111000110011011011101010001100101011001011000000001111100110001011101000101011110110010101010011011101100001111111010001010000001000000000100010100011111100001001111001011110011001010110111001001100001010011000100011111000100010100110001001100101100110001000111110110001001101011111011100100101111001010010011011001111101111001110000111011001101110010110010110011111001001010011010001011010010001001101001111111101001000101101010110010110011011011011001000100110111010111010110011101110001010101011011010110111001000010011100101000011101111111011000101010101100100011100110101011111111100110011100110111101010101000010011010101111010011110001100101011100100000110001000110010001100001110011100111111101101101001100101000101011100001011011100101011101000101011000011110001111111110111100000111000001110011111110011101110100000100110100000100001000111010111001101101010110001110100000011111000001110101100011111010111010111010101110000010001010110001011010000001101101010100000110000010010100110010000101000011011110010010110010101000111101101001010100110001100111111011101010010111110001111011111101001000101010000111001000011000000100110110101100001011100100010000001001100011001001011100101111010101011100001010101101000110100010101101100111100100010100010100001100101100001001011101100100000000111111101000100101100000110111011100011001110110111101110010001111000101101111110110000110010101111100111111111110010001111011110010110100011010010111111011111001000101111100110001000110111110100100010111111010011101101100010101100001010110011110110111111110111011011100110101111100010001100110101101111111011111001000001000111111111101100111011100010111101011000010000111111011100011011010110011111111111
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Generating RTLIL representation for module `$paramod$445d200a8547cde57317e073680b424a372d97e1\$__ICE40_RAM4K_M123'.
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2.9.27. Continuing TECHMAP pass.
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|
Mapping memtest.mem.10.0.0 using $paramod$445d200a8547cde57317e073680b424a372d97e1\$__ICE40_RAM4K_M123.
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2.9.28. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K_M123'.
|
|
Parameter \CFG_ABITS = 11
|
|
Parameter \CFG_DBITS = 2
|
|
Parameter \CLKPOL2 = 1
|
|
Parameter \INIT = 4096'1101101000000010010011000100000001111100110000000100111101100100110111100101100010101101110011000010101110010000010001010001001111000001110111100010111001110100101001010011000001101111010000111001101110100101010011111000001101111000011111100001000111110100001111000001111000110111111000010000000000110000001001001011100110000100001101100000111100101110001011001100110010110111010101110011110101011100101111010010010110011101101111101010010010001000010001010110111101100110111001110100011001101111001011011100010110111101011011111010110101110001010000111100100000010010000000110010100101111000011010100100101011001011100111101111100110111101000110100011000000001000110100010001000010011101101101011011101000011100110010111101010110101000001011110100111011101101000100111111011111001110000000110000100011001111000000111111011111001010110100110100100010000110101010010000000111111111001110110111001110011001111100011000010010110010000001010010001011011100000011100010011011101001111111010110010001010000111011111110000001110101100001100010110100011101110000110000111011111110101110101110010101100000000000111101100011101000101001110101101010000000001000100101101100010100110100010000001001100010001111001001111000000010100111100001001011111100001101000101100010000010110011111000011100000010001001101111100110000111001101000010110001111010100101001010001011100000100000101110010100001110110010100111111001100111111001100010110011000001111011100001010101100011001011110111000110000010111000001010000100111001100100100100010101111001101001011101010100101001110110101001001101001010110110010001100101111011000100100010010110111000110111101011001110000001010101011010001101001111110000111000000111010011101100111011111000010000011000110001011010010100011110010001000111000001001000110000100100100101111101110001010011111101010101101000111000100111000110110110110101010100100000101111111110111100100111001111110000000001000100001100110110011100100111100001110001101101110100000111110011001000101110111000101101010100001111000011011101010111000111000111101000111111101011101110001010101101101111101000001110000100100110011010100111001011110100110100000010000010000011011010011110111010010100001101011001000101100000100100100011110100010001100101001101000100000000001100000010110000101100100011111010000110101010100001101000101101001001111001111100010000101111000000100010101110101111111001111100110011001010000111100110110000000101010011011000100001010100001110010010010011110100000110011100101000100111100000100110000110010110101011101100100110110011011100011101101000101001111110011011101100010000010101001111000101110101011110101011110100001010010111101011111100000000010001101110100000100111001011000111000001111110010001100001110111011000001101101011011011111011010011100110010101111111001101100101100010011110011011110100101011110001011111101111110011001110111101111100111010000110001101001111011010100011101110100000111110001010110110110101000111010111001110010110011100110100101110110000101001100110110010111010100100101111101010100001110101101010000000110011100101001000111100101110010100010110011010000110010110001111110100101100001001111011001110100011100000100001011010011011100011010001010111011010001001110001111000101101110111110001110110110100011001101000101100101000110011011000010011101000000001101100011001000111111001101100110111010001000000010100110001010111001000001010001010100010000000011000110011011011001111001010010111101001001101001011010110110010010010011110101111111011010010100001010111100000110001010000111010111110110010100001100001111011001100111010111000011111111111100111101011110000001100101001101101100111001101001011011000111101001000001010011011111010001100011100000001101100111101001001010001000101001111101001111101110000000010100001001011001010101110101011110001101110010011100100001001101110010001010111000100111010011011101111011100001101011101110010111111010010001011011110110010110111101011011110011101100111111000010001011111010101110000000101010100001010100110100001110100010101001111101101101011011001110011111111110001111111000010101010110010010111011111
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Generating RTLIL representation for module `$paramod$fd670452d9656a3e5387849f125a1ac30d4f6a6c\$__ICE40_RAM4K_M123'.
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2.9.29. Continuing TECHMAP pass.
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|
Mapping memtest.mem.9.0.0 using $paramod$fd670452d9656a3e5387849f125a1ac30d4f6a6c\$__ICE40_RAM4K_M123.
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2.9.30. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K_M123'.
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Parameter \CFG_ABITS = 11
|
|
Parameter \CFG_DBITS = 2
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|
Parameter \CLKPOL2 = 1
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|
Parameter \INIT = 4096'0001110011110010011111010100001100101010011110000101101001001110001111111100101100000001011110010101001111001010010010100111010000110011000000001000101111110000010011011000101110001101010011110100010101100011011001000100110010110101111110110000111000111000001110100110111110111110101010010011111101111011011110100001010111100110101111011010101010101010110001110110011001110000001101100110101111100100110011000110111001100100111111001101110000010001101111101100100000100101110100001100110010011011101001100001101100111001001100000111110011001101110101011111011001010111011100001100100010101110010011110111100010011000111000100100111011011111111001111101111100000000001100001001101001110101110001000000000101101101011001000011111000001000110110110011111110110110001011011101000010100011110010000000110001000011110111100111011001011010101100001101110101001011001110110010111001111000001100001100000110100110011000100101010110000100011000111000010101111010110010100000001100110111110110100000011010111001100010101000111001001010001000010100100001010101111011000100110111001001010010101011111011010010100001100000101010001011010011101011011101110001000101001100111011001011100001000010110110010101010011001100110110101001101011001000011110101001000001000100001001000001110100110100011010000101011100000010101010110110111101000100110011011101010100111100110110010111111011010101111000010001100101001011110100000110011010010111000100011100100010100010001011111111001100000100100000111100100011000011011101000001010111111000000110001011000010100101011001001010101100100101110110001101111101110101010000100011011111000000011111100101100110101000110000111011000110000111110010110101010001010010001100110001011111100111111110110001011011101011011111010010001101110011011001010001010010001010100100001011001101010101101010010100110111101110010001101110011101000010101000001111010010001101000101101100110001101101000100001011111111001111011101111100100001111111010001001000111000000010001011100001110011001011100111110101000101011011110000001111111001000001011001000100000100101000000001100110010000011111111101110110001000011101010111110110100001001101000100100000000101000010000111001111010000111110010011110101110100011010000100101101111111011010100010101101010111111100110100111011011000001010001001001000010110101011101110000011101111101101001011001011111000000010101011011010010100001100110101111011010100101000001110010011000001100000101001111000100101111010110010100011010001111111001000101000100011010111100010100001010000110000010000100001111000101100011101111110100001001111010001101000101010100010110001111101010101000101100011110000001001110010000011001101100101000001100001011100000001110101101000011111101100111010110111011111000000100101101001001000100010000111000100111101100000001111011010000010110000100010010111110100110100111010001000010000111001111110110110001101101101100101100110101101010010011010001001000010111000110001010100110000000100101111011110100010000010101101101001000000101011101100110111101111111010101110111011110100100111100111011001110101100010011010011010001000100100000110111111010010011110001000010100001000110010001111010010000111010110001110011011111011001001010010110110000100111010111100101100011001101001001010101010100001100001000100000010001011011111011011110011111000011011001100101001000001000001100100010010000100111011110001101110011111011101100100010110001101100001110100001011001010011100001000000101110001001110000110000010000110101000001101011100001100010011000101000000110101010001010001000011100100001010100001000000001110100100000111001000001111110101000000110001000100001101101101110001011001000011111001110000100111000001010100000100100110000100010111000010001001000001011001101111100010100111101011000100000101010110011010111101111111001000100111110001101101110010001010010101111110110001010111111110011001101101100010101010000010101010111101010000111110110001001001001010010111101000101010000100100111110101101101011010010001110111001001000000000011111011000100001010010111000001001100001001000010100001110010111100011011011101101111101100111100
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|
Generating RTLIL representation for module `$paramod$cfd4752fe4396a11f4067e795ded473203abc81d\$__ICE40_RAM4K_M123'.
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|
|
|
2.9.31. Continuing TECHMAP pass.
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|
Mapping memtest.mem.8.0.0 using $paramod$cfd4752fe4396a11f4067e795ded473203abc81d\$__ICE40_RAM4K_M123.
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2.9.32. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K_M123'.
|
|
Parameter \CFG_ABITS = 11
|
|
Parameter \CFG_DBITS = 2
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|
Parameter \CLKPOL2 = 1
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|
Parameter \INIT = 4096'0011101110101001010010111010111100000000101110100000001000001000000100000101110010000110110010001111100010010000100101010110110100110011010110100111001000011000010101010010011111011100010111111010000001011001000000111110000100100110110100000100010001001010100010101001001100100000110001100111001101010110100110001101110000110010110101001110000100010001100100110100110111010101000111100010101000101000001000010010010010100010110001101101101100011101010011001001110000011010110100010000001010111101110011111000001111011100101000100000110001000000110101101001101110110110101011100000110011001111000010011000000000011001011110011110010111100111111011010110100010011111101010100111000000001101100100110000011010010111000110011110001001110010100100010110000001001011000111110100001000001011111110101010001000010111100101111111011100010101010101101101010110111001111010000100101011011000010010100000101110001110101011101101111001001010110010111100100111100011110011100001101100111100100101011000010110010000101011101110111110001010001001010010000100100110010001010000101101100110101010100000001101100011001111011111111010000010010100101101011001000001010001100111010001100100010110011001011001110010110001101010111011000011101000010000110110001111100001101100000001010001000101100110010011111000010011000101110001111000011111011010011001101111011111000111110011001101100111010000000110110011000101101000010100001111000000000110000011100011000100110100111010011010001010010010010110000101011001110100010100110110100110010010011000100111101000101111010001000000110010100011011110001011110110000010000000111011110000000000111111101011111110101101001110011101001000111100001010110100011010110001010110100000010010100101110001100010011010101001110000111111110111010000100101010110111101010111100000111001111101001000101111000001100011110111110110100001010110111011110100000001010011110110110001111101000100010110100101000000011011010111010100110010111011000100010011101000111001000101001111110010000000010000110101111000000011011011110101101100110101010110000001111111101001010010000111010011110110010001110110000110000100010000001011000111110000010011101110000001001110001001000001011111011101001001011111011111010100011001111001111000101001110011000000101010010000011001001100111001101001101000110011000000100010000101101000110110000111111100000010110010100001111011000001101010100001000101110101110001000001001010001011100100101110101001001111111101100000110100011000001010001111011110000110011001100010101011010011000001110100100101100111010110000011101011011111010001011101111111111101101110000010010001110011000111100111100000001011011001101001110101010011110000110000001110000010000000011101011000100011110110011011011001110110000101010101100101001100101011011000100001011100001101010110100100011001111010011101010100010101010010011010010001101100100000100101001000011111001011101111101101100111111101101000100100100000010011000110111010101001000101011101010111011001001011010011010110110010001100110010001110011100110010101100100010111010001011010001111101101011101100000011011001000110110000111101101110011010101001101111001011100000110001100111001001010000111110110001110001101100101101101110001001101010011011111000000001011101101111100110000110011001111111100111110111000100110101101100001011001001000000010011010101000110000101011001100110011110000101100011000001010110001111111000110000111010111101000011100011111010100101111110001001011000110001010010010000010000110000000101001110000110011000010100110101101001000100001000111111001001111100100010101001110011011001110010011000001010000000101000110110111100001100010000011000001110101010110010000000111110111101010101111101011110010100101001100100011100111101011100011011111110000010000001010101111110011111101011111001010111011111001011011110001100001111011010110110000101110011111000111111010100011111010101000110010100110000110101001111001011011111011010010100110101111000101110010101001010000000101101111101000101110010111111100101010001011101011001111110001101110010101101100000111000011101110111011001000110100100011110011010000101000011
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Generating RTLIL representation for module `$paramod$5009aff4b1d58846e35b9e6a574f5b3bbebc226b\$__ICE40_RAM4K_M123'.
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|
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2.9.33. Continuing TECHMAP pass.
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|
Mapping memtest.mem.7.0.0 using $paramod$5009aff4b1d58846e35b9e6a574f5b3bbebc226b\$__ICE40_RAM4K_M123.
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|
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2.9.34. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K'.
|
|
Parameter \READ_MODE = 3
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \NEGCLK_R = 1'0
|
|
Parameter \NEGCLK_W = 1'0
|
|
Parameter \INIT_0 = 256'1101100000001001010111011001010101011010100000111111101110001100100010010111100000000100101001111001010111100000011011101011001100101101110010001100001111001110100110101101000111001110101100001001011011111010001011011111011111100010110000101111111110110111
|
|
Parameter \INIT_1 = 256'0010001000101110000010000010100000010010111010000001101101110110010100110000000111000010011000101110100010000100010010001001100011100111001001110011100111100011001000111011011101110100011001110101110010000101011000011000011100001000010101110001001011110001
|
|
Parameter \INIT_2 = 256'0010010111001001111110010001001111110111101100001001011110011110001100110001100001001010011011001011110100010011111111100100010110001001011011011110100101000110000111011111101010111101101110011001011111101001010011100101011011101011001110110101011011100000
|
|
Parameter \INIT_3 = 256'0011000111000110010111110101010100111000100000011110010101001110001101111001010111100000111001111111100101101010100101110010111101110100001001010000011111000110000000100110011001110101101010001110101111000100011000111011100011001010001100111110010010010000
|
|
Parameter \INIT_4 = 256'0010100101010110101010001000001010110110001110011001001110010001110001100011000110100100111010110101111000010000011100111010100001100000011001000011011111111000000100010100110000101011001010100101111111001010110100111000100001011111101001110010111010100000
|
|
Parameter \INIT_5 = 256'0010011110011011001101101011000001001101101010111101101010000101101111101001111001011111111010000101001100101101001000111101111001110111100000101010111001110100111010100101001110001110001000101011110011001111111010110110100001010000000111001001011100011010
|
|
Parameter \INIT_6 = 256'0101010000101110111000100101110010010011101100010101001101111100101010000011001000011111011001011010010010100001101001110111100000010101111101011101110100000011111100011001111011100101000101111110101011011001010010011000000110010000111000001111100111101001
|
|
Parameter \INIT_7 = 256'0001101101000011101000001000011111000110101000100010001111000110101010010000101101100111001001001100011100010001011110010111110010001110110101001111000101000111010000010000111111101011110000011000001000000101110100000010010010011110100110101011100100100011
|
|
Parameter \INIT_8 = 256'1010101111110101001110110100010111001100011000111001110011100100000010100101111011100100011000001000011110000111100110010010110001101010100110101100101100111000011101010100110011001001111110110010010010100111110001001100001111111011000111100010000101110001
|
|
Parameter \INIT_9 = 256'1101011110011011011000110001111111001101001111111100000100111001010001111001011000100001101000101010000111101001001100000111101111010011000001010010001011000010101010100110011100110100101100001000101011001111110010010100111100011010010110001111111001000011
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|
Parameter \INIT_A = 256'1001110010101110001011010000000101111000111111000001110100001111011010110111010011101101011111110000011011100011010111001001000010011110010101011000010101101010001000111100001000011001010101010011100111101011010010001001101010000000000000100001010110110010
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|
Parameter \INIT_B = 256'1010110101111001000100010000000111001010010110000011001111011000001101011111110110010101010001110000110011101001111010101000101001101001010000101010011100001001111001011010111100011011100110111000110110111000101001000010111001011101111001010001101101010010
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|
Parameter \INIT_C = 256'1111110101010010000011011111100000100000001001100100011101001101100000001100010001101101110000000011111111110000110010111000101100101010010111110101100100111100000111111110110011001111100010001000110011110011001110111110110001100100010111100101000110010101
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|
Parameter \INIT_D = 256'0011001011000111011011011100000000010011001110001110100010110100011011111101011001100000010000100110111011111011000110000111110010100000110000001100011110010111111101110001100011001011001010101101010001110111000101101001111101000110101111010101111110001111
|
|
Parameter \INIT_E = 256'1000100101010000000111001100010001100011101011001001110101001111010001001000010111011110110101011000100101111000010001010100100010110100100101011010111011010000101110010100010111100010001011000100100101110110101111001100111000000011110001101111100010101111
|
|
Parameter \INIT_F = 256'1000000100010111010100101101110011101000010101111101000110011001010000011001111111001011110001011011100001011100100101010101000001000110100101100000001010100010001011101000101000110110101010110000001010110011100110110011001100010011111011000010100100010100
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|
Generating RTLIL representation for module `$paramod$cbb4b05670fab0c57b8d232886128f1d03d9d12d\$__ICE40_RAM4K'.
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|
|
2.9.35. Continuing TECHMAP pass.
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|
Mapping memtest.mem.0.0.0 using $paramod$cbb4b05670fab0c57b8d232886128f1d03d9d12d\$__ICE40_RAM4K.
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|
|
|
2.9.36. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K'.
|
|
Parameter \READ_MODE = 3
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \NEGCLK_R = 1'0
|
|
Parameter \NEGCLK_W = 1'0
|
|
Parameter \INIT_0 = 256'1010110001101001011101001010010011011001110001011100110110101011001000111111001000101000010101010000100101010110000100111000100010101010001000001111000110111001001101110111100100010011000100110100111010010000100111111010100011011111111011000000100101010001
|
|
Parameter \INIT_1 = 256'0001011001110000100101010101001010000101011001000010000001101100011111010011000001011011110111100001010111100110011011110010110011100111100110111001010000011100101110111111001111001011010100000111110001011010111100100000010001001101001100111011010111110010
|
|
Parameter \INIT_2 = 256'1011100100011011111010101100111001110111100000001101011111001110111000010010010101011010001101001001011010000111011100101011110111100010100111111000101000011111101101111100101100100000010101111101101101100011110100111101111101011001111100010101111101001111
|
|
Parameter \INIT_3 = 256'1110111010100100001011011010100000110000110000000001110110101100111110100001010100011011110111001011101000001001110000011111110110100100010010101110011100000111101110111101010010011111100010011011101000100110101010000000001001011111000111101010100111110010
|
|
Parameter \INIT_4 = 256'1110011000010011001111001100000001100111001111111111001100011011101001100100000101011011001000111101010011000010001100011010011101100010010011011100101001101110101111011000110010101001010001111111011000101111001101110101001011111100101001101011100101111110
|
|
Parameter \INIT_5 = 256'0110010011001010100101110101101010100100000111011010001000010101111101100010110110010111010110011110111011010001110111110111001100011110001001001101111101100001111100101111011011000000110010001011011010101101101000010000000000101001100001100110000000100100
|
|
Parameter \INIT_6 = 256'0010101101101010011111101000010101000111000110101001010011111010011111000001001010100111100000100001100110000011011101111110101100101010101010011000011111001111111110111100001000110010010110111111011110010111101100111110101100101101100000100010001001100111
|
|
Parameter \INIT_7 = 256'1100100110111010100001110011010010111011101110001001100000001001011001010011111011011101000001100100111000101011110100110000101001010011110011110010010101010111000001011100101101010001100110001110110100001010000111101010011111111001010011101101101101111100
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|
Parameter \INIT_8 = 256'0110110111101001100001111111001001110000100100000100101111100011000100011100000011011100010001111000010010011010100101011001111000110010100111111011010000001000010101011011111010011100001100110001110100100011001110001111101010011110101011101000011010010110
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|
Parameter \INIT_9 = 256'1110111001001110110001000011111100110011000011011001010100100010110011011100011011111000101110101001101110001100100000110011010100110100011101010011010100110011010101110010110011101111011001011000111111001110100111101110011101001010110011011111111111110000
|
|
Parameter \INIT_A = 256'0111101000100001101001110001111110010110011001001100100100011101010101001011101101100000111000110011011001001001110010011100110011111101110010000001101111010010110011101000111100101010111000000101110000011111110111000000111100010100001110010011001010010001
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|
Parameter \INIT_B = 256'1101001111111001101111100110111111110110111101000111010000100010000110010111110010100000000111001111101101110010001111101001000001101110001111110100100011111000001111000111011000111000011001001000011101011010000010101000110110000001100110010101110001110000
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|
Parameter \INIT_C = 256'1011011111100010000111011001100000000110011101111101101000011110111010101010100011001111011011011000001011000000110000000011110011001001000111000110101110011011011101011110011001111000111010111011110010011101110110010110001011000110100111111100101110010101
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Parameter \INIT_D = 256'1010000010110110100011011000110001000000011001101010010001111111110001011011010100110111001101000100111110110010100100000110100110000000011111010010001011111111101111111011111000011111011011001000010000001001000011001111101101110101110010011010111000100011
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|
Parameter \INIT_E = 256'1000000011100111001001101001110101101111101110101111111001100110001100101000001111110111001000110010010100101000111011101110111001001001011010110110111111011101110110001010100000111110110000001011000011101101011110100010001100000101100010110011110110001011
|
|
Parameter \INIT_F = 256'1101111111111000001110100010010011110110100110101010111001110101110101111101000001000101010110001101011111100101100101000100011100110011000100010101101110001100010110100111100111010100011111001101101111011001001011010101000110001111011100111111001100011101
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|
Generating RTLIL representation for module `$paramod$b73ffb7dfcbd93c60e85ae9ac7150e85e2cd1c23\$__ICE40_RAM4K'.
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|
|
2.9.37. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.1.0.0 using $paramod$b73ffb7dfcbd93c60e85ae9ac7150e85e2cd1c23\$__ICE40_RAM4K.
|
|
|
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2.9.38. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K'.
|
|
Parameter \READ_MODE = 3
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \NEGCLK_R = 1'0
|
|
Parameter \NEGCLK_W = 1'0
|
|
Parameter \INIT_0 = 256'1111111100101100010111011100010001011111111000111010110000101010001111110001110011010010110100101010100110010101001110101000110001110010100000000000011010010011100010000111111000100010100010000011110001001110000100000000011011000011110110001110001010001111
|
|
Parameter \INIT_1 = 256'0001111101011011001100111010101000110110011111001101101101011011001011011100101100001110001111110011110001010010001000000101100101000100111010001101011101110010010110100001000011100100101111011101100101100110101010110000010111000010110100110001100111100101
|
|
Parameter \INIT_2 = 256'1110110001011100110111010011101111000011101101001101100101000010001001000111111001001010110011001010011011011101000011000111111110010011101011011011001001010111011001010111000000100001000101100110100100001100110010101010110101101000000000010111110010011011
|
|
Parameter \INIT_3 = 256'0110010000110111011100110110100110010000011111001111011000011011111111100101010001011111100001101110100010011100101001110000101111010011100101010101101111101101100100100000100010011111110110101001011000010110111001111110010001010101001011111110111100001100
|
|
Parameter \INIT_4 = 256'0101001011010101100000011001011101101010111110110001010101110100000001111001111010101000000111110111000110111011111110110011010110011000111011010011111001111110011101101000010000110000011111111100000010110001011111011101010010010001001101011010111110101110
|
|
Parameter \INIT_5 = 256'0010100110010001001101011110101110100110001011010100001010111110110010011111010001110011111100101011000000011001001010001101000010110010111011011001100101011110001110111100101101010010101110101011111101101010010000010111001010011011100001100100011011101001
|
|
Parameter \INIT_6 = 256'1001011000110000101011011100011011111000011001111100100000000010000010010000000101010100110010100000011000110011100100010000101010101110101010001001101000101100111000110011000111110111010000111101010011000010110110000100110110010101001110000000110101110100
|
|
Parameter \INIT_7 = 256'0011000001011110110000010101100100111010101011001101000111101111000100001000000010110110110011111000110110100100111000101011000100110001011101111001001000111110111101011010000010001101011000111111100001111110000101101000001011011110011011010100110110000010
|
|
Parameter \INIT_8 = 256'1000010001110001101010000011111000111011011001011010011111100011011111000011011100100011111101010010101100110101011101010110011101100001110000001110000111110011111101001110111100101111010100001011101001011101000111101010000001101110000001011010111001010111
|
|
Parameter \INIT_9 = 256'0100001000010101000100101111110101111010010011010110100000010111010011011001110111011000111100010011111001000001111110000010100101000110010101101000011100110000110001111100101001001010100001110010011101111001101011111001101100111110110111000011000100000011
|
|
Parameter \INIT_A = 256'0010101010010011111001011011010001110000001010010010111010100111001110101111100101100100010100010101011100100110001001101110010100111100001111110001001000100101011000110000010100010101100100110001101010010101101010100100100011000001001001010101010000100001
|
|
Parameter \INIT_B = 256'0000001110011110100110101010100001110000011111011001101001101100001101010100111011110010101100001101001111001001101011110000010011010100011001111110101001010110011011010010010000000100101000111101000010101110001110000110001011101101111011000100110010110110
|
|
Parameter \INIT_C = 256'0010101110001011100111111010000111001001101011101100000111001000000101100110101110011110011101100011010110100110010100101000100100000110110101000110011101001000011111100000010001000111101001001111110100110010111000001000110111000110111010010010101010000111
|
|
Parameter \INIT_D = 256'0011100000000111011110001001001111111101001010110011000100101100100110001000100001000001110110111100100101111001010000000111101001101101101001101011001001000011011110011110111110001110010100001101010101100001011101010010100010011010110101001011010100000010
|
|
Parameter \INIT_E = 256'1011100000010110011100000001000111000010110111001011011001100000100111001011001111110101100011100010110100000010111000100110100001111100110111111101001001001101011010100011010000011001100000011100110001111010011110001100000001010011101011110000111111011000
|
|
Parameter \INIT_F = 256'1001001001001010011001011010100111001111010010101101100011011101101000101000000101001001100111101000011010101011110010111001010011101000110111001111001111100000110110111110110101001110001100010011010101111100110001011010111001000101101010010000110001110110
|
|
Generating RTLIL representation for module `$paramod$f8c821864499ec5a32f2425089cf17912c41d135\$__ICE40_RAM4K'.
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|
|
2.9.39. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.2.0.0 using $paramod$f8c821864499ec5a32f2425089cf17912c41d135\$__ICE40_RAM4K.
|
|
|
|
2.9.40. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K'.
|
|
Parameter \READ_MODE = 3
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \NEGCLK_R = 1'0
|
|
Parameter \NEGCLK_W = 1'0
|
|
Parameter \INIT_0 = 256'1101101110100101100010000001011100100010110101101011000110110000111011010101100110010010100110011000111011100001100111000110011100001010010100110101010001000100100001001110010111010111001011101001110001111011100111010110010010010000110001000010111010100010
|
|
Parameter \INIT_1 = 256'0110101010011011111010001100110110101000010000001110011100100000001011001001001000100111100110110011001110010100011111011100101111011101111110111001011011101011111101010001100110100100110010011111011011011100010010111010011110010110100000001000000111101100
|
|
Parameter \INIT_2 = 256'1100000101000011101000101101101011110110011101011010011011101001010101111001010011000100011010010111110001000001110110100011010010010001101101010100000011110011000011101100000101111000001111100000010010110110100111110011101110100000001011000110101110101000
|
|
Parameter \INIT_3 = 256'0111001110110111101110101110011010010101101111111001010010101111110110100011010100001111101100001101110010001011001011110101000001100001110110100100011001001110111101001110110001011000111101011101000000110110110010011111010110100001011011000101011010101100
|
|
Parameter \INIT_4 = 256'0010110001010111111001011111101000110110110110111110000011110101011100101111111101001101010100111011111011110011001110110010000000101110011010111000011010001101010101000011100010110100100011101010000001111000111011111011101000100110101010001001000101001101
|
|
Parameter \INIT_5 = 256'1000110110101010101001100100000000101111011011110111111011110010111111111001011000001110000000011110011111011000010110110101101000111011111001011111101100110010111100001001110011111100011111111101111100100100010011001010100110110110001000011110101101001101
|
|
Parameter \INIT_6 = 256'1111010111011001010111000011000000111100000001110010010111100001001010100011000110001110111110110011110001111010010001110010110110011100111111101111001011100100001000010111010110011101101110011101011010101111110100011110110001110010010000011010011010011100
|
|
Parameter \INIT_7 = 256'0011110110011110111001100010000100101000011101001110001100101001101011000110111110000011111011111100101000011001011110110111101101010111010011010001001101100111111011110101011100100001110000000010100000001110000111011100100011001010000111100101110011101101
|
|
Parameter \INIT_8 = 256'1000000000011110000111000110001001001001010111111111000110001000011011011101101111000011110000000101000110000101010001101101110001101010011011010110111010000101101000100001001110100011100110001110100000000111001100111110010110011110100101001101001001000110
|
|
Parameter \INIT_9 = 256'1101001010110010011100101100111111011001000101001101000100011100101001110111101110010011000101001011100011111000100010110111011100110111000111011110101100010110011111000101000011100001101101100000110101101110110101001101100001010111001100100000111000110101
|
|
Parameter \INIT_A = 256'1101110111110011010100101000010001110010110100001010101011100010001010111101101101100101101111000000110001111010001010110000100100001010000111111101100110100110101101100101001100010011000111100011110101010010001001001010111101101001111111100101111110011001
|
|
Parameter \INIT_B = 256'0010100001010000101011011001101001001110011110011000100111110111001101010000111011101110001100010001000001011000110000100000010111011011001001101010101110010100100110100001010110101010110110001010100001100100010011110110100111010000111101000011100111010100
|
|
Parameter \INIT_C = 256'1100001000011010110101111111010011001011011001101001110000010001110001101101011110101100000111100111101110111100000010010011100100011010011001110010110011011111111100001001001110010101110010001010110101011110110001000110111011111010101111011011110100010110
|
|
Parameter \INIT_D = 256'1010110000010111100000011110101110110110001111101100010110001110010010101100001100110101000001100011101011111101100101111110100011100110101010000000101010011110111001101000011011111000000111000111100101110101101111000010000000000010111011110110101000100010
|
|
Parameter \INIT_E = 256'1101010110100100100001001010100001010011001101110101101110100101011111111011010011110101000110011000011000100110000110101011001010100001000010011011111011000100011010100101110110110111010101000101000111010110000001110111111011001010100011111000101001110101
|
|
Parameter \INIT_F = 256'1011100011110000001100110111111100011001011101110000111111101010010111011111010110010011110100000101011111100000001011110001100010101010111100111000100111011100001011011010111101010110100010000111110100101110010111100111110100011010100000011011111000100111
|
|
Generating RTLIL representation for module `$paramod$d20d03106414b31f6d01ddd06e4caced3bed4d08\$__ICE40_RAM4K'.
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|
|
|
2.9.41. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.3.0.0 using $paramod$d20d03106414b31f6d01ddd06e4caced3bed4d08\$__ICE40_RAM4K.
|
|
|
|
2.9.42. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K'.
|
|
Parameter \READ_MODE = 3
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \NEGCLK_R = 1'0
|
|
Parameter \NEGCLK_W = 1'0
|
|
Parameter \INIT_0 = 256'0001101001111100110001111001001001110001001001100011101110000000001011100000100110111111000110010110001001010010010001110011010001000001000101001101000100011111000100011111001111111100001100010110001011011001010110000101100001000011111000000110001001001101
|
|
Parameter \INIT_1 = 256'1111011001110011111111110100111110110000110011000111101010011001110010100011111100110110101011101010001001111110000110111011001110100111110101110001110100110100011101010110101001101110000110000000011101101111110010001101101010000100110010000010101111010100
|
|
Parameter \INIT_2 = 256'1011011001000011000001100000010000101101111110101101111110100000011000001000101110010000111100100111100010001101000110011001011100010111100110010100100101001011110010110011100101010111100101110111110010000011110110100001111011010100000100110110011111101100
|
|
Parameter \INIT_3 = 256'1011000000001011100101011110110111111010100111100101110111010001011101011000100010100000111001000000011001010101011111010010100011111000100100001010011011001100101101111000001001000010101101101101111011110010011100011000001111010101000100101100101001100000
|
|
Parameter \INIT_4 = 256'0111001000101001001001100110011001101010110010101111111000110100111000101000101011000011011101100111011110101001101100111101101111100111010101100010011110110100110111001110111000100110110011010101110101001110011000000100010011100001000001011110010111101100
|
|
Parameter \INIT_5 = 256'0100011100110001010111001100010110110000100101000011001101010000011110110001010100110100100101110011001011001101111101110101001100010100110110111101010011100000010001101000011101011011010111111010101110001110101101011101001000010001001001100100101001100001
|
|
Parameter \INIT_6 = 256'1000100111111001110010100001001010111101101100000010100000011010000010111100011011101110101100101000000111111001000110111110000001011011100011110010011101101110100001011011101111101101011100111110100101111010001000100001010111110000111111100111101001101010
|
|
Parameter \INIT_7 = 256'1100110100000000011001010001100101001010001011100111000111111001101101000111110001000101111010101011010101110101000110001110011100111111010110001011011111011010110110110000010111111110001111001011011100001001111101011010011101111110100101000111000100000010
|
|
Parameter \INIT_8 = 256'1010101001111101001000010101100001111101001100111100100110111001011100000111011100111110111111001000000011011011010001101110110101001110011011111001100001010101100111001101001110101001011110110100010011111010111011100100000011101110000100001100010011111011
|
|
Parameter \INIT_9 = 256'0101010010110001001011111011101010000110010111010101010000001001100000000110010000100001110100001101000000100010001100101101101100110101100000010001100010001100101010000110111100000110100011001001100101101011011101001101000001100110101011011101000001001111
|
|
Parameter \INIT_A = 256'0111010110111100100001100110110010011110110111111111111010101100011010111000100010111000010110111100111111101110100011000100001101010000000011110001000111101011101111110010000010010101010001110010111111001011111011101100111001000110111111000100111111110101
|
|
Parameter \INIT_B = 256'0111100000000000110101101010110110001111011010100110110010100100010000110001010100100111011010100011100001000101111001100011010010011010101000101001101010011001101111001101000010000001101111001110000111011001011010100011010101110100010101011101101111011011
|
|
Parameter \INIT_C = 256'0100000100101111010000000000100100010001001111110101011111001101101111101101011101011111010000010111011000110101101000000000110001000010100110100111110110111010100100010001101110100110010010000111001110111110011111010010000100101001011011101111111101111110
|
|
Parameter \INIT_D = 256'0101110011010111101111110101111111100000001111111000001001001000000101110101010001100111110101010111011000001010000110101010111011101010100001110000001001111011000111011101101111000001110111011010101110100100000011101000100111011100000110000110010100010101
|
|
Parameter \INIT_E = 256'1010100010110011101000011111111111011010010001101101100110110000110001100101101000011010110011100101100010001001101001001111100110110011111111011000111110100000001101011000100010100111100111100010110011010001011111110100111110000100101111000101011011101110
|
|
Parameter \INIT_F = 256'1000111110111111011101111100111001101010111011100001000100111111100101001100001101111000000111100011011100100001011111000110111111000000000100110010001110110010001000001100011001111011010010111100111001000011101110000111110010101111010001000110010011101011
|
|
Generating RTLIL representation for module `$paramod$8b50928abdad807defadcd395783734b2b08c84a\$__ICE40_RAM4K'.
|
|
|
|
2.9.43. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.4.0.0 using $paramod$8b50928abdad807defadcd395783734b2b08c84a\$__ICE40_RAM4K.
|
|
|
|
2.9.44. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K'.
|
|
Parameter \READ_MODE = 3
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \NEGCLK_R = 1'0
|
|
Parameter \NEGCLK_W = 1'0
|
|
Parameter \INIT_0 = 256'0110110100001000010010011011111111011111110000000000100000110110110011100010100010000010011001101000100000110000010000100011110101111100011100101110011000101111111100000111111001011010100001000111110000100000110001100110111100000010101101010101101101010011
|
|
Parameter \INIT_1 = 256'0111110011001010110000010111011110010111111010111111111010101111110011000101001100011110010101111101110000110111011101100111001100010110011011001110110011100101101010110010010001101111110001011010101111011000010001001101010001001000110001101001111100100011
|
|
Parameter \INIT_2 = 256'1011100100111001100001011101001101000110000101100111010001000011100011010001011101011101110100001010110100110001100011101010001100001011010010111011001101110000110000110101101010110001111001011010110101110000110110110110111111000100001111100100011101001010
|
|
Parameter \INIT_3 = 256'0101010100001000010010110000101010100000010110000110001000011101110000101100011101010000101101110010011011100110100001110100011000011001100100111010001111000010110110011000010101100111111001111001111011100000101100100100110001111101000001010011111110010101
|
|
Parameter \INIT_4 = 256'0110111001001000111010100000101010000010111011100101101011110111001100101110110010111101110010011010011100101011111101010011101010111101100011011100001111001011001110000100100010101111000101111101000101011100000010010001111011100011010110101000001111001101
|
|
Parameter \INIT_5 = 256'0111111000110111110100000111100000101110010100111110111110000011000011101000000110100100100111101010001101000001000101111010100000000111100101001011111001111000010000010010000110000010011101101001011100100010000111111110011111001101001110111101100110010101
|
|
Parameter \INIT_6 = 256'1001111010101111010111100100001101111111000010100011101110101100110001001001011110110001101000001000111100001001100100011001010101111101000111111001010001110011100011010010001110111001000011001001110010000111110100000011000001011110110111110001001011111111
|
|
Parameter \INIT_7 = 256'0011011100101010001101101100100101111100001110001001100010110111000000000100100110100010001100010000101001000110101100010001001011011110100100110110111100101011001101001001100010011011101011011011101101010001100000100000000110101110111101010101010101011110
|
|
Parameter \INIT_8 = 256'1010011100011000100110000010000011001001101111110100010011010111000011001101010111100111010100111100010100011100011001111111010001010011001111101111100100101111001111000110000010010000100001101101101110011110110101111011110010011010101011110101000010010010
|
|
Parameter \INIT_9 = 256'1111100101110101111001011011100001001011101101100010011011101010001100000111100110100110000100101111110001110010111101110111101101100111101011000100101011100001111010000000111011100101010101100001011111100010001010111010100100100000100001111111001000001101
|
|
Parameter \INIT_A = 256'0110111110110111001010110100011100100000011011111011000000100010011110111000000001111011000000010111100100011011100101010101101010100001001111011001101010000010111100000101101110110011001101001101000101010101011110011000000000011100001100100100000011010110
|
|
Parameter \INIT_B = 256'1101101101100010110100011000010110010000011000111110100011010101000110001111011100101100110010111011110110111001011010101001111000011010100110101010100011111101001100000100101010111110101100011010101000000000010001000100010111101111000000000010001001010011
|
|
Parameter \INIT_C = 256'0011000110110010010000010000111001011010101011000110010011010000111101000001000010101101011011010001010110100111111001111110110101001110111101111011011010101101000101110101100010100011110000101100000001010000111101110001000001111011110000000110011000001011
|
|
Parameter \INIT_D = 256'1100000011000011111100100101100110010001100100001100110101111101001010111110111111110010100011111111000001111001001100100001100001100011001110000011100001111110101111011111111010010011010110101010011000100001111110110101110110110000100001101011111011101111
|
|
Parameter \INIT_E = 256'1111000111010011001111110110100001011011111111011101010001011011000101111110001101010001110100000001110011110111011101000110111100010001100011010110110011100000100011101011010111111011001111001010000110000110110100000111100110011111001000111100001100010100
|
|
Parameter \INIT_F = 256'1110000101011101000000001101011011010101000001001101010001100110111010100110110000111111000001101111001111001011101100100100000100111100000100011011110110111110100010011000010100010011011000010000100010011101111100001100110100001000111110111010101100011111
|
|
Generating RTLIL representation for module `$paramod$24d504412f6d7aa1e0f7de987e7f387f85a4094d\$__ICE40_RAM4K'.
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|
|
|
2.9.45. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.5.0.0 using $paramod$24d504412f6d7aa1e0f7de987e7f387f85a4094d\$__ICE40_RAM4K.
|
|
|
|
2.9.46. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K'.
|
|
Parameter \READ_MODE = 3
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \NEGCLK_R = 1'0
|
|
Parameter \NEGCLK_W = 1'0
|
|
Parameter \INIT_0 = 256'1001000000100110111111000100011100100111111111011010000110111101111101011000000101100001001000110001001000001100110000100001001101110110011100100111111000010101111001011100100010110100011100010000100010111110110001100111010100001110100000000111110000100010
|
|
Parameter \INIT_1 = 256'1101000000001101001101001111100111111100011000111101101100100010111010101000000011111001001110110111001001011100010001111100000001100001111011010101010111000100001111010010101001111001101111110110001110010001010100100101010001111011101010010111011101011001
|
|
Parameter \INIT_2 = 256'0001011100110000010111110100110110111110101010010000100110110101100010111001111101111100101111101101101101001111011010111100110100110010010111010011010100110001011010110001000001111100111100101001001111111100000000100101110111001100000100010101000110100111
|
|
Parameter \INIT_3 = 256'0100111000111101000111111010001000111110000001010101111110000011101100100110001101100110100000110100110110001001100111001101111110110110001001110101000100010100001000011100001011001101010100011101110101001101010110100000110000101101110110001000100010100111
|
|
Parameter \INIT_4 = 256'1101001100000101010001110100011000100001000000010100111111111010101011000100101001011001110010101111011001000011111101010001111110101001011001010010001010110001011001010001100010101100011111101111010111010000000101100011110101000010000111001110001101000010
|
|
Parameter \INIT_5 = 256'0001101101100001011101011011111011011101000011111001100010111000110000110001110000101010001011111100101101100101001001011100010011101001111111110010111001010111100100111110111001111101011000011010010111001110000010111001011000101011000010001010000111111111
|
|
Parameter \INIT_6 = 256'1001010100011011001010111000010100101010100010101111010111110110111110010100001000101001111010110100001000111101010001010010111101010011001111110100100011001101101010000011100010001000001011010111110001110111101110001101010101110100101101000001010000111101
|
|
Parameter \INIT_7 = 256'1010111001110101011110111111001000111100101110001101011100111101010001101001111011100000111101000011000011100000010011101100010010010110010001010011001010111000101111000010101001111000011011111101100011010011111000100101101111101001001010000010100001010011
|
|
Parameter \INIT_8 = 256'0111101100000100111111001111000101111111100110101001101100111011101111010101101101111110010101011100000010100110101100011110001010010010110000000111001111000000001000110100000001101011110111001001101010110010011110000011111011000001001110001001100001001100
|
|
Parameter \INIT_9 = 256'0110111110000100101000111101011100111101110001110011000100010000010110111100000010101001001100000000000001010110101011111100001110000110111010001111100010010100000000000111010000110111101100110100010110101111100111101110001110111100101001010110100010001000
|
|
Parameter \INIT_A = 256'0000011011110000011100101101101101111011000000101100001000100001011011011001100101001110110001010011001100010001110001101111111001110001100100001111000010101110000110001111111001011010101001101001101110001100110111110000010110111010011110111101101000000100
|
|
Parameter \INIT_B = 256'1110001001001000000111110101001101010100101000000100101001101011110000100100000000100100000111111010010001101110001001111000000011011011000010011000000000010011100001110000011001011000001010100100100110000011011011100111010001100010001000101000111110000010
|
|
Parameter \INIT_C = 256'1110101000000101010000010011110000000110101110111000010011100100100011111111000100011100111000110110100100011101111001010101111111111100111100110000101110000101100101110000001111111100101111111011100011101011000111011110010101010000101001111100110001001011
|
|
Parameter \INIT_D = 256'0110011111110110101000010110001111011001010010100100100010101101110110100011101010100110111110101110111011010000111011011101001000101001001001011011000001010110001101011100101011111000100101110110010111101110111100011010110100010000110100011010111010111000
|
|
Parameter \INIT_E = 256'0000110110010111111101010101100100010001101010100110010101101111111101100000110011010110110100111101010111111010000011011011011100101001000111000111111000100101101101000110110111101100101010011011111000110001100001001000000110101010010000001001011100010001
|
|
Parameter \INIT_F = 256'1100101011001001111010101100010011011010010000101101111010101111101111110110101101001001111111110100011110110111001100101011010010100110110011011011000011001010111111010111110100001010111110011011111100100110011011111101111111010011101000011001101110010001
|
|
Generating RTLIL representation for module `$paramod$3ac7d8d7a788c2eee8ce9642651229ad12a4c75d\$__ICE40_RAM4K'.
|
|
|
|
2.9.47. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.6.0.0 using $paramod$3ac7d8d7a788c2eee8ce9642651229ad12a4c75d\$__ICE40_RAM4K.
|
|
|
|
2.9.48. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K'.
|
|
Parameter \READ_MODE = 3
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \NEGCLK_R = 1'0
|
|
Parameter \NEGCLK_W = 1'0
|
|
Parameter \INIT_0 = 256'1101101100001100001010101100101100101101111110101010011011100010110110000101100100011100010011001100010101000101000011011000000100000101001101000010001100000001010100110110111100000110010111111000101000000110110010100111011000011001100111001000010010100011
|
|
Parameter \INIT_1 = 256'1001000100111110000110010011101011001110010001111010110001001001000010000101100110101011111010011010001001011110100011000000111110001110010111000000000011000110011001100100101101011000010100011101011001010000010001010110001000110101101000010000101101110001
|
|
Parameter \INIT_2 = 256'1111000011110010101010110011010100010000111110011111100101100010001101111011011000101110101110100100000011011000101010111001010110111100000110110110101111100010111111100101110101101110010010011001001011100010010000011101001111011010011001010111100101000110
|
|
Parameter \INIT_3 = 256'1011111011001100000011100000001100111010101000110110111010111001101100001011010100010101110010101100100110100010000000101010100111111001000000001111001100000001100001000110110100110010100000000100110000010010101000000011111001100110111111010010010101111000
|
|
Parameter \INIT_4 = 256'1010011100110000010110101101101000000100011110001111000010100000111110010010101111100011000011110010001100000100001110000011000101100111111001001000001011010001100011011000101101111100100000001100110101000111100011001001001011111100000111011001100011101001
|
|
Parameter \INIT_5 = 256'1110101110101111100111010111110111011001001001011001000100011001101010011100100110001001000101011101101110001000111001101111001110000010100111101000101111100100100110110000011100101001011110000010110100010110010010100111011100010010001011000110111011100111
|
|
Parameter \INIT_6 = 256'1110011010100011000110100000011101000001010010011011000011111001110011000100101111100011000010010010010011001000001011110100011101001110010010000011110001100010110111100010011011010000001001011110000000101100101000111111011000001110011001000001001110101101
|
|
Parameter \INIT_7 = 256'1010101100011001110110010100101011011100110100000110010111111001101101110010100101100000101110110011101111111010111000011011000011001111001010110011101110110010101011001101000010111110110010111110101101111011110000101010001101001000111011100001110111001011
|
|
Parameter \INIT_8 = 256'0101000100100011010100011111100010010111000000100001001110100000110001101000011001110110011011101011110101000110001111000110110010011011011010011011100101000011111100110110100000100100111100101001000001100001000110110011111101100111111111000111110100111100
|
|
Parameter \INIT_9 = 256'0000011001110111100010011000100110110010101100101110010001010000101011111010000000111011000000010110011101010101111011011110110000010100001110001101010000111111001100001100010011000010100101101110111111110110101011100000010011100011101110000101011111010110
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|
Parameter \INIT_A = 256'1111101001111101010111111001110011011001000110000000100001110001111101011100010110110000011101001101100010000101110000011011000011000110100101101101100110000000001100001111100010001110101111000110010101110101111000010001100110100101100110000111111011111010
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|
Parameter \INIT_B = 256'0110111100101010011000011111101110011010010000011110101100101011101100100100011111111001011101101001110011101100111011100110000110000010110011001011111110011100001011100101111110100101010000010111111101011010111001011011011011000111101001110000011001111010
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|
Parameter \INIT_C = 256'1101001101110100000100011011011110100011001101111011000110010010110010010010011101100101000000010110101001111010111011100000100011100001011100010111011010010110001110101010001000010100001110100110111001101100000101110110010110110100011110100110011000111101
|
|
Parameter \INIT_D = 256'1001010000101110000101110101001000111000010011001101011000101100110111000011101001001101001001111100011101000001001000111001011000010001010010100010100110001000000000011000000110010011110101010110101001101001001011101010111110110000010100010100111010101010
|
|
Parameter \INIT_E = 256'0111011111100101111001101010000111111010010001100000011010001101101100100110000111111100010011110101011010000101110101000011110111010011111011110111001100010001000110100111101110001011100110110101111010001010000101000100000101100100111010001100000001100011
|
|
Parameter \INIT_F = 256'1101011010110101001011110111100110110010101101001011010001010011100001101000101100001100010010011000111010111101100110001010011100010111100010111001011000000010001101011100101110011010101111001101101010011110000001001010010011001100111000010101101011101101
|
|
Generating RTLIL representation for module `$paramod$be7ac40a51c787e38583a6712985561e11fbc125\$__ICE40_RAM4K'.
|
|
|
|
2.9.49. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.15.0.0 using $paramod$be7ac40a51c787e38583a6712985561e11fbc125\$__ICE40_RAM4K.
|
|
|
|
2.9.50. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K'.
|
|
Parameter \READ_MODE = 3
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \NEGCLK_R = 1'0
|
|
Parameter \NEGCLK_W = 1'0
|
|
Parameter \INIT_0 = 256'0000100000100101001111011000001101110111111000010101110001100000000010100100010111000010000110111000101110010101010111011011001000100001111011000111011010010100011101111100010011101110000101110101000010110001001100101101010101000001110100001010100010101001
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|
Parameter \INIT_1 = 256'0010101110000100001011111011101110010100100011011011110011111011100100100111011001100010001011100001110110101011110111100010101011100111110101100111100101110000011100010011101010000011011100011010100110110011001001100110010000011100011101111011001100000010
|
|
Parameter \INIT_2 = 256'0111100011111000010001111101000110010011001111001100011000100010001001100010110111001111010101010001100001000000111011011101111001000101100111100000100010000110110000000000000101101001001100000001011000101110001100001101000001000101000101101001101000011111
|
|
Parameter \INIT_3 = 256'0111010011001111101010000000100111100101011111111101100110110101111011100000111000001101001100010011000101101011101011010001001011101110001111100000000000010100001110101010101101100010000111001101110100001011011111011001001100101010011000011000110100101000
|
|
Parameter \INIT_4 = 256'1000101011110111000101110001110111100110010101101100111110010111100101111101110010110011001110110111110001111011000110111010001111011100101100111000011111100001011100011001011010101110101010110000101110111111111111100001110000011100101011100001010011110101
|
|
Parameter \INIT_5 = 256'1100011110011110011000000001010010000010111000111011000101010011100110011101101111001110111110100101001011010010101000110111000010001110111001111101100110110110011000110100101111011100100100011101111010000000010010101011111101110110010110000011110001011100
|
|
Parameter \INIT_6 = 256'0101001101111101101100001100110011001000011110101001101011100000000100011111110101100010101010110010111100100001100001110011111010110101000011011001001110001011011001010101011000011000001001111101100001001011100101010001110111010100111101110010110110001000
|
|
Parameter \INIT_7 = 256'1111010111001010011101100101001110011011101110111100111110011101110110011110011110111011010111010000100010011011001100100010011110101100110001111100000101100110111110110011011001110101001001110000010001100111001001111000011101100101000100101000011110001110
|
|
Parameter \INIT_8 = 256'1100010011011000000000100100000010000011100101011110011110110001100110100110001011001011000101100001011010000000110000101000101010111110100111001100001011001111100101101100000110110100111101001001110010110101110100110100110000010011110101101100010011010100
|
|
Parameter \INIT_9 = 256'1011100110110111100000000000010110000100000110101111011011001100010111111000100010011001001101001000010001110010110010100011110111000111111111101110010100100110010101101001101101101001011101101111010001001111010010000011010111001000011010010100011101011100
|
|
Parameter \INIT_A = 256'0011110111111111010011100110111001111011001100010111100001110011001111011011100000100100100010011100001101001111111001111000000010011011010101100001100001111101111000101010000001010110100110101111101111011110111001110011111011101000011111001100010110011000
|
|
Parameter \INIT_B = 256'0111110011101110100110001111001000010100100000101101111110010101101010000101111111101001000011010101000111110100000101111011110100010110011101111110110000000110100100010000011000110000010010001111100000100000110000010100010010011010110111110010101100100110
|
|
Parameter \INIT_C = 256'0111000000110001000111101100101111011000011010110000110001110010010010100100111100000001110111011010111010000101001110000000010001000011000111000011101000111011110110111000000001100010011001100001110101111011110010101000001110000010000001110001001011101100
|
|
Parameter \INIT_D = 256'0100010100000010001001110110010111111001010001111111010011001000011010000010010110111110110010000110110111101000101011110100010000111011011101110010000101010110101001100010100001011110100000011010001111000000010101001001001010001011100001010110010000000011
|
|
Parameter \INIT_E = 256'1010100010010001111110111000101100011101000101110000101111001100010111101101000011101101100000010111001100000001011100100101111000110001100101010110110000010101000100011101000001110010111010001100000101101011111101011100001110101011110111011001101100111101
|
|
Parameter \INIT_F = 256'1000111011100111011100110001100000000001001010101010001001011011101100011010011111111011001100001000010001101101010000101110010001000011010001010010000010011010000111011111100100110000101001010011110100000000000100011010101001001011110001101011011100000101
|
|
Generating RTLIL representation for module `$paramod$43ee040a7a0e0cae38b99891f31467acf906d27f\$__ICE40_RAM4K'.
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|
|
|
2.9.51. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.14.0.0 using $paramod$43ee040a7a0e0cae38b99891f31467acf906d27f\$__ICE40_RAM4K.
|
|
|
|
2.9.52. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K'.
|
|
Parameter \READ_MODE = 3
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \NEGCLK_R = 1'0
|
|
Parameter \NEGCLK_W = 1'0
|
|
Parameter \INIT_0 = 256'1000001001010001001111011000110100111001010001101110011101110010100100101100001000000011110110101010101110110011111010110100011000001010111010101000101001100001001001110110100000001111001001011010101000101111111110001100110000010010110000110000110001100011
|
|
Parameter \INIT_1 = 256'1001011010101011001110000010000101100101101011001011000110110111101011100110000110101111011011110000111011010100100011110011101001110001101100101100010000011001010101000001100101000011010101011001101001101110010110011111110111111011100111110011111010010011
|
|
Parameter \INIT_2 = 256'0000000001001000001001100111000000011001000000011110010101111011100101111110000101100000010001000011100010011110010101101111010101111110000100111001111010100100010001000110001010010001100001101110100101100111011000101100101010010001001001001111011100001110
|
|
Parameter \INIT_3 = 256'0111000000110100111110111000011010011011001100101000100001110000011011011111110000001010000001000000110101001110011110100001011001010000000010011011011100110110111010000100101100010111001000001011010000000010110010000010101100101000000110111010111100110101
|
|
Parameter \INIT_4 = 256'0011010001010110110111000001010001001111001011001011001011001000101110001010010101111011101010111010100111011001110001111100001010110010010010011111000100011001110001010011101100101001111000110100010101100111010010101000001010000001111100001101101001110110
|
|
Parameter \INIT_5 = 256'0000010101000000100011010010011011101110111011001100011111001000000100001010110101111110110000100110101101100000011100101011110101100110010110001000001011100100011010010000001100101100101111100110111010010101011110000000110100011000001001000110001111101111
|
|
Parameter \INIT_6 = 256'0110000010010011001000000010110010001101010010000000011100000101001011000001011111001011110100111000100010111001110110011011000110011111000000010011000011010100001100111000000111110100100000000100100101011110001101110100101101111101100000000011110000001000
|
|
Parameter \INIT_7 = 256'1111110011000010111011011000001000111100101000110100100011100100000111101110100000100100000101011010110110010110111000010001111110000111000100000110000000001011101101010100000100001010001000101101110100001000010001010100000011111001111101000111100111111000
|
|
Parameter \INIT_8 = 256'0101111000101000110111110101101011111111101101100111101100110010111001000100101100010011011010110011010111110000111110000101100111101110010001010101100000010000110101111010010101000100100011110010001100011000001001011010010110111111101100010001100010001100
|
|
Parameter \INIT_9 = 256'1101111101111000110011001101001110100100111000111000111110110100100111101000010001111100101110001100100001110100100110001110001100100100010011011111101110010001010000101010010000110111110100101100111001111010101101011101111100000001100100101101001101010110
|
|
Parameter \INIT_A = 256'1100110111101010111101001111011001011001011101100011010011100111111111111100100000011010000000010010100101111100001000100011100011100000110101001010111101110100010111100100000001000001111001001000111100110110001101111001111000110001101110111101101101011010
|
|
Parameter \INIT_B = 256'0110101010101110010101011010100110111001001100011110111001101100000110010001100111011100100011010001111011001110010011010001010011000000010001110011011011000010101110011100010100110110110110010110111001000101001101100001110100011011101001110011010111001001
|
|
Parameter \INIT_C = 256'0010100101011100111010001111011011000001010011000001000110000111111001110001011110010000110010011010110000111100001100001100101011101111000110001000101100100110000111111101010000011010101111010010100111111001001010001101001011011001001010011000110100010110
|
|
Parameter \INIT_D = 256'1100000000000110000000000111001111011100101011100111011000100101001100011110001111000100011001001000111110010110110010100010111101010111000111101110010000100100101101000010000011011110110001010010101110010101001010100111001000101101001000101110011011111011
|
|
Parameter \INIT_E = 256'1000101011100101111010011010010111011011101100001001110100110010111110000011110110001010110111100011000100010010100010010000000011000011110000101010001101100101101010100011100101100001011000100101110110001111111011001000010000111001010100100100111101111101
|
|
Parameter \INIT_F = 256'0110001110100101110111011110111110000101111000111100101001110010111110100001110000101010100110101101101010011100010110000110011100110010010001001110011000110101010100101001010110100000110100110001010111001111000100101111100011010101000100011010101110111111
|
|
Generating RTLIL representation for module `$paramod$c88d7c4436960e4714f331f1468ed0db59974b0d\$__ICE40_RAM4K'.
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|
|
|
2.9.53. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.13.0.0 using $paramod$c88d7c4436960e4714f331f1468ed0db59974b0d\$__ICE40_RAM4K.
|
|
|
|
2.9.54. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K'.
|
|
Parameter \READ_MODE = 3
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \NEGCLK_R = 1'0
|
|
Parameter \NEGCLK_W = 1'0
|
|
Parameter \INIT_0 = 256'0000110110001000001110001101110000011100011011010100010101100101101000111111110110001001110010000110110111001010010011000000100010000001110001010100001001010110001011001110001101100110111011011110000010011001101110110111100110100111001001011000111100010100
|
|
Parameter \INIT_1 = 256'1111100100110011111011110011110001010100100010000000000000010100101110011101001111110000100010100101010010000111100010101010000111110110011111100100010010100011001111000100111010111111111011101111111101110010001110000010110110000001011101110110101000010110
|
|
Parameter \INIT_2 = 256'0011000011000011000000101010011100111001010111111011110010000101010100011101100011111111000001100011100101011000000011101110000010110010000011001000010111111001011111001010011000100011000101100000111001011000011101011011100101000000101000010110010011111010
|
|
Parameter \INIT_3 = 256'1010010110001111100011101101101110111010110001001000001000100000000101111110001010101100100111010001110011011111010100001110111100011011101111011100110100111100100010100011101100010111100011000101001111100111001101011010011101110111111011110001100001111100
|
|
Parameter \INIT_4 = 256'1100111011111111110100110001100100001101010100101001010000011010100101101101110101110111110101001100111101001111110100000101100101011000001101011110000010111101100011001000110011000110100110101100111001110011011110011011011010010001110110100000011101000000
|
|
Parameter \INIT_5 = 256'0110110010101010001000100000111111010000010001001001001001011001111110001101001011110111101110000111111111011110110010101001100011000101010100000100010000110100111110001010010000111011110011011000010100011100100111100110110100001010100000001011010011001000
|
|
Parameter \INIT_6 = 256'1111001010110011000110000010110101001101000100010111000100110001110111100001000111110010010110010000010011010001000110100010111010011111010010011001000111011000101011111011001100001110110011111000011001111011010100011000100010100001001000110110011010101001
|
|
Parameter \INIT_7 = 256'1101101111010001110000011011000000100110111111000101010011111001010001100000001100010100000110011101100100000111101001101100010111011011101101100000110010010101000010110101011011001010101100100001000010101110011110101101000010000111100010111110100011001101
|
|
Parameter \INIT_8 = 256'0111010110010101111111111101001000110111101011001010100100010010100111110001000000010101110011010010110100111110100101001101010001011110001000011100001000010101000110101100111010110011101100010011110000110101100100000111110011101110011110100000101010100101
|
|
Parameter \INIT_9 = 256'0000001000101101011010110000011110000101111011011010000001011111000111111100110111000101010100100001111001001101111000001011010110111100111011010110101101011111101111010101010110101100100011101001000111000000000010010000010001110011011011111100000111101110
|
|
Parameter \INIT_A = 256'0011010011010011111010010100000000010111011110110100000010001001000110101000111010101110111001111111001100100100100111010101101010001001011011001111000101111101001111111001011100010110000001101111101010011000000000010010000110010111001110001101100100110000
|
|
Parameter \INIT_B = 256'1110100011010111011001100001100010011011101001011011110001011101000000001010011001101010100000101010110011100001010010111101001110100000000110110111100001110100010101100011100011110101000111000110010000101110010110000010010110000000100101001100001101100001
|
|
Parameter \INIT_C = 256'1001110000011010011100010110100110111110110000100010000010010101111110011011010110101110110100110101011100001010010101101001011100101011001101001100000010001010100100000110010010010111011011101111000011000111111001100111110110100011010000110010000100111101
|
|
Parameter \INIT_D = 256'0101000010001001011110110011110001011011011111110101011011000001011100101111101010110001111001101010101011000101110001101101111111111110100110110110101100111001010100010001010011110111001111100101100011000011000011111101101101001110001000101001110011011100
|
|
Parameter \INIT_E = 256'0000110110011110011101000001000101101000110010100100101110000110000011110101010001100000101010000111100110100100101010110100010011011000010111011000101110111000111111011001010101111010111001010011001000000001111001011101111100011110011011010000000011110100
|
|
Parameter \INIT_F = 256'0100011100111000110101110001011011011001110100001011110011011001000010110001110101010100010010001100100101100000110101011010110111000010011001000011000101110001110101011011010100111001000000111011101010011110010111111011001011111111111000110001110111011010
|
|
Generating RTLIL representation for module `$paramod$00cfa1a09c31f8672099a8eedc17696b3908e1c3\$__ICE40_RAM4K'.
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|
|
|
2.9.55. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.12.0.0 using $paramod$00cfa1a09c31f8672099a8eedc17696b3908e1c3\$__ICE40_RAM4K.
|
|
|
|
2.9.56. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K'.
|
|
Parameter \READ_MODE = 3
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \NEGCLK_R = 1'0
|
|
Parameter \NEGCLK_W = 1'0
|
|
Parameter \INIT_0 = 256'1001000001100001111011110001001101110111011101001010110000011011000000110001000101000110000101100011101111000011010010001001110000110101010111000010011001011110010111110011100100110111110000010001101001111000011010000101001010000001100001001101100111000011
|
|
Parameter \INIT_1 = 256'1011111100000010101100110101110100111010001001011101011100111100000010000100100011010100011000000110010101110000000100101001111110101111000001000101100110000011111100100011010110000111110010100010000000011000011100001110001011001011011111101001100101111011
|
|
Parameter \INIT_2 = 256'1011110000011001000100110000001000010010101010001010011110101001001111011111000110111110010011111010101010101001101110011000111111011010110101011011001111010100000010101101111100101100100101110111011001000111111101101101010100000101110001101000011011111101
|
|
Parameter \INIT_3 = 256'0111000000101010001010100011110011110100100100101111001101001001000110001001100010101110001100011110110100000001000011011100001010111010111110101010001101110000100101110010001000000010000111100010010100101110110010111101011001000110101010110011111100101111
|
|
Parameter \INIT_4 = 256'1001100101111111011100111000101010111100011010110100010011000111110111000011100101010011010111010001100110001011001111111000101011011011101100110001010011100011011111111100100101110001001010010101000100111011100101000000111011001001010001000100101111101111
|
|
Parameter \INIT_5 = 256'0011110100011101110100010111001000110111111100110001110111110001010100110111111100111001111100100100111001110101110100111000111000100111011111100000111101011000100110010001100101101001111101000000110011010100010011101011001000110010100000001011100011111110
|
|
Parameter \INIT_6 = 256'0011110100101100101111111000111101111110010000001001100111000110111101111000000000011111100101111111100011000100111000010011010111001011100111010111011010110110001101111110100001101110110000000100000010000110011011111000011010110011101010101001011100011110
|
|
Parameter \INIT_7 = 256'0101001100001111101000001000100100101000100001011010110110111000101111100111110111111000111011111001101101100000010010101100100100101100000010110010110100001011101011100100001110001000011001111010000110110111001100001100010111100010101110001101110000110101
|
|
Parameter \INIT_8 = 256'0100110010111111001011000010111011110011001101100000110101110111001000000101100101110000100011100011011101001001101101111000110111110011100100111110011010100001001101000110011111000000100000010000000010101010011111101100000110011000010010001101001111101010
|
|
Parameter \INIT_9 = 256'1001001011000011010111110111110100001011001100100110000110111111010011110101010011110010000111010011100111100000010111111111111110100100110100101000011101010001011110111110011000010001111111010110110101100010100101100010001000111111111010110010100000111101
|
|
Parameter \INIT_A = 256'0000100000100110000100000111100001101000110011011011011011000100100011101011111010100100000010010111000111111010101101101110100011010110011001010011100011100111000000100011100001111100101010100010100111001111000111000010100111111100001010001100110001100000
|
|
Parameter \INIT_B = 256'1110010000010110111011110111100111011011110100000000101011110110001111101001110111001100110111000000101110000101111011011010110100011010101110111001011111001101011000011100110010111001011010000010000011000111011111010011100000101001101110111101101010010000
|
|
Parameter \INIT_C = 256'0111010101010010001101100111010011101111110010111111110010010011111011100101000101001111110110001010000000111111100011101111111001100000000001111110001000000100010110110001110001100110110110011101100110101101110010010000100110101100111101111111110010101010
|
|
Parameter \INIT_D = 256'1001010010010100111111100000111010010010010111101110001011001010001111100110000100000011001000110100111001110111100000100101111110001010111011011001100011101110011111111101011100101000111011000011100101100010100100101100110100010111010011010100100001001001
|
|
Parameter \INIT_E = 256'0100011010100000010110100000011100010011000001100000001110110011000000001101110010111100011001100100111100011111010000101011110001101110100101011010111100010110011111010010010110010010010111000001011101101110011111011110010101110100000011000010011010100011
|
|
Parameter \INIT_F = 256'1011111110010011111000101101000111010001011101010001011011110000011111111010000000100011001101101001110011100001011011011000001100000110000001010010000110011100111000000010010101111100100100100000010101000011101001011011000110111110101111101000111010110010
|
|
Generating RTLIL representation for module `$paramod$d02f8b69728aa273339f27f72a108917c00339c5\$__ICE40_RAM4K'.
|
|
|
|
2.9.57. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.11.0.0 using $paramod$d02f8b69728aa273339f27f72a108917c00339c5\$__ICE40_RAM4K.
|
|
|
|
2.9.58. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K'.
|
|
Parameter \READ_MODE = 3
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \NEGCLK_R = 1'0
|
|
Parameter \NEGCLK_W = 1'0
|
|
Parameter \INIT_0 = 256'1100010111000001000101101010000100100101001111011111010010000000000100001111111110000001100010001011001110010011011000001100110101111100110010110000101111001000111111000001001100100001110000010000011110111101111000110011001100001111100010011001100101111011
|
|
Parameter \INIT_1 = 256'0110100110111000100100011011010100010001110000000111111000101100011110010001111010101011010111010100101101110111110111000001011100000100000100111000111110100000000110000000010001100100000001110110010001100010111000101100101011000101011101010001001100110001
|
|
Parameter \INIT_2 = 256'1010011101100111000001111100110010110110110110011011000000001110011111000100100010111000101101111011110000101110010100001111001101111101110001010000100110110101000011111011011110111111111000010100010101101010100111011010000100111100100110001101111110000011
|
|
Parameter \INIT_3 = 256'0010011101111011111101111001101010001100100000100101011100000010110101000101011000000001110000110110010011011000101010110001100110111110001111111110011001100011111010110101110010100101010000010101011110111011010101111011101101001101111111100001011110001111
|
|
Parameter \INIT_4 = 256'0010010011011001001010011000011010010111100011111111101100000001101111110000101101000101101010110011100011001001000000111010110110010110001011011000001111100100010101010010111101101111010101001001010011001101000100110011111011110101001110001010101101100011
|
|
Parameter \INIT_5 = 256'1100100111001000001010111010110100011010110011010001100100010100011110000100111000110011111011000111111110111010100001110001111110011000010001000010101001010100000111010010101011101101101011101000111101101001110000000000111000011001001010110100000101000011
|
|
Parameter \INIT_6 = 256'0110101010100000010010111101110101110010001100010101010101000101000010011010010111111110001001110001000010011100000110011110010000001100101111101111100101111100111000110111110111000111101110010100000111000111100111100000010110001000001101101101010110101101
|
|
Parameter \INIT_7 = 256'1111100111100111100001011010100110010100110000111101110100001011001001010110011111010010001010001100110110000000110101100101010000101011100110101100110100011111000100011101010111000101111100000101010011010101110000110010111010001100100010100110101101101100
|
|
Parameter \INIT_8 = 256'1011100010110000101011010101001110010011111110110111111000100011111100010011111100111101111110100111111000101011111000000111111111111101101101101001011111110110101011001110111011111101111100111100110000101011011000100110011010000001110010001111100111010101
|
|
Parameter \INIT_9 = 256'1101010011010100110010010111001111110110110011101101010110111110111011011000100001110001110011010001000110000001100011110010101001000110111100111000101110111101000111011111100111110101011110010011001100100011001111110000100100111110101101001101001100101110
|
|
Parameter \INIT_A = 256'1100001111011101101001010011110011101000011000111000100011100000110011001100111110101111011100110110110111111110111100001110101001011111000001101001000101100101100101101001111111101001111100110100111101100001110001111111010010010011001110011100011000101010
|
|
Parameter \INIT_B = 256'1110111011000110111101101000011110011001010000001011011101010011000001111111000000011011110001111001001100011000010101101001010001111001001101010101110010101000010000110011010111100101001101100010011110010101100110101011010101100101111011011111010111101000
|
|
Parameter \INIT_C = 256'0111111010111110010010110111111011101110101110100000000010001010010001101111001010101010000001011001010100100001011001011110000110001111100001110110111011000101001101001100100010001100110111011001111001001010000100110100110000111001100110110001111000100010
|
|
Parameter \INIT_D = 256'0010001011010000110001111111110001101011110100100001001011100100001110101110000101101101111101000010101000001001001011101110000110110111111001100111100010010000110111000101010101001010011000101111101111001110110010011010100100111001001111101010111111010111
|
|
Parameter \INIT_E = 256'1000100100011011010000101011110111101000101101101110000000011011010111001110110100110000101000111111100111100110101010010100101100100010111111100001110111111101011101011110110100010010010010000000101101001110000110001100101000100011011101100000100111001100
|
|
Parameter \INIT_F = 256'1100001011001011010111011100000101111101010001001111111100111110011000111111000011001101001111100010101100010011111001010001000010100110010000101010111010110111001000100010111110010110011001010101101000001011001111010000001000001011101101000110111011011000
|
|
Generating RTLIL representation for module `$paramod$ad2999c67c0cc33071080a5b0a3003b439ff4ffe\$__ICE40_RAM4K'.
|
|
|
|
2.9.59. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.10.0.0 using $paramod$ad2999c67c0cc33071080a5b0a3003b439ff4ffe\$__ICE40_RAM4K.
|
|
|
|
2.9.60. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K'.
|
|
Parameter \READ_MODE = 3
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \NEGCLK_R = 1'0
|
|
Parameter \NEGCLK_W = 1'0
|
|
Parameter \INIT_0 = 256'0010010111000001000111000111001000000110100110101011101100010000010010111111101011000001000100001100111111111110110100011111100101001110011011101110011100110000101100101001110100001010101011111010001111011001011111000101000100011001111000110001011111100111
|
|
Parameter \INIT_1 = 256'0011010110000010010101010001000100011000110001010111001110011010011111101110000111100111000001011101011010001110100111111101001101100111110110011110011101011011010011011101000110001011011000011000101011000100111111000011110100111001110101111000101110101101
|
|
Parameter \INIT_2 = 256'1000111100011110000101001010101010010100111101010000001111110001100100100011100111101100100100001000010010001011111010000010111111000100010100111011101001010110011111111111000100100101001001011001100100110000001001110010101111011100010011010100110100100010
|
|
Parameter \INIT_3 = 256'0111000000110111101010111100010111010110101101100010000011011000010101101100110001100100110110111011000010110101000000100100010111111100001010111000101010010110100101101101110000010011101000000110111100100110111000110101111000110010101100110110111110001000
|
|
Parameter \INIT_4 = 256'0001000100001001100011100001110110111111101101000010010001001011111110011111001101011111010110111111011111010000011001100100010010000000001001111110010011101000011001101010111111100000110111110000000111100101011010111101100100000010101011111110110011100111
|
|
Parameter \INIT_5 = 256'1110111001010101001010010101110100001001100110000110110101001101001111000110011010100011100011000100110110001001100111100000101101110101000100010001101100011010100101011101011011111111100110010111011000100111111111010001000111011111101100101000001001100011
|
|
Parameter \INIT_6 = 256'0101000001000001001001000010111101010101011100110101010001000111000011110000011110111000100011000010111100111100010101010101010101000001011000011110011101110101001111101100000101110100010100001110101101010000100110101010010011011111001110000100100110010001
|
|
Parameter \INIT_7 = 256'0101001001010001110101101101101010001101110100010111111101010110010001010100011000101010100100111100100111111110111000010000110100110101001101101011110110110101001101011001100111001100111111011010110110010111100001000001111001001000001110000011111110101111
|
|
Parameter \INIT_8 = 256'0001110110110100110010001010110111100100010000000100100001010110001000111100010010011110100010111100100111001000111111010001001101101011011001000100010010000111011101000110100000101000111101111010111010000011100111101100011100001111101101010110100001110110
|
|
Parameter \INIT_9 = 256'1010011100001110000001011111000011100111011111011011001110000100110100010100000010000111001101100100010110010001011000111100011101101100111110100011001001110101101100011110010010000001110101111100110100000100011011100011111101000110001001001000001110010001
|
|
Parameter \INIT_A = 256'1001001100101111101101000101010100001001100001110011011010010110010110000000111010111110111110000111001001111010000100010100001001100101100011001100000001110110101001101110100110101100110000100100011110011100010100110100110101000100000000001111111110011100
|
|
Parameter \INIT_B = 256'1000011010111000000001010110110001110010000100010111000010110111100111101001111001000000111010011000000010101010100110100001011100110110001011011000010000100100110001111000100110000011001111110101100111010010100000111101011000000100100000110011101101010011
|
|
Parameter \INIT_C = 256'0111101101000000101100100001000011000001001000111111101011110100110100100010001100000011111001010110110001001000011001100001111001101100110100100100110001010001010000011001101000001001110110110101110000000010011110111100111101001101010001111011101011010001
|
|
Parameter \INIT_D = 256'1000111110100110011011101001010011001011100001111001000101001001000010101100101101010110110000001100111100010000001010000011110010111010011011101101011100111100111101011000000001001100100010011011011111111100001001010001010111110101100101110101000100000010
|
|
Parameter \INIT_E = 256'0000101111010100100010011000111010111000101010110111111101000100111111011111010100100010001100110111001100100110001010100001111100101101100001110010000001110100101100111000110111100010100101110010110010110100101101010001100000011111101000010101010001111011
|
|
Parameter \INIT_F = 256'1111011110010011010011011101100111001011011111011010111101011111000011110100010001111100000000110111100101101111110011010111000001011101100111100100110100110011111101111110010100011000011000100011101011100100010010100101000000001001000010010011000001111110
|
|
Generating RTLIL representation for module `$paramod$7e6f70126579c46893ed82c0a9723a8ee513c98e\$__ICE40_RAM4K'.
|
|
|
|
2.9.61. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.9.0.0 using $paramod$7e6f70126579c46893ed82c0a9723a8ee513c98e\$__ICE40_RAM4K.
|
|
|
|
2.9.62. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K'.
|
|
Parameter \READ_MODE = 3
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \NEGCLK_R = 1'0
|
|
Parameter \NEGCLK_W = 1'0
|
|
Parameter \INIT_0 = 256'1101010010100000010110000111011111110101101101000010010101101001111010000000110100001101100001011101001000010111110111111011000011111011000111011001010100000111011000011101110011101001001011010000010001001010000010111001101111101101000110011111101010000100
|
|
Parameter \INIT_1 = 256'1001010100011111101011001010100010111100101101101100010101000110101111001000010101011100010100101011010001100000010001010101100001010111010111101011011001110000010001001011011101101101101110011000010010100100000001111001010000000011010111010100001100110001
|
|
Parameter \INIT_2 = 256'0000010111011101111000010000010000010111100010110110110001001000111110001011111110111000101010001010001011100010001010010110000010000101110000100111110011100011110011001000010101010101000000010101110001110100000100101000001001101100000011110100000010011110
|
|
Parameter \INIT_3 = 256'0101000110111010111110100001110110101000010100001101010010110001100011111111010111110100001111010001000110011111010011100010110010011111110000000000111001100001101010001111100000010100010100000111101010010010100110000001001010100100110100101010111100001011
|
|
Parameter \INIT_4 = 256'1001100110010110010000110010001001000000110100001101110010101001001111101101010011000101011110000100000010100001100011010001111100100001100000111110001011100111001100000010110100011001001101100101000101010001100101101001011100011010101100011010100101000000
|
|
Parameter \INIT_5 = 256'1110001110101101110000000100110000110110101100111001000000110110111011110101100010000100111000011101110011101110001000111110111010110001011111101010100000011001111011000010000111001011011111011000011100111010110101010110100011110010001100001110111101000000
|
|
Parameter \INIT_6 = 256'0011110101111100101101001010001010001010101101001100111111001110010011111111110010011101110000101111011101110110110100111000011100100101111100111101101011110011101011000111011111001010001001000000110001101010000101011110110101011001100001110111110110100010
|
|
Parameter \INIT_7 = 256'0110110001000101100111011101110110001001001101111000101100111001010011011011011011100000001101011001000110000010110111001100110111011111010000001010110110011001111010001001101110101101000000001011101000011010101000110011110011010011011100100011101110000010
|
|
Parameter \INIT_8 = 256'1100011101111111100011101101011001000011100001000110010011010000100011011011001011001011110000001101001001000011110011001110000101110110001011110101000101100001100110111100000111100111001100000000000100101011110001001000100011011000011001010011100001010111
|
|
Parameter \INIT_9 = 256'0011110011000011011110010001000101101101111110010001000111011001001100101101110011000101000111000000101001101000101110111010111000101000100010111111011101010111011011111101111101010000001111100000011010000001000110110001101011001011101100110001100000001001
|
|
Parameter \INIT_A = 256'0110111110010100000110110111010111010100101101100101010010101101100000100111000001011010010100001011101001111001100101101101100111111010011011010001101000011101101011011110100000000100101110110010101110010100001110010000000010111101100100111001000111100001
|
|
Parameter \INIT_B = 256'0111001001101100110100001001010000100100011100111110110011011001011010110111101000001010010001010110011101011100011001110111011110101111000010110001110100001100100000100010100010010111100111101000110110001000111101001101101100100111001001010000000100111110
|
|
Parameter \INIT_C = 256'0101011010100010000010111100010001110000001101111010001110000000111000101100001001110010001111111001011000101000111100100011001100000000111001010010101100110101110101000100011011000000001010100100100111011000100100101111000001011011111111100100110001001111
|
|
Parameter \INIT_D = 256'0110111101111110100101001011110111010011100110011010000010001000111010101000101001001111000010101100000001111111111111011001010100011010010100000001010000000000011000000101101101100010110100110011110011001111110000001101101011110110000001000011000010101101
|
|
Parameter \INIT_E = 256'0101001001101010100001010100001110110100011101011000001101111000011110011111111111011110110111111010111101011101010110000011110000000010111111010000100011011101101000010101111011101000010000110010000011000100011110000110010010100111101000011011000100011001
|
|
Parameter \INIT_F = 256'0000011000011000011000101101000011000001100111110001001101100001100001111011010111000100110011010011001000000101100110000000000000011010111001001101010011110010110001011110000100010000101000000110010011111011001011100001000001110110011110111000111011010010
|
|
Generating RTLIL representation for module `$paramod$78737ad525e8dae59dec7a1c607a6bc5306a8b74\$__ICE40_RAM4K'.
|
|
|
|
2.9.63. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.8.0.0 using $paramod$78737ad525e8dae59dec7a1c607a6bc5306a8b74\$__ICE40_RAM4K.
|
|
|
|
2.9.64. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K'.
|
|
Parameter \READ_MODE = 3
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \NEGCLK_R = 1'0
|
|
Parameter \NEGCLK_W = 1'0
|
|
Parameter \INIT_0 = 256'0111101100001100000100010111101000110010000111111000110000110100110001100001011111110001100001111101111111111000011011001000001111011111110101100110110100011000110001101111110011101000111110111110101000011001001100000000100001000100000001001110001110001101
|
|
Parameter \INIT_1 = 256'0010100010000000000011100100110011000001101010010100011101110010100011100010101001100110110001111101000111110001001001100011100101001001001110110001011011011011100101110110011110001100011000011100011110001000001000001010100100011110011100000010011011011101
|
|
Parameter \INIT_2 = 256'1101001001110101100111010000101001111110001011011110000101001001111111011101101100011001001000100110010010010100101000110100101111001100110101110110000110011011101011100000000011010011111110000101110101010110001101011001000111001000111001110101110110100100
|
|
Parameter \INIT_3 = 256'0100100000011101100111010001110111001000010111101100000100011100010010010010010111110111000101111100000101000101010111010000100001110000011111011011000001000011010101000101101101101100101001000000001001010111100000100010000101001101100101010110100000100111
|
|
Parameter \INIT_4 = 256'1010101001000011001010101011011101000010000000001110110110110100010010111101100000011000011001101101010010101010001001101001010010101101110100000000111110001011010011001010000101001101101000110000100100010111000100001000100111110010101101001110100001111111
|
|
Parameter \INIT_5 = 256'0000111001100101101000111110011000100111011010101100000000010111111001001111110100000100110011000011111111111111000100100111110111100100100110011101111101101011011100110011001000000110111010000100001101010100010100111001000101010101000110100000000010110011
|
|
Parameter \INIT_6 = 256'0000110010110000101110011111111100110000011101101100100011110010011111111000000100110000110000010000001011101111111011100101111011001111011101110110101111011001101101000110000001110111011101101001010110101001001111001111010110111111111101110000111101010001
|
|
Parameter \INIT_7 = 256'1011000101111111001100110011110110101000000100111100111000000001100100000010011000001110100010010111010100101011110110111101011101010010011100011100000001101101011011000010101101001100000111101101101010101001011001010010000000110010100100111101000000010001
|
|
Parameter \INIT_8 = 256'0110100000110111100010010101000000000001100111001001110101000001100110001111011101010101101101000000111000011010000001000011001100001000110111110001010100110111010100001010010001100001010001110000101110100101001100010101000011011000011001101100000101010111
|
|
Parameter \INIT_9 = 256'1111000100000111101011100101001100011001010100010100110101100011000000001000100000010011110101101111000100110111000101001111111101111011010100010100001100011010001101000011010011101001101111011010001011000100110010100100111000011101001000010110011110011001
|
|
Parameter \INIT_A = 256'0000111011110001011000001110101100011011100011010011100110000101001000010011111010001010000111010101100111110111101001111100000111101001100101100011101111000110101000111010101101111111010011110010001110110000000111001000101110010110110000111111011010100111
|
|
Parameter \INIT_B = 256'0101011001101001111110011011101101000110011110001000001011000011000011111111011001110111100011011101000100101101100111010001100101001001101011001000010011111010011011000101111011001011011111100111010000001010010100101010110011000110001001110110001000001111
|
|
Parameter \INIT_C = 256'1001110110110100100000001111001111000010000000010011001001011010101101010110010001001111111110000101101000110011001000010101001011001110011000010101001010001010000000101100000100010001111100010101001011111100110001010000111110001011111011010111101011001101
|
|
Parameter \INIT_D = 256'0001011000110100001000001000011001000111010000110010100100100101010011111100100000100101101000111111000111111111010111000111110110111000001111010011001000100111011100101010011110110011010110011111011110010111000111000001110110011000000000110011101100001011
|
|
Parameter \INIT_E = 256'0101101001001001000000100100110000111110010001000111000000111011110101110011010010100010110110101101101000101110111001010100110101101111000000000111001101000110001001110100110011101101000000000100000100000001010100100001101011010001010000000111010000111010
|
|
Parameter \INIT_F = 256'0101001101011100101111001101111011001000011111001000110010101110110011110001010011101111000001101000010000001100010001011010110100010010100101110010111100000010110101010110011110110111100010011000101001101010100100100001100010000101101100111001101010111100
|
|
Generating RTLIL representation for module `$paramod$37a66f0e87cf155d17acab6ca4babfbf97b805ea\$__ICE40_RAM4K'.
|
|
|
|
2.9.65. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.7.0.0 using $paramod$37a66f0e87cf155d17acab6ca4babfbf97b805ea\$__ICE40_RAM4K.
|
|
No more expansions possible.
|
|
|
|
2.10. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.10.1. Executing OPT_EXPR pass (perform const folding).
|
|
Setting undriven signal in memtest to undef: $techmap237\mem.7.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap236\mem.8.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap235\mem.9.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap234\mem.10.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap233\mem.11.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap232\mem.12.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap231\mem.13.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap230\mem.14.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap229\mem.15.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap228\mem.6.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap227\mem.5.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap226\mem.4.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap225\mem.3.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap224\mem.2.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap223\mem.1.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap222\mem.0.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [15]
|
|
Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [8]
|
|
Setting undriven signal in memtest to undef: \pmod_1
|
|
Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [14:12]
|
|
Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [10]
|
|
Setting undriven signal in memtest to undef: \led_b
|
|
Setting undriven signal in memtest to undef: \led_g
|
|
Setting undriven signal in memtest to undef: \pmod_2
|
|
Setting undriven signal in memtest to undef: \pmod_4
|
|
Setting undriven signal in memtest to undef: $techmap221\mem.7.0.0.B1DATA_16 [2:0]
|
|
Setting undriven signal in memtest to undef: $techmap221\mem.7.0.0.B1DATA_16 [10:4]
|
|
Setting undriven signal in memtest to undef: $techmap221\mem.7.0.0.B1DATA_16 [15:12]
|
|
Setting undriven signal in memtest to undef: $techmap199\mem.4.0.0.B1DATA_16 [2:0]
|
|
Setting undriven signal in memtest to undef: $techmap199\mem.4.0.0.B1DATA_16 [10:4]
|
|
Setting undriven signal in memtest to undef: $techmap199\mem.4.0.0.B1DATA_16 [15:12]
|
|
Setting undriven signal in memtest to undef: $techmap219\mem.8.0.0.B1DATA_16 [2:0]
|
|
Setting undriven signal in memtest to undef: $techmap219\mem.8.0.0.B1DATA_16 [10:4]
|
|
Setting undriven signal in memtest to undef: $techmap219\mem.8.0.0.B1DATA_16 [15:12]
|
|
Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [1]
|
|
Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [4]
|
|
Setting undriven signal in memtest to undef: $techmap217\mem.9.0.0.B1DATA_16 [2:0]
|
|
Setting undriven signal in memtest to undef: $techmap217\mem.9.0.0.B1DATA_16 [10:4]
|
|
Setting undriven signal in memtest to undef: $techmap217\mem.9.0.0.B1DATA_16 [15:12]
|
|
Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [0]
|
|
Setting undriven signal in memtest to undef: $techmap215\mem.10.0.0.B1DATA_16 [2:0]
|
|
Setting undriven signal in memtest to undef: $techmap215\mem.10.0.0.B1DATA_16 [10:4]
|
|
Setting undriven signal in memtest to undef: $techmap215\mem.10.0.0.B1DATA_16 [15:12]
|
|
Setting undriven signal in memtest to undef: $techmap193\mem.1.0.0.B1DATA_16 [2:0]
|
|
Setting undriven signal in memtest to undef: $techmap193\mem.1.0.0.B1DATA_16 [7:4]
|
|
Setting undriven signal in memtest to undef: $techmap197\mem.3.0.0.B1DATA_16 [0]
|
|
Setting undriven signal in memtest to undef: $techmap213\mem.11.0.0.B1DATA_16 [2:0]
|
|
Setting undriven signal in memtest to undef: $techmap213\mem.11.0.0.B1DATA_16 [10:4]
|
|
Setting undriven signal in memtest to undef: $techmap213\mem.11.0.0.B1DATA_16 [15:12]
|
|
Setting undriven signal in memtest to undef: $techmap197\mem.3.0.0.B1DATA_16 [2:1]
|
|
Setting undriven signal in memtest to undef: $techmap197\mem.3.0.0.B1DATA_16 [10:4]
|
|
Setting undriven signal in memtest to undef: $techmap197\mem.3.0.0.B1DATA_16 [15:12]
|
|
Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [5]
|
|
Setting undriven signal in memtest to undef: $techmap211\mem.12.0.0.B1DATA_16 [2:0]
|
|
Setting undriven signal in memtest to undef: $techmap211\mem.12.0.0.B1DATA_16 [10:4]
|
|
Setting undriven signal in memtest to undef: $techmap211\mem.12.0.0.B1DATA_16 [15:12]
|
|
Setting undriven signal in memtest to undef: $techmap209\mem.13.0.0.B1DATA_16 [2:0]
|
|
Setting undriven signal in memtest to undef: $techmap209\mem.13.0.0.B1DATA_16 [10:4]
|
|
Setting undriven signal in memtest to undef: $techmap209\mem.13.0.0.B1DATA_16 [15:12]
|
|
Setting undriven signal in memtest to undef: $techmap193\mem.1.0.0.B1DATA_16 [10:8]
|
|
Setting undriven signal in memtest to undef: $techmap193\mem.1.0.0.B1DATA_16 [12]
|
|
Setting undriven signal in memtest to undef: $techmap207\mem.14.0.0.B1DATA_16 [2:0]
|
|
Setting undriven signal in memtest to undef: $techmap207\mem.14.0.0.B1DATA_16 [10:4]
|
|
Setting undriven signal in memtest to undef: $techmap207\mem.14.0.0.B1DATA_16 [15:12]
|
|
Setting undriven signal in memtest to undef: $techmap193\mem.1.0.0.B1DATA_16 [15:13]
|
|
Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [7]
|
|
Setting undriven signal in memtest to undef: $techmap195\mem.2.0.0.B1DATA_16 [2:0]
|
|
Setting undriven signal in memtest to undef: $techmap195\mem.2.0.0.B1DATA_16 [4]
|
|
Setting undriven signal in memtest to undef: $techmap205\mem.15.0.0.B1DATA_16 [2:0]
|
|
Setting undriven signal in memtest to undef: $techmap205\mem.15.0.0.B1DATA_16 [10:4]
|
|
Setting undriven signal in memtest to undef: $techmap205\mem.15.0.0.B1DATA_16 [15:12]
|
|
Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [9]
|
|
Setting undriven signal in memtest to undef: $techmap195\mem.2.0.0.B1DATA_16 [10:5]
|
|
Setting undriven signal in memtest to undef: $techmap195\mem.2.0.0.B1DATA_16 [15:12]
|
|
Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [6]
|
|
Setting undriven signal in memtest to undef: $techmap203\mem.6.0.0.B1DATA_16 [2:0]
|
|
Setting undriven signal in memtest to undef: $techmap203\mem.6.0.0.B1DATA_16 [10:4]
|
|
Setting undriven signal in memtest to undef: $techmap203\mem.6.0.0.B1DATA_16 [15:12]
|
|
Setting undriven signal in memtest to undef: \pmod_3
|
|
Setting undriven signal in memtest to undef: $techmap201\mem.5.0.0.B1DATA_16 [2:0]
|
|
Setting undriven signal in memtest to undef: $techmap201\mem.5.0.0.B1DATA_16 [10:4]
|
|
Setting undriven signal in memtest to undef: $techmap201\mem.5.0.0.B1DATA_16 [15:12]
|
|
Setting undriven signal in memtest to undef: $techmap191\mem.0.0.0.B1DATA_16 [2]
|
|
Replacing $reduce_or cell `$techmap$techmap195\mem.2.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$194' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap195\mem.2.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$194_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap193\mem.1.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$192' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap193\mem.1.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$192_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap191\mem.0.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$190' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap191\mem.0.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$190_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap199\mem.4.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$198' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap199\mem.4.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$198_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap197\mem.3.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$196' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap197\mem.3.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$196_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap201\mem.5.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$200' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap201\mem.5.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$200_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap203\mem.6.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$202' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap203\mem.6.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$202_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap205\mem.15.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$204' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap205\mem.15.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$204_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap207\mem.14.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$206' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap207\mem.14.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$206_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap209\mem.13.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$208' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap209\mem.13.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$208_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap211\mem.12.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$210' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap211\mem.12.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$210_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap213\mem.11.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$212' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap213\mem.11.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$212_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap215\mem.10.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$214' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap215\mem.10.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$214_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap217\mem.9.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$216' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap217\mem.9.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$216_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap219\mem.8.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$218' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap219\mem.8.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$218_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap221\mem.7.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$220' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap221\mem.7.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$220_Y = 1'0'.
|
|
|
|
2.10.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.10.3. Executing OPT_RMDFF pass (remove dff with constant values).
|
|
|
|
2.10.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
removed 384 unused temporary wires.
|
|
Removed 33 unused cells and 483 unused wires.
|
|
|
|
2.10.5. Finished fast OPT passes.
|
|
|
|
2.11. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).
|
|
|
|
2.12. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.12.1. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
2.12.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \memtest..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
2.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \memtest.
|
|
Performed a total of 0 changes.
|
|
|
|
2.12.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.12.6. Executing OPT_RMDFF pass (remove dff with constant values).
|
|
|
|
2.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
Removed 33 unused cells and 483 unused wires.
|
|
|
|
2.12.8. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
2.12.9. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.13. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.13.1. Executing Verilog-2005 frontend.
|
|
Parsing Verilog input from `D:\Software\Icestorm\bin\../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `\$__div_mod_u'.
|
|
Generating RTLIL representation for module `\$__div_mod'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_pmux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.13.2. Executing Verilog-2005 frontend.
|
|
Parsing Verilog input from `D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_ice40_alu'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.13.3. Executing AST frontend in derive mode using pre-parsed AST for module `\_80_ice40_alu'.
|
|
Parameter \A_SIGNED = 0
|
|
Parameter \B_SIGNED = 0
|
|
Parameter \A_WIDTH = 1
|
|
Parameter \B_WIDTH = 11
|
|
Parameter \Y_WIDTH = 11
|
|
Generating RTLIL representation for module `$paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=11\Y_WIDTH=11'.
|
|
|
|
2.13.4. Continuing TECHMAP pass.
|
|
Mapping memtest.$auto$alumacc.cc:474:replace_alu$167 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=11\Y_WIDTH=11.
|
|
Mapping memtest.$xor$memtest.v:33$100 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:34$101 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:35$102 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:36$103 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:37$104 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:38$105 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:39$106 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:40$107 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:41$108 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:42$109 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:43$110 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:44$111 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:45$112 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:46$113 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:47$114 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:48$115 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:49$116 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:50$117 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:51$118 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:52$119 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:53$120 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:54$121 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:55$122 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:56$123 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:57$124 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:58$125 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:59$126 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:60$127 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:61$128 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:62$129 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:63$130 ($xor) with simplemap.
|
|
Mapping memtest.$procdff$133 ($dff) with simplemap.
|
|
Mapping memtest.$procdff$134 ($dff) with simplemap.
|
|
Mapping memtest.$auto$alumacc.cc:474:replace_alu$167.A_conv ($pos) with simplemap.
|
|
Mapping memtest.$auto$alumacc.cc:474:replace_alu$167.B_conv ($pos) with simplemap.
|
|
Mapping memtest.$techmap$auto$alumacc.cc:474:replace_alu$167.$not$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:42$285 ($not) with simplemap.
|
|
Mapping memtest.$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:42$286 ($mux) with simplemap.
|
|
Mapping memtest.$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:68$287 ($xor) with simplemap.
|
|
No more expansions possible.
|
|
|
|
2.14. Executing ICE40_OPT pass (performing simple optimizations).
|
|
|
|
2.14.1. Running ICE40 specific optimizations.
|
|
|
|
2.14.2. Executing OPT_EXPR pass (perform const folding).
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$348' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:42$286_Y [6] = \memadr [6]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$351' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:42$286_Y [9] = \memadr [9]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$362' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:68$287_Y [9] = \memadr [9]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$347' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:42$286_Y [5] = \memadr [5]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$358' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:68$287_Y [5] = \memadr [5]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$349' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:42$286_Y [7] = \memadr [7]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$360' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:68$287_Y [7] = \memadr [7]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$350' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:42$286_Y [8] = \memadr [8]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$361' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:68$287_Y [8] = \memadr [8]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$352' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:42$286_Y [10] = \memadr [10]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$363' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:68$287_Y [10] = \memadr [10]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$359' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:68$287_Y [6] = \memadr [6]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$346' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:42$286_Y [4] = \memadr [4]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$357' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:68$287_Y [4] = \memadr [4]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$345' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:42$286_Y [3] = \memadr [3]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$356' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:68$287_Y [3] = \memadr [3]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$344' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:42$286_Y [2] = \memadr [2]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$355' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:68$287_Y [2] = \memadr [2]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$343' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:42$286_Y [1] = \memadr [1]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$354' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:68$287_Y [1] = \memadr [1]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$342' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:42$286_Y [0] = \memadr [0]'.
|
|
|
|
2.14.3. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.14.4. Executing OPT_RMDFF pass (remove dff with constant values).
|
|
|
|
2.14.5. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$331'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$336'.
|
|
removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$353'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$338'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$341'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$334'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$340'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$337'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$339'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$335'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$333'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$332'.
|
|
removing unused `\SB_CARRY' cell `$auto$alumacc.cc:474:replace_alu$167.slice[10].carry'.
|
|
removed 17 unused temporary wires.
|
|
Removed 46 unused cells and 500 unused wires.
|
|
|
|
2.14.6. Rerunning OPT passes. (Removed registers in this run.)
|
|
|
|
2.14.7. Running ICE40 specific optimizations.
|
|
Optimized away SB_CARRY cell memtest.$auto$alumacc.cc:474:replace_alu$167.slice[0].carry: CO=\memadr [0]
|
|
Mapping SB_LUT4 cell memtest.$auto$alumacc.cc:474:replace_alu$167.slice[1].adder back to logic.
|
|
|
|
2.14.8. Executing OPT_EXPR pass (perform const folding).
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$365' (010) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$364 [0] = 1'0'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$366' (100) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$364 [1] = 1'1'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$374' (010) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$373 [0] = 1'0'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$367' (100) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$364 [2] = 1'1'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$368' (010) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$364 [3] = 1'0'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$375' (100) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$373 [1] = 1'1'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$379' (01?) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$378 [0] = \memadr [1]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$370' (010) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$364 [5] = 1'0'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$369' (100) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$364 [4] = 1'1'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$376' (100) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$373 [2] = 1'1'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$372' (100) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$364 [7] = 1'1'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$371' (010) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$364 [6] = 1'0'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$377' (010) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$373 [3] = 1'0'.
|
|
|
|
2.14.9. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.14.10. Executing OPT_RMDFF pass (remove dff with constant values).
|
|
|
|
2.14.11. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
removed 3 unused temporary wires.
|
|
Removed 46 unused cells and 503 unused wires.
|
|
|
|
2.14.12. Rerunning OPT passes. (Removed registers in this run.)
|
|
|
|
2.14.13. Running ICE40 specific optimizations.
|
|
|
|
2.14.14. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
2.14.15. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.14.16. Executing OPT_RMDFF pass (remove dff with constant values).
|
|
|
|
2.14.17. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
Removed 46 unused cells and 503 unused wires.
|
|
|
|
2.14.18. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.15. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs).
|
|
|
|
2.16. Executing DFF2DFFE pass (transform $dff to $dffe where applicable).
|
|
Selected cell types for direct conversion:
|
|
$_DFF_PP1_ -> $__DFFE_PP1
|
|
$_DFF_PP0_ -> $__DFFE_PP0
|
|
$_DFF_PN1_ -> $__DFFE_PN1
|
|
$_DFF_PN0_ -> $__DFFE_PN0
|
|
$_DFF_NP1_ -> $__DFFE_NP1
|
|
$_DFF_NP0_ -> $__DFFE_NP0
|
|
$_DFF_NN1_ -> $__DFFE_NN1
|
|
$_DFF_NN0_ -> $__DFFE_NN0
|
|
$_DFF_N_ -> $_DFFE_NP_
|
|
$_DFF_P_ -> $_DFFE_PP_
|
|
Transforming FF to FF+Enable cells in module memtest:
|
|
|
|
2.17. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.17.1. Executing Verilog-2005 frontend.
|
|
Parsing Verilog input from `D:\Software\Icestorm\bin\../share/yosys/ice40/cells_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DFF_N_'.
|
|
Generating RTLIL representation for module `\$_DFF_P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `\$_DFF_NN0_'.
|
|
Generating RTLIL representation for module `\$_DFF_NN1_'.
|
|
Generating RTLIL representation for module `\$_DFF_PN0_'.
|
|
Generating RTLIL representation for module `\$_DFF_PN1_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `\$__DFFE_NN0'.
|
|
Generating RTLIL representation for module `\$__DFFE_NN1'.
|
|
Generating RTLIL representation for module `\$__DFFE_PN0'.
|
|
Generating RTLIL representation for module `\$__DFFE_PN1'.
|
|
Generating RTLIL representation for module `\$__DFFE_NP0'.
|
|
Generating RTLIL representation for module `\$__DFFE_NP1'.
|
|
Generating RTLIL representation for module `\$__DFFE_PP0'.
|
|
Generating RTLIL representation for module `\$__DFFE_PP1'.
|
|
Successfully finished Verilog frontend.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$323 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$330 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$329 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$325 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$328 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$321 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$327 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$324 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$326 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$322 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$320 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$319 using \$_DFF_P_.
|
|
No more expansions possible.
|
|
|
|
2.18. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
2.19. Executing SIMPLEMAP pass (map simple cells to gate primitives).
|
|
|
|
2.20. Executing ICE40_FFINIT pass (implement FF init values).
|
|
Handling FF init values in memtest.
|
|
|
|
2.21. Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells).
|
|
Merging set/reset $_MUX_ cells into SB_FFs in memtest.
|
|
|
|
2.22. Executing ICE40_OPT pass (performing simple optimizations).
|
|
|
|
2.22.1. Running ICE40 specific optimizations.
|
|
|
|
2.22.2. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
2.22.3. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.22.4. Executing OPT_RMDFF pass (remove dff with constant values).
|
|
|
|
2.22.5. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
removed 36 unused temporary wires.
|
|
Removed 46 unused cells and 539 unused wires.
|
|
|
|
2.22.6. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.23. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.23.1. Executing Verilog-2005 frontend.
|
|
Parsing Verilog input from `D:\Software\Icestorm\bin\../share/yosys/ice40/latches_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DLATCH_N_'.
|
|
Generating RTLIL representation for module `\$_DLATCH_P_'.
|
|
Successfully finished Verilog frontend.
|
|
No more expansions possible.
|
|
|
|
2.24. Executing ABC pass (technology mapping using ABC).
|
|
|
|
2.24.1. Extracting gate netlist of module `\memtest' to `<abc-temp-dir>/input.blif'..
|
|
Extracted 33 gates and 67 wires to a netlist network with 34 inputs and 2 outputs.
|
|
|
|
2.24.1.1. Executing ABC.
|
|
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
|
|
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
|
|
ABC:
|
|
ABC: + read_blif <abc-temp-dir>/input.blif
|
|
ABC: + read_lut <abc-temp-dir>/lutdefs.txt
|
|
ABC: + strash
|
|
ABC: + ifraig
|
|
ABC: + scorr
|
|
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
|
|
ABC: + dc2
|
|
ABC: + dretime
|
|
ABC: + strash
|
|
ABC: + dch -f
|
|
ABC: + if
|
|
ABC: + mfs2
|
|
ABC: + lutpack -S 1
|
|
ABC: + write_blif <abc-temp-dir>/output.blif
|
|
|
|
2.24.1.2. Re-integrating ABC results.
|
|
ABC RESULTS: $lut cells: 26
|
|
ABC RESULTS: internal signals: 31
|
|
ABC RESULTS: input signals: 34
|
|
ABC RESULTS: output signals: 2
|
|
Removing temp directory.
|
|
Removed 0 unused cells and 67 unused wires.
|
|
|
|
2.25. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.25.1. Executing Verilog-2005 frontend.
|
|
Parsing Verilog input from `D:\Software\Icestorm\bin\../share/yosys/ice40/cells_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DFF_N_'.
|
|
Generating RTLIL representation for module `\$_DFF_P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `\$_DFF_NN0_'.
|
|
Generating RTLIL representation for module `\$_DFF_NN1_'.
|
|
Generating RTLIL representation for module `\$_DFF_PN0_'.
|
|
Generating RTLIL representation for module `\$_DFF_PN1_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `\$__DFFE_NN0'.
|
|
Generating RTLIL representation for module `\$__DFFE_NN1'.
|
|
Generating RTLIL representation for module `\$__DFFE_PN0'.
|
|
Generating RTLIL representation for module `\$__DFFE_PN1'.
|
|
Generating RTLIL representation for module `\$__DFFE_NP0'.
|
|
Generating RTLIL representation for module `\$__DFFE_NP1'.
|
|
Generating RTLIL representation for module `\$__DFFE_PP0'.
|
|
Generating RTLIL representation for module `\$__DFFE_PP1'.
|
|
Generating RTLIL representation for module `\$lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.25.2. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'.
|
|
Parameter \WIDTH = 4
|
|
Parameter \LUT = 16'1001011001101001
|
|
Generating RTLIL representation for module `$paramod\$lut\WIDTH=4\LUT=16'1001011001101001'.
|
|
|
|
2.25.3. Continuing TECHMAP pass.
|
|
Mapping memtest.$abc$408$auto$blifparse.cc:492:parse_blif$419 using $paramod\$lut\WIDTH=4\LUT=16'1001011001101001.
|
|
|
|
2.25.4. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'.
|
|
Parameter \WIDTH = 4
|
|
Parameter \LUT = 16'0110100110010110
|
|
Generating RTLIL representation for module `$paramod\$lut\WIDTH=4\LUT=16'0110100110010110'.
|
|
|
|
2.25.5. Continuing TECHMAP pass.
|
|
Mapping memtest.$abc$408$auto$blifparse.cc:492:parse_blif$414 using $paramod\$lut\WIDTH=4\LUT=16'0110100110010110.
|
|
|
|
2.25.6. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'.
|
|
Parameter \WIDTH = 3
|
|
Parameter \LUT = 8'10010110
|
|
Generating RTLIL representation for module `$paramod\$lut\WIDTH=3\LUT=8'10010110'.
|
|
|
|
2.25.7. Continuing TECHMAP pass.
|
|
Mapping memtest.$abc$408$auto$blifparse.cc:492:parse_blif$413 using $paramod\$lut\WIDTH=3\LUT=8'10010110.
|
|
Mapping memtest.$abc$408$auto$blifparse.cc:492:parse_blif$412 using $paramod\$lut\WIDTH=4\LUT=16'1001011001101001.
|
|
Mapping memtest.$abc$408$auto$blifparse.cc:492:parse_blif$411 using $paramod\$lut\WIDTH=3\LUT=8'10010110.
|
|
Mapping memtest.$abc$408$auto$blifparse.cc:492:parse_blif$416 using $paramod\$lut\WIDTH=4\LUT=16'0110100110010110.
|
|
Mapping memtest.$abc$408$auto$blifparse.cc:492:parse_blif$417 using $paramod\$lut\WIDTH=4\LUT=16'1001011001101001.
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|
|
|
2.25.8. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'.
|
|
Parameter \WIDTH = 3
|
|
Parameter \LUT = 8'01101001
|
|
Generating RTLIL representation for module `$paramod\$lut\WIDTH=3\LUT=8'01101001'.
|
|
|
|
2.25.9. Continuing TECHMAP pass.
|
|
Mapping memtest.$abc$408$auto$blifparse.cc:492:parse_blif$415 using $paramod\$lut\WIDTH=3\LUT=8'01101001.
|
|
Mapping memtest.$abc$408$auto$blifparse.cc:492:parse_blif$421 using $paramod\$lut\WIDTH=3\LUT=8'10010110.
|
|
Mapping memtest.$abc$408$auto$blifparse.cc:492:parse_blif$420 using $paramod\$lut\WIDTH=3\LUT=8'10010110.
|
|
Mapping memtest.$abc$408$auto$blifparse.cc:492:parse_blif$418 using $paramod\$lut\WIDTH=4\LUT=16'0110100110010110.
|
|
Mapping memtest.$abc$408$auto$blifparse.cc:492:parse_blif$410 using $paramod\$lut\WIDTH=4\LUT=16'0110100110010110.
|
|
|
|
2.25.10. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'.
|
|
Parameter \WIDTH = 2
|
|
Parameter \LUT = 4'0110
|
|
Generating RTLIL representation for module `$paramod\$lut\WIDTH=2\LUT=4'0110'.
|
|
|
|
2.25.11. Continuing TECHMAP pass.
|
|
Mapping memtest.$abc$408$auto$blifparse.cc:492:parse_blif$409 using $paramod\$lut\WIDTH=2\LUT=4'0110.
|
|
No more expansions possible.
|
|
Removed 0 unused cells and 26 unused wires.
|
|
|
|
2.26. Executing HIERARCHY pass (managing design hierarchy).
|
|
|
|
2.26.1. Analyzing design hierarchy..
|
|
Top module: \memtest
|
|
|
|
2.26.2. Analyzing design hierarchy..
|
|
Top module: \memtest
|
|
Removed 0 unused modules.
|
|
|
|
2.26.3. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 4'0110
|
|
Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=4'0110'.
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|
|
|
2.26.4. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
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|
|
|
2.26.5. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 8'10010110
|
|
Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'10010110'.
|
|
|
|
2.26.6. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'1001011001101001
|
|
Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'1001011001101001'.
|
|
|
|
2.26.7. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 8'10010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'10010110'.
|
|
|
|
2.26.8. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.9. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 8'01101001
|
|
Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'01101001'.
|
|
|
|
2.26.10. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.11. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'1001011001101001
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'1001011001101001'.
|
|
|
|
2.26.12. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.13. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'1001011001101001
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'1001011001101001'.
|
|
|
|
2.26.14. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 8'10010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'10010110'.
|
|
|
|
2.26.15. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 8'10010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'10010110'.
|
|
|
|
2.26.16. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.17. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.18. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.19. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.20. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.21. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.22. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.23. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.24. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.25. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.26. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \READ_MODE = 3
|
|
Parameter \INIT_0 = 256'1101100000001001010111011001010101011010100000111111101110001100100010010111100000000100101001111001010111100000011011101011001100101101110010001100001111001110100110101101000111001110101100001001011011111010001011011111011111100010110000101111111110110111
|
|
Parameter \INIT_1 = 256'0010001000101110000010000010100000010010111010000001101101110110010100110000000111000010011000101110100010000100010010001001100011100111001001110011100111100011001000111011011101110100011001110101110010000101011000011000011100001000010101110001001011110001
|
|
Parameter \INIT_2 = 256'0010010111001001111110010001001111110111101100001001011110011110001100110001100001001010011011001011110100010011111111100100010110001001011011011110100101000110000111011111101010111101101110011001011111101001010011100101011011101011001110110101011011100000
|
|
Parameter \INIT_3 = 256'0011000111000110010111110101010100111000100000011110010101001110001101111001010111100000111001111111100101101010100101110010111101110100001001010000011111000110000000100110011001110101101010001110101111000100011000111011100011001010001100111110010010010000
|
|
Parameter \INIT_4 = 256'0010100101010110101010001000001010110110001110011001001110010001110001100011000110100100111010110101111000010000011100111010100001100000011001000011011111111000000100010100110000101011001010100101111111001010110100111000100001011111101001110010111010100000
|
|
Parameter \INIT_5 = 256'0010011110011011001101101011000001001101101010111101101010000101101111101001111001011111111010000101001100101101001000111101111001110111100000101010111001110100111010100101001110001110001000101011110011001111111010110110100001010000000111001001011100011010
|
|
Parameter \INIT_6 = 256'0101010000101110111000100101110010010011101100010101001101111100101010000011001000011111011001011010010010100001101001110111100000010101111101011101110100000011111100011001111011100101000101111110101011011001010010011000000110010000111000001111100111101001
|
|
Parameter \INIT_7 = 256'0001101101000011101000001000011111000110101000100010001111000110101010010000101101100111001001001100011100010001011110010111110010001110110101001111000101000111010000010000111111101011110000011000001000000101110100000010010010011110100110101011100100100011
|
|
Parameter \INIT_8 = 256'1010101111110101001110110100010111001100011000111001110011100100000010100101111011100100011000001000011110000111100110010010110001101010100110101100101100111000011101010100110011001001111110110010010010100111110001001100001111111011000111100010000101110001
|
|
Parameter \INIT_9 = 256'1101011110011011011000110001111111001101001111111100000100111001010001111001011000100001101000101010000111101001001100000111101111010011000001010010001011000010101010100110011100110100101100001000101011001111110010010100111100011010010110001111111001000011
|
|
Parameter \INIT_A = 256'1001110010101110001011010000000101111000111111000001110100001111011010110111010011101101011111110000011011100011010111001001000010011110010101011000010101101010001000111100001000011001010101010011100111101011010010001001101010000000000000100001010110110010
|
|
Parameter \INIT_B = 256'1010110101111001000100010000000111001010010110000011001111011000001101011111110110010101010001110000110011101001111010101000101001101001010000101010011100001001111001011010111100011011100110111000110110111000101001000010111001011101111001010001101101010010
|
|
Parameter \INIT_C = 256'1111110101010010000011011111100000100000001001100100011101001101100000001100010001101101110000000011111111110000110010111000101100101010010111110101100100111100000111111110110011001111100010001000110011110011001110111110110001100100010111100101000110010101
|
|
Parameter \INIT_D = 256'0011001011000111011011011100000000010011001110001110100010110100011011111101011001100000010000100110111011111011000110000111110010100000110000001100011110010111111101110001100011001011001010101101010001110111000101101001111101000110101111010101111110001111
|
|
Parameter \INIT_E = 256'1000100101010000000111001100010001100011101011001001110101001111010001001000010111011110110101011000100101111000010001010100100010110100100101011010111011010000101110010100010111100010001011000100100101110110101111001100111000000011110001101111100010101111
|
|
Parameter \INIT_F = 256'1000000100010111010100101101110011101000010101111101000110011001010000011001111111001011110001011011100001011100100101010101000001000110100101100000001010100010001011101000101000110110101010110000001010110011100110110011001100010011111011000010100100010100
|
|
Generating RTLIL representation for module `$paramod$aec89bda2bb51457738348c30887ba494f48a61a\SB_RAM40_4K'.
|
|
|
|
2.26.27. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \READ_MODE = 3
|
|
Parameter \INIT_0 = 256'1010110001101001011101001010010011011001110001011100110110101011001000111111001000101000010101010000100101010110000100111000100010101010001000001111000110111001001101110111100100010011000100110100111010010000100111111010100011011111111011000000100101010001
|
|
Parameter \INIT_1 = 256'0001011001110000100101010101001010000101011001000010000001101100011111010011000001011011110111100001010111100110011011110010110011100111100110111001010000011100101110111111001111001011010100000111110001011010111100100000010001001101001100111011010111110010
|
|
Parameter \INIT_2 = 256'1011100100011011111010101100111001110111100000001101011111001110111000010010010101011010001101001001011010000111011100101011110111100010100111111000101000011111101101111100101100100000010101111101101101100011110100111101111101011001111100010101111101001111
|
|
Parameter \INIT_3 = 256'1110111010100100001011011010100000110000110000000001110110101100111110100001010100011011110111001011101000001001110000011111110110100100010010101110011100000111101110111101010010011111100010011011101000100110101010000000001001011111000111101010100111110010
|
|
Parameter \INIT_4 = 256'1110011000010011001111001100000001100111001111111111001100011011101001100100000101011011001000111101010011000010001100011010011101100010010011011100101001101110101111011000110010101001010001111111011000101111001101110101001011111100101001101011100101111110
|
|
Parameter \INIT_5 = 256'0110010011001010100101110101101010100100000111011010001000010101111101100010110110010111010110011110111011010001110111110111001100011110001001001101111101100001111100101111011011000000110010001011011010101101101000010000000000101001100001100110000000100100
|
|
Parameter \INIT_6 = 256'0010101101101010011111101000010101000111000110101001010011111010011111000001001010100111100000100001100110000011011101111110101100101010101010011000011111001111111110111100001000110010010110111111011110010111101100111110101100101101100000100010001001100111
|
|
Parameter \INIT_7 = 256'1100100110111010100001110011010010111011101110001001100000001001011001010011111011011101000001100100111000101011110100110000101001010011110011110010010101010111000001011100101101010001100110001110110100001010000111101010011111111001010011101101101101111100
|
|
Parameter \INIT_8 = 256'0110110111101001100001111111001001110000100100000100101111100011000100011100000011011100010001111000010010011010100101011001111000110010100111111011010000001000010101011011111010011100001100110001110100100011001110001111101010011110101011101000011010010110
|
|
Parameter \INIT_9 = 256'1110111001001110110001000011111100110011000011011001010100100010110011011100011011111000101110101001101110001100100000110011010100110100011101010011010100110011010101110010110011101111011001011000111111001110100111101110011101001010110011011111111111110000
|
|
Parameter \INIT_A = 256'0111101000100001101001110001111110010110011001001100100100011101010101001011101101100000111000110011011001001001110010011100110011111101110010000001101111010010110011101000111100101010111000000101110000011111110111000000111100010100001110010011001010010001
|
|
Parameter \INIT_B = 256'1101001111111001101111100110111111110110111101000111010000100010000110010111110010100000000111001111101101110010001111101001000001101110001111110100100011111000001111000111011000111000011001001000011101011010000010101000110110000001100110010101110001110000
|
|
Parameter \INIT_C = 256'1011011111100010000111011001100000000110011101111101101000011110111010101010100011001111011011011000001011000000110000000011110011001001000111000110101110011011011101011110011001111000111010111011110010011101110110010110001011000110100111111100101110010101
|
|
Parameter \INIT_D = 256'1010000010110110100011011000110001000000011001101010010001111111110001011011010100110111001101000100111110110010100100000110100110000000011111010010001011111111101111111011111000011111011011001000010000001001000011001111101101110101110010011010111000100011
|
|
Parameter \INIT_E = 256'1000000011100111001001101001110101101111101110101111111001100110001100101000001111110111001000110010010100101000111011101110111001001001011010110110111111011101110110001010100000111110110000001011000011101101011110100010001100000101100010110011110110001011
|
|
Parameter \INIT_F = 256'1101111111111000001110100010010011110110100110101010111001110101110101111101000001000101010110001101011111100101100101000100011100110011000100010101101110001100010110100111100111010100011111001101101111011001001011010101000110001111011100111111001100011101
|
|
Generating RTLIL representation for module `$paramod$36cd72d0a2aa01f65f2e032aecaf806435b24292\SB_RAM40_4K'.
|
|
|
|
2.26.28. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
|
|
Parameter \WRITE_MODE = 3
|
|
Parameter \READ_MODE = 3
|
|
Parameter \INIT_0 = 256'1100010111000001000101101010000100100101001111011111010010000000000100001111111110000001100010001011001110010011011000001100110101111100110010110000101111001000111111000001001100100001110000010000011110111101111000110011001100001111100010011001100101111011
|
|
Parameter \INIT_1 = 256'0110100110111000100100011011010100010001110000000111111000101100011110010001111010101011010111010100101101110111110111000001011100000100000100111000111110100000000110000000010001100100000001110110010001100010111000101100101011000101011101010001001100110001
|
|
Parameter \INIT_2 = 256'1010011101100111000001111100110010110110110110011011000000001110011111000100100010111000101101111011110000101110010100001111001101111101110001010000100110110101000011111011011110111111111000010100010101101010100111011010000100111100100110001101111110000011
|
|
Parameter \INIT_3 = 256'0010011101111011111101111001101010001100100000100101011100000010110101000101011000000001110000110110010011011000101010110001100110111110001111111110011001100011111010110101110010100101010000010101011110111011010101111011101101001101111111100001011110001111
|
|
Parameter \INIT_4 = 256'0010010011011001001010011000011010010111100011111111101100000001101111110000101101000101101010110011100011001001000000111010110110010110001011011000001111100100010101010010111101101111010101001001010011001101000100110011111011110101001110001010101101100011
|
|
Parameter \INIT_5 = 256'1100100111001000001010111010110100011010110011010001100100010100011110000100111000110011111011000111111110111010100001110001111110011000010001000010101001010100000111010010101011101101101011101000111101101001110000000000111000011001001010110100000101000011
|
|
Parameter \INIT_6 = 256'0110101010100000010010111101110101110010001100010101010101000101000010011010010111111110001001110001000010011100000110011110010000001100101111101111100101111100111000110111110111000111101110010100000111000111100111100000010110001000001101101101010110101101
|
|
Parameter \INIT_7 = 256'1111100111100111100001011010100110010100110000111101110100001011001001010110011111010010001010001100110110000000110101100101010000101011100110101100110100011111000100011101010111000101111100000101010011010101110000110010111010001100100010100110101101101100
|
|
Parameter \INIT_8 = 256'1011100010110000101011010101001110010011111110110111111000100011111100010011111100111101111110100111111000101011111000000111111111111101101101101001011111110110101011001110111011111101111100111100110000101011011000100110011010000001110010001111100111010101
|
|
Parameter \INIT_9 = 256'1101010011010100110010010111001111110110110011101101010110111110111011011000100001110001110011010001000110000001100011110010101001000110111100111000101110111101000111011111100111110101011110010011001100100011001111110000100100111110101101001101001100101110
|
|
Parameter \INIT_A = 256'1100001111011101101001010011110011101000011000111000100011100000110011001100111110101111011100110110110111111110111100001110101001011111000001101001000101100101100101101001111111101001111100110100111101100001110001111111010010010011001110011100011000101010
|
|
Parameter \INIT_B = 256'1110111011000110111101101000011110011001010000001011011101010011000001111111000000011011110001111001001100011000010101101001010001111001001101010101110010101000010000110011010111100101001101100010011110010101100110101011010101100101111011011111010111101000
|
|
Parameter \INIT_C = 256'0111111010111110010010110111111011101110101110100000000010001010010001101111001010101010000001011001010100100001011001011110000110001111100001110110111011000101001101001100100010001100110111011001111001001010000100110100110000111001100110110001111000100010
|
|
Parameter \INIT_D = 256'0010001011010000110001111111110001101011110100100001001011100100001110101110000101101101111101000010101000001001001011101110000110110111111001100111100010010000110111000101010101001010011000101111101111001110110010011010100100111001001111101010111111010111
|
|
Parameter \INIT_E = 256'1000100100011011010000101011110111101000101101101110000000011011010111001110110100110000101000111111100111100110101010010100101100100010111111100001110111111101011101011110110100010010010010000000101101001110000110001100101000100011011101100000100111001100
|
|
Parameter \INIT_F = 256'1100001011001011010111011100000101111101010001001111111100111110011000111111000011001101001111100010101100010011111001010001000010100110010000101010111010110111001000100010111110010110011001010101101000001011001111010000001000001011101101000110111011011000
|
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Generating RTLIL representation for module `$paramod$4634a39a6cd62b13e97c191bc48a5bf27335db8d\SB_RAM40_4K'.
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2.26.29. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
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Parameter \WRITE_MODE = 3
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Parameter \READ_MODE = 3
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Parameter \INIT_0 = 256'1001000001100001111011110001001101110111011101001010110000011011000000110001000101000110000101100011101111000011010010001001110000110101010111000010011001011110010111110011100100110111110000010001101001111000011010000101001010000001100001001101100111000011
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Parameter \INIT_1 = 256'1011111100000010101100110101110100111010001001011101011100111100000010000100100011010100011000000110010101110000000100101001111110101111000001000101100110000011111100100011010110000111110010100010000000011000011100001110001011001011011111101001100101111011
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Parameter \INIT_2 = 256'1011110000011001000100110000001000010010101010001010011110101001001111011111000110111110010011111010101010101001101110011000111111011010110101011011001111010100000010101101111100101100100101110111011001000111111101101101010100000101110001101000011011111101
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Parameter \INIT_3 = 256'0111000000101010001010100011110011110100100100101111001101001001000110001001100010101110001100011110110100000001000011011100001010111010111110101010001101110000100101110010001000000010000111100010010100101110110010111101011001000110101010110011111100101111
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Parameter \INIT_4 = 256'1001100101111111011100111000101010111100011010110100010011000111110111000011100101010011010111010001100110001011001111111000101011011011101100110001010011100011011111111100100101110001001010010101000100111011100101000000111011001001010001000100101111101111
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Parameter \INIT_5 = 256'0011110100011101110100010111001000110111111100110001110111110001010100110111111100111001111100100100111001110101110100111000111000100111011111100000111101011000100110010001100101101001111101000000110011010100010011101011001000110010100000001011100011111110
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Parameter \INIT_6 = 256'0011110100101100101111111000111101111110010000001001100111000110111101111000000000011111100101111111100011000100111000010011010111001011100111010111011010110110001101111110100001101110110000000100000010000110011011111000011010110011101010101001011100011110
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Parameter \INIT_7 = 256'0101001100001111101000001000100100101000100001011010110110111000101111100111110111111000111011111001101101100000010010101100100100101100000010110010110100001011101011100100001110001000011001111010000110110111001100001100010111100010101110001101110000110101
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Parameter \INIT_8 = 256'0100110010111111001011000010111011110011001101100000110101110111001000000101100101110000100011100011011101001001101101111000110111110011100100111110011010100001001101000110011111000000100000010000000010101010011111101100000110011000010010001101001111101010
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Parameter \INIT_9 = 256'1001001011000011010111110111110100001011001100100110000110111111010011110101010011110010000111010011100111100000010111111111111110100100110100101000011101010001011110111110011000010001111111010110110101100010100101100010001000111111111010110010100000111101
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Parameter \INIT_A = 256'0000100000100110000100000111100001101000110011011011011011000100100011101011111010100100000010010111000111111010101101101110100011010110011001010011100011100111000000100011100001111100101010100010100111001111000111000010100111111100001010001100110001100000
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Parameter \INIT_B = 256'1110010000010110111011110111100111011011110100000000101011110110001111101001110111001100110111000000101110000101111011011010110100011010101110111001011111001101011000011100110010111001011010000010000011000111011111010011100000101001101110111101101010010000
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Parameter \INIT_C = 256'0111010101010010001101100111010011101111110010111111110010010011111011100101000101001111110110001010000000111111100011101111111001100000000001111110001000000100010110110001110001100110110110011101100110101101110010010000100110101100111101111111110010101010
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Parameter \INIT_D = 256'1001010010010100111111100000111010010010010111101110001011001010001111100110000100000011001000110100111001110111100000100101111110001010111011011001100011101110011111111101011100101000111011000011100101100010100100101100110100010111010011010100100001001001
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Parameter \INIT_E = 256'0100011010100000010110100000011100010011000001100000001110110011000000001101110010111100011001100100111100011111010000101011110001101110100101011010111100010110011111010010010110010010010111000001011101101110011111011110010101110100000011000010011010100011
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Parameter \INIT_F = 256'1011111110010011111000101101000111010001011101010001011011110000011111111010000000100011001101101001110011100001011011011000001100000110000001010010000110011100111000000010010101111100100100100000010101000011101001011011000110111110101111101000111010110010
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Generating RTLIL representation for module `$paramod$7340fe4b074e1d328bd9dde30b4a8f28ee267b25\SB_RAM40_4K'.
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2.26.30. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
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Parameter \WRITE_MODE = 3
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Parameter \READ_MODE = 3
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Parameter \INIT_0 = 256'0000110110001000001110001101110000011100011011010100010101100101101000111111110110001001110010000110110111001010010011000000100010000001110001010100001001010110001011001110001101100110111011011110000010011001101110110111100110100111001001011000111100010100
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Parameter \INIT_1 = 256'1111100100110011111011110011110001010100100010000000000000010100101110011101001111110000100010100101010010000111100010101010000111110110011111100100010010100011001111000100111010111111111011101111111101110010001110000010110110000001011101110110101000010110
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Parameter \INIT_2 = 256'0011000011000011000000101010011100111001010111111011110010000101010100011101100011111111000001100011100101011000000011101110000010110010000011001000010111111001011111001010011000100011000101100000111001011000011101011011100101000000101000010110010011111010
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Parameter \INIT_3 = 256'1010010110001111100011101101101110111010110001001000001000100000000101111110001010101100100111010001110011011111010100001110111100011011101111011100110100111100100010100011101100010111100011000101001111100111001101011010011101110111111011110001100001111100
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Parameter \INIT_4 = 256'1100111011111111110100110001100100001101010100101001010000011010100101101101110101110111110101001100111101001111110100000101100101011000001101011110000010111101100011001000110011000110100110101100111001110011011110011011011010010001110110100000011101000000
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Parameter \INIT_5 = 256'0110110010101010001000100000111111010000010001001001001001011001111110001101001011110111101110000111111111011110110010101001100011000101010100000100010000110100111110001010010000111011110011011000010100011100100111100110110100001010100000001011010011001000
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Parameter \INIT_6 = 256'1111001010110011000110000010110101001101000100010111000100110001110111100001000111110010010110010000010011010001000110100010111010011111010010011001000111011000101011111011001100001110110011111000011001111011010100011000100010100001001000110110011010101001
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Parameter \INIT_7 = 256'1101101111010001110000011011000000100110111111000101010011111001010001100000001100010100000110011101100100000111101001101100010111011011101101100000110010010101000010110101011011001010101100100001000010101110011110101101000010000111100010111110100011001101
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Parameter \INIT_8 = 256'0111010110010101111111111101001000110111101011001010100100010010100111110001000000010101110011010010110100111110100101001101010001011110001000011100001000010101000110101100111010110011101100010011110000110101100100000111110011101110011110100000101010100101
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Parameter \INIT_9 = 256'0000001000101101011010110000011110000101111011011010000001011111000111111100110111000101010100100001111001001101111000001011010110111100111011010110101101011111101111010101010110101100100011101001000111000000000010010000010001110011011011111100000111101110
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Parameter \INIT_A = 256'0011010011010011111010010100000000010111011110110100000010001001000110101000111010101110111001111111001100100100100111010101101010001001011011001111000101111101001111111001011100010110000001101111101010011000000000010010000110010111001110001101100100110000
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Parameter \INIT_B = 256'1110100011010111011001100001100010011011101001011011110001011101000000001010011001101010100000101010110011100001010010111101001110100000000110110111100001110100010101100011100011110101000111000110010000101110010110000010010110000000100101001100001101100001
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Parameter \INIT_C = 256'1001110000011010011100010110100110111110110000100010000010010101111110011011010110101110110100110101011100001010010101101001011100101011001101001100000010001010100100000110010010010111011011101111000011000111111001100111110110100011010000110010000100111101
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Parameter \INIT_D = 256'0101000010001001011110110011110001011011011111110101011011000001011100101111101010110001111001101010101011000101110001101101111111111110100110110110101100111001010100010001010011110111001111100101100011000011000011111101101101001110001000101001110011011100
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Parameter \INIT_E = 256'0000110110011110011101000001000101101000110010100100101110000110000011110101010001100000101010000111100110100100101010110100010011011000010111011000101110111000111111011001010101111010111001010011001000000001111001011101111100011110011011010000000011110100
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Parameter \INIT_F = 256'0100011100111000110101110001011011011001110100001011110011011001000010110001110101010100010010001100100101100000110101011010110111000010011001000011000101110001110101011011010100111001000000111011101010011110010111111011001011111111111000110001110111011010
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Generating RTLIL representation for module `$paramod$0ce62515d3067330f88e04b97293dc0659fa9113\SB_RAM40_4K'.
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2.26.31. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
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Parameter \WRITE_MODE = 3
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Parameter \READ_MODE = 3
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Parameter \INIT_0 = 256'1000001001010001001111011000110100111001010001101110011101110010100100101100001000000011110110101010101110110011111010110100011000001010111010101000101001100001001001110110100000001111001001011010101000101111111110001100110000010010110000110000110001100011
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Parameter \INIT_1 = 256'1001011010101011001110000010000101100101101011001011000110110111101011100110000110101111011011110000111011010100100011110011101001110001101100101100010000011001010101000001100101000011010101011001101001101110010110011111110111111011100111110011111010010011
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Parameter \INIT_2 = 256'0000000001001000001001100111000000011001000000011110010101111011100101111110000101100000010001000011100010011110010101101111010101111110000100111001111010100100010001000110001010010001100001101110100101100111011000101100101010010001001001001111011100001110
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Parameter \INIT_3 = 256'0111000000110100111110111000011010011011001100101000100001110000011011011111110000001010000001000000110101001110011110100001011001010000000010011011011100110110111010000100101100010111001000001011010000000010110010000010101100101000000110111010111100110101
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Parameter \INIT_4 = 256'0011010001010110110111000001010001001111001011001011001011001000101110001010010101111011101010111010100111011001110001111100001010110010010010011111000100011001110001010011101100101001111000110100010101100111010010101000001010000001111100001101101001110110
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Parameter \INIT_5 = 256'0000010101000000100011010010011011101110111011001100011111001000000100001010110101111110110000100110101101100000011100101011110101100110010110001000001011100100011010010000001100101100101111100110111010010101011110000000110100011000001001000110001111101111
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Parameter \INIT_6 = 256'0110000010010011001000000010110010001101010010000000011100000101001011000001011111001011110100111000100010111001110110011011000110011111000000010011000011010100001100111000000111110100100000000100100101011110001101110100101101111101100000000011110000001000
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Parameter \INIT_7 = 256'1111110011000010111011011000001000111100101000110100100011100100000111101110100000100100000101011010110110010110111000010001111110000111000100000110000000001011101101010100000100001010001000101101110100001000010001010100000011111001111101000111100111111000
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Parameter \INIT_8 = 256'0101111000101000110111110101101011111111101101100111101100110010111001000100101100010011011010110011010111110000111110000101100111101110010001010101100000010000110101111010010101000100100011110010001100011000001001011010010110111111101100010001100010001100
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Parameter \INIT_9 = 256'1101111101111000110011001101001110100100111000111000111110110100100111101000010001111100101110001100100001110100100110001110001100100100010011011111101110010001010000101010010000110111110100101100111001111010101101011101111100000001100100101101001101010110
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Parameter \INIT_A = 256'1100110111101010111101001111011001011001011101100011010011100111111111111100100000011010000000010010100101111100001000100011100011100000110101001010111101110100010111100100000001000001111001001000111100110110001101111001111000110001101110111101101101011010
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Parameter \INIT_B = 256'0110101010101110010101011010100110111001001100011110111001101100000110010001100111011100100011010001111011001110010011010001010011000000010001110011011011000010101110011100010100110110110110010110111001000101001101100001110100011011101001110011010111001001
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Parameter \INIT_C = 256'0010100101011100111010001111011011000001010011000001000110000111111001110001011110010000110010011010110000111100001100001100101011101111000110001000101100100110000111111101010000011010101111010010100111111001001010001101001011011001001010011000110100010110
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Parameter \INIT_D = 256'1100000000000110000000000111001111011100101011100111011000100101001100011110001111000100011001001000111110010110110010100010111101010111000111101110010000100100101101000010000011011110110001010010101110010101001010100111001000101101001000101110011011111011
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Parameter \INIT_E = 256'1000101011100101111010011010010111011011101100001001110100110010111110000011110110001010110111100011000100010010100010010000000011000011110000101010001101100101101010100011100101100001011000100101110110001111111011001000010000111001010100100100111101111101
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Parameter \INIT_F = 256'0110001110100101110111011110111110000101111000111100101001110010111110100001110000101010100110101101101010011100010110000110011100110010010001001110011000110101010100101001010110100000110100110001010111001111000100101111100011010101000100011010101110111111
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Generating RTLIL representation for module `$paramod$60b3dfc4f309aea3ada8285e1d40951195a0353e\SB_RAM40_4K'.
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2.26.32. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
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Parameter \WRITE_MODE = 3
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Parameter \READ_MODE = 3
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Parameter \INIT_0 = 256'0000100000100101001111011000001101110111111000010101110001100000000010100100010111000010000110111000101110010101010111011011001000100001111011000111011010010100011101111100010011101110000101110101000010110001001100101101010101000001110100001010100010101001
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Parameter \INIT_1 = 256'0010101110000100001011111011101110010100100011011011110011111011100100100111011001100010001011100001110110101011110111100010101011100111110101100111100101110000011100010011101010000011011100011010100110110011001001100110010000011100011101111011001100000010
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Parameter \INIT_2 = 256'0111100011111000010001111101000110010011001111001100011000100010001001100010110111001111010101010001100001000000111011011101111001000101100111100000100010000110110000000000000101101001001100000001011000101110001100001101000001000101000101101001101000011111
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Parameter \INIT_3 = 256'0111010011001111101010000000100111100101011111111101100110110101111011100000111000001101001100010011000101101011101011010001001011101110001111100000000000010100001110101010101101100010000111001101110100001011011111011001001100101010011000011000110100101000
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Parameter \INIT_4 = 256'1000101011110111000101110001110111100110010101101100111110010111100101111101110010110011001110110111110001111011000110111010001111011100101100111000011111100001011100011001011010101110101010110000101110111111111111100001110000011100101011100001010011110101
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Parameter \INIT_5 = 256'1100011110011110011000000001010010000010111000111011000101010011100110011101101111001110111110100101001011010010101000110111000010001110111001111101100110110110011000110100101111011100100100011101111010000000010010101011111101110110010110000011110001011100
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Parameter \INIT_6 = 256'0101001101111101101100001100110011001000011110101001101011100000000100011111110101100010101010110010111100100001100001110011111010110101000011011001001110001011011001010101011000011000001001111101100001001011100101010001110111010100111101110010110110001000
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Parameter \INIT_7 = 256'1111010111001010011101100101001110011011101110111100111110011101110110011110011110111011010111010000100010011011001100100010011110101100110001111100000101100110111110110011011001110101001001110000010001100111001001111000011101100101000100101000011110001110
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Parameter \INIT_8 = 256'1100010011011000000000100100000010000011100101011110011110110001100110100110001011001011000101100001011010000000110000101000101010111110100111001100001011001111100101101100000110110100111101001001110010110101110100110100110000010011110101101100010011010100
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Parameter \INIT_9 = 256'1011100110110111100000000000010110000100000110101111011011001100010111111000100010011001001101001000010001110010110010100011110111000111111111101110010100100110010101101001101101101001011101101111010001001111010010000011010111001000011010010100011101011100
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Parameter \INIT_A = 256'0011110111111111010011100110111001111011001100010111100001110011001111011011100000100100100010011100001101001111111001111000000010011011010101100001100001111101111000101010000001010110100110101111101111011110111001110011111011101000011111001100010110011000
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Parameter \INIT_B = 256'0111110011101110100110001111001000010100100000101101111110010101101010000101111111101001000011010101000111110100000101111011110100010110011101111110110000000110100100010000011000110000010010001111100000100000110000010100010010011010110111110010101100100110
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Parameter \INIT_C = 256'0111000000110001000111101100101111011000011010110000110001110010010010100100111100000001110111011010111010000101001110000000010001000011000111000011101000111011110110111000000001100010011001100001110101111011110010101000001110000010000001110001001011101100
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Parameter \INIT_D = 256'0100010100000010001001110110010111111001010001111111010011001000011010000010010110111110110010000110110111101000101011110100010000111011011101110010000101010110101001100010100001011110100000011010001111000000010101001001001010001011100001010110010000000011
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Parameter \INIT_E = 256'1010100010010001111110111000101100011101000101110000101111001100010111101101000011101101100000010111001100000001011100100101111000110001100101010110110000010101000100011101000001110010111010001100000101101011111101011100001110101011110111011001101100111101
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Parameter \INIT_F = 256'1000111011100111011100110001100000000001001010101010001001011011101100011010011111111011001100001000010001101101010000101110010001000011010001010010000010011010000111011111100100110000101001010011110100000000000100011010101001001011110001101011011100000101
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Generating RTLIL representation for module `$paramod$c74655a14c7cc6adeb7816abc7bdb3c44a7ba15e\SB_RAM40_4K'.
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2.26.33. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
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Parameter \WRITE_MODE = 3
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Parameter \READ_MODE = 3
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Parameter \INIT_0 = 256'1101101100001100001010101100101100101101111110101010011011100010110110000101100100011100010011001100010101000101000011011000000100000101001101000010001100000001010100110110111100000110010111111000101000000110110010100111011000011001100111001000010010100011
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Parameter \INIT_1 = 256'1001000100111110000110010011101011001110010001111010110001001001000010000101100110101011111010011010001001011110100011000000111110001110010111000000000011000110011001100100101101011000010100011101011001010000010001010110001000110101101000010000101101110001
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Parameter \INIT_2 = 256'1111000011110010101010110011010100010000111110011111100101100010001101111011011000101110101110100100000011011000101010111001010110111100000110110110101111100010111111100101110101101110010010011001001011100010010000011101001111011010011001010111100101000110
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Parameter \INIT_3 = 256'1011111011001100000011100000001100111010101000110110111010111001101100001011010100010101110010101100100110100010000000101010100111111001000000001111001100000001100001000110110100110010100000000100110000010010101000000011111001100110111111010010010101111000
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Parameter \INIT_4 = 256'1010011100110000010110101101101000000100011110001111000010100000111110010010101111100011000011110010001100000100001110000011000101100111111001001000001011010001100011011000101101111100100000001100110101000111100011001001001011111100000111011001100011101001
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Parameter \INIT_5 = 256'1110101110101111100111010111110111011001001001011001000100011001101010011100100110001001000101011101101110001000111001101111001110000010100111101000101111100100100110110000011100101001011110000010110100010110010010100111011100010010001011000110111011100111
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Parameter \INIT_6 = 256'1110011010100011000110100000011101000001010010011011000011111001110011000100101111100011000010010010010011001000001011110100011101001110010010000011110001100010110111100010011011010000001001011110000000101100101000111111011000001110011001000001001110101101
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Parameter \INIT_7 = 256'1010101100011001110110010100101011011100110100000110010111111001101101110010100101100000101110110011101111111010111000011011000011001111001010110011101110110010101011001101000010111110110010111110101101111011110000101010001101001000111011100001110111001011
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Parameter \INIT_8 = 256'0101000100100011010100011111100010010111000000100001001110100000110001101000011001110110011011101011110101000110001111000110110010011011011010011011100101000011111100110110100000100100111100101001000001100001000110110011111101100111111111000111110100111100
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Parameter \INIT_9 = 256'0000011001110111100010011000100110110010101100101110010001010000101011111010000000111011000000010110011101010101111011011110110000010100001110001101010000111111001100001100010011000010100101101110111111110110101011100000010011100011101110000101011111010110
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Parameter \INIT_A = 256'1111101001111101010111111001110011011001000110000000100001110001111101011100010110110000011101001101100010000101110000011011000011000110100101101101100110000000001100001111100010001110101111000110010101110101111000010001100110100101100110000111111011111010
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Parameter \INIT_B = 256'0110111100101010011000011111101110011010010000011110101100101011101100100100011111111001011101101001110011101100111011100110000110000010110011001011111110011100001011100101111110100101010000010111111101011010111001011011011011000111101001110000011001111010
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Parameter \INIT_C = 256'1101001101110100000100011011011110100011001101111011000110010010110010010010011101100101000000010110101001111010111011100000100011100001011100010111011010010110001110101010001000010100001110100110111001101100000101110110010110110100011110100110011000111101
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Parameter \INIT_D = 256'1001010000101110000101110101001000111000010011001101011000101100110111000011101001001101001001111100011101000001001000111001011000010001010010100010100110001000000000011000000110010011110101010110101001101001001011101010111110110000010100010100111010101010
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Parameter \INIT_E = 256'0111011111100101111001101010000111111010010001100000011010001101101100100110000111111100010011110101011010000101110101000011110111010011111011110111001100010001000110100111101110001011100110110101111010001010000101000100000101100100111010001100000001100011
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Parameter \INIT_F = 256'1101011010110101001011110111100110110010101101001011010001010011100001101000101100001100010010011000111010111101100110001010011100010111100010111001011000000010001101011100101110011010101111001101101010011110000001001010010011001100111000010101101011101101
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Generating RTLIL representation for module `$paramod$7c21166ea4c3b2a9d7a87502f98118a3ea2bbb02\SB_RAM40_4K'.
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2.26.34. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
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Parameter \WRITE_MODE = 3
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Parameter \READ_MODE = 3
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Parameter \INIT_0 = 256'1111111100101100010111011100010001011111111000111010110000101010001111110001110011010010110100101010100110010101001110101000110001110010100000000000011010010011100010000111111000100010100010000011110001001110000100000000011011000011110110001110001010001111
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Parameter \INIT_1 = 256'0001111101011011001100111010101000110110011111001101101101011011001011011100101100001110001111110011110001010010001000000101100101000100111010001101011101110010010110100001000011100100101111011101100101100110101010110000010111000010110100110001100111100101
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Parameter \INIT_2 = 256'1110110001011100110111010011101111000011101101001101100101000010001001000111111001001010110011001010011011011101000011000111111110010011101011011011001001010111011001010111000000100001000101100110100100001100110010101010110101101000000000010111110010011011
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Parameter \INIT_3 = 256'0110010000110111011100110110100110010000011111001111011000011011111111100101010001011111100001101110100010011100101001110000101111010011100101010101101111101101100100100000100010011111110110101001011000010110111001111110010001010101001011111110111100001100
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Parameter \INIT_4 = 256'0101001011010101100000011001011101101010111110110001010101110100000001111001111010101000000111110111000110111011111110110011010110011000111011010011111001111110011101101000010000110000011111111100000010110001011111011101010010010001001101011010111110101110
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Parameter \INIT_5 = 256'0010100110010001001101011110101110100110001011010100001010111110110010011111010001110011111100101011000000011001001010001101000010110010111011011001100101011110001110111100101101010010101110101011111101101010010000010111001010011011100001100100011011101001
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Parameter \INIT_6 = 256'1001011000110000101011011100011011111000011001111100100000000010000010010000000101010100110010100000011000110011100100010000101010101110101010001001101000101100111000110011000111110111010000111101010011000010110110000100110110010101001110000000110101110100
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Parameter \INIT_7 = 256'0011000001011110110000010101100100111010101011001101000111101111000100001000000010110110110011111000110110100100111000101011000100110001011101111001001000111110111101011010000010001101011000111111100001111110000101101000001011011110011011010100110110000010
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Parameter \INIT_8 = 256'1000010001110001101010000011111000111011011001011010011111100011011111000011011100100011111101010010101100110101011101010110011101100001110000001110000111110011111101001110111100101111010100001011101001011101000111101010000001101110000001011010111001010111
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Parameter \INIT_9 = 256'0100001000010101000100101111110101111010010011010110100000010111010011011001110111011000111100010011111001000001111110000010100101000110010101101000011100110000110001111100101001001010100001110010011101111001101011111001101100111110110111000011000100000011
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Parameter \INIT_A = 256'0010101010010011111001011011010001110000001010010010111010100111001110101111100101100100010100010101011100100110001001101110010100111100001111110001001000100101011000110000010100010101100100110001101010010101101010100100100011000001001001010101010000100001
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Parameter \INIT_B = 256'0000001110011110100110101010100001110000011111011001101001101100001101010100111011110010101100001101001111001001101011110000010011010100011001111110101001010110011011010010010000000100101000111101000010101110001110000110001011101101111011000100110010110110
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Parameter \INIT_C = 256'0010101110001011100111111010000111001001101011101100000111001000000101100110101110011110011101100011010110100110010100101000100100000110110101000110011101001000011111100000010001000111101001001111110100110010111000001000110111000110111010010010101010000111
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Parameter \INIT_D = 256'0011100000000111011110001001001111111101001010110011000100101100100110001000100001000001110110111100100101111001010000000111101001101101101001101011001001000011011110011110111110001110010100001101010101100001011101010010100010011010110101001011010100000010
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Parameter \INIT_E = 256'1011100000010110011100000001000111000010110111001011011001100000100111001011001111110101100011100010110100000010111000100110100001111100110111111101001001001101011010100011010000011001100000011100110001111010011110001100000001010011101011110000111111011000
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Parameter \INIT_F = 256'1001001001001010011001011010100111001111010010101101100011011101101000101000000101001001100111101000011010101011110010111001010011101000110111001111001111100000110110111110110101001110001100010011010101111100110001011010111001000101101010010000110001110110
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Generating RTLIL representation for module `$paramod$6b1c6f63ba5f996acd858be247d742a022a819f1\SB_RAM40_4K'.
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2.26.35. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
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Parameter \WRITE_MODE = 3
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Parameter \READ_MODE = 3
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Parameter \INIT_0 = 256'1101101110100101100010000001011100100010110101101011000110110000111011010101100110010010100110011000111011100001100111000110011100001010010100110101010001000100100001001110010111010111001011101001110001111011100111010110010010010000110001000010111010100010
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Parameter \INIT_1 = 256'0110101010011011111010001100110110101000010000001110011100100000001011001001001000100111100110110011001110010100011111011100101111011101111110111001011011101011111101010001100110100100110010011111011011011100010010111010011110010110100000001000000111101100
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Parameter \INIT_2 = 256'1100000101000011101000101101101011110110011101011010011011101001010101111001010011000100011010010111110001000001110110100011010010010001101101010100000011110011000011101100000101111000001111100000010010110110100111110011101110100000001011000110101110101000
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Parameter \INIT_3 = 256'0111001110110111101110101110011010010101101111111001010010101111110110100011010100001111101100001101110010001011001011110101000001100001110110100100011001001110111101001110110001011000111101011101000000110110110010011111010110100001011011000101011010101100
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Parameter \INIT_4 = 256'0010110001010111111001011111101000110110110110111110000011110101011100101111111101001101010100111011111011110011001110110010000000101110011010111000011010001101010101000011100010110100100011101010000001111000111011111011101000100110101010001001000101001101
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Parameter \INIT_5 = 256'1000110110101010101001100100000000101111011011110111111011110010111111111001011000001110000000011110011111011000010110110101101000111011111001011111101100110010111100001001110011111100011111111101111100100100010011001010100110110110001000011110101101001101
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Parameter \INIT_6 = 256'1111010111011001010111000011000000111100000001110010010111100001001010100011000110001110111110110011110001111010010001110010110110011100111111101111001011100100001000010111010110011101101110011101011010101111110100011110110001110010010000011010011010011100
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Parameter \INIT_7 = 256'0011110110011110111001100010000100101000011101001110001100101001101011000110111110000011111011111100101000011001011110110111101101010111010011010001001101100111111011110101011100100001110000000010100000001110000111011100100011001010000111100101110011101101
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Parameter \INIT_8 = 256'1000000000011110000111000110001001001001010111111111000110001000011011011101101111000011110000000101000110000101010001101101110001101010011011010110111010000101101000100001001110100011100110001110100000000111001100111110010110011110100101001101001001000110
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Parameter \INIT_9 = 256'1101001010110010011100101100111111011001000101001101000100011100101001110111101110010011000101001011100011111000100010110111011100110111000111011110101100010110011111000101000011100001101101100000110101101110110101001101100001010111001100100000111000110101
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Parameter \INIT_A = 256'1101110111110011010100101000010001110010110100001010101011100010001010111101101101100101101111000000110001111010001010110000100100001010000111111101100110100110101101100101001100010011000111100011110101010010001001001010111101101001111111100101111110011001
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Parameter \INIT_B = 256'0010100001010000101011011001101001001110011110011000100111110111001101010000111011101110001100010001000001011000110000100000010111011011001001101010101110010100100110100001010110101010110110001010100001100100010011110110100111010000111101000011100111010100
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Parameter \INIT_C = 256'1100001000011010110101111111010011001011011001101001110000010001110001101101011110101100000111100111101110111100000010010011100100011010011001110010110011011111111100001001001110010101110010001010110101011110110001000110111011111010101111011011110100010110
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Parameter \INIT_D = 256'1010110000010111100000011110101110110110001111101100010110001110010010101100001100110101000001100011101011111101100101111110100011100110101010000000101010011110111001101000011011111000000111000111100101110101101111000010000000000010111011110110101000100010
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|
Parameter \INIT_E = 256'1101010110100100100001001010100001010011001101110101101110100101011111111011010011110101000110011000011000100110000110101011001010100001000010011011111011000100011010100101110110110111010101000101000111010110000001110111111011001010100011111000101001110101
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Parameter \INIT_F = 256'1011100011110000001100110111111100011001011101110000111111101010010111011111010110010011110100000101011111100000001011110001100010101010111100111000100111011100001011011010111101010110100010000111110100101110010111100111110100011010100000011011111000100111
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Generating RTLIL representation for module `$paramod$cd87ac4b13c15dbaa504f663e927b7c4b0d5fa2f\SB_RAM40_4K'.
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2.26.36. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
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Parameter \WRITE_MODE = 3
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Parameter \READ_MODE = 3
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Parameter \INIT_0 = 256'0001101001111100110001111001001001110001001001100011101110000000001011100000100110111111000110010110001001010010010001110011010001000001000101001101000100011111000100011111001111111100001100010110001011011001010110000101100001000011111000000110001001001101
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Parameter \INIT_1 = 256'1111011001110011111111110100111110110000110011000111101010011001110010100011111100110110101011101010001001111110000110111011001110100111110101110001110100110100011101010110101001101110000110000000011101101111110010001101101010000100110010000010101111010100
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Parameter \INIT_2 = 256'1011011001000011000001100000010000101101111110101101111110100000011000001000101110010000111100100111100010001101000110011001011100010111100110010100100101001011110010110011100101010111100101110111110010000011110110100001111011010100000100110110011111101100
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Parameter \INIT_3 = 256'1011000000001011100101011110110111111010100111100101110111010001011101011000100010100000111001000000011001010101011111010010100011111000100100001010011011001100101101111000001001000010101101101101111011110010011100011000001111010101000100101100101001100000
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Parameter \INIT_4 = 256'0111001000101001001001100110011001101010110010101111111000110100111000101000101011000011011101100111011110101001101100111101101111100111010101100010011110110100110111001110111000100110110011010101110101001110011000000100010011100001000001011110010111101100
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Parameter \INIT_5 = 256'0100011100110001010111001100010110110000100101000011001101010000011110110001010100110100100101110011001011001101111101110101001100010100110110111101010011100000010001101000011101011011010111111010101110001110101101011101001000010001001001100100101001100001
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Parameter \INIT_6 = 256'1000100111111001110010100001001010111101101100000010100000011010000010111100011011101110101100101000000111111001000110111110000001011011100011110010011101101110100001011011101111101101011100111110100101111010001000100001010111110000111111100111101001101010
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Parameter \INIT_7 = 256'1100110100000000011001010001100101001010001011100111000111111001101101000111110001000101111010101011010101110101000110001110011100111111010110001011011111011010110110110000010111111110001111001011011100001001111101011010011101111110100101000111000100000010
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|
Parameter \INIT_8 = 256'1010101001111101001000010101100001111101001100111100100110111001011100000111011100111110111111001000000011011011010001101110110101001110011011111001100001010101100111001101001110101001011110110100010011111010111011100100000011101110000100001100010011111011
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|
Parameter \INIT_9 = 256'0101010010110001001011111011101010000110010111010101010000001001100000000110010000100001110100001101000000100010001100101101101100110101100000010001100010001100101010000110111100000110100011001001100101101011011101001101000001100110101011011101000001001111
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|
Parameter \INIT_A = 256'0111010110111100100001100110110010011110110111111111111010101100011010111000100010111000010110111100111111101110100011000100001101010000000011110001000111101011101111110010000010010101010001110010111111001011111011101100111001000110111111000100111111110101
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|
Parameter \INIT_B = 256'0111100000000000110101101010110110001111011010100110110010100100010000110001010100100111011010100011100001000101111001100011010010011010101000101001101010011001101111001101000010000001101111001110000111011001011010100011010101110100010101011101101111011011
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Parameter \INIT_C = 256'0100000100101111010000000000100100010001001111110101011111001101101111101101011101011111010000010111011000110101101000000000110001000010100110100111110110111010100100010001101110100110010010000111001110111110011111010010000100101001011011101111111101111110
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Parameter \INIT_D = 256'0101110011010111101111110101111111100000001111111000001001001000000101110101010001100111110101010111011000001010000110101010111011101010100001110000001001111011000111011101101111000001110111011010101110100100000011101000100111011100000110000110010100010101
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|
Parameter \INIT_E = 256'1010100010110011101000011111111111011010010001101101100110110000110001100101101000011010110011100101100010001001101001001111100110110011111111011000111110100000001101011000100010100111100111100010110011010001011111110100111110000100101111000101011011101110
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Parameter \INIT_F = 256'1000111110111111011101111100111001101010111011100001000100111111100101001100001101111000000111100011011100100001011111000110111111000000000100110010001110110010001000001100011001111011010010111100111001000011101110000111110010101111010001000110010011101011
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Generating RTLIL representation for module `$paramod$6b7654ce210c81e8e0bd83db57840a1ffc63b53d\SB_RAM40_4K'.
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2.26.37. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
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Parameter \WRITE_MODE = 3
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Parameter \READ_MODE = 3
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Parameter \INIT_0 = 256'0110110100001000010010011011111111011111110000000000100000110110110011100010100010000010011001101000100000110000010000100011110101111100011100101110011000101111111100000111111001011010100001000111110000100000110001100110111100000010101101010101101101010011
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Parameter \INIT_1 = 256'0111110011001010110000010111011110010111111010111111111010101111110011000101001100011110010101111101110000110111011101100111001100010110011011001110110011100101101010110010010001101111110001011010101111011000010001001101010001001000110001101001111100100011
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Parameter \INIT_2 = 256'1011100100111001100001011101001101000110000101100111010001000011100011010001011101011101110100001010110100110001100011101010001100001011010010111011001101110000110000110101101010110001111001011010110101110000110110110110111111000100001111100100011101001010
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Parameter \INIT_3 = 256'0101010100001000010010110000101010100000010110000110001000011101110000101100011101010000101101110010011011100110100001110100011000011001100100111010001111000010110110011000010101100111111001111001111011100000101100100100110001111101000001010011111110010101
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Parameter \INIT_4 = 256'0110111001001000111010100000101010000010111011100101101011110111001100101110110010111101110010011010011100101011111101010011101010111101100011011100001111001011001110000100100010101111000101111101000101011100000010010001111011100011010110101000001111001101
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Parameter \INIT_5 = 256'0111111000110111110100000111100000101110010100111110111110000011000011101000000110100100100111101010001101000001000101111010100000000111100101001011111001111000010000010010000110000010011101101001011100100010000111111110011111001101001110111101100110010101
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|
Parameter \INIT_6 = 256'1001111010101111010111100100001101111111000010100011101110101100110001001001011110110001101000001000111100001001100100011001010101111101000111111001010001110011100011010010001110111001000011001001110010000111110100000011000001011110110111110001001011111111
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|
Parameter \INIT_7 = 256'0011011100101010001101101100100101111100001110001001100010110111000000000100100110100010001100010000101001000110101100010001001011011110100100110110111100101011001101001001100010011011101011011011101101010001100000100000000110101110111101010101010101011110
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|
Parameter \INIT_8 = 256'1010011100011000100110000010000011001001101111110100010011010111000011001101010111100111010100111100010100011100011001111111010001010011001111101111100100101111001111000110000010010000100001101101101110011110110101111011110010011010101011110101000010010010
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|
Parameter \INIT_9 = 256'1111100101110101111001011011100001001011101101100010011011101010001100000111100110100110000100101111110001110010111101110111101101100111101011000100101011100001111010000000111011100101010101100001011111100010001010111010100100100000100001111111001000001101
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|
Parameter \INIT_A = 256'0110111110110111001010110100011100100000011011111011000000100010011110111000000001111011000000010111100100011011100101010101101010100001001111011001101010000010111100000101101110110011001101001101000101010101011110011000000000011100001100100100000011010110
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Parameter \INIT_B = 256'1101101101100010110100011000010110010000011000111110100011010101000110001111011100101100110010111011110110111001011010101001111000011010100110101010100011111101001100000100101010111110101100011010101000000000010001000100010111101111000000000010001001010011
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Parameter \INIT_C = 256'0011000110110010010000010000111001011010101011000110010011010000111101000001000010101101011011010001010110100111111001111110110101001110111101111011011010101101000101110101100010100011110000101100000001010000111101110001000001111011110000000110011000001011
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Parameter \INIT_D = 256'1100000011000011111100100101100110010001100100001100110101111101001010111110111111110010100011111111000001111001001100100001100001100011001110000011100001111110101111011111111010010011010110101010011000100001111110110101110110110000100001101011111011101111
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|
Parameter \INIT_E = 256'1111000111010011001111110110100001011011111111011101010001011011000101111110001101010001110100000001110011110111011101000110111100010001100011010110110011100000100011101011010111111011001111001010000110000110110100000111100110011111001000111100001100010100
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|
Parameter \INIT_F = 256'1110000101011101000000001101011011010101000001001101010001100110111010100110110000111111000001101111001111001011101100100100000100111100000100011011110110111110100010011000010100010011011000010000100010011101111100001100110100001000111110111010101100011111
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Generating RTLIL representation for module `$paramod$03877972951bada2593735348373f9d59049f3a8\SB_RAM40_4K'.
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2.26.38. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
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Parameter \WRITE_MODE = 3
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Parameter \READ_MODE = 3
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Parameter \INIT_0 = 256'1001000000100110111111000100011100100111111111011010000110111101111101011000000101100001001000110001001000001100110000100001001101110110011100100111111000010101111001011100100010110100011100010000100010111110110001100111010100001110100000000111110000100010
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Parameter \INIT_1 = 256'1101000000001101001101001111100111111100011000111101101100100010111010101000000011111001001110110111001001011100010001111100000001100001111011010101010111000100001111010010101001111001101111110110001110010001010100100101010001111011101010010111011101011001
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Parameter \INIT_2 = 256'0001011100110000010111110100110110111110101010010000100110110101100010111001111101111100101111101101101101001111011010111100110100110010010111010011010100110001011010110001000001111100111100101001001111111100000000100101110111001100000100010101000110100111
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Parameter \INIT_3 = 256'0100111000111101000111111010001000111110000001010101111110000011101100100110001101100110100000110100110110001001100111001101111110110110001001110101000100010100001000011100001011001101010100011101110101001101010110100000110000101101110110001000100010100111
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Parameter \INIT_4 = 256'1101001100000101010001110100011000100001000000010100111111111010101011000100101001011001110010101111011001000011111101010001111110101001011001010010001010110001011001010001100010101100011111101111010111010000000101100011110101000010000111001110001101000010
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|
Parameter \INIT_5 = 256'0001101101100001011101011011111011011101000011111001100010111000110000110001110000101010001011111100101101100101001001011100010011101001111111110010111001010111100100111110111001111101011000011010010111001110000010111001011000101011000010001010000111111111
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|
Parameter \INIT_6 = 256'1001010100011011001010111000010100101010100010101111010111110110111110010100001000101001111010110100001000111101010001010010111101010011001111110100100011001101101010000011100010001000001011010111110001110111101110001101010101110100101101000001010000111101
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|
Parameter \INIT_7 = 256'1010111001110101011110111111001000111100101110001101011100111101010001101001111011100000111101000011000011100000010011101100010010010110010001010011001010111000101111000010101001111000011011111101100011010011111000100101101111101001001010000010100001010011
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|
Parameter \INIT_8 = 256'0111101100000100111111001111000101111111100110101001101100111011101111010101101101111110010101011100000010100110101100011110001010010010110000000111001111000000001000110100000001101011110111001001101010110010011110000011111011000001001110001001100001001100
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|
Parameter \INIT_9 = 256'0110111110000100101000111101011100111101110001110011000100010000010110111100000010101001001100000000000001010110101011111100001110000110111010001111100010010100000000000111010000110111101100110100010110101111100111101110001110111100101001010110100010001000
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Parameter \INIT_A = 256'0000011011110000011100101101101101111011000000101100001000100001011011011001100101001110110001010011001100010001110001101111111001110001100100001111000010101110000110001111111001011010101001101001101110001100110111110000010110111010011110111101101000000100
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Parameter \INIT_B = 256'1110001001001000000111110101001101010100101000000100101001101011110000100100000000100100000111111010010001101110001001111000000011011011000010011000000000010011100001110000011001011000001010100100100110000011011011100111010001100010001000101000111110000010
|
|
Parameter \INIT_C = 256'1110101000000101010000010011110000000110101110111000010011100100100011111111000100011100111000110110100100011101111001010101111111111100111100110000101110000101100101110000001111111100101111111011100011101011000111011110010101010000101001111100110001001011
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Parameter \INIT_D = 256'0110011111110110101000010110001111011001010010100100100010101101110110100011101010100110111110101110111011010000111011011101001000101001001001011011000001010110001101011100101011111000100101110110010111101110111100011010110100010000110100011010111010111000
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|
Parameter \INIT_E = 256'0000110110010111111101010101100100010001101010100110010101101111111101100000110011010110110100111101010111111010000011011011011100101001000111000111111000100101101101000110110111101100101010011011111000110001100001001000000110101010010000001001011100010001
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|
Parameter \INIT_F = 256'1100101011001001111010101100010011011010010000101101111010101111101111110110101101001001111111110100011110110111001100101011010010100110110011011011000011001010111111010111110100001010111110011011111100100110011011111101111111010011101000011001101110010001
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Generating RTLIL representation for module `$paramod$627bd8159a11d7351b0cd002b08e7a85cfce8ce1\SB_RAM40_4K'.
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2.26.39. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
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Parameter \WRITE_MODE = 3
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|
Parameter \READ_MODE = 3
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|
Parameter \INIT_0 = 256'0111101100001100000100010111101000110010000111111000110000110100110001100001011111110001100001111101111111111000011011001000001111011111110101100110110100011000110001101111110011101000111110111110101000011001001100000000100001000100000001001110001110001101
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Parameter \INIT_1 = 256'0010100010000000000011100100110011000001101010010100011101110010100011100010101001100110110001111101000111110001001001100011100101001001001110110001011011011011100101110110011110001100011000011100011110001000001000001010100100011110011100000010011011011101
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Parameter \INIT_2 = 256'1101001001110101100111010000101001111110001011011110000101001001111111011101101100011001001000100110010010010100101000110100101111001100110101110110000110011011101011100000000011010011111110000101110101010110001101011001000111001000111001110101110110100100
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Parameter \INIT_3 = 256'0100100000011101100111010001110111001000010111101100000100011100010010010010010111110111000101111100000101000101010111010000100001110000011111011011000001000011010101000101101101101100101001000000001001010111100000100010000101001101100101010110100000100111
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|
Parameter \INIT_4 = 256'1010101001000011001010101011011101000010000000001110110110110100010010111101100000011000011001101101010010101010001001101001010010101101110100000000111110001011010011001010000101001101101000110000100100010111000100001000100111110010101101001110100001111111
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Parameter \INIT_5 = 256'0000111001100101101000111110011000100111011010101100000000010111111001001111110100000100110011000011111111111111000100100111110111100100100110011101111101101011011100110011001000000110111010000100001101010100010100111001000101010101000110100000000010110011
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Parameter \INIT_6 = 256'0000110010110000101110011111111100110000011101101100100011110010011111111000000100110000110000010000001011101111111011100101111011001111011101110110101111011001101101000110000001110111011101101001010110101001001111001111010110111111111101110000111101010001
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Parameter \INIT_7 = 256'1011000101111111001100110011110110101000000100111100111000000001100100000010011000001110100010010111010100101011110110111101011101010010011100011100000001101101011011000010101101001100000111101101101010101001011001010010000000110010100100111101000000010001
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|
Parameter \INIT_8 = 256'0110100000110111100010010101000000000001100111001001110101000001100110001111011101010101101101000000111000011010000001000011001100001000110111110001010100110111010100001010010001100001010001110000101110100101001100010101000011011000011001101100000101010111
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|
Parameter \INIT_9 = 256'1111000100000111101011100101001100011001010100010100110101100011000000001000100000010011110101101111000100110111000101001111111101111011010100010100001100011010001101000011010011101001101111011010001011000100110010100100111000011101001000010110011110011001
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Parameter \INIT_A = 256'0000111011110001011000001110101100011011100011010011100110000101001000010011111010001010000111010101100111110111101001111100000111101001100101100011101111000110101000111010101101111111010011110010001110110000000111001000101110010110110000111111011010100111
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|
Parameter \INIT_B = 256'0101011001101001111110011011101101000110011110001000001011000011000011111111011001110111100011011101000100101101100111010001100101001001101011001000010011111010011011000101111011001011011111100111010000001010010100101010110011000110001001110110001000001111
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Parameter \INIT_C = 256'1001110110110100100000001111001111000010000000010011001001011010101101010110010001001111111110000101101000110011001000010101001011001110011000010101001010001010000000101100000100010001111100010101001011111100110001010000111110001011111011010111101011001101
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Parameter \INIT_D = 256'0001011000110100001000001000011001000111010000110010100100100101010011111100100000100101101000111111000111111111010111000111110110111000001111010011001000100111011100101010011110110011010110011111011110010111000111000001110110011000000000110011101100001011
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Parameter \INIT_E = 256'0101101001001001000000100100110000111110010001000111000000111011110101110011010010100010110110101101101000101110111001010100110101101111000000000111001101000110001001110100110011101101000000000100000100000001010100100001101011010001010000000111010000111010
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Parameter \INIT_F = 256'0101001101011100101111001101111011001000011111001000110010101110110011110001010011101111000001101000010000001100010001011010110100010010100101110010111100000010110101010110011110110111100010011000101001101010100100100001100010000101101100111001101010111100
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Generating RTLIL representation for module `$paramod$354b058f540860ee145f5e13e91198841fbcc4de\SB_RAM40_4K'.
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2.26.40. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
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Parameter \WRITE_MODE = 3
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Parameter \READ_MODE = 3
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Parameter \INIT_0 = 256'1101010010100000010110000111011111110101101101000010010101101001111010000000110100001101100001011101001000010111110111111011000011111011000111011001010100000111011000011101110011101001001011010000010001001010000010111001101111101101000110011111101010000100
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Parameter \INIT_1 = 256'1001010100011111101011001010100010111100101101101100010101000110101111001000010101011100010100101011010001100000010001010101100001010111010111101011011001110000010001001011011101101101101110011000010010100100000001111001010000000011010111010100001100110001
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Parameter \INIT_2 = 256'0000010111011101111000010000010000010111100010110110110001001000111110001011111110111000101010001010001011100010001010010110000010000101110000100111110011100011110011001000010101010101000000010101110001110100000100101000001001101100000011110100000010011110
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Parameter \INIT_3 = 256'0101000110111010111110100001110110101000010100001101010010110001100011111111010111110100001111010001000110011111010011100010110010011111110000000000111001100001101010001111100000010100010100000111101010010010100110000001001010100100110100101010111100001011
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Parameter \INIT_4 = 256'1001100110010110010000110010001001000000110100001101110010101001001111101101010011000101011110000100000010100001100011010001111100100001100000111110001011100111001100000010110100011001001101100101000101010001100101101001011100011010101100011010100101000000
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Parameter \INIT_5 = 256'1110001110101101110000000100110000110110101100111001000000110110111011110101100010000100111000011101110011101110001000111110111010110001011111101010100000011001111011000010000111001011011111011000011100111010110101010110100011110010001100001110111101000000
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Parameter \INIT_6 = 256'0011110101111100101101001010001010001010101101001100111111001110010011111111110010011101110000101111011101110110110100111000011100100101111100111101101011110011101011000111011111001010001001000000110001101010000101011110110101011001100001110111110110100010
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Parameter \INIT_7 = 256'0110110001000101100111011101110110001001001101111000101100111001010011011011011011100000001101011001000110000010110111001100110111011111010000001010110110011001111010001001101110101101000000001011101000011010101000110011110011010011011100100011101110000010
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|
Parameter \INIT_8 = 256'1100011101111111100011101101011001000011100001000110010011010000100011011011001011001011110000001101001001000011110011001110000101110110001011110101000101100001100110111100000111100111001100000000000100101011110001001000100011011000011001010011100001010111
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Parameter \INIT_9 = 256'0011110011000011011110010001000101101101111110010001000111011001001100101101110011000101000111000000101001101000101110111010111000101000100010111111011101010111011011111101111101010000001111100000011010000001000110110001101011001011101100110001100000001001
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Parameter \INIT_A = 256'0110111110010100000110110111010111010100101101100101010010101101100000100111000001011010010100001011101001111001100101101101100111111010011011010001101000011101101011011110100000000100101110110010101110010100001110010000000010111101100100111001000111100001
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Parameter \INIT_B = 256'0111001001101100110100001001010000100100011100111110110011011001011010110111101000001010010001010110011101011100011001110111011110101111000010110001110100001100100000100010100010010111100111101000110110001000111101001101101100100111001001010000000100111110
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Parameter \INIT_C = 256'0101011010100010000010111100010001110000001101111010001110000000111000101100001001110010001111111001011000101000111100100011001100000000111001010010101100110101110101000100011011000000001010100100100111011000100100101111000001011011111111100100110001001111
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Parameter \INIT_D = 256'0110111101111110100101001011110111010011100110011010000010001000111010101000101001001111000010101100000001111111111111011001010100011010010100000001010000000000011000000101101101100010110100110011110011001111110000001101101011110110000001000011000010101101
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Parameter \INIT_E = 256'0101001001101010100001010100001110110100011101011000001101111000011110011111111111011110110111111010111101011101010110000011110000000010111111010000100011011101101000010101111011101000010000110010000011000100011110000110010010100111101000011011000100011001
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Parameter \INIT_F = 256'0000011000011000011000101101000011000001100111110001001101100001100001111011010111000100110011010011001000000101100110000000000000011010111001001101010011110010110001011110000100010000101000000110010011111011001011100001000001110110011110111000111011010010
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Generating RTLIL representation for module `$paramod$a83cd7853b7ce9d915e398a115a69ef26de5cd7c\SB_RAM40_4K'.
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2.26.41. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
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Parameter \WRITE_MODE = 3
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Parameter \READ_MODE = 3
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Parameter \INIT_0 = 256'0010010111000001000111000111001000000110100110101011101100010000010010111111101011000001000100001100111111111110110100011111100101001110011011101110011100110000101100101001110100001010101011111010001111011001011111000101000100011001111000110001011111100111
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Parameter \INIT_1 = 256'0011010110000010010101010001000100011000110001010111001110011010011111101110000111100111000001011101011010001110100111111101001101100111110110011110011101011011010011011101000110001011011000011000101011000100111111000011110100111001110101111000101110101101
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Parameter \INIT_2 = 256'1000111100011110000101001010101010010100111101010000001111110001100100100011100111101100100100001000010010001011111010000010111111000100010100111011101001010110011111111111000100100101001001011001100100110000001001110010101111011100010011010100110100100010
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Parameter \INIT_3 = 256'0111000000110111101010111100010111010110101101100010000011011000010101101100110001100100110110111011000010110101000000100100010111111100001010111000101010010110100101101101110000010011101000000110111100100110111000110101111000110010101100110110111110001000
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Parameter \INIT_4 = 256'0001000100001001100011100001110110111111101101000010010001001011111110011111001101011111010110111111011111010000011001100100010010000000001001111110010011101000011001101010111111100000110111110000000111100101011010111101100100000010101011111110110011100111
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Parameter \INIT_5 = 256'1110111001010101001010010101110100001001100110000110110101001101001111000110011010100011100011000100110110001001100111100000101101110101000100010001101100011010100101011101011011111111100110010111011000100111111111010001000111011111101100101000001001100011
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Parameter \INIT_6 = 256'0101000001000001001001000010111101010101011100110101010001000111000011110000011110111000100011000010111100111100010101010101010101000001011000011110011101110101001111101100000101110100010100001110101101010000100110101010010011011111001110000100100110010001
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|
Parameter \INIT_7 = 256'0101001001010001110101101101101010001101110100010111111101010110010001010100011000101010100100111100100111111110111000010000110100110101001101101011110110110101001101011001100111001100111111011010110110010111100001000001111001001000001110000011111110101111
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|
Parameter \INIT_8 = 256'0001110110110100110010001010110111100100010000000100100001010110001000111100010010011110100010111100100111001000111111010001001101101011011001000100010010000111011101000110100000101000111101111010111010000011100111101100011100001111101101010110100001110110
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Parameter \INIT_9 = 256'1010011100001110000001011111000011100111011111011011001110000100110100010100000010000111001101100100010110010001011000111100011101101100111110100011001001110101101100011110010010000001110101111100110100000100011011100011111101000110001001001000001110010001
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|
Parameter \INIT_A = 256'1001001100101111101101000101010100001001100001110011011010010110010110000000111010111110111110000111001001111010000100010100001001100101100011001100000001110110101001101110100110101100110000100100011110011100010100110100110101000100000000001111111110011100
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Parameter \INIT_B = 256'1000011010111000000001010110110001110010000100010111000010110111100111101001111001000000111010011000000010101010100110100001011100110110001011011000010000100100110001111000100110000011001111110101100111010010100000111101011000000100100000110011101101010011
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Parameter \INIT_C = 256'0111101101000000101100100001000011000001001000111111101011110100110100100010001100000011111001010110110001001000011001100001111001101100110100100100110001010001010000011001101000001001110110110101110000000010011110111100111101001101010001111011101011010001
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Parameter \INIT_D = 256'1000111110100110011011101001010011001011100001111001000101001001000010101100101101010110110000001100111100010000001010000011110010111010011011101101011100111100111101011000000001001100100010011011011111111100001001010001010111110101100101110101000100000010
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Parameter \INIT_E = 256'0000101111010100100010011000111010111000101010110111111101000100111111011111010100100010001100110111001100100110001010100001111100101101100001110010000001110100101100111000110111100010100101110010110010110100101101010001100000011111101000010101010001111011
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|
Parameter \INIT_F = 256'1111011110010011010011011101100111001011011111011010111101011111000011110100010001111100000000110111100101101111110011010111000001011101100111100100110100110011111101111110010100011000011000100011101011100100010010100101000000001001000010010011000001111110
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Generating RTLIL representation for module `$paramod$846dbb211a861374c6fe88754cd6d7b75e31c8d1\SB_RAM40_4K'.
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2.27. Printing statistics.
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=== memtest ===
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Number of wires: 44
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Number of wire bits: 345
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|
Number of public wires: 13
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|
Number of public wire bits: 23
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Number of memories: 0
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Number of memory bits: 0
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Number of processes: 0
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|
Number of cells: 61
|
|
SB_CARRY 9
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SB_DFF 12
|
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SB_GB 1
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SB_LUT4 23
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|
SB_RAM40_4K 16
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2.28. Executing CHECK pass (checking for obvious problems).
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|
checking module memtest..
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|
found and reported 0 problems.
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2.29. Executing JSON backend.
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Warnings: 9 unique messages, 9 total
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|
End of script. Logfile hash: 2ae37747b9
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Yosys 0.8+ (git sha1 UNKNOWN, x86_64-w64-mingw32-g++ 7.3-posix -O3 -DNDEBUG)
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Time spent: 2% 14x opt_expr (0 sec), 2% 14x opt_clean (0 sec), ...
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