1455 lines
128 KiB
Plaintext
1455 lines
128 KiB
Plaintext
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/----------------------------------------------------------------------------\
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| yosys -- Yosys Open SYnthesis Suite |
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| Copyright (C) 2012 - 2018 Clifford Wolf <clifford@clifford.at> |
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| Permission to use, copy, modify, and/or distribute this software for any |
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| purpose with or without fee is hereby granted, provided that the above |
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| copyright notice and this permission notice appear in all copies. |
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| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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\----------------------------------------------------------------------------/
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Yosys 0.8+ (git sha1 UNKNOWN, x86_64-w64-mingw32-g++ 7.3-posix -O3 -DNDEBUG)
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-- Parsing `memtest.v' using frontend `verilog' --
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1. Executing Verilog-2005 frontend.
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Parsing Verilog input from `memtest.v' to AST representation.
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Generating RTLIL representation for module `\memtest'.
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Warning: wire '\led_r' is assigned in a block at memtest.v:63.
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memtest.v:16: Warning: Identifier `\random_rom_dat_r' is implicitly declared.
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memtest.v:23: Warning: Identifier `\clk' is implicitly declared.
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Successfully finished Verilog frontend.
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-- Running command `synth_ice40 -top memtest -json .build/memtest.json' --
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2. Executing SYNTH_ICE40 pass.
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2.1. Executing Verilog-2005 frontend.
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Parsing Verilog input from `D:\Software\Icestorm\bin\../share/yosys/ice40/cells_sim.v' to AST representation.
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Generating RTLIL representation for module `\SB_IO'.
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Generating RTLIL representation for module `\SB_GB_IO'.
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Generating RTLIL representation for module `\SB_GB'.
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Generating RTLIL representation for module `\SB_LUT4'.
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Generating RTLIL representation for module `\SB_CARRY'.
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Generating RTLIL representation for module `\SB_DFF'.
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Generating RTLIL representation for module `\SB_DFFE'.
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Generating RTLIL representation for module `\SB_DFFSR'.
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Generating RTLIL representation for module `\SB_DFFR'.
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Generating RTLIL representation for module `\SB_DFFSS'.
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Generating RTLIL representation for module `\SB_DFFS'.
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Generating RTLIL representation for module `\SB_DFFESR'.
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Generating RTLIL representation for module `\SB_DFFER'.
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Generating RTLIL representation for module `\SB_DFFESS'.
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Generating RTLIL representation for module `\SB_DFFES'.
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Generating RTLIL representation for module `\SB_DFFN'.
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Generating RTLIL representation for module `\SB_DFFNE'.
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Generating RTLIL representation for module `\SB_DFFNSR'.
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Generating RTLIL representation for module `\SB_DFFNR'.
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Generating RTLIL representation for module `\SB_DFFNSS'.
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Generating RTLIL representation for module `\SB_DFFNS'.
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Generating RTLIL representation for module `\SB_DFFNESR'.
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Generating RTLIL representation for module `\SB_DFFNER'.
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Generating RTLIL representation for module `\SB_DFFNESS'.
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Generating RTLIL representation for module `\SB_DFFNES'.
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Generating RTLIL representation for module `\SB_RAM40_4K'.
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Generating RTLIL representation for module `\SB_RAM40_4KNR'.
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Generating RTLIL representation for module `\SB_RAM40_4KNW'.
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Generating RTLIL representation for module `\SB_RAM40_4KNRNW'.
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Generating RTLIL representation for module `\ICESTORM_LC'.
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Generating RTLIL representation for module `\SB_PLL40_CORE'.
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Generating RTLIL representation for module `\SB_PLL40_PAD'.
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Generating RTLIL representation for module `\SB_PLL40_2_PAD'.
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Generating RTLIL representation for module `\SB_PLL40_2F_CORE'.
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Generating RTLIL representation for module `\SB_PLL40_2F_PAD'.
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Generating RTLIL representation for module `\SB_WARMBOOT'.
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Generating RTLIL representation for module `\SB_MAC16'.
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Generating RTLIL representation for module `\SB_SPRAM256KA'.
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Generating RTLIL representation for module `\SB_HFOSC'.
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Generating RTLIL representation for module `\SB_LFOSC'.
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Generating RTLIL representation for module `\SB_RGBA_DRV'.
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Generating RTLIL representation for module `\SB_I2C'.
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Generating RTLIL representation for module `\SB_SPI'.
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Generating RTLIL representation for module `\SB_LEDDA_IP'.
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Generating RTLIL representation for module `\SB_FILTER_50NS'.
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Generating RTLIL representation for module `\SB_IO_I3C'.
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Generating RTLIL representation for module `\SB_IO_OD'.
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Successfully finished Verilog frontend.
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2.2. Executing HIERARCHY pass (managing design hierarchy).
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2.2.1. Analyzing design hierarchy..
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Top module: \memtest
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2.2.2. Analyzing design hierarchy..
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Top module: \memtest
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Removed 0 unused modules.
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2.3. Executing PROC pass (convert processes to netlists).
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2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Removing empty process `memtest.$proc$memtest.v:25$132'.
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Cleaned up 0 empty switches.
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2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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Removed a total of 0 dead cases.
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2.3.3. Executing PROC_INIT pass (extract init attributes).
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2.3.4. Executing PROC_ARST pass (detect async resets in processes).
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2.3.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
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Creating decoders for process `\memtest.$proc$memtest.v:29$34'.
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1/34: $0\led_r[0:0]
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2/34: $0$mem2bits$\mem$memtest.v:63$32[31:0]$66
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3/34: $0$mem2bits$\mem$memtest.v:62$31[31:0]$65
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4/34: $0$mem2bits$\mem$memtest.v:61$30[31:0]$64
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5/34: $0$mem2bits$\mem$memtest.v:60$29[31:0]$63
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6/34: $0$mem2bits$\mem$memtest.v:59$28[31:0]$62
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7/34: $0$mem2bits$\mem$memtest.v:58$27[31:0]$61
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8/34: $0$mem2bits$\mem$memtest.v:57$26[31:0]$60
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9/34: $0$mem2bits$\mem$memtest.v:56$25[31:0]$59
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10/34: $0$mem2bits$\mem$memtest.v:55$24[31:0]$58
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11/34: $0$mem2bits$\mem$memtest.v:54$23[31:0]$57
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12/34: $0$mem2bits$\mem$memtest.v:53$22[31:0]$56
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13/34: $0$mem2bits$\mem$memtest.v:52$21[31:0]$55
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14/34: $0$mem2bits$\mem$memtest.v:51$20[31:0]$54
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15/34: $0$mem2bits$\mem$memtest.v:50$19[31:0]$53
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16/34: $0$mem2bits$\mem$memtest.v:49$18[31:0]$52
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17/34: $0$mem2bits$\mem$memtest.v:48$17[31:0]$51
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18/34: $0$mem2bits$\mem$memtest.v:47$16[31:0]$50
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19/34: $0$mem2bits$\mem$memtest.v:46$15[31:0]$49
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20/34: $0$mem2bits$\mem$memtest.v:45$14[31:0]$48
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21/34: $0$mem2bits$\mem$memtest.v:44$13[31:0]$47
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22/34: $0$mem2bits$\mem$memtest.v:43$12[31:0]$46
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23/34: $0$mem2bits$\mem$memtest.v:42$11[31:0]$45
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24/34: $0$mem2bits$\mem$memtest.v:41$10[31:0]$44
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25/34: $0$mem2bits$\mem$memtest.v:40$9[31:0]$43
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26/34: $0$mem2bits$\mem$memtest.v:39$8[31:0]$42
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27/34: $0$mem2bits$\mem$memtest.v:38$7[31:0]$41
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28/34: $0$mem2bits$\mem$memtest.v:37$6[31:0]$40
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29/34: $0$mem2bits$\mem$memtest.v:36$5[31:0]$39
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30/34: $0$mem2bits$\mem$memtest.v:35$4[31:0]$38
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31/34: $0$mem2bits$\mem$memtest.v:34$3[31:0]$37
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32/34: $0$mem2bits$\mem$memtest.v:33$2[31:0]$36
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33/34: $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
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34/34: $0\memadr[10:0]
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2.3.6. Executing PROC_DLATCH pass (convert process syncs to latches).
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2.3.7. Executing PROC_DFF pass (convert process syncs to FFs).
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Creating register for signal `\memtest.\led_r' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$133' with positive edge clock.
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Creating register for signal `\memtest.\memadr' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$134' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:32$1' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$135' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:33$2' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$136' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:34$3' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$137' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:35$4' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$138' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:36$5' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$139' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:37$6' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$140' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:38$7' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$141' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:39$8' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$142' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:40$9' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$143' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:41$10' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$144' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:42$11' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$145' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:43$12' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$146' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:44$13' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$147' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:45$14' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$148' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:46$15' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$149' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:47$16' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$150' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:48$17' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$151' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:49$18' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$152' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:50$19' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$153' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:51$20' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$154' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:52$21' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$155' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:53$22' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$156' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:54$23' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$157' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:55$24' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$158' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:56$25' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$159' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:57$26' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$160' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:58$27' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$161' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:59$28' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$162' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:60$29' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$163' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:61$30' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$164' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:62$31' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$165' with positive edge clock.
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Creating register for signal `\memtest.$mem2bits$\mem$memtest.v:63$32' using process `\memtest.$proc$memtest.v:29$34'.
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created $dff cell `$procdff$166' with positive edge clock.
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2.3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Removing empty process `memtest.$proc$memtest.v:29$34'.
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Cleaned up 0 empty switches.
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2.4. Executing FLATTEN pass (flatten design).
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No more expansions possible.
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2.5. Executing TRIBUF pass.
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2.6. Executing DEMINOUT pass (demote inout ports to input or output).
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2.7. Executing SYNTH pass.
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2.7.1. Executing PROC pass (convert processes to netlists).
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2.7.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Cleaned up 0 empty switches.
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2.7.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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Removed a total of 0 dead cases.
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2.7.1.3. Executing PROC_INIT pass (extract init attributes).
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2.7.1.4. Executing PROC_ARST pass (detect async resets in processes).
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2.7.1.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
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2.7.1.6. Executing PROC_DLATCH pass (convert process syncs to latches).
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2.7.1.7. Executing PROC_DFF pass (convert process syncs to FFs).
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2.7.1.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Cleaned up 0 empty switches.
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2.7.2. Executing OPT_EXPR pass (perform const folding).
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2.7.3. Executing OPT_CLEAN pass (remove unused cells and wires).
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Finding unused cells or wires in module \memtest..
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removing unused `$memrd' cell `$memrd$\mem$memtest.v:16$33'.
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removing unused `$dff' cell `$procdff$135'.
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removing unused `$dff' cell `$procdff$136'.
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removing unused `$dff' cell `$procdff$137'.
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removing unused `$dff' cell `$procdff$138'.
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removing unused `$dff' cell `$procdff$139'.
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removing unused `$dff' cell `$procdff$140'.
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removing unused `$dff' cell `$procdff$141'.
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removing unused `$dff' cell `$procdff$142'.
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removing unused `$dff' cell `$procdff$143'.
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removing unused `$dff' cell `$procdff$144'.
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removing unused `$dff' cell `$procdff$145'.
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removing unused `$dff' cell `$procdff$146'.
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removing unused `$dff' cell `$procdff$147'.
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removing unused `$dff' cell `$procdff$148'.
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removing unused `$dff' cell `$procdff$149'.
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removing unused `$dff' cell `$procdff$150'.
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removing unused `$dff' cell `$procdff$151'.
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removing unused `$dff' cell `$procdff$152'.
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removing unused `$dff' cell `$procdff$153'.
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removing unused `$dff' cell `$procdff$154'.
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removing unused `$dff' cell `$procdff$155'.
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removing unused `$dff' cell `$procdff$156'.
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removing unused `$dff' cell `$procdff$157'.
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removing unused `$dff' cell `$procdff$158'.
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removing unused `$dff' cell `$procdff$159'.
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removing unused `$dff' cell `$procdff$160'.
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removing unused `$dff' cell `$procdff$161'.
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removing unused `$dff' cell `$procdff$162'.
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removing unused `$dff' cell `$procdff$163'.
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removing unused `$dff' cell `$procdff$164'.
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removing unused `$dff' cell `$procdff$165'.
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removing unused `$dff' cell `$procdff$166'.
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removing unused non-port wire \random_rom_dat_r.
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removed 67 unused temporary wires.
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Removed 33 unused cells and 67 unused wires.
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2.7.4. Executing CHECK pass (checking for obvious problems).
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checking module memtest..
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Warning: Wire memtest.\pmod_4 is used but has no driver.
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Warning: Wire memtest.\pmod_3 is used but has no driver.
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Warning: Wire memtest.\pmod_2 is used but has no driver.
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Warning: Wire memtest.\pmod_1 is used but has no driver.
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Warning: Wire memtest.\led_g is used but has no driver.
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Warning: Wire memtest.\led_b is used but has no driver.
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found and reported 6 problems.
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2.7.5. Executing OPT pass (performing simple optimizations).
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2.7.5.1. Executing OPT_EXPR pass (perform const folding).
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2.7.5.2. Executing OPT_MERGE pass (detect identical cells).
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Finding identical cells in module `\memtest'.
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Cell `$memrd$\mem$memtest.v:33$69' is identical to cell `$memrd$\mem$memtest.v:32$68'.
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Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:33$2[31:0]$36 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
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Removing $memrd cell `$memrd$\mem$memtest.v:33$69' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:34$70' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:34$3[31:0]$37 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:34$70' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:35$71' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:35$4[31:0]$38 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:35$71' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:36$72' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:36$5[31:0]$39 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:36$72' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:37$73' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:37$6[31:0]$40 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:37$73' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:38$74' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:38$7[31:0]$41 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:38$74' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:39$75' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:39$8[31:0]$42 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:39$75' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:40$76' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:40$9[31:0]$43 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:40$76' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:41$77' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:41$10[31:0]$44 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:41$77' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:42$78' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:42$11[31:0]$45 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:42$78' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:43$79' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:43$12[31:0]$46 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:43$79' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:44$80' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:44$13[31:0]$47 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:44$80' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:45$81' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:45$14[31:0]$48 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:45$81' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:46$82' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:46$15[31:0]$49 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:46$82' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:47$83' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:47$16[31:0]$50 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:47$83' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:48$84' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:48$17[31:0]$51 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:48$84' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:49$85' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:49$18[31:0]$52 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:49$85' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:50$86' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:50$19[31:0]$53 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:50$86' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:51$87' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:51$20[31:0]$54 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:51$87' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:52$88' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:52$21[31:0]$55 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:52$88' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:53$89' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:53$22[31:0]$56 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:53$89' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:54$90' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:54$23[31:0]$57 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:54$90' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:55$91' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:55$24[31:0]$58 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:55$91' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:56$92' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:56$25[31:0]$59 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:56$92' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:57$93' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:57$26[31:0]$60 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:57$93' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:58$94' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:58$27[31:0]$61 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:58$94' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:59$95' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:59$28[31:0]$62 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:59$95' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:60$96' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:60$29[31:0]$63 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:60$96' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:61$97' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:61$30[31:0]$64 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:61$97' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:62$98' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:62$31[31:0]$65 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:62$98' from module `\memtest'.
|
|
Cell `$memrd$\mem$memtest.v:63$99' is identical to cell `$memrd$\mem$memtest.v:32$68'.
|
|
Redirecting output \DATA: $0$mem2bits$\mem$memtest.v:63$32[31:0]$66 = $0$mem2bits$\mem$memtest.v:32$1[31:0]$35
|
|
Removing $memrd cell `$memrd$\mem$memtest.v:63$99' from module `\memtest'.
|
|
Removed a total of 31 cells.
|
|
|
|
2.7.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \memtest..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
2.7.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \memtest.
|
|
Performed a total of 0 changes.
|
|
|
|
2.7.5.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.7.5.6. Executing OPT_RMDFF pass (remove dff with constant values).
|
|
|
|
2.7.5.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
removed 31 unused temporary wires.
|
|
Removed 33 unused cells and 98 unused wires.
|
|
|
|
2.7.5.8. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
2.7.5.9. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.7.6. Executing WREDUCE pass (reducing word size of cells).
|
|
Removed top 23 address bits (of 32) from memory init port memtest.$meminit$\mem$memtest.v:26$131 (mem).
|
|
Removed top 2 address bits (of 11) from memory read port memtest.$memrd$\mem$memtest.v:32$68 (mem).
|
|
Removed top 31 bits (of 32) from port B of cell memtest.$add$memtest.v:30$67 ($add).
|
|
Removed top 21 bits (of 32) from port Y of cell memtest.$add$memtest.v:30$67 ($add).
|
|
|
|
2.7.7. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.7.7.1. Executing Verilog-2005 frontend.
|
|
Parsing Verilog input from `D:\Software\Icestorm\bin\../share/yosys/cmp2lut.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_lut_cmp_'.
|
|
Successfully finished Verilog frontend.
|
|
No more expansions possible.
|
|
|
|
2.7.8. Executing ALUMACC pass (create $alu and $macc cells).
|
|
Extracting $alu and $macc cells in module memtest:
|
|
creating $macc model for $add$memtest.v:30$67 ($add).
|
|
creating $alu model for $macc $add$memtest.v:30$67.
|
|
creating $alu cell for $add$memtest.v:30$67: $auto$alumacc.cc:474:replace_alu$167
|
|
created 1 $alu and 0 $macc cells.
|
|
|
|
2.7.9. Executing SHARE pass (SAT-based resource sharing).
|
|
|
|
2.7.10. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.7.10.1. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
2.7.10.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.7.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \memtest..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
2.7.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \memtest.
|
|
Performed a total of 0 changes.
|
|
|
|
2.7.10.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.7.10.6. Executing OPT_RMDFF pass (remove dff with constant values).
|
|
|
|
2.7.10.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
removed 1 unused temporary wires.
|
|
Removed 33 unused cells and 99 unused wires.
|
|
|
|
2.7.10.8. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
2.7.10.9. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.7.11. Executing FSM pass (extract and optimize FSM).
|
|
|
|
2.7.11.1. Executing FSM_DETECT pass (finding FSMs in design).
|
|
|
|
2.7.11.2. Executing FSM_EXTRACT pass (extracting FSM from design).
|
|
|
|
2.7.11.3. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
|
|
2.7.11.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
Removed 33 unused cells and 99 unused wires.
|
|
|
|
2.7.11.5. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
|
|
2.7.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
|
|
|
|
2.7.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
|
|
|
|
2.7.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
|
|
|
|
2.7.12. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.7.12.1. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
2.7.12.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.7.12.3. Executing OPT_RMDFF pass (remove dff with constant values).
|
|
|
|
2.7.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
Removed 33 unused cells and 99 unused wires.
|
|
|
|
2.7.12.5. Finished fast OPT passes.
|
|
|
|
2.7.13. Executing MEMORY pass.
|
|
|
|
2.7.13.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
|
|
Checking cell `$memrd$\mem$memtest.v:32$68' in module `\memtest': merged address $dff to cell.
|
|
|
|
2.7.13.2. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
Removed 33 unused cells and 99 unused wires.
|
|
|
|
2.7.13.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
|
|
|
|
2.7.13.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
Removed 33 unused cells and 99 unused wires.
|
|
|
|
2.7.13.5. Executing MEMORY_COLLECT pass (generating $mem cells).
|
|
Collecting $memrd, $memwr and $meminit for memory `\mem' in module `\memtest':
|
|
$meminit$\mem$memtest.v:26$131 ($meminit)
|
|
$memrd$\mem$memtest.v:32$68 ($memrd)
|
|
|
|
2.7.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
Removed 33 unused cells and 99 unused wires.
|
|
|
|
2.8. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).
|
|
Processing memtest.mem:
|
|
Properties: ports=1 bits=16384 rports=1 wports=0 dbits=32 abits=9 words=512
|
|
Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1):
|
|
Bram geometry: abits=8 dbits=16 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted.
|
|
Mapping to bram type $__ICE40_RAM4K_M0 (variant 1):
|
|
Read port #0 is in clock domain \clk.
|
|
Mapped to bram port A1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1):
|
|
Bram geometry: abits=9 dbits=8 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted.
|
|
Mapping to bram type $__ICE40_RAM4K_M123 (variant 1):
|
|
Read port #0 is in clock domain \clk.
|
|
Mapped to bram port A1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2):
|
|
Bram geometry: abits=10 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50
|
|
Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted.
|
|
Mapping to bram type $__ICE40_RAM4K_M123 (variant 2):
|
|
Read port #0 is in clock domain \clk.
|
|
Mapped to bram port A1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=50
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3):
|
|
Bram geometry: abits=11 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25
|
|
Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted.
|
|
Mapping to bram type $__ICE40_RAM4K_M123 (variant 3):
|
|
Read port #0 is in clock domain \clk.
|
|
Mapped to bram port A1.1.
|
|
Updated properties: dups=1 waste=3072 efficiency=25
|
|
Storing for later selection.
|
|
Selecting best of 4 rules:
|
|
Efficiency for rule 2.3: efficiency=25, cells=16, acells=1
|
|
Efficiency for rule 2.2: efficiency=50, cells=8, acells=1
|
|
Efficiency for rule 2.1: efficiency=100, cells=4, acells=1
|
|
Efficiency for rule 1.1: efficiency=100, cells=4, acells=2
|
|
Selected rule 2.1 with efficiency 100.
|
|
Mapping to bram type $__ICE40_RAM4K_M123 (variant 1):
|
|
Read port #0 is in clock domain \clk.
|
|
Mapped to bram port A1.1.
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <0 0 0>: mem.0.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <1 0 0>: mem.1.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <2 0 0>: mem.2.0.0
|
|
Creating $__ICE40_RAM4K_M123 cell at grid position <3 0 0>: mem.3.0.0
|
|
|
|
2.9. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.9.1. Executing Verilog-2005 frontend.
|
|
Parsing Verilog input from `D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$__ICE40_RAM4K'.
|
|
Generating RTLIL representation for module `\$__ICE40_RAM4K_M0'.
|
|
Generating RTLIL representation for module `\$__ICE40_RAM4K_M123'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.9.2. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K_M123'.
|
|
Parameter \CFG_ABITS = 9
|
|
Parameter \CFG_DBITS = 8
|
|
Parameter \CLKPOL2 = 1
|
|
Parameter \INIT = 4096'0011100111001010011111011100100000101001100100101011100010100100110010110010101101101011101000110100101110010011100011101101100000010100000010001110111010101101100111000001111011010000111011000001010010101010101000001000101001010001110011011111011110100101010101110101000011010110010001001100001101011001100011111001000010010000111111111101111000101011000000010000011111100010110111111111110110100000110111010000111011111000011110001001101000100011111000110110110001100110001001100101000101000110101011010111100000111000011011001000101001100110010100001010000100101100101010111101110110110010100001011001001100011100100110010000000000010011011110011000110010001000111100011110011000000101011110111010000011010010011011011110111111011000011001010110010101000001100010011110111111100111001010010001010011000111100001010010100011001001101100101110011100111011011110000110111100111101111010101001101101000010010111100110000100111100010100111010010000100111100101001000111110010010110101001010010101100101101001011010111111111100010101111000100100101011100100110100010111110110100011101110110010011110111101011100010100010010010101100011110011100111000110010010110100011010010111100001011010000101110111100111010010011110011010001010110100101101001111011101111000001100100001001000110001000111100111101110000111111010110010111011101010001010110011111010101111011010001111110111001110111001000100101011010010100011011011010101000111111110000011101111101001011101110101101010011011001000101111100010000001010111000011111100111010000111001101101101100111100010010000000111000110101010101110010100100110110011011001001110111100101011001110000111111000100110000111111010010001000100110111011010101010011111100100100010101000101101100110100010110001111101100011010101010001001110111011110000001110011110111110110011010000100010101100110101001011111111100101000100100001001111111100010010111100001001100101001110100110110101000001101010000001000000111100110001011000101100101100011000010001101011111010000011001100011010111011100101101100011001001010111111001100001011111100001110000110010111110110111010101110011100101001100100110010101000111101000001000110101101011011110111111001001110100001100001010011001010110000111001010111101101001010100000001011011101000111000100001110110000100001101000010001111110011011010101000111011010001100101010010001001110101110000111100110000100001001000001011100111010000010101111010100100101010011010010011100111010101110101010010001100011010100000000111010100010110100110100100101101110010010101010011010100101000110100101010010011111001011111000011101010000110000101010101101000011001110010110000010010110100000110110001100010011000010101100010000101111100000101101010000101111000100000001111111010110100101110010010111011000010110011001101001110110101100111001011101000100101101001101011000010011010101111001111110011011111110101001001000011011110111011100011110101100001010011001110010111001001101111000010001111001000111110000101111110001101111001101100010110100111100110011101001100100011100100101101010100111010111011100000100010010000100111000101101111001000010001111011001001011110110100110011111011010111111001100111111101111101110110000100110000100000110000110101111001000001001000101101111000010011100000100101100011101111011100000011100001111111110101111011101001101100111110110100000100111101100110011100011010111000001011010010001101110100101111000111011010010101011000011000101000000101001010110101001101000110100100101011010110000010111010110111101100101110111010111000010111110010101000100001000001010000111100001011010101010001100111110100011010010001110111100000101011010010001111010100101000110101111111011000100111110000010000110111000000010111000101011100100101000110011110011001101101010011010101000111001000000010101110001010111110111010101100110111000100111001011111101110000011111100111000111000001101000000010001011001000111011110110001000100011011000110011110110001111001111010110010010000111110011000111011011100111100101011000110011110110001110111010100100010101111010010010010100001000011110010011011000110001000000100010110010100000011111
|
|
Generating RTLIL representation for module `$paramod$1038d28725934469d8e7d2020b00f70a17d33ec3\$__ICE40_RAM4K_M123'.
|
|
|
|
2.9.3. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.0.0.0 using $paramod$1038d28725934469d8e7d2020b00f70a17d33ec3\$__ICE40_RAM4K_M123.
|
|
|
|
2.9.4. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K_M123'.
|
|
Parameter \CFG_ABITS = 9
|
|
Parameter \CFG_DBITS = 8
|
|
Parameter \CLKPOL2 = 1
|
|
Parameter \INIT = 4096'1010001101100111001100110111010110111001110111010011111000101001111000011101011101000001101010111111001110110000011001101010110110010101100010011001101101010100101011111111001111010100000101001000001011100010100010000000101100100100110000110010110001101011101101010101101111010001000000101011111001111110011000110001101100001011110101111101010110011100110110100000101001000100111011000010010101000100101110011100001000100011100100101100011001011000100111111110100110111001000111101001001101001000100110011001111110101100011100101000011111110000111001101001011100010000001011100010111101010010011101001101100001011000101000101111100011111111101011000111111010110111001001100100101010101001011001111011010101000001110111011101011011111001101000110110001111110110111001100110000011110011000111100100110000100000110011000101010101111111101010001100100000000101001101101001110111111000000001101000100101101010000000000011010100110100010100010010111011010001010110100110111101100100001000010110010110111101000110100100111001000101011011001011100001000011101001000111000010001001010011001110010110101110001011110101001001011010100110100011100111001010000101010001110001101111011111000101100110010111000100111110100011010010111101111000011100000101110000010001010100000010110011011000111110101110110100001101110001001110001010100011010111101010100010110001100111111000111100111000111110011111101111010110010101010010111010101111111110001111001111101001101101010011011111101001011100000011111011100000000101011110010000010010010010101100011110000010000100111100011000110011100000111100111101000000111000011100001101000100111001010011000011111100101110101001000000010101101010100011011001101010110100000110011101010101000100110000111011010110111001001001101011101001001101100001001011110100010100011110000001111000011100011100111111101110011111011111001001111010111101001011110000001101100100011010101010110010000110100100101011101001001001010111111010010000011011001010010111101010001101111010111101000010110110000101010010001001001000101100001010101001111010011111000000100000100000010011101100011011100000111111110001010101010110001010111111001101111100100101001101001111011000111101011111010011101100101100011101101000110000011000001001011111010110101111100100101001011010011010110110010001011110001100001110000010010100110111111010011101110010001110110001111100010001100000011110010100000101101011110110111110011001111101010100001100011110011011011010010101001100000011101100011001111101111101101111000101010000110110011110111101100000010010111110111101101001010110010010001111110100000110010101001000011111010110110011011110000010110000000101010010000010000110001100110000010101001001011001110100111001011100111001011101000010111010010111011111111011001001101011011000001111000110110010111010111101111000010100000100001111101101011110101111100111100001001001001010001011000000011111011100101110000100000000011111100000111011000111001101010111000101011010011001001010101111111101110111010110011100000010010110100101001001111011010010000111100011110010001000100000100100110000011101101011100111010000000111011100000100010001101100001111001001010101100100111001000011000111000101111110010111011001000101101000110111111101000000101000101000111001100111100001011111001111101111111111010110000011111001101111010110010100011100010011010100011101111010000110110100010011100110011100010001111111010110101101111001110100001010110100110011101010101110111010101110011111010111000101100000001100001010010010000000001011100001111100111011101111101101111001100000110011011110101001011000000010110110111001011001111010110001000010110111110101101101010011110001100110100101110001101000011011100011110001110000010000111110111001011100011011011011110001010010111101101111110110001000001111011111011101011111111110110010101110001111101010011101110001010001101110100001000100011111110111001010010100000101011101001100010001100111111100110110011011101010011111001011101101000000001100000111111010001000100111100111101000110010011100011111001110000000010101101000001010010111001000110101000101000001000101000000011011001101
|
|
Generating RTLIL representation for module `$paramod$5cc69d7ecd3300dc9cfc95fc048409f9c13e60f1\$__ICE40_RAM4K_M123'.
|
|
|
|
2.9.5. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.1.0.0 using $paramod$5cc69d7ecd3300dc9cfc95fc048409f9c13e60f1\$__ICE40_RAM4K_M123.
|
|
|
|
2.9.6. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K_M123'.
|
|
Parameter \CFG_ABITS = 9
|
|
Parameter \CFG_DBITS = 8
|
|
Parameter \CLKPOL2 = 1
|
|
Parameter \INIT = 4096'1111111010000010000010011011111010101010110101000011011001000000101101100011010100111000011001000111100100011010111000111110011110011011111001011101010011011010000000010101111111011110100111001011011011000000000010011010110111110000000100000011101011000100001011111110100011111110111000001010111111001011111010011110000010111110010010001100000100110011011110011000000110010110001101000111101110111010111101010101101010111111101010110100001011001111011101001010001010000101100001010011010000101110010101110111100101111010101100001000100111110100101011110011001010100110001011111100101110000000001010100001111101100100001011010100011010001101011011100000001000010101100011001101011000111010010111101001011010110010010001101011100001010101011010100010100000100001001110001100110110010000111110000101100010000010100011000000001011111111011101011010101111000011000001010111001011101111111010110011100001000011010100111111001001110100000110010101111010110011100101001101101110110100010100100001011001011101101111000000100011000101110110000000110000010001000111101001010101101100100001011010000001110110010100001100000101000000010001110011011010010011001011110010000011100101101001100100011110001110111100010000101100000011100100011100101110101001101000100101100111101000110110011100000100001010011000001110001100000001110101100110100010110001111111111100000110101100000101000001101000101111110100001001111001011110010000011101101101111000011001000011011010011100010010001110100111100101011000111001110000100101010000000111101100001110111101000111010110111010010111001011000000011010100101000000000101101010111101101011111011101000110010000111111111111101110111011111101100111100111001001010001110011000000010011101000010010111010101001000010110001101111110000110000011010000100011110100000110110101110001011000000010000001101011010001100000101001001111001101110010011011011011101000000111011000000110000111001011000110011010100000000011100101100011000100100010011100110000001111111100000010000111101110100110011000100011001010100101110011001001000101111011011100011111001110111100101111101010111010010101111101111010000100100010011100010111110001000011010001111000000010110100000000001110000101101110000101110110100001111100010101111010110011010001001101101100011111111000000101101000001100100000101111011001110000101000100001001011110000110001010100111000100101100101010011011000000000100011011001000001011010100101111100111011000111100110001000001000101100110101000010010001001001110101110000001100010111000100010111100010000101110011000010111011000111111000000101000000001101100010100101001101010110001000110101111000101100011101110111110000101011110010101110011110101001100111110111001011100011111000100111010111000000000100010000011100001010000100001001011010010111000100010110001100011111101001101110001100110000101101001001111110111000111111101011101010000111101010111100111011100001000111110111101110111111110010111001001101101100001101101101010010110011010010110010110100000111101000100110110110011101110111101001011001110100001101110110000101110100010000101101101100011111010101110011010111111011101101111010010001011010101001001101011010101111111101111101011001101101110001100010000000100110111010000110111101000001110010110110101111101101001000001010111011111100111100101101101101010011000000111000100100111000101110111110111001111011110011011001111011001100001010101001011011001011011010001110100010011110100110101111001101100000111000111000001101101101111010100110011110000111010101111100111111101101100110110011110101110110000111110101111001101101111100101101101001011111011000110110001011010000000011100001000000110111010111000111101101000001011010010001101000000011100010111000101110000110010011111011011110111010001000010111110011001100010101010000010001001101011001110110101100010111110101111111011010000111110010000101011110001010101111111100011001001000101000100101001111001011000001011110100111101110110001001101100111110000000000000110101111111111111101111100110100011011001001001011110110010010101111111001000111101001001100101011110101101111011100111100001101111011111111111100
|
|
Generating RTLIL representation for module `$paramod$236fa4834bad0cd01f824ed435d347351335f583\$__ICE40_RAM4K_M123'.
|
|
|
|
2.9.7. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.2.0.0 using $paramod$236fa4834bad0cd01f824ed435d347351335f583\$__ICE40_RAM4K_M123.
|
|
|
|
2.9.8. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K_M123'.
|
|
Parameter \CFG_ABITS = 9
|
|
Parameter \CFG_DBITS = 8
|
|
Parameter \CLKPOL2 = 1
|
|
Parameter \INIT = 4096'1011101010100111100101000111110011011010001011001000100001100100111010101101100001001000100001011100011100011011001100111010110110001001101100001101100110100111101000100100110010100100001100101100110010001010110010001110011011010110000100010010011001101000010101001110011000010111100010100100011101100001100011101110111101111111000100100010000010101011101010011101111100100111110111001000000101110100110100110101010001111100000000111110001110000111001010101111110111101000011110111001000110110110011100111010010011011101010100101001001011101000110100010100001100001100101000111011010110011100110100100000100011001001010010001111110011110010100101011011010000100111000101000000101100001011001100100010100111110000000010000010101110110011001111100011110000000110110011001101101000000111110101000010100110101010100000011001001000100100001100000101101100111000110111011101110010000100100001111110110101001000001011111110111010101101111101101111110001100001001100001010101001110010101010110100011000001000111000001011101100000010100101100111010000110110001000001001101101100000110101010011011011011011110101000011001111011111110100011111001001010011011100001110011111000000000100000010100001000110101111100010000011110011100010100111000011011011000100110001011111001100100100011000001011110001000001110011100000011010000100010011111010111011111010101111100010011000111101000000011001101000111100101010001011001100101101111110001000111001001110010110001011111110100100110011110010011000101000000101010000110111011101110110110100010001000011101001000111001111110111101000001000110011010010000101010110011101001100101000110000110111101010100101011101010101101001110000100001000001101010110010000101110100111010001110001100000100100110100101111011011000100001011000011111110110010011001001000001111101011011010111001011000000000101000011100110111101110110010111111010110111010000011101000100101011100111110110000000011101101111111000100011010000011001001100110000101110001111000010110100011100000011001010101111101001111110101100110011100010000011100100011001011110111011100010111001010001011100110110000001010010010001111111000000000111111101110001011100101100001000100110111101111110110101100111110100111000011010100100011001110000011110100100101011111001110111100110011111001001001111010111001100111001011111000010000110110110001100110000010100011100110000101110100110100101101110011010001111000010110101100110110101000011011110000001010010011000110100111101100010001101110111111111010100010010000000011110101000011000001010000000011000111101110100010001111101001011100000011100110001001111111100010101110010110100001000010111101100010101100000000110110011000110100001001010010111011100001011110111100110000010101110110101010111101000000101010111101010100010001000101001101100000011000010001110100011101011100011100010101001111001110101110000011100001001101000111110001011000001100101010010010101101111000100110010100010010010000111101001101110101010110000111000101010111010101110100000011000101111100010100000010011000101110100011001110000000111010110011110110010101100100000011110001110011010001101001111000111110001011101011001101110011101110110101010010100101110011100001101100001111000001010111110100101110101010000011100101101001111011101011101110100110101111011000011111100110010001011110101000100011001101111100001101111100001111010001100100111010000111110011111010011000010100010100110010000010010101000001111110010010011100001100101010100000000010011001001000100110011000010100011000011100101111111101001111101111001100101010111110111101100000111001111110100000010010010100101001000010011010110010111100001110000010010101011000110111001011000011000011111001010010101010000101000110011001101110101011110101100000000011111000101101111100011011001111000110010000000101110010001100100100000110101000001101010000011001100001101101001100110001010011110110110010110000101110001000111110011000011000101001001001010000010010101100100011111100011001010001101110111111110010010010110011111001011100100001011010100110001101011111110111010001010001111000100111010010101110100010101000100111010011101010110
|
|
Generating RTLIL representation for module `$paramod$446237c69b55ceadd7aa1adccf6ba73f79e82ced\$__ICE40_RAM4K_M123'.
|
|
|
|
2.9.9. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.3.0.0 using $paramod$446237c69b55ceadd7aa1adccf6ba73f79e82ced\$__ICE40_RAM4K_M123.
|
|
|
|
2.9.10. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K'.
|
|
Parameter \READ_MODE = 1
|
|
Parameter \WRITE_MODE = 1
|
|
Parameter \NEGCLK_R = 1'0
|
|
Parameter \NEGCLK_W = 1'0
|
|
Parameter \INIT_0 = 256'1101110000010001001101000000010110101111010110110100001001111100010111001110010010011010000100111001010101100100001110001100101110111000100001000000101101011110000100101101100111101000111110000011001010001010010000101100011100001100110010101010101101011111
|
|
Parameter \INIT_1 = 256'1011111110001010000111100110000000001000010010001100111100001110001001110100110111111011111010101100001001100000011100011100000001110000111111111011111000000111010110001111111100010001110000111000011000100001111111011000011110001011011100110100010101101001
|
|
Parameter \INIT_2 = 256'0111000001110101101001111010011110011100110011001001011011101110110000100101110000011000100010000001100110110111100000111001100101011101101101010011101110110110100101001111011000100110001101010010010011111101111110011111101000000001010111111100001111111000
|
|
Parameter \INIT_3 = 256'1111001110000110101011010100110101110000000000010011101101000110100110001001110111001110110000110011000010010110110011110101111101101101001000011010110111111110000010001100101000011110110101000010101010101100010111000010110001000111111010111000110001100000
|
|
Parameter \INIT_4 = 256'0011100110110110011001110000001010111011111110010001010011111101101111101001100101110011111100111011011100101000110011010111110010110001100100001001101010101100000010000100010000100011011111100000000110111110111001001110110010000101001011110101111001101000
|
|
Parameter \INIT_5 = 256'0110010100101111100001111110100011111001000101111010101010011001111001001001101010011110110111001100000110011101111000001111111011011001100011101110011011011000000011111010101100111010000010101100111010010011000101100100110010011110011000001101100100001110
|
|
Parameter \INIT_6 = 256'0101100011100010000001101001100000110011111011010101001000101100100101010010001010110010111011010010101101110001110101101111110000101000100101011000100011110111010111011110011001011111101101111011001011111001010000011111010110010100011000001000010010110101
|
|
Parameter \INIT_7 = 256'0110001001101111100101011100001100001000110010101101011100011110001100000110011111111011011011001001010010111101111110011110010011010111111110001111101001110111111101000111011101000111010011010010001001101001010010101011000010101001011010100001011011000111
|
|
Parameter \INIT_8 = 256'0010000101011101001000101110110101111101000000110100111111110000011100110100101011001101001100000101110100101111100001110110010010010100101110101001011100001100101100110110010011001100001101110011100101110011110110000010001110001001101011101010101110100101
|
|
Parameter \INIT_9 = 256'1010100110101111101110010011111101001001110101110100001101100101111101010110111011000001001001100000100111000101111100011101001111011010000111011110110001111010000011101100101101101011110100000110110111101011000011111011011111101000100110001001011111001011
|
|
Parameter \INIT_A = 256'0111101110010010100001001111010110000001100000001010101101010111111110010011110001000001001101110010111010011011110110010100000010110011010010010110100111100110101111011011111011100111100001010110100100110111001110000011001001100101000100101101000110010110
|
|
Parameter \INIT_B = 256'0000111011010101011010001011010110010001100010000111100000101100011001100100010110011000000001110000110111100001100111001000101011100011101101101100101000001101100101000010011110000011000011110000001011100100110100101001001000000100010101010100001000001110
|
|
Parameter \INIT_C = 256'1010111111100110110011010100010011100110101100100001010010101101101110111000000000101010110101001100011010001100010110010000111110111000010010110011110011110100001110000110110001001100001111000110011000010011001000010110110010011001101100100110101111010101
|
|
Parameter \INIT_D = 256'0011001100101011011100110100010010100111001011000110010000110000101100000101111001100111110000101001010111101011110000100001000010000110000100001010101110111111101001111110110000001000110011100101010100010011000001000011101110111000010110011010011010111111
|
|
Parameter \INIT_E = 256'0100001000110100000000011001000011111000111011001101100010100111110000111011000101010110111110011010011001000100101010001010010001010011011100011000100111011000100110000000010111000101100010000110001000010110111000001011001010111111011111101001110001110011
|
|
Parameter \INIT_F = 256'0000101011000111111101011000100001111110101000111110000110010101010110011100011111000110010011011100101111010000110011000011010010110000110110100100110011001010011111011001101010001001000010110110010011011011100101100101111110010101111111001011001011010100
|
|
Generating RTLIL representation for module `$paramod$2a13c6381633c10f050590d575e21dd5a29284a9\$__ICE40_RAM4K'.
|
|
|
|
2.9.11. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.0.0.0 using $paramod$2a13c6381633c10f050590d575e21dd5a29284a9\$__ICE40_RAM4K.
|
|
|
|
2.9.12. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K'.
|
|
Parameter \READ_MODE = 1
|
|
Parameter \WRITE_MODE = 1
|
|
Parameter \NEGCLK_R = 1'0
|
|
Parameter \NEGCLK_W = 1'0
|
|
Parameter \INIT_0 = 256'1100001001001000011000110111111010111101110001100000010100101100101101011000100101110111101011011100100000001010001110111001110011101010001001000100100110110111100001000010011100110001100000011001001000001001000010011011000000001000100111001101001011111001
|
|
Parameter \INIT_1 = 256'0000000100101011100000010111111101010011111100001110111010111001101010000011101110110111101110100101100000111010100111001011111101110101100011111011010000010100111101101100011000010111110110001100110111001111000110000000001010001101001000001001110111111100
|
|
Parameter \INIT_2 = 256'1001110001011011011011010111100010011001101001100101010100111100011111110111001101100010010000100000111101010001111111011011011100111001111111010111010111000111100011001110110111000010010111110110110001000011010110011111101000110001001000110100011111101100
|
|
Parameter \INIT_3 = 256'0001100101000011010111101110010100101001000010100100111110010101010110111011010011111011001100000101010110101001010000111110010000011011011100000011010011101000001101100101111000000101111110101011010110001010100110001000011101010100010101100011001111011000
|
|
Parameter \INIT_4 = 256'1011110110001001101111101010101010000101101010100100111010111000110000101000101000100110010111100010101111111101100001110110111101000101010111101111100111111100000101000000001001110010111110010111010001000110000110010110000010001000111001010011111011010100
|
|
Parameter \INIT_5 = 256'1001110110111101111001100000000111100111101100000011000011111100000111001001110100001011001000111111110111011001100101001100111100010111110000111111101110000000111011100101101110000101101011111100011011101110110111101111011001101100011101100011011101011001
|
|
Parameter \INIT_6 = 256'0000011110110101011111011011101000101010111001000010011011000010110101100011111000010111010010101011100111010101101001110101110011111111011111111101000100111110000000000111011111100001010001110101001100110110000100010000100111110000101100101101000110111010
|
|
Parameter \INIT_7 = 256'0111100111100100110111101001010100110000000010101001110100110101001010100001000010010000100101100111000010100101111110000110001110011001101111000001100011111110001100100000110100100011110110001001001111011101010010111001011110110100100110000001001101100110
|
|
Parameter \INIT_8 = 256'0011110011001001010000010000010001001110011101110101111100110101001101110001001101001001111110001010001001000011001101101100100100111000111010110111110001110001000011000000001101111100001001111101101011100010010000101100100000100100101110000111000000100011
|
|
Parameter \INIT_9 = 256'0111110001010001101111110100111001010111111010010111010010100001000011000001000011100100101001000111001000100010001111111111101111011000110001011110000010010000000000000010001101011111011010001000011111100111101010111101000001010001001110011101000010010011
|
|
Parameter \INIT_A = 256'1001100011110100001110111111100011011110001110110101100100101000011001011100110010011001110100110111110101111110110110100110001101100100010100111110001010100111111100100011110011111010110001111100110001011111001111010100101010111011001010001011100000101101
|
|
Parameter \INIT_B = 256'1001100011100000011111110101100110000000001111101011101100010000111010000011110111010011001111100101001001010001010111001010100001001101101010100010001100011001001011100010000011100010100101000010011110000101100010000001100110111010110000011011111010111111
|
|
Parameter \INIT_C = 256'0100100101100111001101000110000110011011100001111010000000001101010011010000101111000011010111011011010101111001011001111101000010010011101110101010110110010110100111111100011101010011111010001000001100001110011101011100010111010011110001101001001110111110
|
|
Parameter \INIT_D = 256'1000111000110011001001111001111111110110010000110101000101011000110010101111110001111010101111010111100000011010000101101000101000010101110010111011001000101011101101100110011111010011111001011111011010011100000101011101100100110001001000001111100010110101
|
|
Parameter \INIT_E = 256'1001011101110011100001011100011110000110110110100011011100110100110010001111101010101011010010101010011000110001010101110011000111000100010111011110100100001100110000011001010001000001110011100101100101100001101000010001111101001000111100000010110111001010
|
|
Parameter \INIT_F = 256'1100100101011111001010000010111000001010010010100010101100100111110011111000001111100111111000100000111111111101010110001001001110111001000100111110001001101110011101010101001011011001110111111010111000011011100011110001000001111101001111001000110111110011
|
|
Generating RTLIL representation for module `$paramod$de2bb95e5f9747ac2158f0970276228b3fb17e86\$__ICE40_RAM4K'.
|
|
|
|
2.9.13. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.1.0.0 using $paramod$de2bb95e5f9747ac2158f0970276228b3fb17e86\$__ICE40_RAM4K.
|
|
|
|
2.9.14. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K'.
|
|
Parameter \READ_MODE = 1
|
|
Parameter \WRITE_MODE = 1
|
|
Parameter \NEGCLK_R = 1'0
|
|
Parameter \NEGCLK_W = 1'0
|
|
Parameter \INIT_0 = 256'0001010101010000111110010010001111000101101001000011000011000101110100111110000110100100010001011111111111101011000000010101110001000011101011011010110011000111110100111001010011010101101101011000110111010010001011110001111101001101011101010111011111111000
|
|
Parameter \INIT_1 = 256'1110010001100111110101010101000010010100000100101100100011100110000001101001000100001101110100100100111110100000101100111111010011000011110111100111110011111000100100000101001111100011110101010000001010000000001010100001110011100101011111010111110111011101
|
|
Parameter \INIT_2 = 256'0001111111100101111011000010010010001001000111111101001011010000010100001001001110110011000000001001001000111010011100110011010010010101001101101100010110100011101111111101000100111101010101011011011001000000100101011111101001100000000100111001111101100010
|
|
Parameter \INIT_3 = 256'0010111100110110100011101101100100100010101000001101111000000001000000101000110110010111001100010101000000010111011011011001100010101011001111001100101110101001111011001000000010100101110000000110111111101010111011111110001010110110101100101111111111001111
|
|
Parameter \INIT_4 = 256'0111000101010110111001101001111000111111110000000011110100110001000111110111100011010111111101000111000111000001111011011000011111111001001101110011110000001011110101111011000101011100001101100111000101010101001011101101101101000100101110011111111100110100
|
|
Parameter \INIT_5 = 256'0101010010011101011011010101000011111001010010110101010001010010111100100010110001101100110000011001111001010010111011111011111011100000010101101100100011100001010101100110000101000110110111010000110110111110101000100101010010000111111010000010011110111100
|
|
Parameter \INIT_6 = 256'0100100000010100111111010011001010001001011110000110010100111110110001011111110011111011000001100000000011001110010101000101111111010010010101111010010011011011110011011001001110001101000010000010011111000010111010011000010111100010110001111110010101010110
|
|
Parameter \INIT_7 = 256'1111011110010001000101011010010100010011010101110100011111101101100101110110011000111000101100011100010001100110100110000101000100111110011011000111011101010101101101010101001100110100000101000111000101111010000111100010110010000010000011100001110011111110
|
|
Parameter \INIT_8 = 256'0011000001001111001001110001101011101111000011000111101100100000000101111100011000100110101111001101101101001011110100110111000111110110110010111001111000110101001100100000110100010111001111000010001110110111100110101011000000000100110100011110010100100011
|
|
Parameter \INIT_9 = 256'1011000011100011110101110100010111101010110101010111011011000101110001000100100010010101111001000100010101011000111111101111111000101011001000111101110110011111111001010100111101010101011100100110111101001001101011011011111011111000100011110001111011010001
|
|
Parameter \INIT_A = 256'0010110111111100000001000001110100010011011100101000000010100001101000110010100000011111100010000110011010101001100000100110100110011110010010010011010100101001100010111001010000100111001000110111110111001100000111001101010000001101000001110000101011000101
|
|
Parameter \INIT_B = 256'0010101010001000110110110100000011000100100100111010111100110001100111001010111000001111000110011101110000101100010110001011111110110101100111111101000000000100010011011101100001000110111111100011110101100100010010011110001101110101001111011000010011110110
|
|
Parameter \INIT_C = 256'0110101011001010100011101000110011111010011100110011001010001100100110101011101011001001110110110011010100001000101001011010101100111111001000011000100100011101110000000110001010010001011100100101101000100100010111001111100000110111011111100010101010010011
|
|
Parameter \INIT_D = 256'0000100011101110101011001000000110101110111111011010100001010000100110011011101011110100100011101011100111000011101110010000010110011110101010000010000011000000111100010100001100001010000110110110111011000011100101010101001011010110011110000001111101100001
|
|
Parameter \INIT_E = 256'1000011111001010101110010110011111100010001100011111001111001100000000010101011100100011101110111111011011101101100001111011000010011010011110011110010100000001010101011101011010001000101100111110111000000000010100100100000000001110110111011011010000110101
|
|
Parameter \INIT_F = 256'1111101111111000100101010101100001010100110101111000111011111101110011001100110111100110001100010001111101111001011101000100000010011010011010000100101101110010000110111101010100101001001000000111101110000011010101101000100010101100010110111010100000101010
|
|
Generating RTLIL representation for module `$paramod$cb6b0f67ab14626e9461e88b61012df03159e4cf\$__ICE40_RAM4K'.
|
|
|
|
2.9.15. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.2.0.0 using $paramod$cb6b0f67ab14626e9461e88b61012df03159e4cf\$__ICE40_RAM4K.
|
|
|
|
2.9.16. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K'.
|
|
Parameter \READ_MODE = 1
|
|
Parameter \WRITE_MODE = 1
|
|
Parameter \NEGCLK_R = 1'0
|
|
Parameter \NEGCLK_W = 1'0
|
|
Parameter \INIT_0 = 256'1100000110010100101101110101000001101101011000011010000011100101000110011010110100001011111001000101110111110110010101101110000001000100101001011101100010011010111111001100001110111011110110011010000110110001101010010000110101000100101111010011000100111100
|
|
Parameter \INIT_1 = 256'0110110010110111011011110001110010110001010000000001001101110000000110101001011111011010111100101010011110000011001110101110100110001110011010100010010000010011101101100001001000011101110111101000011110101110011010000101000101010011111101111101111010111010
|
|
Parameter \INIT_2 = 256'0010000000000011110111011000101100011100010101110110101001110001111010011101010010101101000011100000000000100100110101101001100000110110101110001110001010000101100100010010001010010100011011101010101001111000011100001010010110010110010000010110101111100010
|
|
Parameter \INIT_3 = 256'1000001100000111101100011110101110110111111010001001010100001000000110100100111001100101100000010110011101100011100101101010001101001010000111011101000011100100000110110011101110001000110011000010011100101111001001110011011110011001001111110100010011010000
|
|
Parameter \INIT_4 = 256'1100101100101011101011010000110100001010110001100000111110000010011111000001100111111111111111001100001101011111000111111110000111000011100100011001110101010001011101100111000000001011011110100111111101111011001010001010011000010010010001100001000110101100
|
|
Parameter \INIT_5 = 256'1111111001000010010100000110101101011011100000000101011111001001010101110001001001011010101011001100101011001110101111001001100010101011100001001100011010000000111111110111000001000001001011010110100010010100101110110001100110001000000010001011000011110000
|
|
Parameter \INIT_6 = 256'1011110100111011101100000000000101010010010001010001100011010101001101010011100111011011111110010000110100010001111111100101101010000101110111010010111100000100101001101101111100010011000010110000001101101011111001011111010010000011010001111101010000001001
|
|
Parameter \INIT_7 = 256'1101011000101101011010110110010000001111001110000101110100000001110101111000101100111101000100011110001101100111010010110111100111110011110011101110011000110001000011100101111010110111101010101111001101000010101111110100100000100110010011110111111001000001
|
|
Parameter \INIT_8 = 256'0111000010000101010010001110111011101101111011001100110111100110101010100011110010101110111101010110100001000110000010100001000011011000100110010111101100001001110010011101101000100000001111010001000111000001111111000101000011001110110110100100000000001001
|
|
Parameter \INIT_9 = 256'1011011111001001010100010011111110100010001101010000100011000011110011001000110111010100000001101101001000001001010010010011000100001110000100010011011011011111000010111000010110100110111000101110001110100100100000010111010011000001011011111110110011100110
|
|
Parameter \INIT_A = 256'1001011101100011110010100010010001001101011011110001001100110001010101001100101000000001100110110001111101001100010011001000011010101110000001000100000111000101000010001000111110001010010010100101111011101000010111101110010101000000011111001010010011100100
|
|
Parameter \INIT_B = 256'1110001010100011011100100101100010010010010111011111110110000001101100110101001001100101000110100000010010100001100111010100111110001011001100111100001010100000101101100101100001010000100101001110000010010010011001001001000111111011111100001010111001011101
|
|
Parameter \INIT_C = 256'1100000101000010011110110010010111110011010010100110001001110001011110111111010101010101000110111010100100001110100000000010101101011100110011001010101111100010101011001100000000101010100111101000011101010011110110110010100100101011010111111001100001100101
|
|
Parameter \INIT_D = 256'0010011000100001111011010011110000000111001011111000000010011001001000010111101001111000000001101101010011101001111011001011101101101111111010110100011000001101010110000000010011011001100111101001110011010011101100101010111100011101011010101010001110110000
|
|
Parameter \INIT_E = 256'1101000110010110100111110101000110100111110000101001110001101110100110000001110000110101101000001001110101100100000110100100110011110101111000011101000111011100101101001001010111111000011010011010011101111001000101110000011100001101011010010011110111010000
|
|
Parameter \INIT_F = 256'1001101111011100110111000111111010000110011101000011101110100001101101111000110100011100101000001001000110000100001110000011010111111101100010001010001010010101011101011001010110000001001101111010010001111010000001101000111000011110010111111001110111110110
|
|
Generating RTLIL representation for module `$paramod$d46a79f9db485f5e0ae25ea95384f4a64dd34959\$__ICE40_RAM4K'.
|
|
|
|
2.9.17. Continuing TECHMAP pass.
|
|
Mapping memtest.mem.3.0.0 using $paramod$d46a79f9db485f5e0ae25ea95384f4a64dd34959\$__ICE40_RAM4K.
|
|
No more expansions possible.
|
|
|
|
2.10. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.10.1. Executing OPT_EXPR pass (perform const folding).
|
|
Setting undriven signal in memtest to undef: $techmap189\mem.3.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap188\mem.2.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap187\mem.1.0.0.MASK
|
|
Setting undriven signal in memtest to undef: $techmap186\mem.0.0.0.MASK
|
|
Setting undriven signal in memtest to undef: \pmod_1
|
|
Setting undriven signal in memtest to undef: \pmod_2
|
|
Setting undriven signal in memtest to undef: \pmod_4
|
|
Setting undriven signal in memtest to undef: $techmap179\mem.0.0.0.B1DATA_16 [13]
|
|
Setting undriven signal in memtest to undef: $techmap179\mem.0.0.0.B1DATA_16 [15]
|
|
Setting undriven signal in memtest to undef: $techmap179\mem.0.0.0.B1DATA_16 [7]
|
|
Setting undriven signal in memtest to undef: $techmap179\mem.0.0.0.B1DATA_16 [11]
|
|
Setting undriven signal in memtest to undef: \led_b
|
|
Setting undriven signal in memtest to undef: \led_g
|
|
Setting undriven signal in memtest to undef: $techmap181\mem.1.0.0.B1DATA_16 [3]
|
|
Setting undriven signal in memtest to undef: $techmap181\mem.1.0.0.B1DATA_16 [5]
|
|
Setting undriven signal in memtest to undef: $techmap181\mem.1.0.0.B1DATA_16 [7]
|
|
Setting undriven signal in memtest to undef: $techmap181\mem.1.0.0.B1DATA_16 [9]
|
|
Setting undriven signal in memtest to undef: $techmap181\mem.1.0.0.B1DATA_16 [11]
|
|
Setting undriven signal in memtest to undef: $techmap181\mem.1.0.0.B1DATA_16 [13]
|
|
Setting undriven signal in memtest to undef: $techmap181\mem.1.0.0.B1DATA_16 [15]
|
|
Setting undriven signal in memtest to undef: $techmap179\mem.0.0.0.B1DATA_16 [9]
|
|
Setting undriven signal in memtest to undef: $techmap185\mem.3.0.0.B1DATA_16 [1]
|
|
Setting undriven signal in memtest to undef: $techmap185\mem.3.0.0.B1DATA_16 [3]
|
|
Setting undriven signal in memtest to undef: $techmap185\mem.3.0.0.B1DATA_16 [5]
|
|
Setting undriven signal in memtest to undef: $techmap185\mem.3.0.0.B1DATA_16 [7]
|
|
Setting undriven signal in memtest to undef: $techmap185\mem.3.0.0.B1DATA_16 [9]
|
|
Setting undriven signal in memtest to undef: $techmap185\mem.3.0.0.B1DATA_16 [11]
|
|
Setting undriven signal in memtest to undef: $techmap185\mem.3.0.0.B1DATA_16 [13]
|
|
Setting undriven signal in memtest to undef: $techmap185\mem.3.0.0.B1DATA_16 [15]
|
|
Setting undriven signal in memtest to undef: $techmap179\mem.0.0.0.B1DATA_16 [5]
|
|
Setting undriven signal in memtest to undef: $techmap183\mem.2.0.0.B1DATA_16 [1]
|
|
Setting undriven signal in memtest to undef: $techmap183\mem.2.0.0.B1DATA_16 [3]
|
|
Setting undriven signal in memtest to undef: $techmap183\mem.2.0.0.B1DATA_16 [5]
|
|
Setting undriven signal in memtest to undef: $techmap183\mem.2.0.0.B1DATA_16 [7]
|
|
Setting undriven signal in memtest to undef: $techmap183\mem.2.0.0.B1DATA_16 [9]
|
|
Setting undriven signal in memtest to undef: $techmap183\mem.2.0.0.B1DATA_16 [11]
|
|
Setting undriven signal in memtest to undef: $techmap183\mem.2.0.0.B1DATA_16 [13]
|
|
Setting undriven signal in memtest to undef: $techmap183\mem.2.0.0.B1DATA_16 [15]
|
|
Setting undriven signal in memtest to undef: \pmod_3
|
|
Setting undriven signal in memtest to undef: $techmap179\mem.0.0.0.B1DATA_16 [1]
|
|
Setting undriven signal in memtest to undef: $techmap179\mem.0.0.0.B1DATA_16 [3]
|
|
Setting undriven signal in memtest to undef: $techmap181\mem.1.0.0.B1DATA_16 [1]
|
|
Replacing $reduce_or cell `$techmap$techmap185\mem.3.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$184' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap185\mem.3.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$184_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap183\mem.2.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$182' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap183\mem.2.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$182_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap179\mem.0.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$178' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap179\mem.0.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$178_Y = 1'0'.
|
|
Replacing $reduce_or cell `$techmap$techmap181\mem.1.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$180' (unary_buffer) in module `\memtest' with constant driver `$techmap$techmap181\mem.1.0.0.$reduce_or$D:\Software\Icestorm\bin\../share/yosys/ice40/brams_map.v:307$180_Y = 1'0'.
|
|
|
|
2.10.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.10.3. Executing OPT_RMDFF pass (remove dff with constant values).
|
|
|
|
2.10.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
removed 96 unused temporary wires.
|
|
Removed 33 unused cells and 195 unused wires.
|
|
|
|
2.10.5. Finished fast OPT passes.
|
|
|
|
2.11. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).
|
|
|
|
2.12. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.12.1. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
2.12.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \memtest..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
2.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \memtest.
|
|
Performed a total of 0 changes.
|
|
|
|
2.12.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.12.6. Executing OPT_RMDFF pass (remove dff with constant values).
|
|
|
|
2.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
Removed 33 unused cells and 195 unused wires.
|
|
|
|
2.12.8. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
2.12.9. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.13. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.13.1. Executing Verilog-2005 frontend.
|
|
Parsing Verilog input from `D:\Software\Icestorm\bin\../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `\$__div_mod_u'.
|
|
Generating RTLIL representation for module `\$__div_mod'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_pmux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.13.2. Executing Verilog-2005 frontend.
|
|
Parsing Verilog input from `D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_ice40_alu'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.13.3. Executing AST frontend in derive mode using pre-parsed AST for module `\_80_ice40_alu'.
|
|
Parameter \A_SIGNED = 0
|
|
Parameter \B_SIGNED = 0
|
|
Parameter \A_WIDTH = 1
|
|
Parameter \B_WIDTH = 11
|
|
Parameter \Y_WIDTH = 11
|
|
Generating RTLIL representation for module `$paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=11\Y_WIDTH=11'.
|
|
|
|
2.13.4. Continuing TECHMAP pass.
|
|
Mapping memtest.$auto$alumacc.cc:474:replace_alu$167 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=11\Y_WIDTH=11.
|
|
Mapping memtest.$xor$memtest.v:33$100 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:34$101 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:35$102 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:36$103 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:37$104 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:38$105 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:39$106 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:40$107 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:41$108 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:42$109 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:43$110 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:44$111 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:45$112 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:46$113 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:47$114 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:48$115 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:49$116 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:50$117 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:51$118 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:52$119 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:53$120 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:54$121 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:55$122 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:56$123 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:57$124 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:58$125 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:59$126 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:60$127 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:61$128 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:62$129 ($xor) with simplemap.
|
|
Mapping memtest.$xor$memtest.v:63$130 ($xor) with simplemap.
|
|
Mapping memtest.$procdff$133 ($dff) with simplemap.
|
|
Mapping memtest.$procdff$134 ($dff) with simplemap.
|
|
Mapping memtest.$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:68$239 ($xor) with simplemap.
|
|
Mapping memtest.$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:42$238 ($mux) with simplemap.
|
|
Mapping memtest.$techmap$auto$alumacc.cc:474:replace_alu$167.$not$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:42$237 ($not) with simplemap.
|
|
Mapping memtest.$auto$alumacc.cc:474:replace_alu$167.B_conv ($pos) with simplemap.
|
|
Mapping memtest.$auto$alumacc.cc:474:replace_alu$167.A_conv ($pos) with simplemap.
|
|
No more expansions possible.
|
|
|
|
2.14. Executing ICE40_OPT pass (performing simple optimizations).
|
|
|
|
2.14.1. Running ICE40 specific optimizations.
|
|
|
|
2.14.2. Executing OPT_EXPR pass (perform const folding).
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$294' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:42$238_Y [0] = \memadr [0]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$295' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:42$238_Y [1] = \memadr [1]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$284' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:68$239_Y [1] = \memadr [1]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$296' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:42$238_Y [2] = \memadr [2]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$285' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:68$239_Y [2] = \memadr [2]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$297' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:42$238_Y [3] = \memadr [3]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$286' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:68$239_Y [3] = \memadr [3]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$298' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:42$238_Y [4] = \memadr [4]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$287' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:68$239_Y [4] = \memadr [4]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$299' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:42$238_Y [5] = \memadr [5]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$288' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:68$239_Y [5] = \memadr [5]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$300' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:42$238_Y [6] = \memadr [6]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$289' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:68$239_Y [6] = \memadr [6]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$301' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:42$238_Y [7] = \memadr [7]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$290' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:68$239_Y [7] = \memadr [7]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$302' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:42$238_Y [8] = \memadr [8]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$291' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:68$239_Y [8] = \memadr [8]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$303' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:42$238_Y [9] = \memadr [9]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$292' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:68$239_Y [9] = \memadr [9]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$304' (??0) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$ternary$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:42$238_Y [10] = \memadr [10]'.
|
|
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$293' (0?) in module `\memtest' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$167.$xor$D:\Software\Icestorm\bin\../share/yosys/ice40/arith_map.v:68$239_Y [10] = \memadr [10]'.
|
|
|
|
2.14.3. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.14.4. Executing OPT_RMDFF pass (remove dff with constant values).
|
|
|
|
2.14.5. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$283'.
|
|
removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$167.slice[10].adder'.
|
|
removing unused `\SB_CARRY' cell `$auto$alumacc.cc:474:replace_alu$167.slice[10].carry'.
|
|
removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$167.slice[9].adder'.
|
|
removing unused `\SB_CARRY' cell `$auto$alumacc.cc:474:replace_alu$167.slice[9].carry'.
|
|
removing unused `\SB_CARRY' cell `$auto$alumacc.cc:474:replace_alu$167.slice[8].carry'.
|
|
removing unused `$_DFF_P_' cell `$auto$simplemap.cc:420:simplemap_dff$281'.
|
|
removing unused `$_DFF_P_' cell `$auto$simplemap.cc:420:simplemap_dff$282'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$305'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$306'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$307'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$308'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$309'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$310'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$311'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$312'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$313'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$314'.
|
|
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$315'.
|
|
removed 17 unused temporary wires.
|
|
Removed 52 unused cells and 212 unused wires.
|
|
|
|
2.14.6. Rerunning OPT passes. (Removed registers in this run.)
|
|
|
|
2.14.7. Running ICE40 specific optimizations.
|
|
Optimized away SB_CARRY cell memtest.$auto$alumacc.cc:474:replace_alu$167.slice[0].carry: CO=\memadr [0]
|
|
Mapping SB_LUT4 cell memtest.$auto$alumacc.cc:474:replace_alu$167.slice[1].adder back to logic.
|
|
|
|
2.14.8. Executing OPT_EXPR pass (perform const folding).
|
|
Setting undriven signal in memtest to undef: \memadr [10]
|
|
Setting undriven signal in memtest to undef: \memadr [9]
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$320' (010) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$316 [3] = 1'0'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$319' (100) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$316 [2] = 1'1'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$327' (100) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$325 [1] = 1'1'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$318' (100) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$316 [1] = 1'1'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$317' (010) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$316 [0] = 1'0'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$326' (010) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$325 [0] = 1'0'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$331' (01?) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$330 [0] = \memadr [1]'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$324' (100) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$316 [7] = 1'1'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$323' (010) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$316 [6] = 1'0'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$329' (010) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$325 [3] = 1'0'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$322' (010) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$316 [5] = 1'0'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$321' (100) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$316 [4] = 1'1'.
|
|
Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$328' (100) in module `\memtest' with constant driver `$auto$simplemap.cc:309:simplemap_lut$325 [2] = 1'1'.
|
|
|
|
2.14.9. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.14.10. Executing OPT_RMDFF pass (remove dff with constant values).
|
|
|
|
2.14.11. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
removed 3 unused temporary wires.
|
|
Removed 52 unused cells and 215 unused wires.
|
|
|
|
2.14.12. Rerunning OPT passes. (Removed registers in this run.)
|
|
|
|
2.14.13. Running ICE40 specific optimizations.
|
|
|
|
2.14.14. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
2.14.15. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.14.16. Executing OPT_RMDFF pass (remove dff with constant values).
|
|
|
|
2.14.17. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
Removed 52 unused cells and 215 unused wires.
|
|
|
|
2.14.18. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.15. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs).
|
|
|
|
2.16. Executing DFF2DFFE pass (transform $dff to $dffe where applicable).
|
|
Selected cell types for direct conversion:
|
|
$_DFF_PP1_ -> $__DFFE_PP1
|
|
$_DFF_PP0_ -> $__DFFE_PP0
|
|
$_DFF_PN1_ -> $__DFFE_PN1
|
|
$_DFF_PN0_ -> $__DFFE_PN0
|
|
$_DFF_NP1_ -> $__DFFE_NP1
|
|
$_DFF_NP0_ -> $__DFFE_NP0
|
|
$_DFF_NN1_ -> $__DFFE_NN1
|
|
$_DFF_NN0_ -> $__DFFE_NN0
|
|
$_DFF_N_ -> $_DFFE_NP_
|
|
$_DFF_P_ -> $_DFFE_PP_
|
|
Transforming FF to FF+Enable cells in module memtest:
|
|
|
|
2.17. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.17.1. Executing Verilog-2005 frontend.
|
|
Parsing Verilog input from `D:\Software\Icestorm\bin\../share/yosys/ice40/cells_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DFF_N_'.
|
|
Generating RTLIL representation for module `\$_DFF_P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `\$_DFF_NN0_'.
|
|
Generating RTLIL representation for module `\$_DFF_NN1_'.
|
|
Generating RTLIL representation for module `\$_DFF_PN0_'.
|
|
Generating RTLIL representation for module `\$_DFF_PN1_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `\$__DFFE_NN0'.
|
|
Generating RTLIL representation for module `\$__DFFE_NN1'.
|
|
Generating RTLIL representation for module `\$__DFFE_PN0'.
|
|
Generating RTLIL representation for module `\$__DFFE_PN1'.
|
|
Generating RTLIL representation for module `\$__DFFE_NP0'.
|
|
Generating RTLIL representation for module `\$__DFFE_NP1'.
|
|
Generating RTLIL representation for module `\$__DFFE_PP0'.
|
|
Generating RTLIL representation for module `\$__DFFE_PP1'.
|
|
Successfully finished Verilog frontend.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$271 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$272 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$273 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$274 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$275 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$276 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$277 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$278 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$279 using \$_DFF_P_.
|
|
Mapping memtest.$auto$simplemap.cc:420:simplemap_dff$280 using \$_DFF_P_.
|
|
No more expansions possible.
|
|
|
|
2.18. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
2.19. Executing SIMPLEMAP pass (map simple cells to gate primitives).
|
|
|
|
2.20. Executing ICE40_FFINIT pass (implement FF init values).
|
|
Handling FF init values in memtest.
|
|
|
|
2.21. Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells).
|
|
Merging set/reset $_MUX_ cells into SB_FFs in memtest.
|
|
|
|
2.22. Executing ICE40_OPT pass (performing simple optimizations).
|
|
|
|
2.22.1. Running ICE40 specific optimizations.
|
|
|
|
2.22.2. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
2.22.3. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memtest'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.22.4. Executing OPT_RMDFF pass (remove dff with constant values).
|
|
|
|
2.22.5. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memtest..
|
|
removed 30 unused temporary wires.
|
|
Removed 52 unused cells and 245 unused wires.
|
|
|
|
2.22.6. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.23. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.23.1. Executing Verilog-2005 frontend.
|
|
Parsing Verilog input from `D:\Software\Icestorm\bin\../share/yosys/ice40/latches_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DLATCH_N_'.
|
|
Generating RTLIL representation for module `\$_DLATCH_P_'.
|
|
Successfully finished Verilog frontend.
|
|
No more expansions possible.
|
|
|
|
2.24. Executing ABC pass (technology mapping using ABC).
|
|
|
|
2.24.1. Extracting gate netlist of module `\memtest' to `<abc-temp-dir>/input.blif'..
|
|
Extracted 33 gates and 67 wires to a netlist network with 34 inputs and 2 outputs.
|
|
|
|
2.24.1.1. Executing ABC.
|
|
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
|
|
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
|
|
ABC:
|
|
ABC: + read_blif <abc-temp-dir>/input.blif
|
|
ABC: + read_lut <abc-temp-dir>/lutdefs.txt
|
|
ABC: + strash
|
|
ABC: + ifraig
|
|
ABC: + scorr
|
|
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
|
|
ABC: + dc2
|
|
ABC: + dretime
|
|
ABC: + strash
|
|
ABC: + dch -f
|
|
ABC: + if
|
|
ABC: + mfs2
|
|
ABC: + lutpack -S 1
|
|
ABC: + write_blif <abc-temp-dir>/output.blif
|
|
|
|
2.24.1.2. Re-integrating ABC results.
|
|
ABC RESULTS: $lut cells: 26
|
|
ABC RESULTS: internal signals: 31
|
|
ABC RESULTS: input signals: 34
|
|
ABC RESULTS: output signals: 2
|
|
Removing temp directory.
|
|
Removed 0 unused cells and 67 unused wires.
|
|
|
|
2.25. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.25.1. Executing Verilog-2005 frontend.
|
|
Parsing Verilog input from `D:\Software\Icestorm\bin\../share/yosys/ice40/cells_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DFF_N_'.
|
|
Generating RTLIL representation for module `\$_DFF_P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `\$_DFF_NN0_'.
|
|
Generating RTLIL representation for module `\$_DFF_NN1_'.
|
|
Generating RTLIL representation for module `\$_DFF_PN0_'.
|
|
Generating RTLIL representation for module `\$_DFF_PN1_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `\$__DFFE_NN0'.
|
|
Generating RTLIL representation for module `\$__DFFE_NN1'.
|
|
Generating RTLIL representation for module `\$__DFFE_PN0'.
|
|
Generating RTLIL representation for module `\$__DFFE_PN1'.
|
|
Generating RTLIL representation for module `\$__DFFE_NP0'.
|
|
Generating RTLIL representation for module `\$__DFFE_NP1'.
|
|
Generating RTLIL representation for module `\$__DFFE_PP0'.
|
|
Generating RTLIL representation for module `\$__DFFE_PP1'.
|
|
Generating RTLIL representation for module `\$lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.25.2. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'.
|
|
Parameter \WIDTH = 4
|
|
Parameter \LUT = 16'0110100110010110
|
|
Generating RTLIL representation for module `$paramod\$lut\WIDTH=4\LUT=16'0110100110010110'.
|
|
|
|
2.25.3. Continuing TECHMAP pass.
|
|
Mapping memtest.$abc$358$auto$blifparse.cc:492:parse_blif$364 using $paramod\$lut\WIDTH=4\LUT=16'0110100110010110.
|
|
|
|
2.25.4. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'.
|
|
Parameter \WIDTH = 3
|
|
Parameter \LUT = 8'10010110
|
|
Generating RTLIL representation for module `$paramod\$lut\WIDTH=3\LUT=8'10010110'.
|
|
|
|
2.25.5. Continuing TECHMAP pass.
|
|
Mapping memtest.$abc$358$auto$blifparse.cc:492:parse_blif$363 using $paramod\$lut\WIDTH=3\LUT=8'10010110.
|
|
|
|
2.25.6. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'.
|
|
Parameter \WIDTH = 4
|
|
Parameter \LUT = 16'1001011001101001
|
|
Generating RTLIL representation for module `$paramod\$lut\WIDTH=4\LUT=16'1001011001101001'.
|
|
|
|
2.25.7. Continuing TECHMAP pass.
|
|
Mapping memtest.$abc$358$auto$blifparse.cc:492:parse_blif$362 using $paramod\$lut\WIDTH=4\LUT=16'1001011001101001.
|
|
Mapping memtest.$abc$358$auto$blifparse.cc:492:parse_blif$361 using $paramod\$lut\WIDTH=3\LUT=8'10010110.
|
|
|
|
2.25.8. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'.
|
|
Parameter \WIDTH = 2
|
|
Parameter \LUT = 4'0110
|
|
Generating RTLIL representation for module `$paramod\$lut\WIDTH=2\LUT=4'0110'.
|
|
|
|
2.25.9. Continuing TECHMAP pass.
|
|
Mapping memtest.$abc$358$auto$blifparse.cc:492:parse_blif$359 using $paramod\$lut\WIDTH=2\LUT=4'0110.
|
|
Mapping memtest.$abc$358$auto$blifparse.cc:492:parse_blif$371 using $paramod\$lut\WIDTH=3\LUT=8'10010110.
|
|
Mapping memtest.$abc$358$auto$blifparse.cc:492:parse_blif$370 using $paramod\$lut\WIDTH=3\LUT=8'10010110.
|
|
Mapping memtest.$abc$358$auto$blifparse.cc:492:parse_blif$366 using $paramod\$lut\WIDTH=4\LUT=16'0110100110010110.
|
|
Mapping memtest.$abc$358$auto$blifparse.cc:492:parse_blif$367 using $paramod\$lut\WIDTH=4\LUT=16'1001011001101001.
|
|
|
|
2.25.10. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'.
|
|
Parameter \WIDTH = 3
|
|
Parameter \LUT = 8'01101001
|
|
Generating RTLIL representation for module `$paramod\$lut\WIDTH=3\LUT=8'01101001'.
|
|
|
|
2.25.11. Continuing TECHMAP pass.
|
|
Mapping memtest.$abc$358$auto$blifparse.cc:492:parse_blif$365 using $paramod\$lut\WIDTH=3\LUT=8'01101001.
|
|
Mapping memtest.$abc$358$auto$blifparse.cc:492:parse_blif$369 using $paramod\$lut\WIDTH=4\LUT=16'1001011001101001.
|
|
Mapping memtest.$abc$358$auto$blifparse.cc:492:parse_blif$368 using $paramod\$lut\WIDTH=4\LUT=16'0110100110010110.
|
|
Mapping memtest.$abc$358$auto$blifparse.cc:492:parse_blif$360 using $paramod\$lut\WIDTH=4\LUT=16'0110100110010110.
|
|
No more expansions possible.
|
|
Removed 0 unused cells and 26 unused wires.
|
|
|
|
2.26. Executing HIERARCHY pass (managing design hierarchy).
|
|
|
|
2.26.1. Analyzing design hierarchy..
|
|
Top module: \memtest
|
|
|
|
2.26.2. Analyzing design hierarchy..
|
|
Top module: \memtest
|
|
Removed 0 unused modules.
|
|
|
|
2.26.3. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 4'0110
|
|
Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=4'0110'.
|
|
|
|
2.26.4. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.5. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 8'10010110
|
|
Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'10010110'.
|
|
|
|
2.26.6. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'1001011001101001
|
|
Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'1001011001101001'.
|
|
|
|
2.26.7. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 8'10010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'10010110'.
|
|
|
|
2.26.8. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.9. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 8'01101001
|
|
Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'01101001'.
|
|
|
|
2.26.10. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.11. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'1001011001101001
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'1001011001101001'.
|
|
|
|
2.26.12. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.13. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'1001011001101001
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'1001011001101001'.
|
|
|
|
2.26.14. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 8'10010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'10010110'.
|
|
|
|
2.26.15. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 8'10010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'10010110'.
|
|
|
|
2.26.16. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.17. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.18. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.19. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.20. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.21. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.22. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.23. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'.
|
|
Parameter \LUT_INIT = 16'0110100110010110
|
|
Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'.
|
|
|
|
2.26.24. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
|
|
Parameter \WRITE_MODE = 1
|
|
Parameter \READ_MODE = 1
|
|
Parameter \INIT_0 = 256'1101110000010001001101000000010110101111010110110100001001111100010111001110010010011010000100111001010101100100001110001100101110111000100001000000101101011110000100101101100111101000111110000011001010001010010000101100011100001100110010101010101101011111
|
|
Parameter \INIT_1 = 256'1011111110001010000111100110000000001000010010001100111100001110001001110100110111111011111010101100001001100000011100011100000001110000111111111011111000000111010110001111111100010001110000111000011000100001111111011000011110001011011100110100010101101001
|
|
Parameter \INIT_2 = 256'0111000001110101101001111010011110011100110011001001011011101110110000100101110000011000100010000001100110110111100000111001100101011101101101010011101110110110100101001111011000100110001101010010010011111101111110011111101000000001010111111100001111111000
|
|
Parameter \INIT_3 = 256'1111001110000110101011010100110101110000000000010011101101000110100110001001110111001110110000110011000010010110110011110101111101101101001000011010110111111110000010001100101000011110110101000010101010101100010111000010110001000111111010111000110001100000
|
|
Parameter \INIT_4 = 256'0011100110110110011001110000001010111011111110010001010011111101101111101001100101110011111100111011011100101000110011010111110010110001100100001001101010101100000010000100010000100011011111100000000110111110111001001110110010000101001011110101111001101000
|
|
Parameter \INIT_5 = 256'0110010100101111100001111110100011111001000101111010101010011001111001001001101010011110110111001100000110011101111000001111111011011001100011101110011011011000000011111010101100111010000010101100111010010011000101100100110010011110011000001101100100001110
|
|
Parameter \INIT_6 = 256'0101100011100010000001101001100000110011111011010101001000101100100101010010001010110010111011010010101101110001110101101111110000101000100101011000100011110111010111011110011001011111101101111011001011111001010000011111010110010100011000001000010010110101
|
|
Parameter \INIT_7 = 256'0110001001101111100101011100001100001000110010101101011100011110001100000110011111111011011011001001010010111101111110011110010011010111111110001111101001110111111101000111011101000111010011010010001001101001010010101011000010101001011010100001011011000111
|
|
Parameter \INIT_8 = 256'0010000101011101001000101110110101111101000000110100111111110000011100110100101011001101001100000101110100101111100001110110010010010100101110101001011100001100101100110110010011001100001101110011100101110011110110000010001110001001101011101010101110100101
|
|
Parameter \INIT_9 = 256'1010100110101111101110010011111101001001110101110100001101100101111101010110111011000001001001100000100111000101111100011101001111011010000111011110110001111010000011101100101101101011110100000110110111101011000011111011011111101000100110001001011111001011
|
|
Parameter \INIT_A = 256'0111101110010010100001001111010110000001100000001010101101010111111110010011110001000001001101110010111010011011110110010100000010110011010010010110100111100110101111011011111011100111100001010110100100110111001110000011001001100101000100101101000110010110
|
|
Parameter \INIT_B = 256'0000111011010101011010001011010110010001100010000111100000101100011001100100010110011000000001110000110111100001100111001000101011100011101101101100101000001101100101000010011110000011000011110000001011100100110100101001001000000100010101010100001000001110
|
|
Parameter \INIT_C = 256'1010111111100110110011010100010011100110101100100001010010101101101110111000000000101010110101001100011010001100010110010000111110111000010010110011110011110100001110000110110001001100001111000110011000010011001000010110110010011001101100100110101111010101
|
|
Parameter \INIT_D = 256'0011001100101011011100110100010010100111001011000110010000110000101100000101111001100111110000101001010111101011110000100001000010000110000100001010101110111111101001111110110000001000110011100101010100010011000001000011101110111000010110011010011010111111
|
|
Parameter \INIT_E = 256'0100001000110100000000011001000011111000111011001101100010100111110000111011000101010110111110011010011001000100101010001010010001010011011100011000100111011000100110000000010111000101100010000110001000010110111000001011001010111111011111101001110001110011
|
|
Parameter \INIT_F = 256'0000101011000111111101011000100001111110101000111110000110010101010110011100011111000110010011011100101111010000110011000011010010110000110110100100110011001010011111011001101010001001000010110110010011011011100101100101111110010101111111001011001011010100
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Generating RTLIL representation for module `$paramod$fa9c4739b0bad1b827e8ef52d223d84ff6a9572c\SB_RAM40_4K'.
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2.26.25. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
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Parameter \WRITE_MODE = 1
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Parameter \READ_MODE = 1
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Parameter \INIT_0 = 256'1100001001001000011000110111111010111101110001100000010100101100101101011000100101110111101011011100100000001010001110111001110011101010001001000100100110110111100001000010011100110001100000011001001000001001000010011011000000001000100111001101001011111001
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Parameter \INIT_1 = 256'0000000100101011100000010111111101010011111100001110111010111001101010000011101110110111101110100101100000111010100111001011111101110101100011111011010000010100111101101100011000010111110110001100110111001111000110000000001010001101001000001001110111111100
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Parameter \INIT_2 = 256'1001110001011011011011010111100010011001101001100101010100111100011111110111001101100010010000100000111101010001111111011011011100111001111111010111010111000111100011001110110111000010010111110110110001000011010110011111101000110001001000110100011111101100
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Parameter \INIT_3 = 256'0001100101000011010111101110010100101001000010100100111110010101010110111011010011111011001100000101010110101001010000111110010000011011011100000011010011101000001101100101111000000101111110101011010110001010100110001000011101010100010101100011001111011000
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Parameter \INIT_4 = 256'1011110110001001101111101010101010000101101010100100111010111000110000101000101000100110010111100010101111111101100001110110111101000101010111101111100111111100000101000000001001110010111110010111010001000110000110010110000010001000111001010011111011010100
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Parameter \INIT_5 = 256'1001110110111101111001100000000111100111101100000011000011111100000111001001110100001011001000111111110111011001100101001100111100010111110000111111101110000000111011100101101110000101101011111100011011101110110111101111011001101100011101100011011101011001
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Parameter \INIT_6 = 256'0000011110110101011111011011101000101010111001000010011011000010110101100011111000010111010010101011100111010101101001110101110011111111011111111101000100111110000000000111011111100001010001110101001100110110000100010000100111110000101100101101000110111010
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Parameter \INIT_7 = 256'0111100111100100110111101001010100110000000010101001110100110101001010100001000010010000100101100111000010100101111110000110001110011001101111000001100011111110001100100000110100100011110110001001001111011101010010111001011110110100100110000001001101100110
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Parameter \INIT_8 = 256'0011110011001001010000010000010001001110011101110101111100110101001101110001001101001001111110001010001001000011001101101100100100111000111010110111110001110001000011000000001101111100001001111101101011100010010000101100100000100100101110000111000000100011
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Parameter \INIT_9 = 256'0111110001010001101111110100111001010111111010010111010010100001000011000001000011100100101001000111001000100010001111111111101111011000110001011110000010010000000000000010001101011111011010001000011111100111101010111101000001010001001110011101000010010011
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Parameter \INIT_A = 256'1001100011110100001110111111100011011110001110110101100100101000011001011100110010011001110100110111110101111110110110100110001101100100010100111110001010100111111100100011110011111010110001111100110001011111001111010100101010111011001010001011100000101101
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Parameter \INIT_B = 256'1001100011100000011111110101100110000000001111101011101100010000111010000011110111010011001111100101001001010001010111001010100001001101101010100010001100011001001011100010000011100010100101000010011110000101100010000001100110111010110000011011111010111111
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Parameter \INIT_C = 256'0100100101100111001101000110000110011011100001111010000000001101010011010000101111000011010111011011010101111001011001111101000010010011101110101010110110010110100111111100011101010011111010001000001100001110011101011100010111010011110001101001001110111110
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Parameter \INIT_D = 256'1000111000110011001001111001111111110110010000110101000101011000110010101111110001111010101111010111100000011010000101101000101000010101110010111011001000101011101101100110011111010011111001011111011010011100000101011101100100110001001000001111100010110101
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Parameter \INIT_E = 256'1001011101110011100001011100011110000110110110100011011100110100110010001111101010101011010010101010011000110001010101110011000111000100010111011110100100001100110000011001010001000001110011100101100101100001101000010001111101001000111100000010110111001010
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Parameter \INIT_F = 256'1100100101011111001010000010111000001010010010100010101100100111110011111000001111100111111000100000111111111101010110001001001110111001000100111110001001101110011101010101001011011001110111111010111000011011100011110001000001111101001111001000110111110011
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Generating RTLIL representation for module `$paramod$c0677c5f874d489c6aefa96e8c2fc89bec062c38\SB_RAM40_4K'.
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2.26.26. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
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Parameter \WRITE_MODE = 1
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Parameter \READ_MODE = 1
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Parameter \INIT_0 = 256'0001010101010000111110010010001111000101101001000011000011000101110100111110000110100100010001011111111111101011000000010101110001000011101011011010110011000111110100111001010011010101101101011000110111010010001011110001111101001101011101010111011111111000
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Parameter \INIT_1 = 256'1110010001100111110101010101000010010100000100101100100011100110000001101001000100001101110100100100111110100000101100111111010011000011110111100111110011111000100100000101001111100011110101010000001010000000001010100001110011100101011111010111110111011101
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Parameter \INIT_2 = 256'0001111111100101111011000010010010001001000111111101001011010000010100001001001110110011000000001001001000111010011100110011010010010101001101101100010110100011101111111101000100111101010101011011011001000000100101011111101001100000000100111001111101100010
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Parameter \INIT_3 = 256'0010111100110110100011101101100100100010101000001101111000000001000000101000110110010111001100010101000000010111011011011001100010101011001111001100101110101001111011001000000010100101110000000110111111101010111011111110001010110110101100101111111111001111
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Parameter \INIT_4 = 256'0111000101010110111001101001111000111111110000000011110100110001000111110111100011010111111101000111000111000001111011011000011111111001001101110011110000001011110101111011000101011100001101100111000101010101001011101101101101000100101110011111111100110100
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Parameter \INIT_5 = 256'0101010010011101011011010101000011111001010010110101010001010010111100100010110001101100110000011001111001010010111011111011111011100000010101101100100011100001010101100110000101000110110111010000110110111110101000100101010010000111111010000010011110111100
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Parameter \INIT_6 = 256'0100100000010100111111010011001010001001011110000110010100111110110001011111110011111011000001100000000011001110010101000101111111010010010101111010010011011011110011011001001110001101000010000010011111000010111010011000010111100010110001111110010101010110
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Parameter \INIT_7 = 256'1111011110010001000101011010010100010011010101110100011111101101100101110110011000111000101100011100010001100110100110000101000100111110011011000111011101010101101101010101001100110100000101000111000101111010000111100010110010000010000011100001110011111110
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Parameter \INIT_8 = 256'0011000001001111001001110001101011101111000011000111101100100000000101111100011000100110101111001101101101001011110100110111000111110110110010111001111000110101001100100000110100010111001111000010001110110111100110101011000000000100110100011110010100100011
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Parameter \INIT_9 = 256'1011000011100011110101110100010111101010110101010111011011000101110001000100100010010101111001000100010101011000111111101111111000101011001000111101110110011111111001010100111101010101011100100110111101001001101011011011111011111000100011110001111011010001
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Parameter \INIT_A = 256'0010110111111100000001000001110100010011011100101000000010100001101000110010100000011111100010000110011010101001100000100110100110011110010010010011010100101001100010111001010000100111001000110111110111001100000111001101010000001101000001110000101011000101
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Parameter \INIT_B = 256'0010101010001000110110110100000011000100100100111010111100110001100111001010111000001111000110011101110000101100010110001011111110110101100111111101000000000100010011011101100001000110111111100011110101100100010010011110001101110101001111011000010011110110
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Parameter \INIT_C = 256'0110101011001010100011101000110011111010011100110011001010001100100110101011101011001001110110110011010100001000101001011010101100111111001000011000100100011101110000000110001010010001011100100101101000100100010111001111100000110111011111100010101010010011
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Parameter \INIT_D = 256'0000100011101110101011001000000110101110111111011010100001010000100110011011101011110100100011101011100111000011101110010000010110011110101010000010000011000000111100010100001100001010000110110110111011000011100101010101001011010110011110000001111101100001
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Parameter \INIT_E = 256'1000011111001010101110010110011111100010001100011111001111001100000000010101011100100011101110111111011011101101100001111011000010011010011110011110010100000001010101011101011010001000101100111110111000000000010100100100000000001110110111011011010000110101
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Parameter \INIT_F = 256'1111101111111000100101010101100001010100110101111000111011111101110011001100110111100110001100010001111101111001011101000100000010011010011010000100101101110010000110111101010100101001001000000111101110000011010101101000100010101100010110111010100000101010
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Generating RTLIL representation for module `$paramod$3725bf38e61942d5903b6c04e36a9c50c471da56\SB_RAM40_4K'.
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2.26.27. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_RAM40_4K'.
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Parameter \WRITE_MODE = 1
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Parameter \READ_MODE = 1
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Parameter \INIT_0 = 256'1100000110010100101101110101000001101101011000011010000011100101000110011010110100001011111001000101110111110110010101101110000001000100101001011101100010011010111111001100001110111011110110011010000110110001101010010000110101000100101111010011000100111100
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Parameter \INIT_1 = 256'0110110010110111011011110001110010110001010000000001001101110000000110101001011111011010111100101010011110000011001110101110100110001110011010100010010000010011101101100001001000011101110111101000011110101110011010000101000101010011111101111101111010111010
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Parameter \INIT_2 = 256'0010000000000011110111011000101100011100010101110110101001110001111010011101010010101101000011100000000000100100110101101001100000110110101110001110001010000101100100010010001010010100011011101010101001111000011100001010010110010110010000010110101111100010
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Parameter \INIT_3 = 256'1000001100000111101100011110101110110111111010001001010100001000000110100100111001100101100000010110011101100011100101101010001101001010000111011101000011100100000110110011101110001000110011000010011100101111001001110011011110011001001111110100010011010000
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Parameter \INIT_4 = 256'1100101100101011101011010000110100001010110001100000111110000010011111000001100111111111111111001100001101011111000111111110000111000011100100011001110101010001011101100111000000001011011110100111111101111011001010001010011000010010010001100001000110101100
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Parameter \INIT_5 = 256'1111111001000010010100000110101101011011100000000101011111001001010101110001001001011010101011001100101011001110101111001001100010101011100001001100011010000000111111110111000001000001001011010110100010010100101110110001100110001000000010001011000011110000
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Parameter \INIT_6 = 256'1011110100111011101100000000000101010010010001010001100011010101001101010011100111011011111110010000110100010001111111100101101010000101110111010010111100000100101001101101111100010011000010110000001101101011111001011111010010000011010001111101010000001001
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Parameter \INIT_7 = 256'1101011000101101011010110110010000001111001110000101110100000001110101111000101100111101000100011110001101100111010010110111100111110011110011101110011000110001000011100101111010110111101010101111001101000010101111110100100000100110010011110111111001000001
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Parameter \INIT_8 = 256'0111000010000101010010001110111011101101111011001100110111100110101010100011110010101110111101010110100001000110000010100001000011011000100110010111101100001001110010011101101000100000001111010001000111000001111111000101000011001110110110100100000000001001
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Parameter \INIT_9 = 256'1011011111001001010100010011111110100010001101010000100011000011110011001000110111010100000001101101001000001001010010010011000100001110000100010011011011011111000010111000010110100110111000101110001110100100100000010111010011000001011011111110110011100110
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Parameter \INIT_A = 256'1001011101100011110010100010010001001101011011110001001100110001010101001100101000000001100110110001111101001100010011001000011010101110000001000100000111000101000010001000111110001010010010100101111011101000010111101110010101000000011111001010010011100100
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Parameter \INIT_B = 256'1110001010100011011100100101100010010010010111011111110110000001101100110101001001100101000110100000010010100001100111010100111110001011001100111100001010100000101101100101100001010000100101001110000010010010011001001001000111111011111100001010111001011101
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Parameter \INIT_C = 256'1100000101000010011110110010010111110011010010100110001001110001011110111111010101010101000110111010100100001110100000000010101101011100110011001010101111100010101011001100000000101010100111101000011101010011110110110010100100101011010111111001100001100101
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Parameter \INIT_D = 256'0010011000100001111011010011110000000111001011111000000010011001001000010111101001111000000001101101010011101001111011001011101101101111111010110100011000001101010110000000010011011001100111101001110011010011101100101010111100011101011010101010001110110000
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Parameter \INIT_E = 256'1101000110010110100111110101000110100111110000101001110001101110100110000001110000110101101000001001110101100100000110100100110011110101111000011101000111011100101101001001010111111000011010011010011101111001000101110000011100001101011010010011110111010000
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Parameter \INIT_F = 256'1001101111011100110111000111111010000110011101000011101110100001101101111000110100011100101000001001000110000100001110000011010111111101100010001010001010010101011101011001010110000001001101111010010001111010000001101000111000011110010111111001110111110110
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Generating RTLIL representation for module `$paramod$be6a86056d534463ff3ebe0d909e46f73bcf2843\SB_RAM40_4K'.
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2.27. Printing statistics.
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=== memtest ===
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Number of wires: 32
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Number of wire bits: 153
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Number of public wires: 13
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Number of public wire bits: 23
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Number of memories: 0
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Number of memory bits: 0
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Number of processes: 0
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Number of cells: 43
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SB_CARRY 7
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SB_DFF 10
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SB_GB 1
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SB_LUT4 21
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SB_RAM40_4K 4
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2.28. Executing CHECK pass (checking for obvious problems).
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checking module memtest..
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found and reported 0 problems.
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2.29. Executing JSON backend.
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Warnings: 9 unique messages, 9 total
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End of script. Logfile hash: c41236f0c4
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Yosys 0.8+ (git sha1 UNKNOWN, x86_64-w64-mingw32-g++ 7.3-posix -O3 -DNDEBUG)
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Time spent: 2% 14x opt_expr (0 sec), 2% 14x opt_clean (0 sec), ...
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