998 lines
26 KiB
Rust
998 lines
26 KiB
Rust
#[doc = r" Value read from the register"]
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pub struct R {
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bits: u16,
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}
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#[doc = r" Value to write to the register"]
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pub struct W {
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bits: u16,
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}
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impl super::TCD10_CSR {
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#[doc = r" Modifies the contents of the register"]
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#[inline]
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pub fn modify<F>(&self, f: F)
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where
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for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
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{
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let bits = self.register.get();
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let r = R { bits: bits };
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let mut w = W { bits: bits };
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f(&r, &mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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pub fn write<F>(&self, f: F)
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where
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F: FnOnce(&mut W) -> &mut W,
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{
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let mut w = W::reset_value();
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f(&mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Writes the reset value to the register"]
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#[inline]
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pub fn reset(&self) {
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self.write(|w| w)
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}
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}
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#[doc = "Possible values of the field `START`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum STARTR {
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#[doc = "The channel is not explicitly started."]
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_0,
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#[doc = "The channel is explicitly started via a software initiated service request."]
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_1,
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}
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impl STARTR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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STARTR::_0 => false,
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STARTR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> STARTR {
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match value {
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false => STARTR::_0,
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true => STARTR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == STARTR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == STARTR::_1
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}
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}
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#[doc = "Possible values of the field `INTMAJOR`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum INTMAJORR {
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#[doc = "The end-of-major loop interrupt is disabled."]
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_0,
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#[doc = "The end-of-major loop interrupt is enabled."]
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_1,
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}
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impl INTMAJORR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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INTMAJORR::_0 => false,
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INTMAJORR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> INTMAJORR {
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match value {
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false => INTMAJORR::_0,
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true => INTMAJORR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == INTMAJORR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == INTMAJORR::_1
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}
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}
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#[doc = "Possible values of the field `INTHALF`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum INTHALFR {
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#[doc = "The half-point interrupt is disabled."]
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_0,
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#[doc = "The half-point interrupt is enabled."]
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_1,
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}
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impl INTHALFR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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INTHALFR::_0 => false,
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INTHALFR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> INTHALFR {
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match value {
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false => INTHALFR::_0,
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true => INTHALFR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == INTHALFR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == INTHALFR::_1
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}
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}
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#[doc = r" Value of the field"]
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pub struct DREQR {
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bits: bool,
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}
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impl DREQR {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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self.bits
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}
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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}
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#[doc = "Possible values of the field `ESG`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ESGR {
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#[doc = "The current channel's TCD is normal format."]
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_0,
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#[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."]
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_1,
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}
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impl ESGR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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ESGR::_0 => false,
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ESGR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> ESGR {
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match value {
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false => ESGR::_0,
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true => ESGR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == ESGR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == ESGR::_1
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}
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}
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#[doc = "Possible values of the field `MAJORELINK`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum MAJORELINKR {
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#[doc = "The channel-to-channel linking is disabled."]
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_0,
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#[doc = "The channel-to-channel linking is enabled."]
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_1,
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}
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impl MAJORELINKR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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MAJORELINKR::_0 => false,
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MAJORELINKR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> MAJORELINKR {
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match value {
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false => MAJORELINKR::_0,
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true => MAJORELINKR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == MAJORELINKR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == MAJORELINKR::_1
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}
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}
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#[doc = r" Value of the field"]
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pub struct ACTIVER {
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bits: bool,
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}
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impl ACTIVER {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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self.bits
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}
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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}
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#[doc = r" Value of the field"]
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pub struct DONER {
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bits: bool,
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}
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impl DONER {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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self.bits
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}
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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}
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#[doc = r" Value of the field"]
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pub struct MAJORLINKCHR {
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bits: u8,
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}
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impl MAJORLINKCHR {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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self.bits
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}
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}
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#[doc = "Possible values of the field `BWC`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum BWCR {
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#[doc = "No eDMA engine stalls."]
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_0,
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#[doc = "eDMA engine stalls for 4 cycles after each R/W."]
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_10,
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#[doc = "eDMA engine stalls for 8 cycles after each R/W."]
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_11,
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#[doc = r" Reserved"]
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_Reserved(u8),
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}
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impl BWCR {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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match *self {
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BWCR::_0 => 0,
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BWCR::_10 => 2,
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BWCR::_11 => 3,
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BWCR::_Reserved(bits) => bits,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: u8) -> BWCR {
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match value {
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0 => BWCR::_0,
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2 => BWCR::_10,
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3 => BWCR::_11,
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i => BWCR::_Reserved(i),
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == BWCR::_0
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}
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#[doc = "Checks if the value of the field is `_10`"]
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#[inline]
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pub fn is_10(&self) -> bool {
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*self == BWCR::_10
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}
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#[doc = "Checks if the value of the field is `_11`"]
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#[inline]
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pub fn is_11(&self) -> bool {
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*self == BWCR::_11
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}
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}
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#[doc = "Values that can be written to the field `START`"]
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pub enum STARTW {
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#[doc = "The channel is not explicitly started."]
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_0,
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#[doc = "The channel is explicitly started via a software initiated service request."]
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_1,
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}
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impl STARTW {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> bool {
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match *self {
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STARTW::_0 => false,
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STARTW::_1 => true,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _STARTW<'a> {
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w: &'a mut W,
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}
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impl<'a> _STARTW<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: STARTW) -> &'a mut W {
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{
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self.bit(variant._bits())
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}
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}
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#[doc = "The channel is not explicitly started."]
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#[inline]
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pub fn _0(self) -> &'a mut W {
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self.variant(STARTW::_0)
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}
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#[doc = "The channel is explicitly started via a software initiated service request."]
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#[inline]
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pub fn _1(self) -> &'a mut W {
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self.variant(STARTW::_1)
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}
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#[doc = r" Sets the field bit"]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r" Clears the field bit"]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub fn bit(self, value: bool) -> &'a mut W {
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const MASK: bool = true;
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const OFFSET: u8 = 0;
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self.w.bits &= !((MASK as u16) << OFFSET);
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self.w.bits |= ((value & MASK) as u16) << OFFSET;
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self.w
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}
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}
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#[doc = "Values that can be written to the field `INTMAJOR`"]
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pub enum INTMAJORW {
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#[doc = "The end-of-major loop interrupt is disabled."]
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_0,
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#[doc = "The end-of-major loop interrupt is enabled."]
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_1,
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}
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impl INTMAJORW {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> bool {
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match *self {
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INTMAJORW::_0 => false,
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INTMAJORW::_1 => true,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _INTMAJORW<'a> {
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w: &'a mut W,
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}
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impl<'a> _INTMAJORW<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: INTMAJORW) -> &'a mut W {
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{
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self.bit(variant._bits())
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}
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}
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#[doc = "The end-of-major loop interrupt is disabled."]
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#[inline]
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pub fn _0(self) -> &'a mut W {
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self.variant(INTMAJORW::_0)
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}
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#[doc = "The end-of-major loop interrupt is enabled."]
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#[inline]
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pub fn _1(self) -> &'a mut W {
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self.variant(INTMAJORW::_1)
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}
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#[doc = r" Sets the field bit"]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r" Clears the field bit"]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub fn bit(self, value: bool) -> &'a mut W {
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const MASK: bool = true;
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const OFFSET: u8 = 1;
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self.w.bits &= !((MASK as u16) << OFFSET);
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self.w.bits |= ((value & MASK) as u16) << OFFSET;
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self.w
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}
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}
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|
#[doc = "Values that can be written to the field `INTHALF`"]
|
|
pub enum INTHALFW {
|
|
#[doc = "The half-point interrupt is disabled."]
|
|
_0,
|
|
#[doc = "The half-point interrupt is enabled."]
|
|
_1,
|
|
}
|
|
impl INTHALFW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> bool {
|
|
match *self {
|
|
INTHALFW::_0 => false,
|
|
INTHALFW::_1 => true,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _INTHALFW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _INTHALFW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: INTHALFW) -> &'a mut W {
|
|
{
|
|
self.bit(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "The half-point interrupt is disabled."]
|
|
#[inline]
|
|
pub fn _0(self) -> &'a mut W {
|
|
self.variant(INTHALFW::_0)
|
|
}
|
|
#[doc = "The half-point interrupt is enabled."]
|
|
#[inline]
|
|
pub fn _1(self) -> &'a mut W {
|
|
self.variant(INTHALFW::_1)
|
|
}
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 2;
|
|
self.w.bits &= !((MASK as u16) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u16) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _DREQW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _DREQW<'a> {
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 3;
|
|
self.w.bits &= !((MASK as u16) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u16) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `ESG`"]
|
|
pub enum ESGW {
|
|
#[doc = "The current channel's TCD is normal format."]
|
|
_0,
|
|
#[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."]
|
|
_1,
|
|
}
|
|
impl ESGW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> bool {
|
|
match *self {
|
|
ESGW::_0 => false,
|
|
ESGW::_1 => true,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ESGW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ESGW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: ESGW) -> &'a mut W {
|
|
{
|
|
self.bit(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "The current channel's TCD is normal format."]
|
|
#[inline]
|
|
pub fn _0(self) -> &'a mut W {
|
|
self.variant(ESGW::_0)
|
|
}
|
|
#[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."]
|
|
#[inline]
|
|
pub fn _1(self) -> &'a mut W {
|
|
self.variant(ESGW::_1)
|
|
}
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 4;
|
|
self.w.bits &= !((MASK as u16) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u16) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `MAJORELINK`"]
|
|
pub enum MAJORELINKW {
|
|
#[doc = "The channel-to-channel linking is disabled."]
|
|
_0,
|
|
#[doc = "The channel-to-channel linking is enabled."]
|
|
_1,
|
|
}
|
|
impl MAJORELINKW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> bool {
|
|
match *self {
|
|
MAJORELINKW::_0 => false,
|
|
MAJORELINKW::_1 => true,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _MAJORELINKW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _MAJORELINKW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: MAJORELINKW) -> &'a mut W {
|
|
{
|
|
self.bit(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "The channel-to-channel linking is disabled."]
|
|
#[inline]
|
|
pub fn _0(self) -> &'a mut W {
|
|
self.variant(MAJORELINKW::_0)
|
|
}
|
|
#[doc = "The channel-to-channel linking is enabled."]
|
|
#[inline]
|
|
pub fn _1(self) -> &'a mut W {
|
|
self.variant(MAJORELINKW::_1)
|
|
}
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 5;
|
|
self.w.bits &= !((MASK as u16) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u16) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ACTIVEW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ACTIVEW<'a> {
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 6;
|
|
self.w.bits &= !((MASK as u16) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u16) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _DONEW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _DONEW<'a> {
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 7;
|
|
self.w.bits &= !((MASK as u16) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u16) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _MAJORLINKCHW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _MAJORLINKCHW<'a> {
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
|
const MASK: u8 = 15;
|
|
const OFFSET: u8 = 8;
|
|
self.w.bits &= !((MASK as u16) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u16) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `BWC`"]
|
|
pub enum BWCW {
|
|
#[doc = "No eDMA engine stalls."]
|
|
_0,
|
|
#[doc = "eDMA engine stalls for 4 cycles after each R/W."]
|
|
_10,
|
|
#[doc = "eDMA engine stalls for 8 cycles after each R/W."]
|
|
_11,
|
|
}
|
|
impl BWCW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> u8 {
|
|
match *self {
|
|
BWCW::_0 => 0,
|
|
BWCW::_10 => 2,
|
|
BWCW::_11 => 3,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _BWCW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _BWCW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: BWCW) -> &'a mut W {
|
|
unsafe { self.bits(variant._bits()) }
|
|
}
|
|
#[doc = "No eDMA engine stalls."]
|
|
#[inline]
|
|
pub fn _0(self) -> &'a mut W {
|
|
self.variant(BWCW::_0)
|
|
}
|
|
#[doc = "eDMA engine stalls for 4 cycles after each R/W."]
|
|
#[inline]
|
|
pub fn _10(self) -> &'a mut W {
|
|
self.variant(BWCW::_10)
|
|
}
|
|
#[doc = "eDMA engine stalls for 8 cycles after each R/W."]
|
|
#[inline]
|
|
pub fn _11(self) -> &'a mut W {
|
|
self.variant(BWCW::_11)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
|
const MASK: u8 = 3;
|
|
const OFFSET: u8 = 14;
|
|
self.w.bits &= !((MASK as u16) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u16) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
impl R {
|
|
#[doc = r" Value of the register as raw bits"]
|
|
#[inline]
|
|
pub fn bits(&self) -> u16 {
|
|
self.bits
|
|
}
|
|
#[doc = "Bit 0 - Channel Start"]
|
|
#[inline]
|
|
pub fn start(&self) -> STARTR {
|
|
STARTR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 0;
|
|
((self.bits >> OFFSET) & MASK as u16) != 0
|
|
})
|
|
}
|
|
#[doc = "Bit 1 - Enable an interrupt when major iteration count completes."]
|
|
#[inline]
|
|
pub fn intmajor(&self) -> INTMAJORR {
|
|
INTMAJORR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 1;
|
|
((self.bits >> OFFSET) & MASK as u16) != 0
|
|
})
|
|
}
|
|
#[doc = "Bit 2 - Enable an interrupt when major counter is half complete."]
|
|
#[inline]
|
|
pub fn inthalf(&self) -> INTHALFR {
|
|
INTHALFR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 2;
|
|
((self.bits >> OFFSET) & MASK as u16) != 0
|
|
})
|
|
}
|
|
#[doc = "Bit 3 - Disable Request"]
|
|
#[inline]
|
|
pub fn dreq(&self) -> DREQR {
|
|
let bits = {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 3;
|
|
((self.bits >> OFFSET) & MASK as u16) != 0
|
|
};
|
|
DREQR { bits }
|
|
}
|
|
#[doc = "Bit 4 - Enable Scatter/Gather Processing"]
|
|
#[inline]
|
|
pub fn esg(&self) -> ESGR {
|
|
ESGR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 4;
|
|
((self.bits >> OFFSET) & MASK as u16) != 0
|
|
})
|
|
}
|
|
#[doc = "Bit 5 - Enable channel-to-channel linking on major loop complete"]
|
|
#[inline]
|
|
pub fn majorelink(&self) -> MAJORELINKR {
|
|
MAJORELINKR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 5;
|
|
((self.bits >> OFFSET) & MASK as u16) != 0
|
|
})
|
|
}
|
|
#[doc = "Bit 6 - Channel Active"]
|
|
#[inline]
|
|
pub fn active(&self) -> ACTIVER {
|
|
let bits = {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 6;
|
|
((self.bits >> OFFSET) & MASK as u16) != 0
|
|
};
|
|
ACTIVER { bits }
|
|
}
|
|
#[doc = "Bit 7 - Channel Done"]
|
|
#[inline]
|
|
pub fn done(&self) -> DONER {
|
|
let bits = {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 7;
|
|
((self.bits >> OFFSET) & MASK as u16) != 0
|
|
};
|
|
DONER { bits }
|
|
}
|
|
#[doc = "Bits 8:11 - Major Loop Link Channel Number"]
|
|
#[inline]
|
|
pub fn majorlinkch(&self) -> MAJORLINKCHR {
|
|
let bits = {
|
|
const MASK: u8 = 15;
|
|
const OFFSET: u8 = 8;
|
|
((self.bits >> OFFSET) & MASK as u16) as u8
|
|
};
|
|
MAJORLINKCHR { bits }
|
|
}
|
|
#[doc = "Bits 14:15 - Bandwidth Control"]
|
|
#[inline]
|
|
pub fn bwc(&self) -> BWCR {
|
|
BWCR::_from({
|
|
const MASK: u8 = 3;
|
|
const OFFSET: u8 = 14;
|
|
((self.bits >> OFFSET) & MASK as u16) as u8
|
|
})
|
|
}
|
|
}
|
|
impl W {
|
|
#[doc = r" Reset value of the register"]
|
|
#[inline]
|
|
pub fn reset_value() -> W {
|
|
W { bits: 0 }
|
|
}
|
|
#[doc = r" Writes raw bits to the register"]
|
|
#[inline]
|
|
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
|
|
self.bits = bits;
|
|
self
|
|
}
|
|
#[doc = "Bit 0 - Channel Start"]
|
|
#[inline]
|
|
pub fn start(&mut self) -> _STARTW {
|
|
_STARTW { w: self }
|
|
}
|
|
#[doc = "Bit 1 - Enable an interrupt when major iteration count completes."]
|
|
#[inline]
|
|
pub fn intmajor(&mut self) -> _INTMAJORW {
|
|
_INTMAJORW { w: self }
|
|
}
|
|
#[doc = "Bit 2 - Enable an interrupt when major counter is half complete."]
|
|
#[inline]
|
|
pub fn inthalf(&mut self) -> _INTHALFW {
|
|
_INTHALFW { w: self }
|
|
}
|
|
#[doc = "Bit 3 - Disable Request"]
|
|
#[inline]
|
|
pub fn dreq(&mut self) -> _DREQW {
|
|
_DREQW { w: self }
|
|
}
|
|
#[doc = "Bit 4 - Enable Scatter/Gather Processing"]
|
|
#[inline]
|
|
pub fn esg(&mut self) -> _ESGW {
|
|
_ESGW { w: self }
|
|
}
|
|
#[doc = "Bit 5 - Enable channel-to-channel linking on major loop complete"]
|
|
#[inline]
|
|
pub fn majorelink(&mut self) -> _MAJORELINKW {
|
|
_MAJORELINKW { w: self }
|
|
}
|
|
#[doc = "Bit 6 - Channel Active"]
|
|
#[inline]
|
|
pub fn active(&mut self) -> _ACTIVEW {
|
|
_ACTIVEW { w: self }
|
|
}
|
|
#[doc = "Bit 7 - Channel Done"]
|
|
#[inline]
|
|
pub fn done(&mut self) -> _DONEW {
|
|
_DONEW { w: self }
|
|
}
|
|
#[doc = "Bits 8:11 - Major Loop Link Channel Number"]
|
|
#[inline]
|
|
pub fn majorlinkch(&mut self) -> _MAJORLINKCHW {
|
|
_MAJORLINKCHW { w: self }
|
|
}
|
|
#[doc = "Bits 14:15 - Bandwidth Control"]
|
|
#[inline]
|
|
pub fn bwc(&mut self) -> _BWCW {
|
|
_BWCW { w: self }
|
|
}
|
|
}
|