600 lines
16 KiB
Rust
600 lines
16 KiB
Rust
#[doc = r" Value read from the register"]
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pub struct R {
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bits: u32,
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}
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#[doc = r" Value to write to the register"]
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pub struct W {
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bits: u32,
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}
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impl super::FDCTRL {
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#[doc = r" Modifies the contents of the register"]
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#[inline]
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pub fn modify<F>(&self, f: F)
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where
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for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
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{
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let bits = self.register.get();
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let r = R { bits: bits };
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let mut w = W { bits: bits };
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f(&r, &mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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pub fn write<F>(&self, f: F)
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where
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F: FnOnce(&mut W) -> &mut W,
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{
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let mut w = W::reset_value();
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f(&mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Writes the reset value to the register"]
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#[inline]
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pub fn reset(&self) {
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self.write(|w| w)
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}
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}
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#[doc = r" Value of the field"]
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pub struct TDCVALR {
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bits: u8,
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}
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impl TDCVALR {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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self.bits
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}
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}
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#[doc = r" Value of the field"]
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pub struct TDCOFFR {
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bits: u8,
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}
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impl TDCOFFR {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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self.bits
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}
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}
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#[doc = "Possible values of the field `TDCFAIL`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum TDCFAILR {
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#[doc = "Measured loop delay is in range."] _0,
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#[doc = "Measured loop delay is out of range."] _1,
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}
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impl TDCFAILR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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TDCFAILR::_0 => false,
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TDCFAILR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> TDCFAILR {
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match value {
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false => TDCFAILR::_0,
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true => TDCFAILR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == TDCFAILR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == TDCFAILR::_1
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}
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}
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#[doc = "Possible values of the field `TDCEN`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum TDCENR {
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#[doc = "TDC is disabled"] _0,
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#[doc = "TDC is enabled"] _1,
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}
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impl TDCENR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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TDCENR::_0 => false,
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TDCENR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> TDCENR {
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match value {
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false => TDCENR::_0,
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true => TDCENR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == TDCENR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == TDCENR::_1
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}
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}
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#[doc = "Possible values of the field `MBDSR0`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum MBDSR0R {
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#[doc = "Selects 8 bytes per Message Buffer."] _00,
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#[doc = "Selects 16 bytes per Message Buffer."] _01,
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#[doc = "Selects 32 bytes per Message Buffer."] _10,
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#[doc = "Selects 64 bytes per Message Buffer."] _11,
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}
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impl MBDSR0R {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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match *self {
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MBDSR0R::_00 => 0,
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MBDSR0R::_01 => 1,
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MBDSR0R::_10 => 2,
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MBDSR0R::_11 => 3,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: u8) -> MBDSR0R {
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match value {
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0 => MBDSR0R::_00,
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1 => MBDSR0R::_01,
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2 => MBDSR0R::_10,
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3 => MBDSR0R::_11,
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_ => unreachable!(),
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}
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}
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#[doc = "Checks if the value of the field is `_00`"]
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#[inline]
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pub fn is_00(&self) -> bool {
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*self == MBDSR0R::_00
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}
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#[doc = "Checks if the value of the field is `_01`"]
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#[inline]
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pub fn is_01(&self) -> bool {
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*self == MBDSR0R::_01
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}
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#[doc = "Checks if the value of the field is `_10`"]
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#[inline]
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pub fn is_10(&self) -> bool {
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*self == MBDSR0R::_10
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}
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#[doc = "Checks if the value of the field is `_11`"]
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#[inline]
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pub fn is_11(&self) -> bool {
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*self == MBDSR0R::_11
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}
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}
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#[doc = "Possible values of the field `FDRATE`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum FDRATER {
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#[doc = "Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect."] _0,
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#[doc = "Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive."] _1,
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}
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impl FDRATER {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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FDRATER::_0 => false,
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FDRATER::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> FDRATER {
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match value {
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false => FDRATER::_0,
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true => FDRATER::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == FDRATER::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == FDRATER::_1
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}
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}
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#[doc = r" Proxy"]
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pub struct _TDCOFFW<'a> {
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w: &'a mut W,
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}
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impl<'a> _TDCOFFW<'a> {
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub unsafe fn bits(self, value: u8) -> &'a mut W {
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const MASK: u8 = 31;
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const OFFSET: u8 = 8;
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self.w.bits &= !((MASK as u32) << OFFSET);
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
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self.w
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}
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}
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#[doc = "Values that can be written to the field `TDCFAIL`"]
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pub enum TDCFAILW {
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#[doc = "Measured loop delay is in range."] _0,
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#[doc = "Measured loop delay is out of range."] _1,
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}
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impl TDCFAILW {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> bool {
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match *self {
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TDCFAILW::_0 => false,
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TDCFAILW::_1 => true,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _TDCFAILW<'a> {
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w: &'a mut W,
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}
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impl<'a> _TDCFAILW<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: TDCFAILW) -> &'a mut W {
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{
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self.bit(variant._bits())
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}
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}
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#[doc = "Measured loop delay is in range."]
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#[inline]
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pub fn _0(self) -> &'a mut W {
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self.variant(TDCFAILW::_0)
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}
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#[doc = "Measured loop delay is out of range."]
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#[inline]
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pub fn _1(self) -> &'a mut W {
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self.variant(TDCFAILW::_1)
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}
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#[doc = r" Sets the field bit"]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r" Clears the field bit"]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub fn bit(self, value: bool) -> &'a mut W {
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const MASK: bool = true;
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const OFFSET: u8 = 14;
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self.w.bits &= !((MASK as u32) << OFFSET);
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
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self.w
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}
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}
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#[doc = "Values that can be written to the field `TDCEN`"]
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pub enum TDCENW {
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#[doc = "TDC is disabled"] _0,
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#[doc = "TDC is enabled"] _1,
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}
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impl TDCENW {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> bool {
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match *self {
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TDCENW::_0 => false,
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TDCENW::_1 => true,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _TDCENW<'a> {
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w: &'a mut W,
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}
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impl<'a> _TDCENW<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: TDCENW) -> &'a mut W {
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{
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self.bit(variant._bits())
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}
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}
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#[doc = "TDC is disabled"]
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#[inline]
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pub fn _0(self) -> &'a mut W {
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self.variant(TDCENW::_0)
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}
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#[doc = "TDC is enabled"]
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#[inline]
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pub fn _1(self) -> &'a mut W {
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self.variant(TDCENW::_1)
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}
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#[doc = r" Sets the field bit"]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r" Clears the field bit"]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub fn bit(self, value: bool) -> &'a mut W {
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const MASK: bool = true;
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const OFFSET: u8 = 15;
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self.w.bits &= !((MASK as u32) << OFFSET);
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
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self.w
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}
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}
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#[doc = "Values that can be written to the field `MBDSR0`"]
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pub enum MBDSR0W {
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#[doc = "Selects 8 bytes per Message Buffer."] _00,
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#[doc = "Selects 16 bytes per Message Buffer."] _01,
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#[doc = "Selects 32 bytes per Message Buffer."] _10,
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#[doc = "Selects 64 bytes per Message Buffer."] _11,
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}
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impl MBDSR0W {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> u8 {
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match *self {
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MBDSR0W::_00 => 0,
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MBDSR0W::_01 => 1,
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MBDSR0W::_10 => 2,
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MBDSR0W::_11 => 3,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _MBDSR0W<'a> {
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w: &'a mut W,
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}
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impl<'a> _MBDSR0W<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: MBDSR0W) -> &'a mut W {
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{
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self.bits(variant._bits())
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}
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}
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#[doc = "Selects 8 bytes per Message Buffer."]
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#[inline]
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pub fn _00(self) -> &'a mut W {
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self.variant(MBDSR0W::_00)
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}
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#[doc = "Selects 16 bytes per Message Buffer."]
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#[inline]
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pub fn _01(self) -> &'a mut W {
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self.variant(MBDSR0W::_01)
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}
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#[doc = "Selects 32 bytes per Message Buffer."]
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#[inline]
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pub fn _10(self) -> &'a mut W {
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self.variant(MBDSR0W::_10)
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}
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#[doc = "Selects 64 bytes per Message Buffer."]
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#[inline]
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pub fn _11(self) -> &'a mut W {
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self.variant(MBDSR0W::_11)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub fn bits(self, value: u8) -> &'a mut W {
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const MASK: u8 = 3;
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const OFFSET: u8 = 16;
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self.w.bits &= !((MASK as u32) << OFFSET);
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
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self.w
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}
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}
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#[doc = "Values that can be written to the field `FDRATE`"]
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pub enum FDRATEW {
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#[doc = "Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect."] _0,
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#[doc = "Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive."] _1,
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}
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impl FDRATEW {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> bool {
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match *self {
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FDRATEW::_0 => false,
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FDRATEW::_1 => true,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _FDRATEW<'a> {
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w: &'a mut W,
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}
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impl<'a> _FDRATEW<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: FDRATEW) -> &'a mut W {
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{
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self.bit(variant._bits())
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}
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}
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#[doc = "Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect."]
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#[inline]
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pub fn _0(self) -> &'a mut W {
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self.variant(FDRATEW::_0)
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}
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#[doc = "Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive."]
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#[inline]
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pub fn _1(self) -> &'a mut W {
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self.variant(FDRATEW::_1)
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}
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#[doc = r" Sets the field bit"]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r" Clears the field bit"]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub fn bit(self, value: bool) -> &'a mut W {
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const MASK: bool = true;
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const OFFSET: u8 = 31;
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self.w.bits &= !((MASK as u32) << OFFSET);
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
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self.w
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}
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}
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impl R {
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#[doc = r" Value of the register as raw bits"]
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#[inline]
|
|
pub fn bits(&self) -> u32 {
|
|
self.bits
|
|
}
|
|
#[doc = "Bits 0:5 - Transceiver Delay Compensation Value"]
|
|
#[inline]
|
|
pub fn tdcval(&self) -> TDCVALR {
|
|
let bits = {
|
|
const MASK: u8 = 63;
|
|
const OFFSET: u8 = 0;
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
|
};
|
|
TDCVALR { bits }
|
|
}
|
|
#[doc = "Bits 8:12 - Transceiver Delay Compensation Offset"]
|
|
#[inline]
|
|
pub fn tdcoff(&self) -> TDCOFFR {
|
|
let bits = {
|
|
const MASK: u8 = 31;
|
|
const OFFSET: u8 = 8;
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
|
};
|
|
TDCOFFR { bits }
|
|
}
|
|
#[doc = "Bit 14 - Transceiver Delay Compensation Fail"]
|
|
#[inline]
|
|
pub fn tdcfail(&self) -> TDCFAILR {
|
|
TDCFAILR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 14;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
#[doc = "Bit 15 - Transceiver Delay Compensation Enable"]
|
|
#[inline]
|
|
pub fn tdcen(&self) -> TDCENR {
|
|
TDCENR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 15;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
#[doc = "Bits 16:17 - Message Buffer Data Size for Region 0"]
|
|
#[inline]
|
|
pub fn mbdsr0(&self) -> MBDSR0R {
|
|
MBDSR0R::_from({
|
|
const MASK: u8 = 3;
|
|
const OFFSET: u8 = 16;
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
|
})
|
|
}
|
|
#[doc = "Bit 31 - Bit Rate Switch Enable"]
|
|
#[inline]
|
|
pub fn fdrate(&self) -> FDRATER {
|
|
FDRATER::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 31;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
}
|
|
impl W {
|
|
#[doc = r" Reset value of the register"]
|
|
#[inline]
|
|
pub fn reset_value() -> W {
|
|
W { bits: 2147483904 }
|
|
}
|
|
#[doc = r" Writes raw bits to the register"]
|
|
#[inline]
|
|
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
|
self.bits = bits;
|
|
self
|
|
}
|
|
#[doc = "Bits 8:12 - Transceiver Delay Compensation Offset"]
|
|
#[inline]
|
|
pub fn tdcoff(&mut self) -> _TDCOFFW {
|
|
_TDCOFFW { w: self }
|
|
}
|
|
#[doc = "Bit 14 - Transceiver Delay Compensation Fail"]
|
|
#[inline]
|
|
pub fn tdcfail(&mut self) -> _TDCFAILW {
|
|
_TDCFAILW { w: self }
|
|
}
|
|
#[doc = "Bit 15 - Transceiver Delay Compensation Enable"]
|
|
#[inline]
|
|
pub fn tdcen(&mut self) -> _TDCENW {
|
|
_TDCENW { w: self }
|
|
}
|
|
#[doc = "Bits 16:17 - Message Buffer Data Size for Region 0"]
|
|
#[inline]
|
|
pub fn mbdsr0(&mut self) -> _MBDSR0W {
|
|
_MBDSR0W { w: self }
|
|
}
|
|
#[doc = "Bit 31 - Bit Rate Switch Enable"]
|
|
#[inline]
|
|
pub fn fdrate(&mut self) -> _FDRATEW {
|
|
_FDRATEW { w: self }
|
|
}
|
|
}
|