198 lines
5.7 KiB
Rust
198 lines
5.7 KiB
Rust
#[doc = "Reader of register TRGMUX_FLEXIO"]
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pub type R = crate::R<u32, super::TRGMUX_FLEXIO>;
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#[doc = "Writer for register TRGMUX_FLEXIO"]
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pub type W = crate::W<u32, super::TRGMUX_FLEXIO>;
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#[doc = "Register TRGMUX_FLEXIO `reset()`'s with value 0"]
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impl crate::ResetValue for super::TRGMUX_FLEXIO {
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type Type = u32;
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#[inline(always)]
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fn reset_value() -> Self::Type {
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0
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}
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}
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#[doc = "Reader of field `SEL0`"]
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pub type SEL0_R = crate::R<u8, u8>;
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#[doc = "Write proxy for field `SEL0`"]
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pub struct SEL0_W<'a> {
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w: &'a mut W,
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}
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impl<'a> SEL0_W<'a> {
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub unsafe fn bits(self, value: u8) -> &'a mut W {
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self.w.bits = (self.w.bits & !0x3f) | ((value as u32) & 0x3f);
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self.w
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}
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}
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#[doc = "Reader of field `SEL1`"]
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pub type SEL1_R = crate::R<u8, u8>;
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#[doc = "Write proxy for field `SEL1`"]
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pub struct SEL1_W<'a> {
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w: &'a mut W,
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}
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impl<'a> SEL1_W<'a> {
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub unsafe fn bits(self, value: u8) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x3f << 8)) | (((value as u32) & 0x3f) << 8);
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self.w
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}
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}
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#[doc = "Reader of field `SEL2`"]
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pub type SEL2_R = crate::R<u8, u8>;
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#[doc = "Write proxy for field `SEL2`"]
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pub struct SEL2_W<'a> {
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w: &'a mut W,
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}
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impl<'a> SEL2_W<'a> {
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub unsafe fn bits(self, value: u8) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x3f << 16)) | (((value as u32) & 0x3f) << 16);
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self.w
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}
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}
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#[doc = "Reader of field `SEL3`"]
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pub type SEL3_R = crate::R<u8, u8>;
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#[doc = "Write proxy for field `SEL3`"]
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pub struct SEL3_W<'a> {
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w: &'a mut W,
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}
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impl<'a> SEL3_W<'a> {
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub unsafe fn bits(self, value: u8) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x3f << 24)) | (((value as u32) & 0x3f) << 24);
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self.w
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}
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}
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#[doc = "TRGMUX register lock.\n\nValue on reset: 0"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum LK_A {
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#[doc = "0: Register can be written."]
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_0 = 0,
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#[doc = "1: Register cannot be written until the next system Reset."]
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_1 = 1,
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}
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impl From<LK_A> for bool {
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#[inline(always)]
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fn from(variant: LK_A) -> Self {
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variant as u8 != 0
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}
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}
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#[doc = "Reader of field `LK`"]
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pub type LK_R = crate::R<bool, LK_A>;
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impl LK_R {
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#[doc = r"Get enumerated values variant"]
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#[inline(always)]
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pub fn variant(&self) -> LK_A {
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match self.bits {
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false => LK_A::_0,
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true => LK_A::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline(always)]
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pub fn is_0(&self) -> bool {
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*self == LK_A::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline(always)]
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pub fn is_1(&self) -> bool {
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*self == LK_A::_1
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}
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}
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#[doc = "Write proxy for field `LK`"]
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pub struct LK_W<'a> {
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w: &'a mut W,
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}
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impl<'a> LK_W<'a> {
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#[doc = r"Writes `variant` to the field"]
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#[inline(always)]
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pub fn variant(self, variant: LK_A) -> &'a mut W {
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{
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self.bit(variant.into())
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}
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}
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#[doc = "Register can be written."]
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#[inline(always)]
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pub fn _0(self) -> &'a mut W {
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self.variant(LK_A::_0)
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}
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#[doc = "Register cannot be written until the next system Reset."]
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#[inline(always)]
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pub fn _1(self) -> &'a mut W {
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self.variant(LK_A::_1)
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}
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
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self.w
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}
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}
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impl R {
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#[doc = "Bits 0:5 - Trigger MUX Input 0 Source Select"]
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#[inline(always)]
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pub fn sel0(&self) -> SEL0_R {
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SEL0_R::new((self.bits & 0x3f) as u8)
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}
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#[doc = "Bits 8:13 - Trigger MUX Input 1 Source Select"]
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#[inline(always)]
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pub fn sel1(&self) -> SEL1_R {
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SEL1_R::new(((self.bits >> 8) & 0x3f) as u8)
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}
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#[doc = "Bits 16:21 - Trigger MUX Input 2 Source Select"]
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#[inline(always)]
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pub fn sel2(&self) -> SEL2_R {
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SEL2_R::new(((self.bits >> 16) & 0x3f) as u8)
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}
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#[doc = "Bits 24:29 - Trigger MUX Input 3 Source Select"]
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#[inline(always)]
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pub fn sel3(&self) -> SEL3_R {
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SEL3_R::new(((self.bits >> 24) & 0x3f) as u8)
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}
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#[doc = "Bit 31 - TRGMUX register lock."]
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#[inline(always)]
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pub fn lk(&self) -> LK_R {
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LK_R::new(((self.bits >> 31) & 0x01) != 0)
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}
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}
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impl W {
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#[doc = "Bits 0:5 - Trigger MUX Input 0 Source Select"]
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#[inline(always)]
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pub fn sel0(&mut self) -> SEL0_W {
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SEL0_W { w: self }
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}
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#[doc = "Bits 8:13 - Trigger MUX Input 1 Source Select"]
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#[inline(always)]
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pub fn sel1(&mut self) -> SEL1_W {
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SEL1_W { w: self }
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}
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#[doc = "Bits 16:21 - Trigger MUX Input 2 Source Select"]
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#[inline(always)]
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pub fn sel2(&mut self) -> SEL2_W {
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SEL2_W { w: self }
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}
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#[doc = "Bits 24:29 - Trigger MUX Input 3 Source Select"]
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#[inline(always)]
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pub fn sel3(&mut self) -> SEL3_W {
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SEL3_W { w: self }
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}
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#[doc = "Bit 31 - TRGMUX register lock."]
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#[inline(always)]
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pub fn lk(&mut self) -> LK_W {
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LK_W { w: self }
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}
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}
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