51 lines
1.6 KiB
Rust
51 lines
1.6 KiB
Rust
#[doc = "Reader of register MISCTRL1"]
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pub type R = crate::R<u32, super::MISCTRL1>;
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#[doc = "Writer for register MISCTRL1"]
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pub type W = crate::W<u32, super::MISCTRL1>;
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#[doc = "Register MISCTRL1 `reset()`'s with value 0"]
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impl crate::ResetValue for super::MISCTRL1 {
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type Type = u32;
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#[inline(always)]
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fn reset_value() -> Self::Type {
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0
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}
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}
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#[doc = "Reader of field `SW_TRG`"]
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pub type SW_TRG_R = crate::R<bool, bool>;
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#[doc = "Write proxy for field `SW_TRG`"]
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pub struct SW_TRG_W<'a> {
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w: &'a mut W,
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}
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impl<'a> SW_TRG_W<'a> {
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
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self.w
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}
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}
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impl R {
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#[doc = "Bit 0 - Software trigger to TRGMUX. Writing to this bit generates software trigger to peripherals through TRGMUX (Refer to Figure: Trigger interconnectivity)."]
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#[inline(always)]
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pub fn sw_trg(&self) -> SW_TRG_R {
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SW_TRG_R::new((self.bits & 0x01) != 0)
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}
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}
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impl W {
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#[doc = "Bit 0 - Software trigger to TRGMUX. Writing to this bit generates software trigger to peripherals through TRGMUX (Refer to Figure: Trigger interconnectivity)."]
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#[inline(always)]
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pub fn sw_trg(&mut self) -> SW_TRG_W {
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SW_TRG_W { w: self }
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}
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}
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