373 lines
14 KiB
Rust
373 lines
14 KiB
Rust
#[doc = "Reader of register MISCTRL0"]
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pub type R = crate::R<u32, super::MISCTRL0>;
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#[doc = "Writer for register MISCTRL0"]
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pub type W = crate::W<u32, super::MISCTRL0>;
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#[doc = "Register MISCTRL0 `reset()`'s with value 0"]
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impl crate::ResetValue for super::MISCTRL0 {
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type Type = u32;
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#[inline(always)]
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fn reset_value() -> Self::Type {
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0
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}
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}
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#[doc = "FTM0 OBE CTRL bit\n\nValue on reset: 0"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum FTM0_OBE_CTRL_A {
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#[doc = "0: The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\]
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= 1'b1). Otherwise the channel output is tristated."]
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_0 = 0,
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#[doc = "1: The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\]
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or dual edge capture mode \\[DECAPEN=1'b1\\]."]
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_1 = 1,
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}
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impl From<FTM0_OBE_CTRL_A> for bool {
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#[inline(always)]
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fn from(variant: FTM0_OBE_CTRL_A) -> Self {
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variant as u8 != 0
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}
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}
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#[doc = "Reader of field `FTM0_OBE_CTRL`"]
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pub type FTM0_OBE_CTRL_R = crate::R<bool, FTM0_OBE_CTRL_A>;
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impl FTM0_OBE_CTRL_R {
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#[doc = r"Get enumerated values variant"]
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#[inline(always)]
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pub fn variant(&self) -> FTM0_OBE_CTRL_A {
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match self.bits {
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false => FTM0_OBE_CTRL_A::_0,
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true => FTM0_OBE_CTRL_A::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline(always)]
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pub fn is_0(&self) -> bool {
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*self == FTM0_OBE_CTRL_A::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline(always)]
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pub fn is_1(&self) -> bool {
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*self == FTM0_OBE_CTRL_A::_1
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}
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}
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#[doc = "Write proxy for field `FTM0_OBE_CTRL`"]
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pub struct FTM0_OBE_CTRL_W<'a> {
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w: &'a mut W,
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}
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impl<'a> FTM0_OBE_CTRL_W<'a> {
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#[doc = r"Writes `variant` to the field"]
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#[inline(always)]
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pub fn variant(self, variant: FTM0_OBE_CTRL_A) -> &'a mut W {
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{
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self.bit(variant.into())
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}
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}
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#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\]
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= 1'b1). Otherwise the channel output is tristated."]
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#[inline(always)]
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pub fn _0(self) -> &'a mut W {
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self.variant(FTM0_OBE_CTRL_A::_0)
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}
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#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\]
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or dual edge capture mode \\[DECAPEN=1'b1\\]."]
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#[inline(always)]
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pub fn _1(self) -> &'a mut W {
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self.variant(FTM0_OBE_CTRL_A::_1)
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}
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
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self.w
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}
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}
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#[doc = "FTM1 OBE CTRL bit\n\nValue on reset: 0"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum FTM1_OBE_CTRL_A {
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#[doc = "0: The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\]
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= 1'b1). Otherwise the channel output is tristated."]
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_0 = 0,
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#[doc = "1: The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\]
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or dual edge capture mode \\[DECAPEN=1'b1\\]."]
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_1 = 1,
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}
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impl From<FTM1_OBE_CTRL_A> for bool {
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#[inline(always)]
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fn from(variant: FTM1_OBE_CTRL_A) -> Self {
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variant as u8 != 0
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}
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}
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#[doc = "Reader of field `FTM1_OBE_CTRL`"]
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pub type FTM1_OBE_CTRL_R = crate::R<bool, FTM1_OBE_CTRL_A>;
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impl FTM1_OBE_CTRL_R {
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#[doc = r"Get enumerated values variant"]
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#[inline(always)]
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pub fn variant(&self) -> FTM1_OBE_CTRL_A {
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match self.bits {
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false => FTM1_OBE_CTRL_A::_0,
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true => FTM1_OBE_CTRL_A::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline(always)]
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pub fn is_0(&self) -> bool {
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*self == FTM1_OBE_CTRL_A::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline(always)]
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pub fn is_1(&self) -> bool {
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*self == FTM1_OBE_CTRL_A::_1
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}
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}
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#[doc = "Write proxy for field `FTM1_OBE_CTRL`"]
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pub struct FTM1_OBE_CTRL_W<'a> {
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w: &'a mut W,
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}
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impl<'a> FTM1_OBE_CTRL_W<'a> {
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#[doc = r"Writes `variant` to the field"]
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#[inline(always)]
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pub fn variant(self, variant: FTM1_OBE_CTRL_A) -> &'a mut W {
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{
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self.bit(variant.into())
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}
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}
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#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\]
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= 1'b1). Otherwise the channel output is tristated."]
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#[inline(always)]
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pub fn _0(self) -> &'a mut W {
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self.variant(FTM1_OBE_CTRL_A::_0)
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}
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#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\]
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or dual edge capture mode \\[DECAPEN=1'b1\\]."]
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#[inline(always)]
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pub fn _1(self) -> &'a mut W {
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self.variant(FTM1_OBE_CTRL_A::_1)
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}
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
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self.w
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}
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}
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#[doc = "FTM2 OBE CTRL bit\n\nValue on reset: 0"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum FTM2_OBE_CTRL_A {
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#[doc = "0: The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\]
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= 1'b1). Otherwise the channel output is tristated."]
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_0 = 0,
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#[doc = "1: The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\]
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or dual edge capture mode \\[DECAPEN=1'b1\\]."]
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_1 = 1,
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}
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impl From<FTM2_OBE_CTRL_A> for bool {
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#[inline(always)]
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fn from(variant: FTM2_OBE_CTRL_A) -> Self {
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variant as u8 != 0
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}
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}
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#[doc = "Reader of field `FTM2_OBE_CTRL`"]
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pub type FTM2_OBE_CTRL_R = crate::R<bool, FTM2_OBE_CTRL_A>;
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impl FTM2_OBE_CTRL_R {
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#[doc = r"Get enumerated values variant"]
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#[inline(always)]
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pub fn variant(&self) -> FTM2_OBE_CTRL_A {
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match self.bits {
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false => FTM2_OBE_CTRL_A::_0,
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true => FTM2_OBE_CTRL_A::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline(always)]
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pub fn is_0(&self) -> bool {
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*self == FTM2_OBE_CTRL_A::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline(always)]
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pub fn is_1(&self) -> bool {
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*self == FTM2_OBE_CTRL_A::_1
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}
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}
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#[doc = "Write proxy for field `FTM2_OBE_CTRL`"]
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pub struct FTM2_OBE_CTRL_W<'a> {
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w: &'a mut W,
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}
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impl<'a> FTM2_OBE_CTRL_W<'a> {
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#[doc = r"Writes `variant` to the field"]
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#[inline(always)]
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pub fn variant(self, variant: FTM2_OBE_CTRL_A) -> &'a mut W {
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{
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self.bit(variant.into())
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}
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}
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#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\]
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= 1'b1). Otherwise the channel output is tristated."]
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#[inline(always)]
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pub fn _0(self) -> &'a mut W {
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self.variant(FTM2_OBE_CTRL_A::_0)
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}
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#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\]
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or dual edge capture mode \\[DECAPEN=1'b1\\]."]
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#[inline(always)]
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pub fn _1(self) -> &'a mut W {
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self.variant(FTM2_OBE_CTRL_A::_1)
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}
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
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self.w
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}
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}
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#[doc = "FTM3 OBE CTRL bit\n\nValue on reset: 0"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum FTM3_OBE_CTRL_A {
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#[doc = "0: The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\]
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= 1'b1). Otherwise the channel output is tristated."]
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_0 = 0,
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#[doc = "1: The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\]
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or dual edge capture mode \\[DECAPEN=1'b1\\]."]
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_1 = 1,
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}
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impl From<FTM3_OBE_CTRL_A> for bool {
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#[inline(always)]
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fn from(variant: FTM3_OBE_CTRL_A) -> Self {
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variant as u8 != 0
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}
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}
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#[doc = "Reader of field `FTM3_OBE_CTRL`"]
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pub type FTM3_OBE_CTRL_R = crate::R<bool, FTM3_OBE_CTRL_A>;
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impl FTM3_OBE_CTRL_R {
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#[doc = r"Get enumerated values variant"]
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#[inline(always)]
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pub fn variant(&self) -> FTM3_OBE_CTRL_A {
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match self.bits {
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false => FTM3_OBE_CTRL_A::_0,
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true => FTM3_OBE_CTRL_A::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline(always)]
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pub fn is_0(&self) -> bool {
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*self == FTM3_OBE_CTRL_A::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline(always)]
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pub fn is_1(&self) -> bool {
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*self == FTM3_OBE_CTRL_A::_1
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}
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}
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#[doc = "Write proxy for field `FTM3_OBE_CTRL`"]
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pub struct FTM3_OBE_CTRL_W<'a> {
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w: &'a mut W,
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}
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impl<'a> FTM3_OBE_CTRL_W<'a> {
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#[doc = r"Writes `variant` to the field"]
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#[inline(always)]
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pub fn variant(self, variant: FTM3_OBE_CTRL_A) -> &'a mut W {
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{
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self.bit(variant.into())
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}
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}
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#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\]
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= 1'b1). Otherwise the channel output is tristated."]
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#[inline(always)]
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pub fn _0(self) -> &'a mut W {
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self.variant(FTM3_OBE_CTRL_A::_0)
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}
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#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\]
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or dual edge capture mode \\[DECAPEN=1'b1\\]."]
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#[inline(always)]
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pub fn _1(self) -> &'a mut W {
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self.variant(FTM3_OBE_CTRL_A::_1)
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}
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
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self.w
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}
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}
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impl R {
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#[doc = "Bit 16 - FTM0 OBE CTRL bit"]
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#[inline(always)]
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pub fn ftm0_obe_ctrl(&self) -> FTM0_OBE_CTRL_R {
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FTM0_OBE_CTRL_R::new(((self.bits >> 16) & 0x01) != 0)
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}
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#[doc = "Bit 17 - FTM1 OBE CTRL bit"]
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#[inline(always)]
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pub fn ftm1_obe_ctrl(&self) -> FTM1_OBE_CTRL_R {
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FTM1_OBE_CTRL_R::new(((self.bits >> 17) & 0x01) != 0)
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}
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#[doc = "Bit 18 - FTM2 OBE CTRL bit"]
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#[inline(always)]
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pub fn ftm2_obe_ctrl(&self) -> FTM2_OBE_CTRL_R {
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FTM2_OBE_CTRL_R::new(((self.bits >> 18) & 0x01) != 0)
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}
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#[doc = "Bit 19 - FTM3 OBE CTRL bit"]
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#[inline(always)]
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pub fn ftm3_obe_ctrl(&self) -> FTM3_OBE_CTRL_R {
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FTM3_OBE_CTRL_R::new(((self.bits >> 19) & 0x01) != 0)
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}
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}
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impl W {
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#[doc = "Bit 16 - FTM0 OBE CTRL bit"]
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#[inline(always)]
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pub fn ftm0_obe_ctrl(&mut self) -> FTM0_OBE_CTRL_W {
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FTM0_OBE_CTRL_W { w: self }
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}
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#[doc = "Bit 17 - FTM1 OBE CTRL bit"]
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#[inline(always)]
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pub fn ftm1_obe_ctrl(&mut self) -> FTM1_OBE_CTRL_W {
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FTM1_OBE_CTRL_W { w: self }
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}
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#[doc = "Bit 18 - FTM2 OBE CTRL bit"]
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#[inline(always)]
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pub fn ftm2_obe_ctrl(&mut self) -> FTM2_OBE_CTRL_W {
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FTM2_OBE_CTRL_W { w: self }
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}
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#[doc = "Bit 19 - FTM3 OBE CTRL bit"]
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#[inline(always)]
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pub fn ftm3_obe_ctrl(&mut self) -> FTM3_OBE_CTRL_W {
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FTM3_OBE_CTRL_W { w: self }
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}
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}
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