357 lines
10 KiB
Rust
357 lines
10 KiB
Rust
#[doc = "Reader of register LR"]
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pub type R = crate::R<u32, super::LR>;
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#[doc = "Writer for register LR"]
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pub type W = crate::W<u32, super::LR>;
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#[doc = "Register LR `reset()`'s with value 0xff"]
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impl crate::ResetValue for super::LR {
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type Type = u32;
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#[inline(always)]
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fn reset_value() -> Self::Type {
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0xff
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}
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}
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#[doc = "Time Compensation Lock\n\nValue on reset: 1"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum TCL_A {
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#[doc = "0: Time Compensation Register is locked and writes are ignored."]
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_0 = 0,
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#[doc = "1: Time Compensation Register is not locked and writes complete as normal."]
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_1 = 1,
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}
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impl From<TCL_A> for bool {
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#[inline(always)]
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fn from(variant: TCL_A) -> Self {
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variant as u8 != 0
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}
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}
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#[doc = "Reader of field `TCL`"]
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pub type TCL_R = crate::R<bool, TCL_A>;
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impl TCL_R {
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#[doc = r"Get enumerated values variant"]
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#[inline(always)]
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pub fn variant(&self) -> TCL_A {
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match self.bits {
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false => TCL_A::_0,
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true => TCL_A::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline(always)]
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pub fn is_0(&self) -> bool {
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*self == TCL_A::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline(always)]
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pub fn is_1(&self) -> bool {
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*self == TCL_A::_1
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}
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}
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#[doc = "Write proxy for field `TCL`"]
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pub struct TCL_W<'a> {
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w: &'a mut W,
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}
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impl<'a> TCL_W<'a> {
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#[doc = r"Writes `variant` to the field"]
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#[inline(always)]
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pub fn variant(self, variant: TCL_A) -> &'a mut W {
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{
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self.bit(variant.into())
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}
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}
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#[doc = "Time Compensation Register is locked and writes are ignored."]
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#[inline(always)]
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pub fn _0(self) -> &'a mut W {
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self.variant(TCL_A::_0)
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}
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#[doc = "Time Compensation Register is not locked and writes complete as normal."]
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#[inline(always)]
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pub fn _1(self) -> &'a mut W {
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self.variant(TCL_A::_1)
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}
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
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self.w
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}
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}
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#[doc = "Control Register Lock\n\nValue on reset: 1"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum CRL_A {
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#[doc = "0: Control Register is locked and writes are ignored."]
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_0 = 0,
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#[doc = "1: Control Register is not locked and writes complete as normal."]
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_1 = 1,
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}
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impl From<CRL_A> for bool {
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#[inline(always)]
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fn from(variant: CRL_A) -> Self {
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variant as u8 != 0
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}
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}
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#[doc = "Reader of field `CRL`"]
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pub type CRL_R = crate::R<bool, CRL_A>;
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impl CRL_R {
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#[doc = r"Get enumerated values variant"]
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#[inline(always)]
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pub fn variant(&self) -> CRL_A {
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match self.bits {
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false => CRL_A::_0,
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true => CRL_A::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline(always)]
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pub fn is_0(&self) -> bool {
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*self == CRL_A::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline(always)]
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pub fn is_1(&self) -> bool {
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*self == CRL_A::_1
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}
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}
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#[doc = "Write proxy for field `CRL`"]
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pub struct CRL_W<'a> {
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w: &'a mut W,
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}
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impl<'a> CRL_W<'a> {
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#[doc = r"Writes `variant` to the field"]
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#[inline(always)]
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pub fn variant(self, variant: CRL_A) -> &'a mut W {
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{
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self.bit(variant.into())
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}
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}
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#[doc = "Control Register is locked and writes are ignored."]
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#[inline(always)]
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pub fn _0(self) -> &'a mut W {
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self.variant(CRL_A::_0)
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}
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#[doc = "Control Register is not locked and writes complete as normal."]
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#[inline(always)]
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pub fn _1(self) -> &'a mut W {
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self.variant(CRL_A::_1)
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}
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
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self.w
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}
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}
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#[doc = "Status Register Lock\n\nValue on reset: 1"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SRL_A {
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#[doc = "0: Status Register is locked and writes are ignored."]
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_0 = 0,
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#[doc = "1: Status Register is not locked and writes complete as normal."]
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_1 = 1,
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}
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impl From<SRL_A> for bool {
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#[inline(always)]
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fn from(variant: SRL_A) -> Self {
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variant as u8 != 0
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}
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}
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#[doc = "Reader of field `SRL`"]
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pub type SRL_R = crate::R<bool, SRL_A>;
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impl SRL_R {
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#[doc = r"Get enumerated values variant"]
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#[inline(always)]
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pub fn variant(&self) -> SRL_A {
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match self.bits {
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false => SRL_A::_0,
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true => SRL_A::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline(always)]
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pub fn is_0(&self) -> bool {
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*self == SRL_A::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline(always)]
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pub fn is_1(&self) -> bool {
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*self == SRL_A::_1
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}
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}
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#[doc = "Write proxy for field `SRL`"]
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pub struct SRL_W<'a> {
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w: &'a mut W,
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}
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impl<'a> SRL_W<'a> {
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#[doc = r"Writes `variant` to the field"]
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#[inline(always)]
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pub fn variant(self, variant: SRL_A) -> &'a mut W {
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{
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self.bit(variant.into())
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}
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}
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#[doc = "Status Register is locked and writes are ignored."]
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#[inline(always)]
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pub fn _0(self) -> &'a mut W {
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self.variant(SRL_A::_0)
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}
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#[doc = "Status Register is not locked and writes complete as normal."]
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#[inline(always)]
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pub fn _1(self) -> &'a mut W {
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self.variant(SRL_A::_1)
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}
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
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self.w
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}
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}
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#[doc = "Lock Register Lock\n\nValue on reset: 1"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum LRL_A {
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#[doc = "0: Lock Register is locked and writes are ignored."]
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_0 = 0,
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#[doc = "1: Lock Register is not locked and writes complete as normal."]
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_1 = 1,
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}
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impl From<LRL_A> for bool {
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#[inline(always)]
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fn from(variant: LRL_A) -> Self {
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variant as u8 != 0
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}
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}
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#[doc = "Reader of field `LRL`"]
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pub type LRL_R = crate::R<bool, LRL_A>;
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impl LRL_R {
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#[doc = r"Get enumerated values variant"]
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#[inline(always)]
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pub fn variant(&self) -> LRL_A {
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match self.bits {
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false => LRL_A::_0,
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true => LRL_A::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline(always)]
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pub fn is_0(&self) -> bool {
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*self == LRL_A::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline(always)]
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pub fn is_1(&self) -> bool {
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*self == LRL_A::_1
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}
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}
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#[doc = "Write proxy for field `LRL`"]
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pub struct LRL_W<'a> {
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w: &'a mut W,
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}
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impl<'a> LRL_W<'a> {
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#[doc = r"Writes `variant` to the field"]
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#[inline(always)]
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pub fn variant(self, variant: LRL_A) -> &'a mut W {
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{
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self.bit(variant.into())
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}
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}
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#[doc = "Lock Register is locked and writes are ignored."]
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#[inline(always)]
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pub fn _0(self) -> &'a mut W {
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self.variant(LRL_A::_0)
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}
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#[doc = "Lock Register is not locked and writes complete as normal."]
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#[inline(always)]
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pub fn _1(self) -> &'a mut W {
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self.variant(LRL_A::_1)
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}
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
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self.w
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}
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}
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impl R {
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#[doc = "Bit 3 - Time Compensation Lock"]
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#[inline(always)]
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pub fn tcl(&self) -> TCL_R {
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TCL_R::new(((self.bits >> 3) & 0x01) != 0)
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}
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#[doc = "Bit 4 - Control Register Lock"]
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#[inline(always)]
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pub fn crl(&self) -> CRL_R {
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CRL_R::new(((self.bits >> 4) & 0x01) != 0)
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}
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#[doc = "Bit 5 - Status Register Lock"]
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#[inline(always)]
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pub fn srl(&self) -> SRL_R {
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SRL_R::new(((self.bits >> 5) & 0x01) != 0)
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}
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#[doc = "Bit 6 - Lock Register Lock"]
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#[inline(always)]
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pub fn lrl(&self) -> LRL_R {
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LRL_R::new(((self.bits >> 6) & 0x01) != 0)
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}
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}
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impl W {
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#[doc = "Bit 3 - Time Compensation Lock"]
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#[inline(always)]
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pub fn tcl(&mut self) -> TCL_W {
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TCL_W { w: self }
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}
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#[doc = "Bit 4 - Control Register Lock"]
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#[inline(always)]
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pub fn crl(&mut self) -> CRL_W {
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CRL_W { w: self }
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}
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#[doc = "Bit 5 - Status Register Lock"]
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#[inline(always)]
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pub fn srl(&mut self) -> SRL_W {
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SRL_W { w: self }
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}
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#[doc = "Bit 6 - Lock Register Lock"]
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#[inline(always)]
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pub fn lrl(&mut self) -> LRL_W {
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LRL_W { w: self }
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}
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}
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