93 lines
3.3 KiB
Rust
93 lines
3.3 KiB
Rust
#[doc = "Reader of register ISFR"]
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pub type R = crate::R<u32, super::ISFR>;
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#[doc = "Writer for register ISFR"]
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pub type W = crate::W<u32, super::ISFR>;
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#[doc = "Register ISFR `reset()`'s with value 0"]
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impl crate::ResetValue for super::ISFR {
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type Type = u32;
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#[inline(always)]
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fn reset_value() -> Self::Type {
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0
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}
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}
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#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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#[repr(u32)]
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pub enum ISF_A {
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#[doc = "0: Configured interrupt is not detected."]
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_0 = 0,
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#[doc = "1: Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
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_1 = 1,
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}
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impl From<ISF_A> for u32 {
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#[inline(always)]
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fn from(variant: ISF_A) -> Self {
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variant as _
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}
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}
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#[doc = "Reader of field `ISF`"]
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pub type ISF_R = crate::R<u32, ISF_A>;
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impl ISF_R {
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#[doc = r"Get enumerated values variant"]
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#[inline(always)]
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pub fn variant(&self) -> crate::Variant<u32, ISF_A> {
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use crate::Variant::*;
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match self.bits {
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0 => Val(ISF_A::_0),
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1 => Val(ISF_A::_1),
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i => Res(i),
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline(always)]
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pub fn is_0(&self) -> bool {
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*self == ISF_A::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline(always)]
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pub fn is_1(&self) -> bool {
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*self == ISF_A::_1
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}
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}
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#[doc = "Write proxy for field `ISF`"]
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pub struct ISF_W<'a> {
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w: &'a mut W,
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}
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impl<'a> ISF_W<'a> {
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#[doc = r"Writes `variant` to the field"]
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#[inline(always)]
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pub fn variant(self, variant: ISF_A) -> &'a mut W {
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unsafe { self.bits(variant.into()) }
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}
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#[doc = "Configured interrupt is not detected."]
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#[inline(always)]
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pub fn _0(self) -> &'a mut W {
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self.variant(ISF_A::_0)
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}
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#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
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#[inline(always)]
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pub fn _1(self) -> &'a mut W {
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self.variant(ISF_A::_1)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub unsafe fn bits(self, value: u32) -> &'a mut W {
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self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
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self.w
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}
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}
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impl R {
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#[doc = "Bits 0:31 - Interrupt Status Flag"]
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#[inline(always)]
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pub fn isf(&self) -> ISF_R {
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ISF_R::new((self.bits & 0xffff_ffff) as u32)
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}
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}
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impl W {
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#[doc = "Bits 0:31 - Interrupt Status Flag"]
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#[inline(always)]
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pub fn isf(&mut self) -> ISF_W {
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ISF_W { w: self }
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}
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}
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