120 lines
3.6 KiB
Rust
120 lines
3.6 KiB
Rust
#[doc = "Reader of register PINCFG"]
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pub type R = crate::R<u32, super::PINCFG>;
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#[doc = "Writer for register PINCFG"]
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pub type W = crate::W<u32, super::PINCFG>;
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#[doc = "Register PINCFG `reset()`'s with value 0"]
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impl crate::ResetValue for super::PINCFG {
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type Type = u32;
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#[inline(always)]
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fn reset_value() -> Self::Type {
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0
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}
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}
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#[doc = "Trigger Select\n\nValue on reset: 0"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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#[repr(u8)]
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pub enum TRGSEL_A {
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#[doc = "0: Input trigger is disabled."]
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_00 = 0,
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#[doc = "1: Input trigger is used instead of RXD pin input."]
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_01 = 1,
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#[doc = "2: Input trigger is used instead of CTS_B pin input."]
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_10 = 2,
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#[doc = "3: Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger."]
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_11 = 3,
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}
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impl From<TRGSEL_A> for u8 {
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#[inline(always)]
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fn from(variant: TRGSEL_A) -> Self {
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variant as _
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}
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}
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#[doc = "Reader of field `TRGSEL`"]
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pub type TRGSEL_R = crate::R<u8, TRGSEL_A>;
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impl TRGSEL_R {
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#[doc = r"Get enumerated values variant"]
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#[inline(always)]
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pub fn variant(&self) -> TRGSEL_A {
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match self.bits {
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0 => TRGSEL_A::_00,
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1 => TRGSEL_A::_01,
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2 => TRGSEL_A::_10,
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3 => TRGSEL_A::_11,
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_ => unreachable!(),
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}
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}
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#[doc = "Checks if the value of the field is `_00`"]
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#[inline(always)]
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pub fn is_00(&self) -> bool {
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*self == TRGSEL_A::_00
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}
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#[doc = "Checks if the value of the field is `_01`"]
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#[inline(always)]
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pub fn is_01(&self) -> bool {
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*self == TRGSEL_A::_01
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}
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#[doc = "Checks if the value of the field is `_10`"]
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#[inline(always)]
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pub fn is_10(&self) -> bool {
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*self == TRGSEL_A::_10
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}
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#[doc = "Checks if the value of the field is `_11`"]
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#[inline(always)]
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pub fn is_11(&self) -> bool {
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*self == TRGSEL_A::_11
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}
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}
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#[doc = "Write proxy for field `TRGSEL`"]
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pub struct TRGSEL_W<'a> {
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w: &'a mut W,
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}
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impl<'a> TRGSEL_W<'a> {
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#[doc = r"Writes `variant` to the field"]
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#[inline(always)]
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pub fn variant(self, variant: TRGSEL_A) -> &'a mut W {
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{
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self.bits(variant.into())
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}
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}
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#[doc = "Input trigger is disabled."]
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#[inline(always)]
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pub fn _00(self) -> &'a mut W {
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self.variant(TRGSEL_A::_00)
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}
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#[doc = "Input trigger is used instead of RXD pin input."]
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#[inline(always)]
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pub fn _01(self) -> &'a mut W {
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self.variant(TRGSEL_A::_01)
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}
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#[doc = "Input trigger is used instead of CTS_B pin input."]
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#[inline(always)]
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pub fn _10(self) -> &'a mut W {
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self.variant(TRGSEL_A::_10)
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}
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#[doc = "Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger."]
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#[inline(always)]
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pub fn _11(self) -> &'a mut W {
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self.variant(TRGSEL_A::_11)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bits(self, value: u8) -> &'a mut W {
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self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
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self.w
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}
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}
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impl R {
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#[doc = "Bits 0:1 - Trigger Select"]
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#[inline(always)]
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pub fn trgsel(&self) -> TRGSEL_R {
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TRGSEL_R::new((self.bits & 0x03) as u8)
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}
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}
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impl W {
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#[doc = "Bits 0:1 - Trigger Select"]
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#[inline(always)]
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pub fn trgsel(&mut self) -> TRGSEL_W {
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TRGSEL_W { w: self }
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}
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}
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