211 lines
6.5 KiB
Rust
211 lines
6.5 KiB
Rust
#[doc = "Reader of register CHCFG3"]
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pub type R = crate::R<u8, super::CHCFG3>;
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#[doc = "Writer for register CHCFG3"]
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pub type W = crate::W<u8, super::CHCFG3>;
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#[doc = "Register CHCFG3 `reset()`'s with value 0"]
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impl crate::ResetValue for super::CHCFG3 {
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type Type = u8;
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#[inline(always)]
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fn reset_value() -> Self::Type {
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0
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}
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}
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#[doc = "Reader of field `SOURCE`"]
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pub type SOURCE_R = crate::R<u8, u8>;
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#[doc = "Write proxy for field `SOURCE`"]
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pub struct SOURCE_W<'a> {
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w: &'a mut W,
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}
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impl<'a> SOURCE_W<'a> {
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub unsafe fn bits(self, value: u8) -> &'a mut W {
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self.w.bits = (self.w.bits & !0x3f) | ((value as u8) & 0x3f);
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self.w
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}
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}
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#[doc = "DMA Channel Trigger Enable\n\nValue on reset: 0"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum TRIG_A {
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#[doc = "0: Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)"]
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_0 = 0,
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#[doc = "1: Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode."]
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_1 = 1,
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}
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impl From<TRIG_A> for bool {
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#[inline(always)]
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fn from(variant: TRIG_A) -> Self {
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variant as u8 != 0
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}
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}
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#[doc = "Reader of field `TRIG`"]
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pub type TRIG_R = crate::R<bool, TRIG_A>;
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impl TRIG_R {
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#[doc = r"Get enumerated values variant"]
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#[inline(always)]
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pub fn variant(&self) -> TRIG_A {
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match self.bits {
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false => TRIG_A::_0,
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true => TRIG_A::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline(always)]
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pub fn is_0(&self) -> bool {
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*self == TRIG_A::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline(always)]
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pub fn is_1(&self) -> bool {
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*self == TRIG_A::_1
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}
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}
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#[doc = "Write proxy for field `TRIG`"]
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pub struct TRIG_W<'a> {
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w: &'a mut W,
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}
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impl<'a> TRIG_W<'a> {
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#[doc = r"Writes `variant` to the field"]
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#[inline(always)]
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pub fn variant(self, variant: TRIG_A) -> &'a mut W {
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{
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self.bit(variant.into())
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}
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}
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#[doc = "Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)"]
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#[inline(always)]
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pub fn _0(self) -> &'a mut W {
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self.variant(TRIG_A::_0)
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}
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#[doc = "Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode."]
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#[inline(always)]
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pub fn _1(self) -> &'a mut W {
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self.variant(TRIG_A::_1)
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}
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u8) & 0x01) << 6);
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self.w
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}
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}
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#[doc = "DMA Channel Enable\n\nValue on reset: 0"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ENBL_A {
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#[doc = "0: DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."]
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_0 = 0,
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#[doc = "1: DMA channel is enabled"]
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_1 = 1,
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}
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impl From<ENBL_A> for bool {
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#[inline(always)]
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fn from(variant: ENBL_A) -> Self {
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variant as u8 != 0
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}
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}
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#[doc = "Reader of field `ENBL`"]
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pub type ENBL_R = crate::R<bool, ENBL_A>;
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impl ENBL_R {
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#[doc = r"Get enumerated values variant"]
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#[inline(always)]
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pub fn variant(&self) -> ENBL_A {
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match self.bits {
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false => ENBL_A::_0,
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true => ENBL_A::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline(always)]
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pub fn is_0(&self) -> bool {
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*self == ENBL_A::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline(always)]
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pub fn is_1(&self) -> bool {
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*self == ENBL_A::_1
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}
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}
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#[doc = "Write proxy for field `ENBL`"]
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pub struct ENBL_W<'a> {
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w: &'a mut W,
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}
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impl<'a> ENBL_W<'a> {
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#[doc = r"Writes `variant` to the field"]
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#[inline(always)]
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pub fn variant(self, variant: ENBL_A) -> &'a mut W {
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{
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self.bit(variant.into())
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}
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}
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#[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."]
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#[inline(always)]
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pub fn _0(self) -> &'a mut W {
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self.variant(ENBL_A::_0)
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}
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#[doc = "DMA channel is enabled"]
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#[inline(always)]
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pub fn _1(self) -> &'a mut W {
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self.variant(ENBL_A::_1)
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}
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u8) & 0x01) << 7);
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self.w
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}
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}
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impl R {
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#[doc = "Bits 0:5 - DMA Channel Source (Slot)"]
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#[inline(always)]
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pub fn source(&self) -> SOURCE_R {
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SOURCE_R::new((self.bits & 0x3f) as u8)
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}
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#[doc = "Bit 6 - DMA Channel Trigger Enable"]
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#[inline(always)]
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pub fn trig(&self) -> TRIG_R {
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TRIG_R::new(((self.bits >> 6) & 0x01) != 0)
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}
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#[doc = "Bit 7 - DMA Channel Enable"]
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#[inline(always)]
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pub fn enbl(&self) -> ENBL_R {
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ENBL_R::new(((self.bits >> 7) & 0x01) != 0)
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}
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}
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impl W {
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#[doc = "Bits 0:5 - DMA Channel Source (Slot)"]
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#[inline(always)]
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pub fn source(&mut self) -> SOURCE_W {
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SOURCE_W { w: self }
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}
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#[doc = "Bit 6 - DMA Channel Trigger Enable"]
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#[inline(always)]
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pub fn trig(&mut self) -> TRIG_W {
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TRIG_W { w: self }
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}
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#[doc = "Bit 7 - DMA Channel Enable"]
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#[inline(always)]
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pub fn enbl(&mut self) -> ENBL_W {
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ENBL_W { w: self }
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}
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}
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