s32k118.rs/src/cse_pram/_embedded_ram17hl.rs

41 lines
1.2 KiB
Rust

#[doc = "Reader of register _EmbeddedRAM17HL"]
pub type R = crate::R<u8, super::_EMBEDDEDRAM17HL>;
#[doc = "Writer for register _EmbeddedRAM17HL"]
pub type W = crate::W<u8, super::_EMBEDDEDRAM17HL>;
#[doc = "Register _EmbeddedRAM17HL `reset()`'s with value 0"]
impl crate::ResetValue for super::_EMBEDDEDRAM17HL {
type Type = u8;
#[inline(always)]
fn reset_value() -> Self::Type {
0
}
}
#[doc = "Reader of field `RAM_HL`"]
pub type RAM_HL_R = crate::R<u8, u8>;
#[doc = "Write proxy for field `RAM_HL`"]
pub struct RAM_HL_W<'a> {
w: &'a mut W,
}
impl<'a> RAM_HL_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !0xff) | ((value as u8) & 0xff);
self.w
}
}
impl R {
#[doc = "Bits 0:7 - RAM_HL stores the third 8 bits of the 32 bit CRC"]
#[inline(always)]
pub fn ram_hl(&self) -> RAM_HL_R {
RAM_HL_R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - RAM_HL stores the third 8 bits of the 32 bit CRC"]
#[inline(always)]
pub fn ram_hl(&mut self) -> RAM_HL_W {
RAM_HL_W { w: self }
}
}