339 lines
9.7 KiB
Rust
339 lines
9.7 KiB
Rust
#[doc = "Reader of register CFG1"]
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pub type R = crate::R<u32, super::CFG1>;
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#[doc = "Writer for register CFG1"]
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pub type W = crate::W<u32, super::CFG1>;
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#[doc = "Register CFG1 `reset()`'s with value 0"]
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impl crate::ResetValue for super::CFG1 {
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type Type = u32;
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#[inline(always)]
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fn reset_value() -> Self::Type {
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0
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}
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}
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#[doc = "Input Clock Select\n\nValue on reset: 0"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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#[repr(u8)]
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pub enum ADICLK_A {
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#[doc = "0: Alternate clock 1 (ADC_ALTCLK1)"]
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_00 = 0,
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#[doc = "1: Alternate clock 2 (ADC_ALTCLK2)"]
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_01 = 1,
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#[doc = "2: Alternate clock 3 (ADC_ALTCLK3)"]
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_10 = 2,
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#[doc = "3: Alternate clock 4 (ADC_ALTCLK4)"]
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_11 = 3,
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}
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impl From<ADICLK_A> for u8 {
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#[inline(always)]
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fn from(variant: ADICLK_A) -> Self {
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variant as _
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}
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}
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#[doc = "Reader of field `ADICLK`"]
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pub type ADICLK_R = crate::R<u8, ADICLK_A>;
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impl ADICLK_R {
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#[doc = r"Get enumerated values variant"]
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#[inline(always)]
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pub fn variant(&self) -> ADICLK_A {
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match self.bits {
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0 => ADICLK_A::_00,
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1 => ADICLK_A::_01,
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2 => ADICLK_A::_10,
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3 => ADICLK_A::_11,
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_ => unreachable!(),
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}
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}
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#[doc = "Checks if the value of the field is `_00`"]
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#[inline(always)]
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pub fn is_00(&self) -> bool {
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*self == ADICLK_A::_00
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}
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#[doc = "Checks if the value of the field is `_01`"]
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#[inline(always)]
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pub fn is_01(&self) -> bool {
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*self == ADICLK_A::_01
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}
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#[doc = "Checks if the value of the field is `_10`"]
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#[inline(always)]
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pub fn is_10(&self) -> bool {
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*self == ADICLK_A::_10
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}
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#[doc = "Checks if the value of the field is `_11`"]
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#[inline(always)]
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pub fn is_11(&self) -> bool {
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*self == ADICLK_A::_11
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}
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}
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#[doc = "Write proxy for field `ADICLK`"]
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pub struct ADICLK_W<'a> {
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w: &'a mut W,
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}
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impl<'a> ADICLK_W<'a> {
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#[doc = r"Writes `variant` to the field"]
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#[inline(always)]
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pub fn variant(self, variant: ADICLK_A) -> &'a mut W {
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{
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self.bits(variant.into())
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}
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}
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#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
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#[inline(always)]
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pub fn _00(self) -> &'a mut W {
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self.variant(ADICLK_A::_00)
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}
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#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
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#[inline(always)]
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pub fn _01(self) -> &'a mut W {
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self.variant(ADICLK_A::_01)
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}
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#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
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#[inline(always)]
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pub fn _10(self) -> &'a mut W {
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self.variant(ADICLK_A::_10)
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}
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#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
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#[inline(always)]
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pub fn _11(self) -> &'a mut W {
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self.variant(ADICLK_A::_11)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bits(self, value: u8) -> &'a mut W {
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self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
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self.w
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}
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}
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#[doc = "Conversion mode selection\n\nValue on reset: 0"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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#[repr(u8)]
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pub enum MODE_A {
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#[doc = "0: 8-bit conversion."]
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_00 = 0,
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#[doc = "1: 12-bit conversion."]
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_01 = 1,
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#[doc = "2: 10-bit conversion."]
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_10 = 2,
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}
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impl From<MODE_A> for u8 {
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#[inline(always)]
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fn from(variant: MODE_A) -> Self {
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variant as _
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}
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}
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#[doc = "Reader of field `MODE`"]
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pub type MODE_R = crate::R<u8, MODE_A>;
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impl MODE_R {
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#[doc = r"Get enumerated values variant"]
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#[inline(always)]
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pub fn variant(&self) -> crate::Variant<u8, MODE_A> {
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use crate::Variant::*;
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match self.bits {
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0 => Val(MODE_A::_00),
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1 => Val(MODE_A::_01),
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2 => Val(MODE_A::_10),
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i => Res(i),
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}
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}
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#[doc = "Checks if the value of the field is `_00`"]
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#[inline(always)]
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pub fn is_00(&self) -> bool {
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*self == MODE_A::_00
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}
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#[doc = "Checks if the value of the field is `_01`"]
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#[inline(always)]
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pub fn is_01(&self) -> bool {
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*self == MODE_A::_01
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}
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#[doc = "Checks if the value of the field is `_10`"]
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#[inline(always)]
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pub fn is_10(&self) -> bool {
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*self == MODE_A::_10
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}
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}
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#[doc = "Write proxy for field `MODE`"]
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pub struct MODE_W<'a> {
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w: &'a mut W,
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}
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impl<'a> MODE_W<'a> {
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#[doc = r"Writes `variant` to the field"]
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#[inline(always)]
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pub fn variant(self, variant: MODE_A) -> &'a mut W {
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unsafe { self.bits(variant.into()) }
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}
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#[doc = "8-bit conversion."]
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#[inline(always)]
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pub fn _00(self) -> &'a mut W {
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self.variant(MODE_A::_00)
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}
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#[doc = "12-bit conversion."]
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#[inline(always)]
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pub fn _01(self) -> &'a mut W {
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self.variant(MODE_A::_01)
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}
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#[doc = "10-bit conversion."]
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#[inline(always)]
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pub fn _10(self) -> &'a mut W {
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self.variant(MODE_A::_10)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub unsafe fn bits(self, value: u8) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
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self.w
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}
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}
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#[doc = "Clock Divide Select\n\nValue on reset: 0"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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#[repr(u8)]
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pub enum ADIV_A {
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#[doc = "0: The divide ratio is 1 and the clock rate is input clock."]
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_00 = 0,
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#[doc = "1: The divide ratio is 2 and the clock rate is (input clock)/2."]
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_01 = 1,
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#[doc = "2: The divide ratio is 4 and the clock rate is (input clock)/4."]
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_10 = 2,
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#[doc = "3: The divide ratio is 8 and the clock rate is (input clock)/8."]
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_11 = 3,
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}
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impl From<ADIV_A> for u8 {
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#[inline(always)]
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fn from(variant: ADIV_A) -> Self {
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variant as _
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}
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}
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#[doc = "Reader of field `ADIV`"]
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pub type ADIV_R = crate::R<u8, ADIV_A>;
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impl ADIV_R {
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#[doc = r"Get enumerated values variant"]
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#[inline(always)]
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pub fn variant(&self) -> ADIV_A {
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match self.bits {
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0 => ADIV_A::_00,
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1 => ADIV_A::_01,
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2 => ADIV_A::_10,
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3 => ADIV_A::_11,
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_ => unreachable!(),
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}
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}
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#[doc = "Checks if the value of the field is `_00`"]
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#[inline(always)]
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pub fn is_00(&self) -> bool {
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*self == ADIV_A::_00
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}
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#[doc = "Checks if the value of the field is `_01`"]
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#[inline(always)]
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pub fn is_01(&self) -> bool {
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*self == ADIV_A::_01
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}
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#[doc = "Checks if the value of the field is `_10`"]
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#[inline(always)]
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pub fn is_10(&self) -> bool {
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*self == ADIV_A::_10
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}
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#[doc = "Checks if the value of the field is `_11`"]
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#[inline(always)]
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pub fn is_11(&self) -> bool {
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*self == ADIV_A::_11
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}
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}
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#[doc = "Write proxy for field `ADIV`"]
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pub struct ADIV_W<'a> {
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w: &'a mut W,
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}
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impl<'a> ADIV_W<'a> {
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#[doc = r"Writes `variant` to the field"]
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#[inline(always)]
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pub fn variant(self, variant: ADIV_A) -> &'a mut W {
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{
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self.bits(variant.into())
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}
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}
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#[doc = "The divide ratio is 1 and the clock rate is input clock."]
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#[inline(always)]
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pub fn _00(self) -> &'a mut W {
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self.variant(ADIV_A::_00)
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}
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#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
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#[inline(always)]
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pub fn _01(self) -> &'a mut W {
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self.variant(ADIV_A::_01)
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}
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#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
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#[inline(always)]
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pub fn _10(self) -> &'a mut W {
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self.variant(ADIV_A::_10)
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}
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#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
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#[inline(always)]
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pub fn _11(self) -> &'a mut W {
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self.variant(ADIV_A::_11)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bits(self, value: u8) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x03 << 5)) | (((value as u32) & 0x03) << 5);
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self.w
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}
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}
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#[doc = "Write proxy for field `CLRLTRG`"]
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pub struct CLRLTRG_W<'a> {
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w: &'a mut W,
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}
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impl<'a> CLRLTRG_W<'a> {
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
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self.w
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}
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}
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impl R {
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#[doc = "Bits 0:1 - Input Clock Select"]
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#[inline(always)]
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pub fn adiclk(&self) -> ADICLK_R {
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ADICLK_R::new((self.bits & 0x03) as u8)
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}
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#[doc = "Bits 2:3 - Conversion mode selection"]
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#[inline(always)]
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pub fn mode(&self) -> MODE_R {
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MODE_R::new(((self.bits >> 2) & 0x03) as u8)
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}
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#[doc = "Bits 5:6 - Clock Divide Select"]
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#[inline(always)]
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pub fn adiv(&self) -> ADIV_R {
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ADIV_R::new(((self.bits >> 5) & 0x03) as u8)
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}
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}
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impl W {
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#[doc = "Bits 0:1 - Input Clock Select"]
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#[inline(always)]
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pub fn adiclk(&mut self) -> ADICLK_W {
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ADICLK_W { w: self }
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}
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#[doc = "Bits 2:3 - Conversion mode selection"]
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#[inline(always)]
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pub fn mode(&mut self) -> MODE_W {
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MODE_W { w: self }
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}
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#[doc = "Bits 5:6 - Clock Divide Select"]
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#[inline(always)]
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pub fn adiv(&mut self) -> ADIV_W {
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ADIV_W { w: self }
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}
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#[doc = "Bit 8 - Clear Latch Trigger in Trigger Handler Block"]
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#[inline(always)]
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pub fn clrltrg(&mut self) -> CLRLTRG_W {
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CLRLTRG_W { w: self }
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}
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}
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