NXP NXP S32K118 S32K 1.6 S32K118 NXP Microcontroller Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CM0PLUS r0p0 little true true 2 false 8 32 CSE_PRAM CSE_PRAM CSE_PRAM 0x14000800 0 0x80 registers _EmbeddedRAM0 CSE PRAM 0 Register CSE_PRAM 0 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM0LL CSE PRAM0LL register. CSE_PRAM 0 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM0LU CSE PRAM0LU register. 0x1 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM0HL CSE PRAM0HL register. 0x2 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM0HU CSE PRAM0HU register. 0x3 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM1 CSE PRAM 1 Register CSE_PRAM 0x4 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM1LL CSE PRAM1LL register. CSE_PRAM 0x4 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM1LU CSE PRAM1LU register. 0x5 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM1HL CSE PRAM1HL register. 0x6 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM1HU CSE PRAM1HU register. 0x7 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM2 CSE PRAM 2 Register CSE_PRAM 0x8 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM2LL CSE PRAM2LL register. CSE_PRAM 0x8 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM2LU CSE PRAM2LU register. 0x9 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM2HL CSE PRAM2HL register. 0xA 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM2HU CSE PRAM2HU register. 0xB 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM3 CSE PRAM 3 Register CSE_PRAM 0xC 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM3LL CSE PRAM3LL register. CSE_PRAM 0xC 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM3LU CSE PRAM3LU register. 0xD 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM3HL CSE PRAM3HL register. 0xE 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM3HU CSE PRAM3HU register. 0xF 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM4 CSE PRAM 4 Register CSE_PRAM 0x10 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM4LL CSE PRAM4LL register. CSE_PRAM 0x10 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM4LU CSE PRAM4LU register. 0x11 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM4HL CSE PRAM4HL register. 0x12 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM4HU CSE PRAM4HU register. 0x13 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM5 CSE PRAM 5 Register CSE_PRAM 0x14 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM5LL CSE PRAM5LL register. CSE_PRAM 0x14 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM5LU CSE PRAM5LU register. 0x15 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM5HL CSE PRAM5HL register. 0x16 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM5HU CSE PRAM5HU register. 0x17 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM6 CSE PRAM 6 Register CSE_PRAM 0x18 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM6LL CSE PRAM6LL register. CSE_PRAM 0x18 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM6LU CSE PRAM6LU register. 0x19 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM6HL CSE PRAM6HL register. 0x1A 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM6HU CSE PRAM6HU register. 0x1B 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM7 CSE PRAM 7 Register CSE_PRAM 0x1C 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM7LL CSE PRAM7LL register. CSE_PRAM 0x1C 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM7LU CSE PRAM7LU register. 0x1D 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM7HL CSE PRAM7HL register. 0x1E 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM7HU CSE PRAM7HU register. 0x1F 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM8 CSE PRAM 8 Register CSE_PRAM 0x20 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM8LL CSE PRAM8LL register. CSE_PRAM 0x20 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM8LU CSE PRAM8LU register. 0x21 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM8HL CSE PRAM8HL register. 0x22 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM8HU CSE PRAM8HU register. 0x23 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM9 CSE PRAM 9 Register CSE_PRAM 0x24 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM9LL CSE PRAM9LL register. CSE_PRAM 0x24 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM9LU CSE PRAM9LU register. 0x25 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM9HL CSE PRAM9HL register. 0x26 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM9HU CSE PRAM9HU register. 0x27 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM10 CSE PRAM 10 Register CSE_PRAM 0x28 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM10LL CSE PRAM10LL register. CSE_PRAM 0x28 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM10LU CSE PRAM10LU register. 0x29 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM10HL CSE PRAM10HL register. 0x2A 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM10HU CSE PRAM10HU register. 0x2B 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM11 CSE PRAM 11 Register CSE_PRAM 0x2C 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM11LL CSE PRAM11LL register. CSE_PRAM 0x2C 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM11LU CSE PRAM11LU register. 0x2D 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM11HL CSE PRAM11HL register. 0x2E 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM11HU CSE PRAM11HU register. 0x2F 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM12 CSE PRAM 12 Register CSE_PRAM 0x30 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM12LL CSE PRAM12LL register. CSE_PRAM 0x30 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM12LU CSE PRAM12LU register. 0x31 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM12HL CSE PRAM12HL register. 0x32 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM12HU CSE PRAM12HU register. 0x33 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM13 CSE PRAM 13 Register CSE_PRAM 0x34 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM13LL CSE PRAM13LL register. CSE_PRAM 0x34 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM13LU CSE PRAM13LU register. 0x35 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM13HL CSE PRAM13HL register. 0x36 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM13HU CSE PRAM13HU register. 0x37 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM14 CSE PRAM 14 Register CSE_PRAM 0x38 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM14LL CSE PRAM14LL register. CSE_PRAM 0x38 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM14LU CSE PRAM14LU register. 0x39 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM14HL CSE PRAM14HL register. 0x3A 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM14HU CSE PRAM14HU register. 0x3B 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM15 CSE PRAM 15 Register CSE_PRAM 0x3C 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM15LL CSE PRAM15LL register. CSE_PRAM 0x3C 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM15LU CSE PRAM15LU register. 0x3D 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM15HL CSE PRAM15HL register. 0x3E 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM15HU CSE PRAM15HU register. 0x3F 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM16 CSE PRAM 16 Register CSE_PRAM 0x40 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM16LL CSE PRAM16LL register. CSE_PRAM 0x40 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM16LU CSE PRAM16LU register. 0x41 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM16HL CSE PRAM16HL register. 0x42 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM16HU CSE PRAM16HU register. 0x43 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM17 CSE PRAM 17 Register CSE_PRAM 0x44 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM17LL CSE PRAM17LL register. CSE_PRAM 0x44 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM17LU CSE PRAM17LU register. 0x45 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM17HL CSE PRAM17HL register. 0x46 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM17HU CSE PRAM17HU register. 0x47 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM18 CSE PRAM 18 Register CSE_PRAM 0x48 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM18LL CSE PRAM18LL register. CSE_PRAM 0x48 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM18LU CSE PRAM18LU register. 0x49 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM18HL CSE PRAM18HL register. 0x4A 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM18HU CSE PRAM18HU register. 0x4B 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM19 CSE PRAM 19 Register CSE_PRAM 0x4C 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM19LL CSE PRAM19LL register. CSE_PRAM 0x4C 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM19LU CSE PRAM19LU register. 0x4D 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM19HL CSE PRAM19HL register. 0x4E 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM19HU CSE PRAM19HU register. 0x4F 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM20 CSE PRAM 20 Register CSE_PRAM 0x50 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM20LL CSE PRAM20LL register. CSE_PRAM 0x50 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM20LU CSE PRAM20LU register. 0x51 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM20HL CSE PRAM20HL register. 0x52 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM20HU CSE PRAM20HU register. 0x53 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM21 CSE PRAM 21 Register CSE_PRAM 0x54 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM21LL CSE PRAM21LL register. CSE_PRAM 0x54 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM21LU CSE PRAM21LU register. 0x55 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM21HL CSE PRAM21HL register. 0x56 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM21HU CSE PRAM21HU register. 0x57 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM22 CSE PRAM 22 Register CSE_PRAM 0x58 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM22LL CSE PRAM22LL register. CSE_PRAM 0x58 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM22LU CSE PRAM22LU register. 0x59 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM22HL CSE PRAM22HL register. 0x5A 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM22HU CSE PRAM22HU register. 0x5B 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM23 CSE PRAM 23 Register CSE_PRAM 0x5C 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM23LL CSE PRAM23LL register. CSE_PRAM 0x5C 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM23LU CSE PRAM23LU register. 0x5D 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM23HL CSE PRAM23HL register. 0x5E 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM23HU CSE PRAM23HU register. 0x5F 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM24 CSE PRAM 24 Register CSE_PRAM 0x60 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM24LL CSE PRAM24LL register. CSE_PRAM 0x60 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM24LU CSE PRAM24LU register. 0x61 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM24HL CSE PRAM24HL register. 0x62 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM24HU CSE PRAM24HU register. 0x63 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM25 CSE PRAM 25 Register CSE_PRAM 0x64 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM25LL CSE PRAM25LL register. CSE_PRAM 0x64 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM25LU CSE PRAM25LU register. 0x65 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM25HL CSE PRAM25HL register. 0x66 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM25HU CSE PRAM25HU register. 0x67 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM26 CSE PRAM 26 Register CSE_PRAM 0x68 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM26LL CSE PRAM26LL register. CSE_PRAM 0x68 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM26LU CSE PRAM26LU register. 0x69 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM26HL CSE PRAM26HL register. 0x6A 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM26HU CSE PRAM26HU register. 0x6B 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM27 CSE PRAM 27 Register CSE_PRAM 0x6C 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM27LL CSE PRAM27LL register. CSE_PRAM 0x6C 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM27LU CSE PRAM27LU register. 0x6D 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM27HL CSE PRAM27HL register. 0x6E 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM27HU CSE PRAM27HU register. 0x6F 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM28 CSE PRAM 28 Register CSE_PRAM 0x70 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM28LL CSE PRAM28LL register. CSE_PRAM 0x70 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM28LU CSE PRAM28LU register. 0x71 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM28HL CSE PRAM28HL register. 0x72 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM28HU CSE PRAM28HU register. 0x73 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM29 CSE PRAM 29 Register CSE_PRAM 0x74 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM29LL CSE PRAM29LL register. CSE_PRAM 0x74 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM29LU CSE PRAM29LU register. 0x75 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM29HL CSE PRAM29HL register. 0x76 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM29HU CSE PRAM29HU register. 0x77 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM30 CSE PRAM 30 Register CSE_PRAM 0x78 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM30LL CSE PRAM30LL register. CSE_PRAM 0x78 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM30LU CSE PRAM30LU register. 0x79 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM30HL CSE PRAM30HL register. 0x7A 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM30HU CSE PRAM30HU register. 0x7B 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM31 CSE PRAM 31 Register CSE_PRAM 0x7C 32 read-write 0 0xFFFFFFFF BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write _EmbeddedRAM31LL CSE PRAM31LL register. CSE_PRAM 0x7C 8 read-write 0 0xFF RAM_LL RAM_LL stores the first 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM31LU CSE PRAM31LU register. 0x7D 8 read-write 0 0xFF RAM_LU RAM_LU stores the second 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM31HL CSE PRAM31HL register. 0x7E 8 read-write 0 0xFF RAM_HL RAM_HL stores the third 8 bits of the 32 bit CRC 0 8 read-write _EmbeddedRAM31HU CSE PRAM31HU register. 0x7F 8 read-write 0 0xFF RAM_HU RAM_HU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write AIPS AIPS-Lite Bridge AIPS_ 0x40000000 0 0x70 registers MPRA Master Privilege Register A 0 32 read-write 0x77700000 0xFFFFFFFF MPL2 Master 2 Privilege Level 20 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MTW2 Master 2 Trusted For Writes 21 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTR2 Master 2 Trusted For Read 22 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MPL1 Master 1 Privilege Level 24 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MTW1 Master 1 Trusted for Writes 25 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTR1 Master 1 Trusted for Read 26 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MPL0 Master 0 Privilege Level 28 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MTW0 Master 0 Trusted For Writes 29 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTR0 Master 0 Trusted For Read 30 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 PACRA Peripheral Access Control Register 0x20 32 read-write 0x54000000 0xFFFFFFFF TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRB Peripheral Access Control Register 0x24 32 read-write 0x44000400 0xFFFFFFFF TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 PACRC Peripheral Access Control Register 0x28 32 read-only 0 0xFFFFFFFF PACRD Peripheral Access Control Register 0x2C 32 read-write 0x44000000 0xFFFFFFFF TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 OPACRA Off-Platform Peripheral Access Control Register 0x40 32 read-write 0x44004444 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 OPACRB Off-Platform Peripheral Access Control Register 0x44 32 read-write 0x44440 0xFFFFFFFF TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 OPACRC Off-Platform Peripheral Access Control Register 0x48 32 read-write 0x4400044 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 OPACRD Off-Platform Peripheral Access Control Register 0x4C 32 read-write 0x44440400 0xFFFFFFFF TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 OPACRE Off-Platform Peripheral Access Control Register 0x50 32 read-write 0x40000040 0xFFFFFFFF TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 OPACRF Off-Platform Peripheral Access Control Register 0x54 32 read-write 0x44444400 0xFFFFFFFF TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 OPACRG Off-Platform Peripheral Access Control Register 0x58 32 read-write 0x400000 0xFFFFFFFF TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 OPACRH Off-Platform Peripheral Access Control Register 0x5C 32 read-write 0x400000 0xFFFFFFFF TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 OPACRI Off-Platform Peripheral Access Control Register 0x60 32 read-write 0x4044440 0xFFFFFFFF TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 OPACRJ Off-Platform Peripheral Access Control Register 0x64 32 read-write 0x444000 0xFFFFFFFF TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 OPACRK Off-Platform Peripheral Access Control Register 0x68 32 read-write 0x40000 0xFFFFFFFF TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 OPACRL Off-Platform Peripheral Access Control Register 0x6C 32 read-write 0x444 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 MSCM MSCM MSCM_ 0x40001000 0 0x40C registers CPxTYPE Processor X Type Register 0 32 read-only 0 0 RYPZ Processor x Revision 0 8 read-only PERSONALITY Processor x Personality 8 24 read-only CPxNUM Processor X Number Register 0x4 32 read-only 0 0xFFFFFFFE CPN Processor x Number 0 1 read-only CPxMASTER Processor X Master Register 0x8 32 read-only 0 0xFFFFFFC0 PPMN Processor x Physical Master Number 0 6 read-only CPxCOUNT Processor X Count Register 0xC 32 read-only 0 0xFFFFFFFF PCNT Processor Count 0 2 read-only CPxCFG0 Processor X Configuration Register 0 0x10 32 read-only 0 0 DCWY Level 1 Data Cache Ways 0 8 read-only DCSZ Level 1 Data Cache Size 8 8 read-only ICWY Level 1 Instruction Cache Ways 16 8 read-only ICSZ Level 1 Instruction Cache Size 24 8 read-only CPxCFG1 Processor X Configuration Register 1 0x14 32 read-only 0 0xFFFF L2WY Level 2 Instruction Cache Ways 16 8 read-only L2SZ Level 2 Instruction Cache Size 24 8 read-only CPxCFG2 Processor X Configuration Register 2 0x18 32 read-only 0x10001 0xFF00FF TMUSZ Tightly-coupled Memory Upper Size 8 8 read-only TMLSZ Tightly-coupled Memory Lower Size 24 8 read-only CPxCFG3 Processor X Configuration Register 3 0x1C 32 read-only 0 0xFFFFFC80 FPU Floating Point Unit 0 1 read-only 0 FPU support is not included. #0 1 FPU support is included. #1 SIMD SIMD/NEON instruction support 1 1 read-only 0 SIMD/NEON support is not included. #0 1 SIMD/NEON support is included. #1 JAZ Jazelle support 2 1 read-only 0 Jazelle support is not included. #0 1 Jazelle support is included. #1 MMU Memory Management Unit 3 1 read-only 0 MMU support is not included. #0 1 MMU support is included. #1 TZ Trust Zone 4 1 read-only 0 Trust Zone support is not included. #0 1 Trust Zone support is included. #1 CMP Core Memory Protection unit 5 1 read-only 0 Core Memory Protection is not included. #0 1 Core Memory Protection is included. #1 BB Bit Banding 6 1 read-only 0 Bit Banding is not supported. #0 1 Bit Banding is supported. #1 SBP System Bus Ports 8 2 read-only CP0TYPE Processor 0 Type Register 0x20 32 read-only 0x434D3401 0xFFFFFFFF RYPZ Processor 0 Revision 0 8 read-only PERSONALITY Processor 0 Personality 8 24 read-only CP0NUM Processor 0 Number Register 0x24 32 read-only 0 0xFFFFFFFF CPN Processor 0 Number 0 1 read-only CP0MASTER Processor 0 Master Register 0x28 32 read-only 0 0xFFFFFFFF PPMN Processor 0 Physical Master Number 0 6 read-only CP0COUNT Processor 0 Count Register 0x2C 32 read-only 0 0xFFFFFFFF PCNT Processor Count 0 2 read-only CP0CFG0 Processor 0 Configuration Register 0 0x30 32 read-only 0x4000000 0xFFFFFFFF DCWY Level 1 Data Cache Ways 0 8 read-only DCSZ Level 1 Data Cache Size 8 8 read-only ICWY Level 1 Instruction Cache Ways 16 8 read-only ICSZ Level 1 Instruction Cache Size 24 8 read-only CP0CFG1 Processor 0 Configuration Register 1 0x34 32 read-only 0 0xFFFFFFFF L2WY Level 2 Instruction Cache Ways 16 8 read-only L2SZ Level 2 Instruction Cache Size 24 8 read-only CP0CFG2 Processor 0 Configuration Register 2 0x38 32 read-only 0x7010701 0xFFFFFFFF TMUSZ Tightly-coupled Memory Upper Size 8 8 read-only TMLSZ Tightly-coupled Memory Lower Size 24 8 read-only CP0CFG3 Processor 0 Configuration Register 3 0x3C 32 read-only 0x101 0xFFFFFFFF FPU Floating Point Unit 0 1 read-only 0 FPU support is not included. #0 1 FPU support is included. #1 SIMD SIMD/NEON instruction support 1 1 read-only 0 SIMD/NEON support is not included. #0 1 SIMD/NEON support is included. #1 JAZ Jazelle support 2 1 read-only 0 Jazelle support is not included. #0 1 Jazelle support is included. #1 MMU Memory Management Unit 3 1 read-only 0 MMU support is not included. #0 1 MMU support is included. #1 TZ Trust Zone 4 1 read-only 0 Trust Zone support is not included. #0 1 Trust Zone support is included. #1 CMP Core Memory Protection unit 5 1 read-only 0 Core Memory Protection is not included. #0 1 Core Memory Protection is included. #1 BB Bit Banding 6 1 read-only 0 Bit Banding is not supported. #0 1 Bit Banding is supported. #1 SBP System Bus Ports 8 2 read-only OCMDR0 On-Chip Memory Descriptor Register 0x400 32 read-write 0xCA089000 0xFFFFFFFF OCM1 OCMEM Control Field 1 4 2 read-write OCMPU OCMPU 12 1 read-only OCMT OCMT 13 3 read-only 100 OCMEMn is a Program Flash. #100 101 OCMEMn is a Data Flash. #101 110 OCMEMn is an EEE. #110 RO RO 16 1 read-write 0 Writes to the OCMDRn[11:0] are allowed #0 1 Writes to the OCMDRn[11:0] are ignored #1 OCMW OCMW 17 3 read-only 010 OCMEMn 32-bits wide #010 011 OCMEMn 64-bits wide #011 100 OCMEMn 128-bits wide #100 101 OCMEMn 256-bits wide #101 OCMSZ OCMSZ 24 4 read-only 0000 no OCMEMn #0000 0001 1KB OCMEMn #0001 0010 2KB OCMEMn #0010 0011 4KB OCMEMn #0011 0100 8KB OCMEMn #0100 0101 16KB OCMEMn #0101 0110 32KB OCMEMn #0110 0111 64KB OCMEMn #0111 1000 128KB OCMEMn #1000 1001 256KB OCMEMn #1001 1010 512KB OCMEMn #1010 1011 1MB OCMEMn #1011 1100 2MB OCMEMn #1100 1101 4MB OCMEMn #1101 1110 8MB OCMEMn #1110 1111 16MB OCMEMn #1111 OCMSZH OCMSZH 28 1 read-only 0 OCMEMn is a power-of-2 capacity. #0 1 OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. #1 V V 31 1 read-only 0 OCMEMn is not present. #0 1 OCMEMn is present. #1 OCMDR1 On-Chip Memory Descriptor Register 0x404 32 read-write 0xC706B000 0xFFFFFFFF OCM1 OCMEM Control Field 1 4 2 read-write OCMPU OCMPU 12 1 read-only OCMT OCMT 13 3 read-only 100 OCMEMn is a Program Flash. #100 101 OCMEMn is a Data Flash. #101 110 OCMEMn is an EEE. #110 RO RO 16 1 read-write 0 Writes to the OCMDRn[11:0] are allowed #0 1 Writes to the OCMDRn[11:0] are ignored #1 OCMW OCMW 17 3 read-only 010 OCMEMn 32-bits wide #010 011 OCMEMn 64-bits wide #011 100 OCMEMn 128-bits wide #100 101 OCMEMn 256-bits wide #101 OCMSZ OCMSZ 24 4 read-only 0000 no OCMEMn #0000 0001 1KB OCMEMn #0001 0010 2KB OCMEMn #0010 0011 4KB OCMEMn #0011 0100 8KB OCMEMn #0100 0101 16KB OCMEMn #0101 0110 32KB OCMEMn #0110 0111 64KB OCMEMn #0111 1000 128KB OCMEMn #1000 1001 256KB OCMEMn #1001 1010 512KB OCMEMn #1010 1011 1MB OCMEMn #1011 1100 2MB OCMEMn #1100 1101 4MB OCMEMn #1101 1110 8MB OCMEMn #1110 1111 16MB OCMEMn #1111 OCMSZH OCMSZH 28 1 read-only 0 OCMEMn is a power-of-2 capacity. #0 1 OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. #1 V V 31 1 read-only 0 OCMEMn is not present. #0 1 OCMEMn is present. #1 OCMDR2 On-Chip Memory Descriptor Register 0x408 32 read-write 0xC304D000 0xFFFFFFFF OCMPU OCMPU 12 1 read-only OCMT OCMT 13 3 read-only 100 OCMEMn is a Program Flash. #100 101 OCMEMn is a Data Flash. #101 110 OCMEMn is an EEE. #110 RO RO 16 1 read-write 0 Writes to the OCMDRn[11:0] are allowed #0 1 Writes to the OCMDRn[11:0] are ignored #1 OCMW OCMW 17 3 read-only 010 OCMEMn 32-bits wide #010 011 OCMEMn 64-bits wide #011 100 OCMEMn 128-bits wide #100 101 OCMEMn 256-bits wide #101 OCMSZ OCMSZ 24 4 read-only 0000 no OCMEMn #0000 0001 1KB OCMEMn #0001 0010 2KB OCMEMn #0010 0011 4KB OCMEMn #0011 0100 8KB OCMEMn #0100 0101 16KB OCMEMn #0101 0110 32KB OCMEMn #0110 0111 64KB OCMEMn #0111 1000 128KB OCMEMn #1000 1001 256KB OCMEMn #1001 1010 512KB OCMEMn #1010 1011 1MB OCMEMn #1011 1100 2MB OCMEMn #1100 1101 4MB OCMEMn #1101 1110 8MB OCMEMn #1110 1111 16MB OCMEMn #1111 OCMSZH OCMSZH 28 1 read-only 0 OCMEMn is a power-of-2 capacity. #0 1 OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. #1 V V 31 1 read-only 0 OCMEMn is not present. #0 1 OCMEMn is present. #1 DMA Enhanced Direct Memory Access DMA_ 0x40008000 0 0x1080 registers DMA0 0 DMA1 1 DMA2 2 DMA3 3 DMA_Error 4 CR Control Register 0 32 read-write 0 0xFFFFFFFF EDBG Enable Debug 1 1 read-write ERCA Enable Round Robin Channel Arbitration 2 1 read-write HOE Halt On Error 4 1 read-write 0 Normal operation #0 1 Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. #1 HALT Halt DMA Operations 5 1 read-write 0 Normal operation #0 1 Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. #1 CLM Continuous Link Mode 6 1 read-write 0 A minor loop channel link made to itself goes through channel arbitration before being activated again. #0 1 A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. #1 EMLM Enable Minor Loop Mapping 7 1 read-write 0 Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. #0 1 Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. #1 ECX Error Cancel Transfer 16 1 read-write 0 Normal operation #0 1 Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt. #1 CX Cancel Transfer 17 1 read-write 0 Normal operation #0 1 Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. #1 ES Error Status Register 0x4 32 read-only 0 0xFFFFFFFF DBE Destination Bus Error 0 1 read-only 0 No destination bus error #0 1 The last recorded error was a bus error on a destination write #1 SBE Source Bus Error 1 1 read-only 0 No source bus error #0 1 The last recorded error was a bus error on a source read #1 SGE Scatter/Gather Configuration Error 2 1 read-only 0 No scatter/gather configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. #1 NCE NBYTES/CITER Configuration Error 3 1 read-only 0 No NBYTES/CITER configuration error #0 DOE Destination Offset Error 4 1 read-only 0 No destination offset configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. #1 DAE Destination Address Error 5 1 read-only 0 No destination address configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. #1 SOE Source Offset Error 6 1 read-only 0 No source offset configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. #1 SAE Source Address Error 7 1 read-only 0 No source address configuration error. #0 1 The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. #1 ERRCHN Error Channel Number or Canceled Channel Number 8 4 read-only CPE Channel Priority Error 14 1 read-only 0 No channel priority error #0 ECX Transfer Canceled 16 1 read-only 0 No canceled transfers #0 1 The last recorded entry was a canceled transfer by the error cancel transfer input #1 VLD VLD 31 1 read-only 0 No ERR bits are set. #0 1 At least one ERR bit is set indicating a valid error exists that has not been cleared. #1 ERQ Enable Request Register 0xC 32 read-write 0 0xFFFFFFFF ERQ0 Enable DMA Request 0 0 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ1 Enable DMA Request 1 1 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ2 Enable DMA Request 2 2 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ3 Enable DMA Request 3 3 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ4 Enable DMA Request 4 4 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ5 Enable DMA Request 5 5 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ6 Enable DMA Request 6 6 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ7 Enable DMA Request 7 7 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ8 Enable DMA Request 8 8 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ9 Enable DMA Request 9 9 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ10 Enable DMA Request 10 10 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ11 Enable DMA Request 11 11 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ12 Enable DMA Request 12 12 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ13 Enable DMA Request 13 13 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ14 Enable DMA Request 14 14 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ15 Enable DMA Request 15 15 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 EEI Enable Error Interrupt Register 0x14 32 read-write 0 0xFFFFFFFF EEI0 Enable Error Interrupt 0 0 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI1 Enable Error Interrupt 1 1 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI2 Enable Error Interrupt 2 2 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI3 Enable Error Interrupt 3 3 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI4 Enable Error Interrupt 4 4 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI5 Enable Error Interrupt 5 5 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI6 Enable Error Interrupt 6 6 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI7 Enable Error Interrupt 7 7 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI8 Enable Error Interrupt 8 8 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI9 Enable Error Interrupt 9 9 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI10 Enable Error Interrupt 10 10 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI11 Enable Error Interrupt 11 11 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI12 Enable Error Interrupt 12 12 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI13 Enable Error Interrupt 13 13 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI14 Enable Error Interrupt 14 14 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI15 Enable Error Interrupt 15 15 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 CEEI Clear Enable Error Interrupt Register 0x18 8 write-only 0 0xFF CEEI Clear Enable Error Interrupt 0 4 write-only CAEE Clear All Enable Error Interrupts 6 1 write-only NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SEEI Set Enable Error Interrupt Register 0x19 8 write-only 0 0xFF SEEI Set Enable Error Interrupt 0 4 write-only SAEE Sets All Enable Error Interrupts 6 1 write-only NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CERQ Clear Enable Request Register 0x1A 8 write-only 0 0xFF CERQ Clear Enable Request 0 4 write-only CAER Clear All Enable Requests 6 1 write-only NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SERQ Set Enable Request Register 0x1B 8 write-only 0 0xFF SERQ Set Enable Request 0 4 write-only SAER Set All Enable Requests 6 1 write-only NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CDNE Clear DONE Status Bit Register 0x1C 8 write-only 0 0xFF CDNE Clear DONE Bit 0 4 write-only CADN Clears All DONE Bits 6 1 write-only 0 Clears only the TCDn_CSR[DONE] bit specified in the CDNE field #0 1 Clears all bits in TCDn_CSR[DONE] #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SSRT Set START Bit Register 0x1D 8 write-only 0 0xFF SSRT Set START Bit 0 4 write-only SAST Set All START Bits (activates all channels) 6 1 write-only 0 Set only the TCDn_CSR[START] bit specified in the SSRT field #0 1 Set all bits in TCDn_CSR[START] #1 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CERR Clear Error Register 0x1E 8 write-only 0 0xFF CERR Clear Error Indicator 0 4 write-only CAEI Clear All Error Indicators 6 1 write-only NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CINT Clear Interrupt Request Register 0x1F 8 write-only 0 0xFF CINT Clear Interrupt Request 0 4 write-only CAIR Clear All Interrupt Requests 6 1 write-only NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 INT Interrupt Request Register 0x24 32 read-write 0 0xFFFFFFFF INT0 Interrupt Request 0 0 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT1 Interrupt Request 1 1 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT2 Interrupt Request 2 2 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT3 Interrupt Request 3 3 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT4 Interrupt Request 4 4 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT5 Interrupt Request 5 5 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT6 Interrupt Request 6 6 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT7 Interrupt Request 7 7 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT8 Interrupt Request 8 8 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT9 Interrupt Request 9 9 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT10 Interrupt Request 10 10 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT11 Interrupt Request 11 11 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT12 Interrupt Request 12 12 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT13 Interrupt Request 13 13 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT14 Interrupt Request 14 14 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT15 Interrupt Request 15 15 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 ERR Error Register 0x2C 32 read-write 0 0xFFFFFFFF ERR0 Error In Channel 0 0 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR1 Error In Channel 1 1 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR2 Error In Channel 2 2 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR3 Error In Channel 3 3 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR4 Error In Channel 4 4 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR5 Error In Channel 5 5 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR6 Error In Channel 6 6 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR7 Error In Channel 7 7 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR8 Error In Channel 8 8 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR9 Error In Channel 9 9 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR10 Error In Channel 10 10 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR11 Error In Channel 11 11 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR12 Error In Channel 12 12 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR13 Error In Channel 13 13 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR14 Error In Channel 14 14 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR15 Error In Channel 15 15 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 HRS Hardware Request Status Register 0x34 32 read-only 0 0xFFFFFFFF HRS0 Hardware Request Status Channel 0 0 1 read-only 0 A hardware service request for channel 0 is not present #0 1 A hardware service request for channel 0 is present #1 HRS1 Hardware Request Status Channel 1 1 1 read-only 0 A hardware service request for channel 1 is not present #0 1 A hardware service request for channel 1 is present #1 HRS2 Hardware Request Status Channel 2 2 1 read-only 0 A hardware service request for channel 2 is not present #0 1 A hardware service request for channel 2 is present #1 HRS3 Hardware Request Status Channel 3 3 1 read-only 0 A hardware service request for channel 3 is not present #0 1 A hardware service request for channel 3 is present #1 HRS4 Hardware Request Status Channel 4 4 1 read-only 0 A hardware service request for channel 4 is not present #0 1 A hardware service request for channel 4 is present #1 HRS5 Hardware Request Status Channel 5 5 1 read-only 0 A hardware service request for channel 5 is not present #0 1 A hardware service request for channel 5 is present #1 HRS6 Hardware Request Status Channel 6 6 1 read-only 0 A hardware service request for channel 6 is not present #0 1 A hardware service request for channel 6 is present #1 HRS7 Hardware Request Status Channel 7 7 1 read-only 0 A hardware service request for channel 7 is not present #0 1 A hardware service request for channel 7 is present #1 HRS8 Hardware Request Status Channel 8 8 1 read-only 0 A hardware service request for channel 8 is not present #0 1 A hardware service request for channel 8 is present #1 HRS9 Hardware Request Status Channel 9 9 1 read-only 0 A hardware service request for channel 9 is not present #0 1 A hardware service request for channel 9 is present #1 HRS10 Hardware Request Status Channel 10 10 1 read-only 0 A hardware service request for channel 10 is not present #0 1 A hardware service request for channel 10 is present #1 HRS11 Hardware Request Status Channel 11 11 1 read-only 0 A hardware service request for channel 11 is not present #0 1 A hardware service request for channel 11 is present #1 HRS12 Hardware Request Status Channel 12 12 1 read-only 0 A hardware service request for channel 12 is not present #0 1 A hardware service request for channel 12 is present #1 HRS13 Hardware Request Status Channel 13 13 1 read-only 0 A hardware service request for channel 13 is not present #0 1 A hardware service request for channel 13 is present #1 HRS14 Hardware Request Status Channel 14 14 1 read-only 0 A hardware service request for channel 14 is not present #0 1 A hardware service request for channel 14 is present #1 HRS15 Hardware Request Status Channel 15 15 1 read-only 0 A hardware service request for channel 15 is not present #0 1 A hardware service request for channel 15 is present #1 EARS Enable Asynchronous Request in Stop Register 0x44 32 read-write 0 0xFFFFFFFF EDREQ_0 Enable asynchronous DMA request in stop mode for channel 0. 0 1 read-write 0 Disable asynchronous DMA request for channel 0. #0 1 Enable asynchronous DMA request for channel 0. #1 EDREQ_1 Enable asynchronous DMA request in stop mode for channel 1. 1 1 read-write 0 Disable asynchronous DMA request for channel 1 #0 1 Enable asynchronous DMA request for channel 1. #1 EDREQ_2 Enable asynchronous DMA request in stop mode for channel 2. 2 1 read-write 0 Disable asynchronous DMA request for channel 2. #0 1 Enable asynchronous DMA request for channel 2. #1 EDREQ_3 Enable asynchronous DMA request in stop mode for channel 3. 3 1 read-write 0 Disable asynchronous DMA request for channel 3. #0 1 Enable asynchronous DMA request for channel 3. #1 EDREQ_4 Enable asynchronous DMA request in stop mode for channel 4 4 1 read-write 0 Disable asynchronous DMA request for channel 4. #0 1 Enable asynchronous DMA request for channel 4. #1 EDREQ_5 Enable asynchronous DMA request in stop mode for channel 5 5 1 read-write 0 Disable asynchronous DMA request for channel 5. #0 1 Enable asynchronous DMA request for channel 5. #1 EDREQ_6 Enable asynchronous DMA request in stop mode for channel 6 6 1 read-write 0 Disable asynchronous DMA request for channel 6. #0 1 Enable asynchronous DMA request for channel 6. #1 EDREQ_7 Enable asynchronous DMA request in stop mode for channel 7 7 1 read-write 0 Disable asynchronous DMA request for channel 7. #0 1 Enable asynchronous DMA request for channel 7. #1 EDREQ_8 Enable asynchronous DMA request in stop mode for channel 8 8 1 read-write 0 Disable asynchronous DMA request for channel 8. #0 1 Enable asynchronous DMA request for channel 8. #1 EDREQ_9 Enable asynchronous DMA request in stop mode for channel 9 9 1 read-write 0 Disable asynchronous DMA request for channel 9. #0 1 Enable asynchronous DMA request for channel 9. #1 EDREQ_10 Enable asynchronous DMA request in stop mode for channel 10 10 1 read-write 0 Disable asynchronous DMA request for channel 10. #0 1 Enable asynchronous DMA request for channel 10. #1 EDREQ_11 Enable asynchronous DMA request in stop mode for channel 11 11 1 read-write 0 Disable asynchronous DMA request for channel 11. #0 1 Enable asynchronous DMA request for channel 11. #1 EDREQ_12 Enable asynchronous DMA request in stop mode for channel 12 12 1 read-write 0 Disable asynchronous DMA request for channel 12. #0 1 Enable asynchronous DMA request for channel 12. #1 EDREQ_13 Enable asynchronous DMA request in stop mode for channel 13 13 1 read-write 0 Disable asynchronous DMA request for channel 13. #0 1 Enable asynchronous DMA request for channel 13. #1 EDREQ_14 Enable asynchronous DMA request in stop mode for channel 14 14 1 read-write 0 Disable asynchronous DMA request for channel 14. #0 1 Enable asynchronous DMA request for channel 14. #1 EDREQ_15 Enable asynchronous DMA request in stop mode for channel 15 15 1 read-write 0 Disable asynchronous DMA request for channel 15. #0 1 Enable asynchronous DMA request for channel 15. #1 DCHPRI3 Channel n Priority Register 0x100 8 read-write 0x3 0xCF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 DCHPRI2 Channel n Priority Register 0x101 8 read-write 0x2 0xCF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 DCHPRI1 Channel n Priority Register 0x102 8 read-write 0x1 0xCF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 DCHPRI0 Channel n Priority Register 0x103 8 read-write 0 0xCF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 TCD0_SADDR TCD Source Address 0x1000 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD0_SOFF TCD Signed Source Address Offset 0x1004 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD0_ATTR TCD Transfer Attributes 0x1006 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write 0 8-bit #000 1 16-bit #001 10 32-bit #010 SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 TCD0_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x1008 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD0_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x1008 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD0_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x1008 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD0_SLAST TCD Last Source Address Adjustment 0x100C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD0_DADDR TCD Destination Address 0x1010 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD0_DOFF TCD Signed Destination Address Offset 0x1014 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD0_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1016 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD0_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1016 16 read-write 0 0 CITER_LE Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD0_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1018 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD0_CSR TCD Control and Status 0x101C 16 read-write 0 0 START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 DREQ Disable Request 3 1 read-write ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 ACTIVE Channel Active 6 1 read-write DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write 0 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 TCD0_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x101E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD0_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x101E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD1_SADDR TCD Source Address 0x1020 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD1_SOFF TCD Signed Source Address Offset 0x1024 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD1_ATTR TCD Transfer Attributes 0x1026 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write 0 8-bit #000 1 16-bit #001 10 32-bit #010 SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 TCD1_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x1028 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD1_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x1028 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD1_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x1028 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD1_SLAST TCD Last Source Address Adjustment 0x102C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD1_DADDR TCD Destination Address 0x1030 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD1_DOFF TCD Signed Destination Address Offset 0x1034 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD1_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1036 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD1_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1036 16 read-write 0 0 CITER_LE Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD1_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1038 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD1_CSR TCD Control and Status 0x103C 16 read-write 0 0 START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 DREQ Disable Request 3 1 read-write ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 ACTIVE Channel Active 6 1 read-write DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write 0 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 TCD1_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x103E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD1_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x103E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD2_SADDR TCD Source Address 0x1040 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD2_SOFF TCD Signed Source Address Offset 0x1044 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD2_ATTR TCD Transfer Attributes 0x1046 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write 0 8-bit #000 1 16-bit #001 10 32-bit #010 SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 TCD2_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x1048 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD2_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x1048 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD2_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x1048 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD2_SLAST TCD Last Source Address Adjustment 0x104C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD2_DADDR TCD Destination Address 0x1050 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD2_DOFF TCD Signed Destination Address Offset 0x1054 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD2_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1056 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD2_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1056 16 read-write 0 0 CITER_LE Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD2_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1058 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD2_CSR TCD Control and Status 0x105C 16 read-write 0 0 START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 DREQ Disable Request 3 1 read-write ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 ACTIVE Channel Active 6 1 read-write DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write 0 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 TCD2_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x105E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD2_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x105E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD3_SADDR TCD Source Address 0x1060 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD3_SOFF TCD Signed Source Address Offset 0x1064 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD3_ATTR TCD Transfer Attributes 0x1066 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write 0 8-bit #000 1 16-bit #001 10 32-bit #010 SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 TCD3_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x1068 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD3_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x1068 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD3_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x1068 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD3_SLAST TCD Last Source Address Adjustment 0x106C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD3_DADDR TCD Destination Address 0x1070 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD3_DOFF TCD Signed Destination Address Offset 0x1074 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD3_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1076 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD3_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1076 16 read-write 0 0 CITER_LE Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD3_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1078 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD3_CSR TCD Control and Status 0x107C 16 read-write 0 0 START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 DREQ Disable Request 3 1 read-write ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 ACTIVE Channel Active 6 1 read-write DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write 0 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 TCD3_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x107E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD3_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x107E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MPU Memory protection unit MPU_ 0x4000D000 0 0x820 registers CESR Control/Error Status Register 0 32 read-write 0x814001 0xFFFFFFFF VLD Valid 0 1 read-write 0 MPU is disabled. All accesses from all bus masters are allowed. #0 1 MPU is enabled #1 NRGD Number Of Region Descriptors 8 4 read-only 0000 8 region descriptors #0000 0001 12 region descriptors #0001 0010 16 region descriptors #0010 NSP Number Of Slave Ports 12 4 read-only HRL Hardware Revision Level 16 4 read-only SPERR1 Slave Port 1 Error 30 1 read-write 0 No error has occurred for slave port 1. #0 1 An error has occurred for slave port 1. #1 SPERR0 Slave Port 0 Error 31 1 read-write 0 No error has occurred for slave port 0. #0 1 An error has occurred for slave port 0. #1 EAR0 Error Address Register, slave port 0 0x10 32 read-only 0 0xFFFFFFFF EADDR Error Address 0 32 read-only EDR0 Error Detail Register, slave port 0 0x14 32 read-only 0 0xFFFFFFFF ERW Error Read/Write 0 1 read-only 0 Read #0 1 Write #1 EATTR Error Attributes 1 3 read-only 000 User mode, instruction access #000 001 User mode, data access #001 010 Supervisor mode, instruction access #010 011 Supervisor mode, data access #011 EMN Error Master Number 4 4 read-only EPID Error Process Identification 8 8 read-only EACD Error Access Control Detail 16 16 read-only EAR1 Error Address Register, slave port 1 0x18 32 read-only 0 0xFFFFFFFF EADDR Error Address 0 32 read-only EDR1 Error Detail Register, slave port 1 0x1C 32 read-only 0 0xFFFFFFFF ERW Error Read/Write 0 1 read-only 0 Read #0 1 Write #1 EATTR Error Attributes 1 3 read-only 000 User mode, instruction access #000 001 User mode, data access #001 010 Supervisor mode, instruction access #010 011 Supervisor mode, data access #011 EMN Error Master Number 4 4 read-only EPID Error Process Identification 8 8 read-only EACD Error Access Control Detail 16 16 read-only RGD0_WORD0 Region Descriptor 0, Word 0 0x400 32 read-write 0 0xFFFFFFFF SRTADDR Start Address 5 27 read-write RGD0_WORD1 Region Descriptor 0, Word 1 0x404 32 read-write 0xFFFFFFFF 0xFFFFFFFF ENDADDR End Address 5 27 read-write RGD0_WORD2 Region Descriptor 0, Word 2 0x408 32 read-write 0x61F7DF 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M0UM #11 M0PE Bus Master 0 Process Identifier enable 5 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M1UM #11 M2UM Bus Master 2 User Mode Access control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M2UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 RGD0_WORD3 Region Descriptor 0, Word 3 0x40C 32 read-write 0x1 0xFFFFFFFF VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 PIDMASK Process Identifier Mask 16 8 read-write PID Process Identifier 24 8 read-write RGD1_WORD0 Region Descriptor 1, Word 0 0x410 32 read-write 0 0xFFFFFFFF SRTADDR Start Address 5 27 read-write RGD1_WORD1 Region Descriptor 1, Word 1 0x414 32 read-write 0x1F 0xFFFFFFFF ENDADDR End Address 5 27 read-write RGD1_WORD2 Region Descriptor 1, Word 2 0x418 32 read-write 0 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M0UM #11 M0PE Bus Master 0 Process Identifier enable 5 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M1UM #11 M2UM Bus Master 2 User Mode Access control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M2UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 RGD1_WORD3 Region Descriptor 1, Word 3 0x41C 32 read-write 0 0xFFFFFFFF VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 PIDMASK Process Identifier Mask 16 8 read-write PID Process Identifier 24 8 read-write RGD2_WORD0 Region Descriptor 2, Word 0 0x420 32 read-write 0 0xFFFFFFFF SRTADDR Start Address 5 27 read-write RGD2_WORD1 Region Descriptor 2, Word 1 0x424 32 read-write 0x1F 0xFFFFFFFF ENDADDR End Address 5 27 read-write RGD2_WORD2 Region Descriptor 2, Word 2 0x428 32 read-write 0 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M0UM #11 M0PE Bus Master 0 Process Identifier enable 5 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M1UM #11 M2UM Bus Master 2 User Mode Access control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M2UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 RGD2_WORD3 Region Descriptor 2, Word 3 0x42C 32 read-write 0 0xFFFFFFFF VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 PIDMASK Process Identifier Mask 16 8 read-write PID Process Identifier 24 8 read-write RGD3_WORD0 Region Descriptor 3, Word 0 0x430 32 read-write 0 0xFFFFFFFF SRTADDR Start Address 5 27 read-write RGD3_WORD1 Region Descriptor 3, Word 1 0x434 32 read-write 0x1F 0xFFFFFFFF ENDADDR End Address 5 27 read-write RGD3_WORD2 Region Descriptor 3, Word 2 0x438 32 read-write 0 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M0UM #11 M0PE Bus Master 0 Process Identifier enable 5 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M1UM #11 M2UM Bus Master 2 User Mode Access control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M2UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 RGD3_WORD3 Region Descriptor 3, Word 3 0x43C 32 read-write 0 0xFFFFFFFF VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 PIDMASK Process Identifier Mask 16 8 read-write PID Process Identifier 24 8 read-write RGD4_WORD0 Region Descriptor 4, Word 0 0x440 32 read-write 0 0xFFFFFFFF SRTADDR Start Address 5 27 read-write RGD4_WORD1 Region Descriptor 4, Word 1 0x444 32 read-write 0x1F 0xFFFFFFFF ENDADDR End Address 5 27 read-write RGD4_WORD2 Region Descriptor 4, Word 2 0x448 32 read-write 0 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M0UM #11 M0PE Bus Master 0 Process Identifier enable 5 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M1UM #11 M2UM Bus Master 2 User Mode Access control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M2UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 RGD4_WORD3 Region Descriptor 4, Word 3 0x44C 32 read-write 0 0xFFFFFFFF VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 PIDMASK Process Identifier Mask 16 8 read-write PID Process Identifier 24 8 read-write RGD5_WORD0 Region Descriptor 5, Word 0 0x450 32 read-write 0 0xFFFFFFFF SRTADDR Start Address 5 27 read-write RGD5_WORD1 Region Descriptor 5, Word 1 0x454 32 read-write 0x1F 0xFFFFFFFF ENDADDR End Address 5 27 read-write RGD5_WORD2 Region Descriptor 5, Word 2 0x458 32 read-write 0 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M0UM #11 M0PE Bus Master 0 Process Identifier enable 5 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M1UM #11 M2UM Bus Master 2 User Mode Access control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M2UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 RGD5_WORD3 Region Descriptor 5, Word 3 0x45C 32 read-write 0 0xFFFFFFFF VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 PIDMASK Process Identifier Mask 16 8 read-write PID Process Identifier 24 8 read-write RGD6_WORD0 Region Descriptor 6, Word 0 0x460 32 read-write 0 0xFFFFFFFF SRTADDR Start Address 5 27 read-write RGD6_WORD1 Region Descriptor 6, Word 1 0x464 32 read-write 0x1F 0xFFFFFFFF ENDADDR End Address 5 27 read-write RGD6_WORD2 Region Descriptor 6, Word 2 0x468 32 read-write 0 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M0UM #11 M0PE Bus Master 0 Process Identifier enable 5 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M1UM #11 M2UM Bus Master 2 User Mode Access control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M2UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 RGD6_WORD3 Region Descriptor 6, Word 3 0x46C 32 read-write 0 0xFFFFFFFF VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 PIDMASK Process Identifier Mask 16 8 read-write PID Process Identifier 24 8 read-write RGD7_WORD0 Region Descriptor 7, Word 0 0x470 32 read-write 0 0xFFFFFFFF SRTADDR Start Address 5 27 read-write RGD7_WORD1 Region Descriptor 7, Word 1 0x474 32 read-write 0x1F 0xFFFFFFFF ENDADDR End Address 5 27 read-write RGD7_WORD2 Region Descriptor 7, Word 2 0x478 32 read-write 0 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M0UM #11 M0PE Bus Master 0 Process Identifier enable 5 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M1UM #11 M2UM Bus Master 2 User Mode Access control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M2UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 RGD7_WORD3 Region Descriptor 7, Word 3 0x47C 32 read-write 0 0xFFFFFFFF VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 PIDMASK Process Identifier Mask 16 8 read-write PID Process Identifier 24 8 read-write RGDAAC0 Region Descriptor Alternate Access Control 0 0x800 32 read-write 0x61F7DF 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M0UM #11 M0PE Bus Master 0 Process Identifier Enable 5 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M1UM #11 M2UM Bus Master 2 User Mode Access Control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M2UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 RGDAAC1 Region Descriptor Alternate Access Control 1 0x804 32 read-write 0 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M0UM #11 M0PE Bus Master 0 Process Identifier Enable 5 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M1UM #11 M2UM Bus Master 2 User Mode Access Control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M2UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 RGDAAC2 Region Descriptor Alternate Access Control 2 0x808 32 read-write 0 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M0UM #11 M0PE Bus Master 0 Process Identifier Enable 5 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M1UM #11 M2UM Bus Master 2 User Mode Access Control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M2UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 RGDAAC3 Region Descriptor Alternate Access Control 3 0x80C 32 read-write 0 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M0UM #11 M0PE Bus Master 0 Process Identifier Enable 5 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M1UM #11 M2UM Bus Master 2 User Mode Access Control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M2UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 RGDAAC4 Region Descriptor Alternate Access Control 4 0x810 32 read-write 0 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M0UM #11 M0PE Bus Master 0 Process Identifier Enable 5 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M1UM #11 M2UM Bus Master 2 User Mode Access Control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M2UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 RGDAAC5 Region Descriptor Alternate Access Control 5 0x814 32 read-write 0 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M0UM #11 M0PE Bus Master 0 Process Identifier Enable 5 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M1UM #11 M2UM Bus Master 2 User Mode Access Control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M2UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 RGDAAC6 Region Descriptor Alternate Access Control 6 0x818 32 read-write 0 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M0UM #11 M0PE Bus Master 0 Process Identifier Enable 5 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M1UM #11 M2UM Bus Master 2 User Mode Access Control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M2UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 RGDAAC7 Region Descriptor Alternate Access Control 7 0x81C 32 read-write 0 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M0UM #11 M0PE Bus Master 0 Process Identifier Enable 5 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M1UM #11 M2UM Bus Master 2 User Mode Access Control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M2UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 ERM ERM ERM_ 0x40018000 0 0x104 registers ERM_fault 5 CR0 ERM Configuration Register 0 0 32 read-write 0 0xFFFFFFFF ENCIE0 ENCIE0 30 1 read-write 0 Interrupt notification of Memory 0 non-correctable error events is disabled. #0 1 Interrupt notification of Memory 0 non-correctable error events is enabled. #1 ESCIE0 ESCIE0 31 1 read-write 0 Interrupt notification of Memory 0 single-bit correction events is disabled. #0 1 Interrupt notification of Memory 0 single-bit correction events is enabled. #1 SR0 ERM Status Register 0 0x10 32 read-write 0 0xFFFFFFFF NCE0 NCE0 30 1 read-write 0 No non-correctable error event on Memory 0 detected #0 1 Non-correctable error event on Memory 0 detected #1 SBC0 SBC0 31 1 read-write 0 No single-bit correction event on Memory 0 detected #0 1 Single-bit correction event on Memory 0 detected #1 EAR0 ERM Memory n Error Address Register 0x100 32 read-only 0 0xFFFFFFFF EAR EAR 0 32 read-only EIM Error Injection Module EIM_ 0x40019000 0 0x108 registers EIMCR Error Injection Module Configuration Register 0 32 read-write 0 0xFFFFFFFF GEIEN Global Error Injection Enable 0 1 read-write 0 Disabled #0 1 Enabled #1 EICHEN Error Injection Channel Enable register 0x4 32 read-write 0 0xFFFFFFFF EICH0EN Error Injection Channel 0 Enable 31 1 read-write 0 Error injection is disabled on Error Injection Channel 0 #0 1 Error injection is enabled on Error Injection Channel 0 #1 EICHD0_WORD0 Error Injection Channel Descriptor n, Word0 0x100 32 read-write 0 0xFFFFFFFF CHKBIT_MASK Checkbit Mask 25 7 read-write EICHD0_WORD1 Error Injection Channel Descriptor n, Word1 0x104 32 read-write 0 0xFFFFFFFF B0_3DATA_MASK Data Mask Bytes 0-3 0 32 read-write FTFC FTFC FTFC_ 0x40020000 0 0x30 registers FTFC 18 FSTAT Flash Status Register 0 8 read-write 0x80 0xFF MGSTAT0 Memory Controller Command Completion Status Flag 0 1 read-only FPVIOL Flash Protection Violation Flag 4 1 read-write 0 No protection violation detected #0 1 Protection violation detected #1 ACCERR Flash Access Error Flag 5 1 read-write 0 No access error detected #0 1 Access error detected #1 RDCOLERR FTFC Read Collision Error Flag 6 1 read-write 0 No collision error detected #0 1 Collision error detected #1 CCIF Command Complete Interrupt Flag 7 1 read-write FCNFG Flash Configuration Register 0x1 8 read-write 0x2 0xFF EEERDY EEERDY 0 1 read-only RAMRDY RAM Ready 1 1 read-only ERSSUSP Erase Suspend 4 1 read-write 0 No suspend requested #0 1 Suspend the current Erase Flash Sector command execution #1 ERSAREQ Erase All Request 5 1 read-only 0 No request or request complete #0 RDCOLLIE Read Collision Error Interrupt Enable 6 1 read-write 0 Read collision error interrupt disabled #0 1 Read collision error interrupt enabled. An interrupt request is generated whenever an FTFC read collision error is detected (see the description of FSTAT[RDCOLERR]). #1 CCIE Command Complete Interrupt Enable 7 1 read-write 0 Command complete interrupt disabled #0 1 Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. #1 FSEC Flash Security Register 0x2 8 read-only 0 0 SEC Flash Security 0 2 read-only 10 MCU security status is unsecure (The standard shipping condition of the FTFC is unsecure.) #10 FSLACC Factory Failure Analysis Access Code 2 2 read-only 00 Factory access granted #00 11 Factory access granted #11 MEEN Mass Erase Enable Bits 4 2 read-only 00 Mass erase is enabled #00 01 Mass erase is enabled #01 11 Mass erase is enabled #11 KEYEN Backdoor Key Security Enable 6 2 read-only 00 Backdoor key access disabled #00 01 Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) #01 10 Backdoor key access enabled #10 11 Backdoor key access disabled #11 FOPT Flash Option Register 0x3 8 read-only 0 0 OPT Nonvolatile Option 0 8 read-only FCCOB3 Flash Common Command Object Registers 0x4 8 read-write 0 0xFF CCOBn CCOBn 0 8 read-write FCCOB2 Flash Common Command Object Registers 0x5 8 read-write 0 0xFF CCOBn CCOBn 0 8 read-write FCCOB1 Flash Common Command Object Registers 0x6 8 read-write 0 0xFF CCOBn CCOBn 0 8 read-write FCCOB0 Flash Common Command Object Registers 0x7 8 read-write 0 0xFF CCOBn CCOBn 0 8 read-write FCCOB7 Flash Common Command Object Registers 0x8 8 read-write 0 0xFF CCOBn CCOBn 0 8 read-write FCCOB6 Flash Common Command Object Registers 0x9 8 read-write 0 0xFF CCOBn CCOBn 0 8 read-write FCCOB5 Flash Common Command Object Registers 0xA 8 read-write 0 0xFF CCOBn CCOBn 0 8 read-write FCCOB4 Flash Common Command Object Registers 0xB 8 read-write 0 0xFF CCOBn CCOBn 0 8 read-write FCCOBB Flash Common Command Object Registers 0xC 8 read-write 0 0xFF CCOBn CCOBn 0 8 read-write FCCOBA Flash Common Command Object Registers 0xD 8 read-write 0 0xFF CCOBn CCOBn 0 8 read-write FCCOB9 Flash Common Command Object Registers 0xE 8 read-write 0 0xFF CCOBn CCOBn 0 8 read-write FCCOB8 Flash Common Command Object Registers 0xF 8 read-write 0 0xFF CCOBn CCOBn 0 8 read-write FPROT3 Program Flash Protection Registers 0x10 8 read-write 0 0 PROT Program Flash Region Protect 0 8 read-write FPROT2 Program Flash Protection Registers 0x11 8 read-write 0 0 PROT Program Flash Region Protect 0 8 read-write FPROT1 Program Flash Protection Registers 0x12 8 read-write 0 0 PROT Program Flash Region Protect 0 8 read-write FPROT0 Program Flash Protection Registers 0x13 8 read-write 0 0 PROT Program Flash Region Protect 0 8 read-write FEPROT EEPROM Protection Register 0x16 8 read-write 0 0 EPROT EEPROM Region Protect 0 8 read-write FDPROT Data Flash Protection Register 0x17 8 read-write 0 0 DPROT Data Flash Region Protect 0 8 read-write 00000000 Data Flash region is protected #0 00000001 Data Flash region is not protected #1 FCSESTAT Flash CSEc Status Register 0x2C 8 read-only 0 0xFF BSY Busy 0 1 read-only SB Secure Boot 1 1 read-only BIN Secure Boot Initialization 2 1 read-only BFN Secure Boot Finished 3 1 read-only BOK Secure Boot OK 4 1 read-only RIN Random Number Generator Initialized 5 1 read-only EDB External Debug 6 1 read-only IDB Internal Debug 7 1 read-only FERSTAT Flash Error Status Register 0x2E 8 read-write 0 0xFF DFDIF Double Bit Fault Detect Interrupt Flag 1 1 read-write 0 Double bit fault not detected during a valid flash read access from the platform flash controller #0 1 Double bit fault detected (or FERCNFG[FDFD] is set) during a valid flash read access from the platform flash controller #1 FERCNFG Flash Error Configuration Register 0x2F 8 read-write 0 0xFF DFDIE Double Bit Fault Detect Interrupt Enable 1 1 read-write 0 Double bit fault detect interrupt disabled #0 1 Double bit fault detect interrupt enabled. An interrupt request is generated whenever the FERSTAT[DFDIF] flag is set. #1 FDFD Force Double Bit Fault Detect 5 1 read-write 0 FERSTAT[DFDIF] sets only if a double bit fault is detected during read access from the platform flash controller #0 1 FERSTAT[DFDIF] sets during any valid flash read access from the platform flash controller. An interrupt request is generated if the DFDIE bit is set. #1 DMAMUX DMA channel multiplexor DMAMUX_ 0x40021000 0 0x4 registers CHCFG0 Channel Configuration register 0 8 read-write 0 0xFF SOURCE DMA Channel Source (Slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 CHCFG1 Channel Configuration register 0x1 8 read-write 0 0xFF SOURCE DMA Channel Source (Slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 CHCFG2 Channel Configuration register 0x2 8 read-write 0 0xFF SOURCE DMA Channel Source (Slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 CHCFG3 Channel Configuration register 0x3 8 read-write 0 0xFF SOURCE DMA Channel Source (Slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 CAN0 Flex Controller Area Network module CAN0_ 0x40024000 0 0xC0C registers CAN0_ORed_Err_Wakeup 10 CAN0_ORed_0_31_MB 11 MCR Module Configuration Register 0 32 read-write 0xD890000F 0xFFFFFFFF MAXMB Number Of The Last Message Buffer 0 7 read-write IDAM ID Acceptance Mode 8 2 read-write 00 Format A: One full ID (standard and extended) per ID Filter Table element. #00 01 Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element. #01 10 Format C: Four partial 8-bit Standard IDs per ID Filter Table element. #10 11 Format D: All frames rejected. #11 FDEN CAN FD operation enable 11 1 read-write 1 CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats. #1 0 CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format. #0 AEN Abort Enable 12 1 read-write 0 Abort disabled. #0 1 Abort enabled. #1 LPRIOEN Local Priority Enable 13 1 read-write 0 Local Priority disabled. #0 1 Local Priority enabled. #1 PNET_EN Pretended Networking Enable 14 1 read-write 0 Pretended Networking mode is disabled. #0 1 Pretended Networking mode is enabled. #1 DMA DMA Enable 15 1 read-write 0 DMA feature for RX FIFO disabled. #0 1 DMA feature for RX FIFO enabled. #1 IRMQ Individual Rx Masking And Queue Enable 16 1 read-write 0 Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY. #0 1 Individual Rx masking and queue feature are enabled. #1 SRXDIS Self Reception Disable 17 1 read-write 0 Self reception enabled. #0 1 Self reception disabled. #1 LPMACK Low-Power Mode Acknowledge 20 1 read-only 0 FlexCAN is not in a low-power mode. #0 1 FlexCAN is in a low-power mode. #1 WRNEN Warning Interrupt Enable 21 1 read-write 0 TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. #0 1 TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96. #1 SUPV Supervisor Mode 23 1 read-write FRZACK Freeze Mode Acknowledge 24 1 read-only 0 FlexCAN not in Freeze mode, prescaler running. #0 1 FlexCAN in Freeze mode, prescaler stopped. #1 SOFTRST Soft Reset 25 1 read-write 0 No reset request. #0 1 Resets the registers affected by soft reset. #1 NOTRDY FlexCAN Not Ready 27 1 read-only 0 FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode. #0 HALT Halt FlexCAN 28 1 read-write 0 No Freeze mode request. #0 1 Enters Freeze mode if the FRZ bit is asserted. #1 RFEN Rx FIFO Enable 29 1 read-write 0 Rx FIFO not enabled. #0 1 Rx FIFO enabled. #1 FRZ Freeze Enable 30 1 read-write 0 Not enabled to enter Freeze mode. #0 1 Enabled to enter Freeze mode. #1 MDIS Module Disable 31 1 read-write 0 Enable the FlexCAN module. #0 1 Disable the FlexCAN module. #1 CTRL1 Control 1 register 0x4 32 read-write 0 0xFFFFFFFF PROPSEG Propagation Segment 0 3 read-write LOM Listen-Only Mode 3 1 read-write 0 Listen-Only mode is deactivated. #0 1 FlexCAN module operates in Listen-Only mode. #1 LBUF Lowest Buffer Transmitted First 4 1 read-write 0 Buffer with highest priority is transmitted first. #0 1 Lowest number buffer is transmitted first. #1 TSYN Timer Sync 5 1 read-write 0 Timer Sync feature disabled #0 1 Timer Sync feature enabled #1 BOFFREC Bus Off Recovery 6 1 read-write 0 Automatic recovering from Bus Off state enabled. #0 1 Automatic recovering from Bus Off state disabled. #1 SMP CAN Bit Sampling 7 1 read-write 0 Just one sample is used to determine the bit value. #0 1 Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used. #1 RWRNMSK Rx Warning Interrupt Mask 10 1 read-write 0 Rx Warning Interrupt disabled. #0 1 Rx Warning Interrupt enabled. #1 TWRNMSK Tx Warning Interrupt Mask 11 1 read-write 0 Tx Warning Interrupt disabled. #0 1 Tx Warning Interrupt enabled. #1 LPB Loop Back Mode 12 1 read-write 0 Loop Back disabled. #0 1 Loop Back enabled. #1 CLKSRC CAN Engine Clock Source 13 1 read-write 0 The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock. #0 1 The CAN engine clock source is the peripheral clock. #1 ERRMSK Error Interrupt Mask 14 1 read-write 0 Error interrupt disabled. #0 1 Error interrupt enabled. #1 BOFFMSK Bus Off Interrupt Mask 15 1 read-write 0 Bus Off interrupt disabled. #0 1 Bus Off interrupt enabled. #1 PSEG2 Phase Segment 2 16 3 read-write PSEG1 Phase Segment 1 19 3 read-write RJW Resync Jump Width 22 2 read-write PRESDIV Prescaler Division Factor 24 8 read-write TIMER Free Running Timer 0x8 32 read-write 0 0xFFFFFFFF TIMER Timer Value 0 16 read-write RXMGMASK Rx Mailboxes Global Mask Register 0x10 32 read-write 0 0 MG Rx Mailboxes Global Mask Bits 0 32 read-write RX14MASK Rx 14 Mask register 0x14 32 read-write 0 0 RX14M Rx Buffer 14 Mask Bits 0 32 read-write RX15MASK Rx 15 Mask register 0x18 32 read-write 0 0 RX15M Rx Buffer 15 Mask Bits 0 32 read-write ECR Error Counter 0x1C 32 read-write 0 0xFFFFFFFF TXERRCNT Transmit Error Counter 0 8 read-write RXERRCNT Receive Error Counter 8 8 read-write TXERRCNT_FAST Transmit Error Counter for fast bits 16 8 read-write RXERRCNT_FAST Receive Error Counter for fast bits 24 8 read-write ESR1 Error and Status 1 register 0x20 32 read-write 0 0xFFFFFFFF ERRINT Error Interrupt 1 1 read-write 0 No such occurrence. #0 1 Indicates setting of any Error Bit in the Error and Status Register. #1 BOFFINT Bus Off Interrupt 2 1 read-write 0 No such occurrence. #0 1 FlexCAN module entered Bus Off state. #1 RX FlexCAN In Reception 3 1 read-only 0 FlexCAN is not receiving a message. #0 1 FlexCAN is receiving a message. #1 FLTCONF Fault Confinement State 4 2 read-only 00 Error Active #00 01 Error Passive #01 1x Bus Off #1x TX FlexCAN In Transmission 6 1 read-only 0 FlexCAN is not transmitting a message. #0 1 FlexCAN is transmitting a message. #1 IDLE IDLE 7 1 read-only 0 No such occurrence. #0 1 CAN bus is now IDLE. #1 RXWRN Rx Error Warning 8 1 read-only 0 No such occurrence. #0 1 RXERRCNT is greater than or equal to 96. #1 TXWRN TX Error Warning 9 1 read-only 0 No such occurrence. #0 1 TXERRCNT is greater than or equal to 96. #1 STFERR Stuffing Error 10 1 read-only 0 No such occurrence. #0 1 A Stuffing Error occurred since last read of this register. #1 FRMERR Form Error 11 1 read-only 0 No such occurrence. #0 1 A Form Error occurred since last read of this register. #1 CRCERR Cyclic Redundancy Check Error 12 1 read-only 0 No such occurrence. #0 1 A CRC error occurred since last read of this register. #1 ACKERR Acknowledge Error 13 1 read-only 0 No such occurrence. #0 1 An ACK error occurred since last read of this register. #1 BIT0ERR Bit0 Error 14 1 read-only 0 No such occurrence. #0 1 At least one bit sent as dominant is received as recessive. #1 BIT1ERR Bit1 Error 15 1 read-only 0 No such occurrence. #0 1 At least one bit sent as recessive is received as dominant. #1 RWRNINT Rx Warning Interrupt Flag 16 1 read-write 0 No such occurrence. #0 1 The Rx error counter transitioned from less than 96 to greater than or equal to 96. #1 TWRNINT Tx Warning Interrupt Flag 17 1 read-write 0 No such occurrence. #0 1 The Tx error counter transitioned from less than 96 to greater than or equal to 96. #1 SYNCH CAN Synchronization Status 18 1 read-only 0 FlexCAN is not synchronized to the CAN bus. #0 1 FlexCAN is synchronized to the CAN bus. #1 BOFFDONEINT Bus Off Done Interrupt 19 1 read-write 0 No such occurrence. #0 1 FlexCAN module has completed Bus Off process. #1 ERRINT_FAST Error Interrupt for errors detected in the Data Phase of CAN FD frames with the BRS bit set 20 1 read-write 0 No such occurrence. #0 1 Indicates setting of any Error Bit detected in the Data Phase of CAN FD frames with the BRS bit set. #1 ERROVR Error Overrun bit 21 1 read-write 0 Overrun has not occurred. #0 1 Overrun has occurred. #1 STFERR_FAST Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set 26 1 read-only 0 No such occurrence. #0 1 A Stuffing Error occurred since last read of this register. #1 FRMERR_FAST Form Error in the Data Phase of CAN FD frames with the BRS bit set 27 1 read-only 0 No such occurrence. #0 1 A Form Error occurred since last read of this register. #1 CRCERR_FAST Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set 28 1 read-only 0 No such occurrence. #0 1 A CRC error occurred since last read of this register. #1 BIT0ERR_FAST Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set 30 1 read-only 0 No such occurrence. #0 1 At least one bit sent as dominant is received as recessive. #1 BIT1ERR_FAST Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set 31 1 read-only 0 No such occurrence. #0 1 At least one bit sent as recessive is received as dominant. #1 IMASK1 Interrupt Masks 1 register 0x28 32 read-write 0 0xFFFFFFFF BUF31TO0M Buffer MB i Mask 0 32 read-write IFLAG1 Interrupt Flags 1 register 0x30 32 read-write 0 0xFFFFFFFF BUF0I Buffer MB0 Interrupt Or Clear FIFO bit 0 1 read-write 0 The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. #0 1 The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. #1 BUF4TO1I Buffer MB i Interrupt Or "reserved" 1 4 read-write BUF5I Buffer MB5 Interrupt Or "Frames available in Rx FIFO" 5 1 read-write 0 No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1 #0 1 MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled. #1 BUF6I Buffer MB6 Interrupt Or "Rx FIFO Warning" 6 1 read-write 0 No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1 #0 1 MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1 #1 BUF7I Buffer MB7 Interrupt Or "Rx FIFO Overflow" 7 1 read-write 0 No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1 #0 1 MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1 #1 BUF31TO8I Buffer MBi Interrupt 8 24 read-write CTRL2 Control 2 register 0x34 32 read-write 0xA00000 0xFFFFFFFF EDFLTDIS Edge Filter Disable 11 1 read-write 0 Edge Filter is enabled. #0 1 Edge Filter is disabled. #1 ISOCANFDEN ISO CAN FD Enable 12 1 read-write 0 FlexCAN operates using the non-ISO CAN FD protocol. #0 1 FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1). #1 PREXCEN Protocol Exception Enable 14 1 read-write 0 Protocol Exception is disabled. #0 1 Protocol Exception is enabled. #1 TIMER_SRC Timer Source 15 1 read-write 0 The Free Running Timer is clocked by the CAN bit clock, which defines the baud rate on the CAN bus. #0 1 The Free Running Timer is clocked by an external time tick. The period can be either adjusted to be equal to the baud rate on the CAN bus, or a different value as required. See the device specific section for details about the external time tick. #1 EACEN Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes 16 1 read-write 0 Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. #0 1 Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. #1 RRS Remote Request Storing 17 1 read-write 0 Remote Response Frame is generated. #0 1 Remote Request Frame is stored. #1 MRP Mailboxes Reception Priority 18 1 read-write 0 Matching starts from Rx FIFO and continues on Mailboxes. #0 1 Matching starts from Mailboxes and continues on Rx FIFO. #1 TASD Tx Arbitration Start Delay 19 5 read-write RFFN Number Of Rx FIFO Filters 24 4 read-write BOFFDONEMSK Bus Off Done Interrupt Mask 30 1 read-write 0 Bus Off Done interrupt disabled. #0 1 Bus Off Done interrupt enabled. #1 ERRMSK_FAST Error Interrupt Mask for errors detected in the Data Phase of fast CAN FD frames 31 1 read-write 0 ERRINT_FAST Error interrupt disabled. #0 1 ERRINT_FAST Error interrupt enabled. #1 ESR2 Error and Status 2 register 0x38 32 read-only 0 0xFFFFFFFF IMB Inactive Mailbox 13 1 read-only 0 If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. #0 1 If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. #1 VPS Valid Priority Status 14 1 read-only 0 Contents of IMB and LPTM are invalid. #0 1 Contents of IMB and LPTM are valid. #1 LPTM Lowest Priority Tx Mailbox 16 7 read-only CRCR CRC Register 0x44 32 read-only 0 0xFFFFFFFF TXCRC Transmitted CRC value 0 15 read-only MBCRC CRC Mailbox 16 7 read-only RXFGMASK Rx FIFO Global Mask register 0x48 32 read-write 0 0 FGM Rx FIFO Global Mask Bits 0 32 read-write RXFIR Rx FIFO Information Register 0x4C 32 read-only 0 0 IDHIT Identifier Acceptance Filter Hit Indicator 0 9 read-only CBT CAN Bit Timing Register 0x50 32 read-write 0 0xFFFFFFFF EPSEG2 Extended Phase Segment 2 0 5 read-write EPSEG1 Extended Phase Segment 1 5 5 read-write EPROPSEG Extended Propagation Segment 10 6 read-write ERJW Extended Resync Jump Width 16 5 read-write EPRESDIV Extended Prescaler Division Factor 21 10 read-write BTF Bit Timing Format Enable 31 1 read-write 0 Extended bit time definitions disabled. #0 1 Extended bit time definitions enabled. #1 RAMn0 Embedded RAM 0x80 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn1 Embedded RAM 0x84 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn2 Embedded RAM 0x88 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn3 Embedded RAM 0x8C 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn4 Embedded RAM 0x90 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn5 Embedded RAM 0x94 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn6 Embedded RAM 0x98 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn7 Embedded RAM 0x9C 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn8 Embedded RAM 0xA0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn9 Embedded RAM 0xA4 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn10 Embedded RAM 0xA8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn11 Embedded RAM 0xAC 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn12 Embedded RAM 0xB0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn13 Embedded RAM 0xB4 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn14 Embedded RAM 0xB8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn15 Embedded RAM 0xBC 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn16 Embedded RAM 0xC0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn17 Embedded RAM 0xC4 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn18 Embedded RAM 0xC8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn19 Embedded RAM 0xCC 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn20 Embedded RAM 0xD0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn21 Embedded RAM 0xD4 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn22 Embedded RAM 0xD8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn23 Embedded RAM 0xDC 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn24 Embedded RAM 0xE0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn25 Embedded RAM 0xE4 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn26 Embedded RAM 0xE8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn27 Embedded RAM 0xEC 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn28 Embedded RAM 0xF0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn29 Embedded RAM 0xF4 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn30 Embedded RAM 0xF8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn31 Embedded RAM 0xFC 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn32 Embedded RAM 0x100 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn33 Embedded RAM 0x104 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn34 Embedded RAM 0x108 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn35 Embedded RAM 0x10C 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn36 Embedded RAM 0x110 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn37 Embedded RAM 0x114 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn38 Embedded RAM 0x118 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn39 Embedded RAM 0x11C 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn40 Embedded RAM 0x120 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn41 Embedded RAM 0x124 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn42 Embedded RAM 0x128 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn43 Embedded RAM 0x12C 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn44 Embedded RAM 0x130 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn45 Embedded RAM 0x134 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn46 Embedded RAM 0x138 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn47 Embedded RAM 0x13C 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn48 Embedded RAM 0x140 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn49 Embedded RAM 0x144 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn50 Embedded RAM 0x148 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn51 Embedded RAM 0x14C 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn52 Embedded RAM 0x150 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn53 Embedded RAM 0x154 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn54 Embedded RAM 0x158 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn55 Embedded RAM 0x15C 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn56 Embedded RAM 0x160 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn57 Embedded RAM 0x164 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn58 Embedded RAM 0x168 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn59 Embedded RAM 0x16C 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn60 Embedded RAM 0x170 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn61 Embedded RAM 0x174 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn62 Embedded RAM 0x178 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn63 Embedded RAM 0x17C 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn64 Embedded RAM 0x180 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn65 Embedded RAM 0x184 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn66 Embedded RAM 0x188 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn67 Embedded RAM 0x18C 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn68 Embedded RAM 0x190 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn69 Embedded RAM 0x194 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn70 Embedded RAM 0x198 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn71 Embedded RAM 0x19C 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn72 Embedded RAM 0x1A0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn73 Embedded RAM 0x1A4 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn74 Embedded RAM 0x1A8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn75 Embedded RAM 0x1AC 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn76 Embedded RAM 0x1B0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn77 Embedded RAM 0x1B4 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn78 Embedded RAM 0x1B8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn79 Embedded RAM 0x1BC 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn80 Embedded RAM 0x1C0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn81 Embedded RAM 0x1C4 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn82 Embedded RAM 0x1C8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn83 Embedded RAM 0x1CC 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn84 Embedded RAM 0x1D0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn85 Embedded RAM 0x1D4 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn86 Embedded RAM 0x1D8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn87 Embedded RAM 0x1DC 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn88 Embedded RAM 0x1E0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn89 Embedded RAM 0x1E4 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn90 Embedded RAM 0x1E8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn91 Embedded RAM 0x1EC 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn92 Embedded RAM 0x1F0 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn93 Embedded RAM 0x1F4 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn94 Embedded RAM 0x1F8 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn95 Embedded RAM 0x1FC 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn96 Embedded RAM 0x200 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn97 Embedded RAM 0x204 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn98 Embedded RAM 0x208 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn99 Embedded RAM 0x20C 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn100 Embedded RAM 0x210 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn101 Embedded RAM 0x214 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn102 Embedded RAM 0x218 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn103 Embedded RAM 0x21C 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn104 Embedded RAM 0x220 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn105 Embedded RAM 0x224 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn106 Embedded RAM 0x228 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn107 Embedded RAM 0x22C 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn108 Embedded RAM 0x230 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn109 Embedded RAM 0x234 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn110 Embedded RAM 0x238 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn111 Embedded RAM 0x23C 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn112 Embedded RAM 0x240 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn113 Embedded RAM 0x244 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn114 Embedded RAM 0x248 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn115 Embedded RAM 0x24C 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn116 Embedded RAM 0x250 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn117 Embedded RAM 0x254 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn118 Embedded RAM 0x258 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn119 Embedded RAM 0x25C 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn120 Embedded RAM 0x260 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn121 Embedded RAM 0x264 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn122 Embedded RAM 0x268 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn123 Embedded RAM 0x26C 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn124 Embedded RAM 0x270 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn125 Embedded RAM 0x274 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn126 Embedded RAM 0x278 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RAMn127 Embedded RAM 0x27C 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write RXIMR0 Rx Individual Mask Registers 0x880 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR1 Rx Individual Mask Registers 0x884 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR2 Rx Individual Mask Registers 0x888 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR3 Rx Individual Mask Registers 0x88C 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR4 Rx Individual Mask Registers 0x890 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR5 Rx Individual Mask Registers 0x894 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR6 Rx Individual Mask Registers 0x898 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR7 Rx Individual Mask Registers 0x89C 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR8 Rx Individual Mask Registers 0x8A0 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR9 Rx Individual Mask Registers 0x8A4 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR10 Rx Individual Mask Registers 0x8A8 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR11 Rx Individual Mask Registers 0x8AC 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR12 Rx Individual Mask Registers 0x8B0 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR13 Rx Individual Mask Registers 0x8B4 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR14 Rx Individual Mask Registers 0x8B8 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR15 Rx Individual Mask Registers 0x8BC 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR16 Rx Individual Mask Registers 0x8C0 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR17 Rx Individual Mask Registers 0x8C4 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR18 Rx Individual Mask Registers 0x8C8 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR19 Rx Individual Mask Registers 0x8CC 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR20 Rx Individual Mask Registers 0x8D0 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR21 Rx Individual Mask Registers 0x8D4 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR22 Rx Individual Mask Registers 0x8D8 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR23 Rx Individual Mask Registers 0x8DC 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR24 Rx Individual Mask Registers 0x8E0 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR25 Rx Individual Mask Registers 0x8E4 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR26 Rx Individual Mask Registers 0x8E8 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR27 Rx Individual Mask Registers 0x8EC 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR28 Rx Individual Mask Registers 0x8F0 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR29 Rx Individual Mask Registers 0x8F4 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR30 Rx Individual Mask Registers 0x8F8 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write RXIMR31 Rx Individual Mask Registers 0x8FC 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write CTRL1_PN Pretended Networking Control 1 Register 0xB00 32 read-write 0x100 0xFFFFFFFF FCS Filtering Combination Selection 0 2 read-write 00 Message ID filtering only #00 01 Message ID filtering and payload filtering #01 10 Message ID filtering occurring a specified number of times. #10 11 Message ID filtering and payload filtering a specified number of times #11 IDFS ID Filtering Selection 2 2 read-write 00 Match upon a ID contents against an exact target value #00 01 Match upon a ID value greater than or equal to a specified target value #01 10 Match upon a ID value smaller than or equal to a specified target value #10 11 Match upon a ID value inside a range, greater than or equal to a specified lower limit and smaller than or equal a specified upper limit #11 PLFS Payload Filtering Selection 4 2 read-write 00 Match upon a payload contents against an exact target value #00 01 Match upon a payload value greater than or equal to a specified target value #01 10 Match upon a payload value smaller than or equal to a specified target value #10 11 Match upon a payload value inside a range, greater than or equal to a specified lower limit and smaller than or equal a specified upper limit #11 NMATCH Number of Messages Matching the Same Filtering Criteria 8 8 read-write 00000001 Received message must match the predefined filtering criteria for ID and/or PL once before generating a wake up event. #1 00000010 Received message must match the predefined filtering criteria for ID and/or PL twice before generating a wake up event. #10 11111111 Received message must match the predefined filtering criteria for ID and/or PL 255 times before generating a wake up event. #11111111 WUMF_MSK Wake Up by Match Flag Mask Bit 16 1 read-write 0 Wake up match event is disabled #0 1 Wake up match event is enabled #1 WTOF_MSK Wake Up by Timeout Flag Mask Bit 17 1 read-write 0 Timeout wake up event is disabled #0 1 Timeout wake up event is enabled #1 CTRL2_PN Pretended Networking Control 2 Register 0xB04 32 read-write 0 0xFFFFFFFF MATCHTO Timeout for No Message Matching the Filtering Criteria 0 16 read-write WU_MTC Pretended Networking Wake Up Match Register 0xB08 32 read-write 0 0xFFFFFFFF MCOUNTER Number of Matches while in Pretended Networking 8 8 read-only WUMF Wake Up by Match Flag Bit 16 1 read-write 0 No wake up by match event detected #0 1 Wake up by match event detected #1 WTOF Wake Up by Timeout Flag Bit 17 1 read-write 0 No wake up by timeout event detected #0 1 Wake up by timeout event detected #1 FLT_ID1 Pretended Networking ID Filter 1 Register 0xB0C 32 read-write 0 0xFFFFFFFF FLT_ID1 ID Filter 1 for Pretended Networking filtering 0 29 read-write FLT_RTR Remote Transmission Request Filter 29 1 read-write 0 Reject remote frame (accept data frame) #0 1 Accept remote frame #1 FLT_IDE ID Extended Filter 30 1 read-write 0 Accept standard frame format #0 1 Accept extended frame format #1 FLT_DLC Pretended Networking DLC Filter Register 0xB10 32 read-write 0x8 0xFFFFFFFF FLT_DLC_HI Upper Limit for Length of Data Bytes Filter 0 4 read-write FLT_DLC_LO Lower Limit for Length of Data Bytes Filter 16 4 read-write PL1_LO Pretended Networking Payload Low Filter 1 Register 0xB14 32 read-write 0 0xFFFFFFFF Data_byte_3 Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 3. 0 8 read-write Data_byte_2 Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 2. 8 8 read-write Data_byte_1 Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 1. 16 8 read-write Data_byte_0 Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 0. 24 8 read-write PL1_HI Pretended Networking Payload High Filter 1 Register 0xB18 32 read-write 0 0xFFFFFFFF Data_byte_7 Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 7. 0 8 read-write Data_byte_6 Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 6. 8 8 read-write Data_byte_5 Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 5. 16 8 read-write Data_byte_4 Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 4. 24 8 read-write FLT_ID2_IDMASK Pretended Networking ID Filter 2 Register / ID Mask Register 0xB1C 32 read-write 0 0xFFFFFFFF FLT_ID2_IDMASK ID Filter 2 for Pretended Networking Filtering / ID Mask Bits for Pretended Networking ID Filtering 0 29 read-write RTR_MSK Remote Transmission Request Mask Bit 29 1 read-write 0 The corresponding bit in the filter is "don't care" #0 1 The corresponding bit in the filter is checked #1 IDE_MSK ID Extended Mask Bit 30 1 read-write 0 The corresponding bit in the filter is "don't care" #0 1 The corresponding bit in the filter is checked #1 PL2_PLMASK_LO Pretended Networking Payload Low Filter 2 Register / Payload Low Mask Register 0xB20 32 read-write 0 0xFFFFFFFF Data_byte_3 Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 3. 0 8 read-write Data_byte_2 Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 2. 8 8 read-write Data_byte_1 Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 1. 16 8 read-write Data_byte_0 Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 0. 24 8 read-write PL2_PLMASK_HI Pretended Networking Payload High Filter 2 low order bits / Payload High Mask Register 0xB24 32 read-write 0 0xFFFFFFFF Data_byte_7 Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 7. 0 8 read-write Data_byte_6 Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 6. 8 8 read-write Data_byte_5 Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 5. 16 8 read-write Data_byte_4 Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 4. 24 8 read-write WMB0_CS Wake Up Message Buffer Register for C/S 0xB40 32 read-only 0 0xFFFFFFFF DLC Length of Data in Bytes 16 4 read-only RTR Remote Transmission Request Bit 20 1 read-only 0 Frame is data one (not remote) #0 1 Frame is a remote one #1 IDE ID Extended Bit 21 1 read-only 0 Frame format is standard #0 1 Frame format is extended #1 SRR Substitute Remote Request 22 1 read-only WMB0_ID Wake Up Message Buffer Register for ID 0xB44 32 read-only 0 0xFFFFFFFF ID Received ID under Pretended Networking mode 0 29 read-only WMB0_D03 Wake Up Message Buffer Register for Data 0-3 0xB48 32 read-only 0 0xFFFFFFFF Data_byte_3 Received payload corresponding to the data byte 3 under Pretended Networking mode 0 8 read-only Data_byte_2 Received payload corresponding to the data byte 2 under Pretended Networking mode 8 8 read-only Data_byte_1 Received payload corresponding to the data byte 1 under Pretended Networking mode 16 8 read-only Data_byte_0 Received payload corresponding to the data byte 0 under Pretended Networking mode 24 8 read-only WMB0_D47 Wake Up Message Buffer Register Data 4-7 0xB4C 32 read-only 0 0xFFFFFFFF Data_byte_7 Received payload corresponding to the data byte 7 under Pretended Networking mode 0 8 read-only Data_byte_6 Received payload corresponding to the data byte 6 under Pretended Networking mode 8 8 read-only Data_byte_5 Received payload corresponding to the data byte 5 under Pretended Networking mode 16 8 read-only Data_byte_4 Received payload corresponding to the data byte 4 under Pretended Networking mode 24 8 read-only WMB1_CS Wake Up Message Buffer Register for C/S 0xB50 32 read-only 0 0xFFFFFFFF DLC Length of Data in Bytes 16 4 read-only RTR Remote Transmission Request Bit 20 1 read-only 0 Frame is data one (not remote) #0 1 Frame is a remote one #1 IDE ID Extended Bit 21 1 read-only 0 Frame format is standard #0 1 Frame format is extended #1 SRR Substitute Remote Request 22 1 read-only WMB1_ID Wake Up Message Buffer Register for ID 0xB54 32 read-only 0 0xFFFFFFFF ID Received ID under Pretended Networking mode 0 29 read-only WMB1_D03 Wake Up Message Buffer Register for Data 0-3 0xB58 32 read-only 0 0xFFFFFFFF Data_byte_3 Received payload corresponding to the data byte 3 under Pretended Networking mode 0 8 read-only Data_byte_2 Received payload corresponding to the data byte 2 under Pretended Networking mode 8 8 read-only Data_byte_1 Received payload corresponding to the data byte 1 under Pretended Networking mode 16 8 read-only Data_byte_0 Received payload corresponding to the data byte 0 under Pretended Networking mode 24 8 read-only WMB1_D47 Wake Up Message Buffer Register Data 4-7 0xB5C 32 read-only 0 0xFFFFFFFF Data_byte_7 Received payload corresponding to the data byte 7 under Pretended Networking mode 0 8 read-only Data_byte_6 Received payload corresponding to the data byte 6 under Pretended Networking mode 8 8 read-only Data_byte_5 Received payload corresponding to the data byte 5 under Pretended Networking mode 16 8 read-only Data_byte_4 Received payload corresponding to the data byte 4 under Pretended Networking mode 24 8 read-only WMB2_CS Wake Up Message Buffer Register for C/S 0xB60 32 read-only 0 0xFFFFFFFF DLC Length of Data in Bytes 16 4 read-only RTR Remote Transmission Request Bit 20 1 read-only 0 Frame is data one (not remote) #0 1 Frame is a remote one #1 IDE ID Extended Bit 21 1 read-only 0 Frame format is standard #0 1 Frame format is extended #1 SRR Substitute Remote Request 22 1 read-only WMB2_ID Wake Up Message Buffer Register for ID 0xB64 32 read-only 0 0xFFFFFFFF ID Received ID under Pretended Networking mode 0 29 read-only WMB2_D03 Wake Up Message Buffer Register for Data 0-3 0xB68 32 read-only 0 0xFFFFFFFF Data_byte_3 Received payload corresponding to the data byte 3 under Pretended Networking mode 0 8 read-only Data_byte_2 Received payload corresponding to the data byte 2 under Pretended Networking mode 8 8 read-only Data_byte_1 Received payload corresponding to the data byte 1 under Pretended Networking mode 16 8 read-only Data_byte_0 Received payload corresponding to the data byte 0 under Pretended Networking mode 24 8 read-only WMB2_D47 Wake Up Message Buffer Register Data 4-7 0xB6C 32 read-only 0 0xFFFFFFFF Data_byte_7 Received payload corresponding to the data byte 7 under Pretended Networking mode 0 8 read-only Data_byte_6 Received payload corresponding to the data byte 6 under Pretended Networking mode 8 8 read-only Data_byte_5 Received payload corresponding to the data byte 5 under Pretended Networking mode 16 8 read-only Data_byte_4 Received payload corresponding to the data byte 4 under Pretended Networking mode 24 8 read-only WMB3_CS Wake Up Message Buffer Register for C/S 0xB70 32 read-only 0 0xFFFFFFFF DLC Length of Data in Bytes 16 4 read-only RTR Remote Transmission Request Bit 20 1 read-only 0 Frame is data one (not remote) #0 1 Frame is a remote one #1 IDE ID Extended Bit 21 1 read-only 0 Frame format is standard #0 1 Frame format is extended #1 SRR Substitute Remote Request 22 1 read-only WMB3_ID Wake Up Message Buffer Register for ID 0xB74 32 read-only 0 0xFFFFFFFF ID Received ID under Pretended Networking mode 0 29 read-only WMB3_D03 Wake Up Message Buffer Register for Data 0-3 0xB78 32 read-only 0 0xFFFFFFFF Data_byte_3 Received payload corresponding to the data byte 3 under Pretended Networking mode 0 8 read-only Data_byte_2 Received payload corresponding to the data byte 2 under Pretended Networking mode 8 8 read-only Data_byte_1 Received payload corresponding to the data byte 1 under Pretended Networking mode 16 8 read-only Data_byte_0 Received payload corresponding to the data byte 0 under Pretended Networking mode 24 8 read-only WMB3_D47 Wake Up Message Buffer Register Data 4-7 0xB7C 32 read-only 0 0xFFFFFFFF Data_byte_7 Received payload corresponding to the data byte 7 under Pretended Networking mode 0 8 read-only Data_byte_6 Received payload corresponding to the data byte 6 under Pretended Networking mode 8 8 read-only Data_byte_5 Received payload corresponding to the data byte 5 under Pretended Networking mode 16 8 read-only Data_byte_4 Received payload corresponding to the data byte 4 under Pretended Networking mode 24 8 read-only FDCTRL CAN FD Control Register 0xC00 32 read-write 0x80000100 0xFFFFFFFF TDCVAL Transceiver Delay Compensation Value 0 6 read-only TDCOFF Transceiver Delay Compensation Offset 8 5 read-write TDCFAIL Transceiver Delay Compensation Fail 14 1 read-write 0 Measured loop delay is in range. #0 1 Measured loop delay is out of range. #1 TDCEN Transceiver Delay Compensation Enable 15 1 read-write 0 TDC is disabled #0 1 TDC is enabled #1 MBDSR0 Message Buffer Data Size for Region 0 16 2 read-write 00 Selects 8 bytes per Message Buffer. #00 01 Selects 16 bytes per Message Buffer. #01 10 Selects 32 bytes per Message Buffer. #10 11 Selects 64 bytes per Message Buffer. #11 FDRATE Bit Rate Switch Enable 31 1 read-write 0 Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect. #0 1 Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive. #1 FDCBT CAN FD Bit Timing Register 0xC04 32 read-write 0 0xFFFFFFFF FPSEG2 Fast Phase Segment 2 0 3 read-write FPSEG1 Fast Phase Segment 1 5 3 read-write FPROPSEG Fast Propagation Segment 10 5 read-write FRJW Fast Resync Jump Width 16 3 read-write FPRESDIV Fast Prescaler Division Factor 20 10 read-write FDCRC CAN FD CRC Register 0xC08 32 read-only 0 0xFFFFFFFF FD_TXCRC Extended Transmitted CRC value 0 21 read-only FD_MBCRC CRC Mailbox Number for FD_TXCRC 24 7 read-only LPSPI0 The LPSPI Memory Map/Register Definition can be found here. LPSPI LPSPI0_ 0x4002C000 0 0x78 registers LPSPI0 26 VERID Version ID Register 0 32 read-only 0x1000004 0xFFFFFFFF FEATURE Module Identification Number 0 16 read-only 0000000000000100 Standard feature set supporting 32-bit shift register. #100 MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM Parameter Register 0x4 32 read-only 0x202 0xFFFFFFFF TXFIFO Transmit FIFO Size 0 8 read-only RXFIFO Receive FIFO Size 8 8 read-only CR Control Register 0x10 32 read-write 0 0xFFFFFFFF MEN Module Enable 0 1 read-write 0 Module is disabled. #0 1 Module is enabled. #1 RST Software Reset 1 1 read-write 0 Master logic is not reset. #0 1 Master logic is reset. #1 DOZEN Doze mode enable 2 1 read-write 0 Module is enabled in Doze mode. #0 1 Module is disabled in Doze mode. #1 DBGEN Debug Enable 3 1 read-write 0 Module is disabled in debug mode. #0 1 Module is enabled in debug mode. #1 RTF Reset Transmit FIFO 8 1 write-only 0 No effect. #0 1 Transmit FIFO is reset. #1 RRF Reset Receive FIFO 9 1 write-only 0 No effect. #0 1 Receive FIFO is reset. #1 SR Status Register 0x14 32 read-write 0x1 0xFFFFFFFF TDF Transmit Data Flag 0 1 read-only 0 Transmit data not requested. #0 1 Transmit data is requested. #1 RDF Receive Data Flag 1 1 read-only 0 Receive Data is not ready. #0 1 Receive data is ready. #1 WCF Word Complete Flag 8 1 read-write 0 Transfer word not completed. #0 1 Transfer word completed. #1 FCF Frame Complete Flag 9 1 read-write 0 Frame transfer has not completed. #0 1 Frame transfer has completed. #1 TCF Transfer Complete Flag 10 1 read-write 0 All transfers have not completed. #0 1 All transfers have completed. #1 TEF Transmit Error Flag 11 1 read-write 0 Transmit FIFO underrun has not occurred. #0 1 Transmit FIFO underrun has occurred #1 REF Receive Error Flag 12 1 read-write 0 Receive FIFO has not overflowed. #0 1 Receive FIFO has overflowed. #1 DMF Data Match Flag 13 1 read-write 0 Have not received matching data. #0 1 Have received matching data. #1 MBF Module Busy Flag 24 1 read-only 0 LPSPI is idle. #0 1 LPSPI is busy. #1 IER Interrupt Enable Register 0x18 32 read-write 0 0xFFFFFFFF TDIE Transmit Data Interrupt Enable 0 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled #1 RDIE Receive Data Interrupt Enable 1 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 WCIE Word Complete Interrupt Enable 8 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 FCIE Frame Complete Interrupt Enable 9 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 TCIE Transfer Complete Interrupt Enable 10 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 TEIE Transmit Error Interrupt Enable 11 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 REIE Receive Error Interrupt Enable 12 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 DMIE Data Match Interrupt Enable 13 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 DER DMA Enable Register 0x1C 32 read-write 0 0xFFFFFFFF TDDE Transmit Data DMA Enable 0 1 read-write 0 DMA request disabled. #0 1 DMA request enabled #1 RDDE Receive Data DMA Enable 1 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 CFGR0 Configuration Register 0 0x20 32 read-write 0 0xFFFFFFFF HREN Host Request Enable 0 1 read-write 0 Host request is disabled. #0 1 Host request is enabled. #1 HRPOL Host Request Polarity 1 1 read-write 0 Active low. #0 1 Active high. #1 HRSEL Host Request Select 2 1 read-write 0 Host request input is pin LPSPI_HREQ. #0 1 Host request input is input trigger. #1 CIRFIFO Circular FIFO Enable 8 1 read-write 0 Circular FIFO is disabled. #0 1 Circular FIFO is enabled. #1 RDMO Receive Data Match Only 9 1 read-write 0 Received data is stored in the receive FIFO as normal. #0 1 Received data is discarded unless the DMF is set. #1 CFGR1 Configuration Register 1 0x24 32 read-write 0 0xFFFFFFFF MASTER Master Mode 0 1 read-write 0 Slave mode. #0 1 Master mode. #1 SAMPLE Sample Point 1 1 read-write 0 Input data sampled on SCK edge. #0 1 Input data sampled on delayed SCK edge. #1 AUTOPCS Automatic PCS 2 1 read-write 0 Automatic PCS generation disabled. #0 1 Automatic PCS generation enabled. #1 NOSTALL No Stall 3 1 read-write 0 Transfers will stall when transmit FIFO is empty or receive FIFO is full. #0 1 Transfers will not stall, allowing transmit FIFO underrun or receive FIFO overrun to occur. #1 PCSPOL Peripheral Chip Select Polarity 8 4 read-write 0000 The PCSx is active low. #0000 0001 The PCSx is active high. #0001 MATCFG Match Configuration 16 3 read-write 000 Match is disabled. #000 010 010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1) #010 011 011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1) #011 100 100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)] #100 101 101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)] #101 110 110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)] #110 111 111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)] #111 PINCFG Pin Configuration 24 2 read-write 00 SIN is used for input data and SOUT for output data. #00 01 SIN is used for both input and output data. #01 10 SOUT is used for both input and output data. #10 11 SOUT is used for input data and SIN for output data. #11 OUTCFG Output Config 26 1 read-write 0 Output data retains last value when chip select is negated. #0 1 Output data is tristated when chip select is negated. #1 PCSCFG Peripheral Chip Select Configuration 27 1 read-write 0 PCS[3:2] are enabled. #0 1 PCS[3:2] are disabled. #1 DMR0 Data Match Register 0 0x30 32 read-write 0 0xFFFFFFFF MATCH0 Match 0 Value 0 32 read-write DMR1 Data Match Register 1 0x34 32 read-write 0 0xFFFFFFFF MATCH1 Match 1 Value 0 32 read-write CCR Clock Configuration Register 0x40 32 read-write 0 0xFFFFFFFF SCKDIV SCK Divider 0 8 read-write DBT Delay Between Transfers 8 8 read-write PCSSCK PCS to SCK Delay 16 8 read-write SCKPCS SCK to PCS Delay 24 8 read-write FCR FIFO Control Register 0x58 32 read-write 0 0xFFFFFFFF TXWATER Transmit FIFO Watermark 0 2 read-write RXWATER Receive FIFO Watermark 16 2 read-write FSR FIFO Status Register 0x5C 32 read-only 0 0xFFFFFFFF TXCOUNT Transmit FIFO Count 0 3 read-only RXCOUNT Receive FIFO Count 16 3 read-only TCR Transmit Command Register 0x60 32 read-write 0x1F 0xFFFFFFFF FRAMESZ Frame Size 0 12 read-write WIDTH Transfer Width 16 2 read-write 00 Single bit transfer. #00 01 Two bit transfer. #01 10 Four bit transfer. #10 TXMSK Transmit Data Mask 18 1 read-write 0 Normal transfer. #0 1 Mask transmit data. #1 RXMSK Receive Data Mask 19 1 read-write 0 Normal transfer. #0 1 Receive data is masked. #1 CONTC Continuing Command 20 1 read-write 0 Command word for start of new transfer. #0 1 Command word for continuing transfer. #1 CONT Continuous Transfer 21 1 read-write 0 Continuous transfer disabled. #0 1 Continuous transfer enabled. #1 BYSW Byte Swap 22 1 read-write 0 Byte swap disabled. #0 1 Byte swap enabled. #1 LSBF LSB First 23 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 PCS Peripheral Chip Select 24 2 read-write 00 Transfer using LPSPI_PCS[0] #00 01 Transfer using LPSPI_PCS[1] #01 10 Transfer using LPSPI_PCS[2] #10 11 Transfer using LPSPI_PCS[3] #11 PRESCALE Prescaler Value 27 3 read-write 000 Divide by 1. #000 001 Divide by 2. #001 010 Divide by 4. #010 011 Divide by 8. #011 100 Divide by 16. #100 101 Divide by 32. #101 110 Divide by 64. #110 111 Divide by 128. #111 CPHA Clock Phase 30 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 31 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 TDR Transmit Data Register 0x64 32 write-only 0 0xFFFFFFFF DATA Transmit Data 0 32 write-only RSR Receive Status Register 0x70 32 read-only 0x2 0xFFFFFFFF SOF Start Of Frame 0 1 read-only 0 Subsequent data word received after LPSPI_PCS assertion. #0 1 First data word received after LPSPI_PCS assertion. #1 RXEMPTY RX FIFO Empty 1 1 read-only 0 RX FIFO is not empty. #0 1 RX FIFO is empty. #1 RDR Receive Data Register 0x74 32 read-only 0 0xFFFFFFFF DATA Receive Data 0 32 read-only LPSPI1 The LPSPI Memory Map/Register Definition can be found here. LPSPI LPSPI1_ 0x4002D000 0 0x78 registers LPSPI1 27 VERID Version ID Register 0 32 read-only 0x1000004 0xFFFFFFFF FEATURE Module Identification Number 0 16 read-only 0000000000000100 Standard feature set supporting 32-bit shift register. #100 MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM Parameter Register 0x4 32 read-only 0x202 0xFFFFFFFF TXFIFO Transmit FIFO Size 0 8 read-only RXFIFO Receive FIFO Size 8 8 read-only CR Control Register 0x10 32 read-write 0 0xFFFFFFFF MEN Module Enable 0 1 read-write 0 Module is disabled. #0 1 Module is enabled. #1 RST Software Reset 1 1 read-write 0 Master logic is not reset. #0 1 Master logic is reset. #1 DOZEN Doze mode enable 2 1 read-write 0 Module is enabled in Doze mode. #0 1 Module is disabled in Doze mode. #1 DBGEN Debug Enable 3 1 read-write 0 Module is disabled in debug mode. #0 1 Module is enabled in debug mode. #1 RTF Reset Transmit FIFO 8 1 write-only 0 No effect. #0 1 Transmit FIFO is reset. #1 RRF Reset Receive FIFO 9 1 write-only 0 No effect. #0 1 Receive FIFO is reset. #1 SR Status Register 0x14 32 read-write 0x1 0xFFFFFFFF TDF Transmit Data Flag 0 1 read-only 0 Transmit data not requested. #0 1 Transmit data is requested. #1 RDF Receive Data Flag 1 1 read-only 0 Receive Data is not ready. #0 1 Receive data is ready. #1 WCF Word Complete Flag 8 1 read-write 0 Transfer word not completed. #0 1 Transfer word completed. #1 FCF Frame Complete Flag 9 1 read-write 0 Frame transfer has not completed. #0 1 Frame transfer has completed. #1 TCF Transfer Complete Flag 10 1 read-write 0 All transfers have not completed. #0 1 All transfers have completed. #1 TEF Transmit Error Flag 11 1 read-write 0 Transmit FIFO underrun has not occurred. #0 1 Transmit FIFO underrun has occurred #1 REF Receive Error Flag 12 1 read-write 0 Receive FIFO has not overflowed. #0 1 Receive FIFO has overflowed. #1 DMF Data Match Flag 13 1 read-write 0 Have not received matching data. #0 1 Have received matching data. #1 MBF Module Busy Flag 24 1 read-only 0 LPSPI is idle. #0 1 LPSPI is busy. #1 IER Interrupt Enable Register 0x18 32 read-write 0 0xFFFFFFFF TDIE Transmit Data Interrupt Enable 0 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled #1 RDIE Receive Data Interrupt Enable 1 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 WCIE Word Complete Interrupt Enable 8 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 FCIE Frame Complete Interrupt Enable 9 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 TCIE Transfer Complete Interrupt Enable 10 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 TEIE Transmit Error Interrupt Enable 11 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 REIE Receive Error Interrupt Enable 12 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 DMIE Data Match Interrupt Enable 13 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 DER DMA Enable Register 0x1C 32 read-write 0 0xFFFFFFFF TDDE Transmit Data DMA Enable 0 1 read-write 0 DMA request disabled. #0 1 DMA request enabled #1 RDDE Receive Data DMA Enable 1 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 CFGR0 Configuration Register 0 0x20 32 read-write 0 0xFFFFFFFF HREN Host Request Enable 0 1 read-write 0 Host request is disabled. #0 1 Host request is enabled. #1 HRPOL Host Request Polarity 1 1 read-write 0 Active low. #0 1 Active high. #1 HRSEL Host Request Select 2 1 read-write 0 Host request input is pin LPSPI_HREQ. #0 1 Host request input is input trigger. #1 CIRFIFO Circular FIFO Enable 8 1 read-write 0 Circular FIFO is disabled. #0 1 Circular FIFO is enabled. #1 RDMO Receive Data Match Only 9 1 read-write 0 Received data is stored in the receive FIFO as normal. #0 1 Received data is discarded unless the DMF is set. #1 CFGR1 Configuration Register 1 0x24 32 read-write 0 0xFFFFFFFF MASTER Master Mode 0 1 read-write 0 Slave mode. #0 1 Master mode. #1 SAMPLE Sample Point 1 1 read-write 0 Input data sampled on SCK edge. #0 1 Input data sampled on delayed SCK edge. #1 AUTOPCS Automatic PCS 2 1 read-write 0 Automatic PCS generation disabled. #0 1 Automatic PCS generation enabled. #1 NOSTALL No Stall 3 1 read-write 0 Transfers will stall when transmit FIFO is empty or receive FIFO is full. #0 1 Transfers will not stall, allowing transmit FIFO underrun or receive FIFO overrun to occur. #1 PCSPOL Peripheral Chip Select Polarity 8 4 read-write 0000 The PCSx is active low. #0000 0001 The PCSx is active high. #0001 MATCFG Match Configuration 16 3 read-write 000 Match is disabled. #000 010 010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1) #010 011 011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1) #011 100 100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)] #100 101 101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)] #101 110 110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)] #110 111 111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)] #111 PINCFG Pin Configuration 24 2 read-write 00 SIN is used for input data and SOUT for output data. #00 01 SIN is used for both input and output data. #01 10 SOUT is used for both input and output data. #10 11 SOUT is used for input data and SIN for output data. #11 OUTCFG Output Config 26 1 read-write 0 Output data retains last value when chip select is negated. #0 1 Output data is tristated when chip select is negated. #1 PCSCFG Peripheral Chip Select Configuration 27 1 read-write 0 PCS[3:2] are enabled. #0 1 PCS[3:2] are disabled. #1 DMR0 Data Match Register 0 0x30 32 read-write 0 0xFFFFFFFF MATCH0 Match 0 Value 0 32 read-write DMR1 Data Match Register 1 0x34 32 read-write 0 0xFFFFFFFF MATCH1 Match 1 Value 0 32 read-write CCR Clock Configuration Register 0x40 32 read-write 0 0xFFFFFFFF SCKDIV SCK Divider 0 8 read-write DBT Delay Between Transfers 8 8 read-write PCSSCK PCS to SCK Delay 16 8 read-write SCKPCS SCK to PCS Delay 24 8 read-write FCR FIFO Control Register 0x58 32 read-write 0 0xFFFFFFFF TXWATER Transmit FIFO Watermark 0 2 read-write RXWATER Receive FIFO Watermark 16 2 read-write FSR FIFO Status Register 0x5C 32 read-only 0 0xFFFFFFFF TXCOUNT Transmit FIFO Count 0 3 read-only RXCOUNT Receive FIFO Count 16 3 read-only TCR Transmit Command Register 0x60 32 read-write 0x1F 0xFFFFFFFF FRAMESZ Frame Size 0 12 read-write WIDTH Transfer Width 16 2 read-write 00 Single bit transfer. #00 01 Two bit transfer. #01 10 Four bit transfer. #10 TXMSK Transmit Data Mask 18 1 read-write 0 Normal transfer. #0 1 Mask transmit data. #1 RXMSK Receive Data Mask 19 1 read-write 0 Normal transfer. #0 1 Receive data is masked. #1 CONTC Continuing Command 20 1 read-write 0 Command word for start of new transfer. #0 1 Command word for continuing transfer. #1 CONT Continuous Transfer 21 1 read-write 0 Continuous transfer disabled. #0 1 Continuous transfer enabled. #1 BYSW Byte Swap 22 1 read-write 0 Byte swap disabled. #0 1 Byte swap enabled. #1 LSBF LSB First 23 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 PCS Peripheral Chip Select 24 2 read-write 00 Transfer using LPSPI_PCS[0] #00 01 Transfer using LPSPI_PCS[1] #01 10 Transfer using LPSPI_PCS[2] #10 11 Transfer using LPSPI_PCS[3] #11 PRESCALE Prescaler Value 27 3 read-write 000 Divide by 1. #000 001 Divide by 2. #001 010 Divide by 4. #010 011 Divide by 8. #011 100 Divide by 16. #100 101 Divide by 32. #101 110 Divide by 64. #110 111 Divide by 128. #111 CPHA Clock Phase 30 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 31 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 TDR Transmit Data Register 0x64 32 write-only 0 0xFFFFFFFF DATA Transmit Data 0 32 write-only RSR Receive Status Register 0x70 32 read-only 0x2 0xFFFFFFFF SOF Start Of Frame 0 1 read-only 0 Subsequent data word received after LPSPI_PCS assertion. #0 1 First data word received after LPSPI_PCS assertion. #1 RXEMPTY RX FIFO Empty 1 1 read-only 0 RX FIFO is not empty. #0 1 RX FIFO is empty. #1 RDR Receive Data Register 0x74 32 read-only 0 0xFFFFFFFF DATA Receive Data 0 32 read-only CRC Cyclic Redundancy Check CRC_ 0x40032000 0 0xC registers DATA CRC Data register CRC 0 32 read-write 0xFFFFFFFF 0xFFFFFFFF LL CRC Low Lower Byte 0 8 read-write LU CRC Low Upper Byte 8 8 read-write HL CRC High Lower Byte 16 8 read-write HU CRC High Upper Byte 24 8 read-write DATAL CRC_DATAL register. CRC 0 16 read-write 0xFFFF 0xFFFF DATAL DATAL stores the lower 16 bits of the 16/32 bit CRC 0 16 read-write DATALL CRC_DATALL register. CRC 0 8 read-write 0xFF 0xFF DATALL CRCLL stores the first 8 bits of the 32 bit DATA 0 8 read-write DATALU CRC_DATALU register. 0x1 8 read-write 0xFF 0xFF DATALU DATALL stores the second 8 bits of the 32 bit CRC 0 8 read-write DATAH CRC_DATAH register. CRC 0x2 16 read-write 0xFFFF 0xFFFF DATAH DATAH stores the high 16 bits of the 16/32 bit CRC 0 16 read-write DATAHL CRC_DATAHL register. CRC 0x2 8 read-write 0xFF 0xFF DATAHL DATAHL stores the third 8 bits of the 32 bit CRC 0 8 read-write DATAHU CRC_DATAHU register. 0x3 8 read-write 0xFF 0xFF DATAHU DATAHU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write GPOLY CRC Polynomial register 0x4 32 read-write 0x1021 0xFFFFFFFF LOW Low Polynominal Half-word 0 16 read-write HIGH High Polynominal Half-word 16 16 read-write CTRL CRC Control register 0x8 32 read-write 0 0xFFFFFFFF TCRC TCRC 24 1 read-write 0 16-bit CRC protocol. #0 1 32-bit CRC protocol. #1 WAS Write CRC Data Register As Seed 25 1 read-write 0 Writes to the CRC data register are data values. #0 1 Writes to the CRC data register are seed values. #1 FXOR Complement Read Of CRC Data Register 26 1 read-write 0 No XOR on reading. #0 1 Invert or complement the read value of the CRC Data register. #1 TOTR Type Of Transpose For Read 28 2 read-write 00 No transposition. #00 01 Bits in bytes are transposed; bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 TOT Type Of Transpose For Writes 30 2 read-write 00 No transposition. #00 01 Bits in bytes are transposed; bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 PDB0 Programmable Delay Block PDB0_ 0x40036000 0 0x198 registers PDB0 19 SC Status and Control register 0 32 read-write 0 0xFFFFFFFF LDOK Load OK 0 1 read-write CONT Continuous Mode Enable 1 1 read-write 0 PDB operation in One-Shot mode #0 1 PDB operation in Continuous mode #1 MULT Multiplication Factor Select for Prescaler 2 2 read-write 00 Multiplication factor is 1. #00 01 Multiplication factor is 10. #01 10 Multiplication factor is 20. #10 11 Multiplication factor is 40. #11 PDBIE PDB Interrupt Enable 5 1 read-write 0 PDB interrupt disabled. #0 1 PDB interrupt enabled. #1 PDBIF PDB Interrupt Flag 6 1 read-write PDBEN PDB Enable 7 1 read-write 0 PDB disabled. Counter is off. #0 1 PDB enabled. #1 TRGSEL Trigger Input Source Select 8 4 read-write 0000 Trigger-In 0 is selected. #0000 0001 Trigger-In 1 is selected. #0001 0010 Trigger-In 2 is selected. #0010 0011 Trigger-In 3 is selected. #0011 0100 Trigger-In 4 is selected. #0100 0101 Trigger-In 5 is selected. #0101 0110 Trigger-In 6 is selected. #0110 0111 Trigger-In 7 is selected. #0111 1000 Trigger-In 8 is selected. #1000 1001 Trigger-In 9 is selected. #1001 1010 Trigger-In 10 is selected. #1010 1011 Trigger-In 11 is selected. #1011 1100 Trigger-In 12 is selected. #1100 1101 Trigger-In 13 is selected. #1101 1110 Trigger-In 14 is selected. #1110 1111 Software trigger is selected. #1111 PRESCALER Prescaler Divider Select 12 3 read-write 000 Counting uses the peripheral clock divided by MULT (the multiplication factor). #000 001 Counting uses the peripheral clock divided by 2 x MULT (the multiplication factor). #001 010 Counting uses the peripheral clock divided by 4 x MULT (the multiplication factor). #010 011 Counting uses the peripheral clock divided by 8 x MULT (the multiplication factor). #011 100 Counting uses the peripheral clock divided by 16 x MULT (the multiplication factor). #100 101 Counting uses the peripheral clock divided by 32 x MULT (the multiplication factor). #101 110 Counting uses the peripheral clock divided by 64 x MULT (the multiplication factor). #110 111 Counting uses the peripheral clock divided by 128 x MULT (the multiplication factor). #111 DMAEN DMA Enable 15 1 read-write 0 DMA disabled. #0 1 DMA enabled. #1 SWTRIG Software Trigger 16 1 write-only PDBEIE PDB Sequence Error Interrupt Enable 17 1 read-write 0 PDB sequence error interrupt disabled. #0 1 PDB sequence error interrupt enabled. #1 LDMOD Load Mode Select 18 2 read-write 00 The internal registers are loaded with the values from their buffers, immediately after 1 is written to LDOK. #00 01 The internal registers are loaded with the values from their buffers when the PDB counter (CNT) = MOD + 1 CNT delay elapsed, after 1 is written to LDOK. #01 10 The internal registers are loaded with the values from their buffers when a trigger input event is detected, after 1 is written to LDOK. #10 11 The internal registers are loaded with the values from their buffers when either the PDB counter (CNT) = MOD + 1 CNT delay elapsed, or a trigger input event is detected, after 1 is written to LDOK. #11 MOD Modulus register 0x4 32 read-write 0xFFFF 0xFFFFFFFF MOD PDB Modulus 0 16 read-write CNT Counter register 0x8 32 read-only 0 0xFFFFFFFF CNT PDB Counter 0 16 read-only IDLY Interrupt Delay register 0xC 32 read-write 0xFFFF 0xFFFFFFFF IDLY PDB Interrupt Delay 0 16 read-write 2 0x28 0,1 CH%sC1 Channel n Control register 1 0x10 32 read-write 0 0xFFFFFFFF EN PDB Channel Pre-Trigger Enable 0 8 read-write 0 PDB channel's corresponding pre-trigger disabled. #0 1 PDB channel's corresponding pre-trigger enabled. #1 TOS PDB Channel Pre-Trigger Output Select 8 8 read-write 0 PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #1 BB PDB Channel Pre-Trigger Back-to-Back Operation Enable 16 8 read-write 0 PDB channel's corresponding pre-trigger back-to-back operation disabled. #0 1 PDB channel's corresponding pre-trigger back-to-back operation enabled. #1 2 0x28 0,1 CH%sS Channel n Status register 0x14 32 read-write 0 0xFFFFFFFF ERR PDB Channel Sequence Error Flags 0 8 read-write 0 Sequence error not detected on PDB channel's corresponding pre-trigger. #0 1 Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags. #1 CF PDB Channel Flags 16 8 read-write 2 0x28 0,1 CH%sDLY0 Channel n Delay 0 register 0x18 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write 2 0x28 0,1 CH%sDLY1 Channel n Delay 1 register 0x1C 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write 2 0x28 0,1 CH%sDLY2 Channel n Delay 2 register 0x20 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write 2 0x28 0,1 CH%sDLY3 Channel n Delay 3 register 0x24 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write 2 0x28 0,1 CH%sDLY4 Channel n Delay 4 register 0x28 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write 2 0x28 0,1 CH%sDLY5 Channel n Delay 5 register 0x2C 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write 2 0x28 0,1 CH%sDLY6 Channel n Delay 6 register 0x30 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write 2 0x28 0,1 CH%sDLY7 Channel n Delay 7 register 0x34 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write POEN Pulse-Out n Enable register 0x190 32 read-write 0 0xFFFFFFFF POEN PDB Pulse-Out Enable 0 8 read-write 0 PDB Pulse-Out disabled #0 1 PDB Pulse-Out enabled #1 PODLY Pulse-Out n Delay register PDB0 0x194 32 read-write 0 0xFFFFFFFF DLY2 PDB Pulse-Out Delay 2 0 16 read-write DLY1 PDB Pulse-Out Delay 1 16 16 read-write DLY2 PDB0_DLY2 register. PDB0 0x194 16 read-write 0 0 DLY2 DLY2 0 16 read-write DLY1 PDB0_DLY1 register. 0x196 16 read-write 0xFFFF 0xFFFF DLY1 DLY1 0 16 read-write LPIT0 Low Power Periodic Interrupt Timer (LPIT) LPIT0_ 0x40037000 0 0x5C registers LPIT0 20 VERID Version ID Register 0 32 read-only 0x1000000 0xFFFFFFFF FEATURE Feature Number 0 16 read-only MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM Parameter Register 0x4 32 read-only 0x404 0xFFFFFFFF CHANNEL Number of Timer Channels 0 8 read-only EXT_TRIG Number of External Trigger Inputs 8 8 read-only MCR Module Control Register 0x8 32 read-write 0 0xFFFFFFFF M_CEN Module Clock Enable 0 1 read-write 0 Peripheral clock to timers is disabled #0 1 Peripheral clock to timers is enabled #1 SW_RST Software Reset Bit 1 1 read-write 0 Timer channels and registers are not reset #0 1 Timer channels and registers are reset #1 DOZE_EN DOZE Mode Enable Bit 2 1 read-write 0 Timer channels are stopped in DOZE mode #0 1 Timer channels continue to run in DOZE mode #1 DBG_EN Debug Enable Bit 3 1 read-write 0 Timer channels are stopped in Debug mode #0 1 Timer channels continue to run in Debug mode #1 MSR Module Status Register 0xC 32 read-write 0 0xFFFFFFFF TIF0 Channel 0 Timer Interrupt Flag 0 1 read-write 0 Timer has not timed out #0 1 Timeout has occurred #1 TIF1 Channel 1 Timer Interrupt Flag 1 1 read-write 0 Timer has not timed out #0 1 Timeout has occurred #1 TIF2 Channel 2 Timer Interrupt Flag 2 1 read-write 0 Timer has not timed out #0 1 Timeout has occurred #1 TIF3 Channel 3 Timer Interrupt Flag 3 1 read-write 0 Timer has not timed out #0 1 Timeout has occurred #1 MIER Module Interrupt Enable Register 0x10 32 read-write 0 0xFFFFFFFF TIE0 Channel 0 Timer Interrupt Enable 0 1 read-write 0 Interrupt generation is disabled #0 1 Interrupt generation is enabled #1 TIE1 Channel 1 Timer Interrupt Enable 1 1 read-write 0 Interrupt generation is disabled #0 1 Interrupt generation is enabled #1 TIE2 Channel 2 Timer Interrupt Enable 2 1 read-write 0 Interrupt generation is disabled #0 1 Interrupt generation is enabled #1 TIE3 Channel 3 Timer Interrupt Enable 3 1 read-write 0 Interrupt generation is disabled #0 1 Interrupt generation is enabled #1 SETTEN Set Timer Enable Register 0x14 32 read-write 0 0xFFFFFFFF SET_T_EN_0 Set Timer 0 Enable 0 1 read-write 0 No effect #0 1 Enables the Timer Channel 0 #1 SET_T_EN_1 Set Timer 1 Enable 1 1 read-write 0 No Effect #0 1 Enables the Timer Channel 1 #1 SET_T_EN_2 Set Timer 2 Enable 2 1 read-write 0 No Effect #0 1 Enables the Timer Channel 2 #1 SET_T_EN_3 Set Timer 3 Enable 3 1 read-write 0 No effect #0 1 Enables the Timer Channel 3 #1 CLRTEN Clear Timer Enable Register 0x18 32 read-write 0 0xFFFFFFFF CLR_T_EN_0 Clear Timer 0 Enable 0 1 write-only 0 No action #0 1 Clear T_EN bit for Timer Channel 0 #1 CLR_T_EN_1 Clear Timer 1 Enable 1 1 write-only 0 No Action #0 1 Clear T_EN bit for Timer Channel 1 #1 CLR_T_EN_2 Clear Timer 2 Enable 2 1 write-only 0 No Action #0 1 Clear T_EN bit for Timer Channel 2 #1 CLR_T_EN_3 Clear Timer 3 Enable 3 1 write-only 0 No Action #0 1 Clear T_EN bit for Timer Channel 3 #1 TVAL0 Timer Value Register 0x20 32 read-write 0 0xFFFFFFFF TMR_VAL Timer Value 0 32 read-write 0 Invalid load value in compare modes. #0 1 Invalid load value in compare modes. #1 CVAL0 Current Timer Value 0x24 32 read-only 0xFFFFFFFF 0xFFFFFFFF TMR_CUR_VAL Current Timer Value 0 32 read-only TCTRL0 Timer Control Register 0x28 32 read-write 0 0xFFFFFFFF T_EN Timer Enable 0 1 read-write 0 Timer Channel is disabled #0 1 Timer Channel is enabled #1 CHAIN Chain Channel 1 1 read-write 0 Channel Chaining is disabled. Channel Timer runs independently. #0 1 Channel Chaining is enabled. Timer decrements on previous channel's timeout #1 MODE Timer Operation Mode 2 2 read-write 0 32-bit Periodic Counter #00 1 Dual 16-bit Periodic Counter #01 10 32-bit Trigger Accumulator #10 11 32-bit Trigger Input Capture #11 TSOT Timer Start On Trigger 16 1 read-write 0 Timer starts to decrement immediately based on restart condition (controlled by TSOI bit) #0 1 Timer starts to decrement when rising edge on selected trigger is detected #1 TSOI Timer Stop On Interrupt 17 1 read-write 0 The channel timer does not stop after timeout. #0 1 The channel timer will stop after a timeout, and the channel timer will restart based on TSOT. When TSOT = 0, the channel timer will restart after a rising edge on the T_EN bit is detected (which means that the timer channel is disabled and then enabled); when TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected. #1 TROT Timer Reload On Trigger 18 1 read-write 0 Timer will not reload on selected trigger #0 1 Timer will reload on selected trigger #1 TRG_SRC Trigger Source 23 1 read-write 0 Trigger source selected in external #0 1 Trigger source selected is the internal trigger #1 TRG_SEL Trigger Select 24 4 read-write TVAL1 Timer Value Register 0x30 32 read-write 0 0xFFFFFFFF TMR_VAL Timer Value 0 32 read-write 0 Invalid load value in compare modes. #0 1 Invalid load value in compare modes. #1 CVAL1 Current Timer Value 0x34 32 read-only 0xFFFFFFFF 0xFFFFFFFF TMR_CUR_VAL Current Timer Value 0 32 read-only TCTRL1 Timer Control Register 0x38 32 read-write 0 0xFFFFFFFF T_EN Timer Enable 0 1 read-write 0 Timer Channel is disabled #0 1 Timer Channel is enabled #1 CHAIN Chain Channel 1 1 read-write 0 Channel Chaining is disabled. Channel Timer runs independently. #0 1 Channel Chaining is enabled. Timer decrements on previous channel's timeout #1 MODE Timer Operation Mode 2 2 read-write 0 32-bit Periodic Counter #00 1 Dual 16-bit Periodic Counter #01 10 32-bit Trigger Accumulator #10 11 32-bit Trigger Input Capture #11 TSOT Timer Start On Trigger 16 1 read-write 0 Timer starts to decrement immediately based on restart condition (controlled by TSOI bit) #0 1 Timer starts to decrement when rising edge on selected trigger is detected #1 TSOI Timer Stop On Interrupt 17 1 read-write 0 The channel timer does not stop after timeout. #0 1 The channel timer will stop after a timeout, and the channel timer will restart based on TSOT. When TSOT = 0, the channel timer will restart after a rising edge on the T_EN bit is detected (which means that the timer channel is disabled and then enabled); when TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected. #1 TROT Timer Reload On Trigger 18 1 read-write 0 Timer will not reload on selected trigger #0 1 Timer will reload on selected trigger #1 TRG_SRC Trigger Source 23 1 read-write 0 Trigger source selected in external #0 1 Trigger source selected is the internal trigger #1 TRG_SEL Trigger Select 24 4 read-write TVAL2 Timer Value Register 0x40 32 read-write 0 0xFFFFFFFF TMR_VAL Timer Value 0 32 read-write 0 Invalid load value in compare modes. #0 1 Invalid load value in compare modes. #1 CVAL2 Current Timer Value 0x44 32 read-only 0xFFFFFFFF 0xFFFFFFFF TMR_CUR_VAL Current Timer Value 0 32 read-only TCTRL2 Timer Control Register 0x48 32 read-write 0 0xFFFFFFFF T_EN Timer Enable 0 1 read-write 0 Timer Channel is disabled #0 1 Timer Channel is enabled #1 CHAIN Chain Channel 1 1 read-write 0 Channel Chaining is disabled. Channel Timer runs independently. #0 1 Channel Chaining is enabled. Timer decrements on previous channel's timeout #1 MODE Timer Operation Mode 2 2 read-write 0 32-bit Periodic Counter #00 1 Dual 16-bit Periodic Counter #01 10 32-bit Trigger Accumulator #10 11 32-bit Trigger Input Capture #11 TSOT Timer Start On Trigger 16 1 read-write 0 Timer starts to decrement immediately based on restart condition (controlled by TSOI bit) #0 1 Timer starts to decrement when rising edge on selected trigger is detected #1 TSOI Timer Stop On Interrupt 17 1 read-write 0 The channel timer does not stop after timeout. #0 1 The channel timer will stop after a timeout, and the channel timer will restart based on TSOT. When TSOT = 0, the channel timer will restart after a rising edge on the T_EN bit is detected (which means that the timer channel is disabled and then enabled); when TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected. #1 TROT Timer Reload On Trigger 18 1 read-write 0 Timer will not reload on selected trigger #0 1 Timer will reload on selected trigger #1 TRG_SRC Trigger Source 23 1 read-write 0 Trigger source selected in external #0 1 Trigger source selected is the internal trigger #1 TRG_SEL Trigger Select 24 4 read-write TVAL3 Timer Value Register 0x50 32 read-write 0 0xFFFFFFFF TMR_VAL Timer Value 0 32 read-write 0 Invalid load value in compare modes. #0 1 Invalid load value in compare modes. #1 CVAL3 Current Timer Value 0x54 32 read-only 0xFFFFFFFF 0xFFFFFFFF TMR_CUR_VAL Current Timer Value 0 32 read-only TCTRL3 Timer Control Register 0x58 32 read-write 0 0xFFFFFFFF T_EN Timer Enable 0 1 read-write 0 Timer Channel is disabled #0 1 Timer Channel is enabled #1 CHAIN Chain Channel 1 1 read-write 0 Channel Chaining is disabled. Channel Timer runs independently. #0 1 Channel Chaining is enabled. Timer decrements on previous channel's timeout #1 MODE Timer Operation Mode 2 2 read-write 0 32-bit Periodic Counter #00 1 Dual 16-bit Periodic Counter #01 10 32-bit Trigger Accumulator #10 11 32-bit Trigger Input Capture #11 TSOT Timer Start On Trigger 16 1 read-write 0 Timer starts to decrement immediately based on restart condition (controlled by TSOI bit) #0 1 Timer starts to decrement when rising edge on selected trigger is detected #1 TSOI Timer Stop On Interrupt 17 1 read-write 0 The channel timer does not stop after timeout. #0 1 The channel timer will stop after a timeout, and the channel timer will restart based on TSOT. When TSOT = 0, the channel timer will restart after a rising edge on the T_EN bit is detected (which means that the timer channel is disabled and then enabled); when TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected. #1 TROT Timer Reload On Trigger 18 1 read-write 0 Timer will not reload on selected trigger #0 1 Timer will reload on selected trigger #1 TRG_SRC Trigger Source 23 1 read-write 0 Trigger source selected in external #0 1 Trigger source selected is the internal trigger #1 TRG_SEL Trigger Select 24 4 read-write FTM0 FlexTimer Module FTM FTM0_ 0x40038000 0 0x224 registers FTM0_Ch0_7 12 FTM0_Fault 13 FTM0_Ovf_Reload 14 SC Status And Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CLKS Clock Source Selection 3 2 read-write 00 No clock selected. This in effect disables the FTM counter. #00 01 FTM input clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-Aligned PWM Select 5 1 read-write 0 FTM counter operates in Up Counting mode. #0 1 FTM counter operates in Up-Down Counting mode. #1 RIE Reload Point Interrupt Enable 6 1 read-write 0 Reload point interrupt is disabled. #0 1 Reload point interrupt is enabled. #1 RF Reload Flag 7 1 read-only 0 A selected reload point did not happen. #0 1 A selected reload point happened. #1 TOIE Timer Overflow Interrupt Enable 8 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 9 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 PWMEN0 Channel 0 PWM enable bit 16 1 read-write 0 Channel output port is disabled #0 1 Channel output port is enabled #1 PWMEN1 Channel 1 PWM enable bit 17 1 read-write 0 Channel output port is disabled #0 1 Channel output port is enabled #1 PWMEN2 Channel 2 PWM enable bit 18 1 read-write 0 Channel output port is disabled #0 1 Channel output port is enabled #1 PWMEN3 Channel 3 PWM enable bit 19 1 read-write 0 Channel output port is disabled #0 1 Channel output port is enabled #1 PWMEN4 Channel 4 PWM enable bit 20 1 read-write 0 Channel output port is disabled #0 1 Channel output port is enabled #1 PWMEN5 Channel 5 PWM enable bit 21 1 read-write 0 Channel output port is disabled #0 1 Channel output port is enabled #1 PWMEN6 Channel 6 PWM enable bit 22 1 read-write 0 Channel output port is disabled #0 1 Channel output port is enabled #1 PWMEN7 Channel 7 PWM enable bit 23 1 read-write 0 Channel output port is disabled #0 1 Channel output port is enabled #1 FLTPS Filter Prescaler 24 4 read-write 0000 Divide by 1 #0000 0001 Divide by 2 #0001 0010 Divide by 3 #0010 0011 Divide by 4 #0011 0100 Divide by 5 #0100 0101 Divide by 6 #0101 0110 Divide by 7 #0110 0111 Divide by 8 #0111 1000 Divide by 9 #1000 1001 Divide by 10 #1001 1010 Divide by 11 #1010 1011 Divide by 12 #1011 1100 Divide by 13 #1100 1101 Divide by 14 #1101 1110 Divide by 15 #1110 1111 Divide by 16 #1111 CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter Value 0 16 read-write MOD Modulo 0x8 32 read-write 0 0xFFFFFFFF MOD MOD 0 16 read-write C0SC Channel (n) Status And Control 0xC 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 ELSA Channel (n) Edge or Level Select 2 1 read-write ELSB Channel (n) Edge or Level Select 3 1 read-write MSA Channel (n) Mode Select 4 1 read-write MSB Channel (n) Mode Select 5 1 read-write CHIE Channel (n) Interrupt Enable 6 1 read-write 0 Disable channel (n) interrupt. Use software polling. #0 1 Enable channel (n) interrupt. #1 CHF Channel (n) Flag 7 1 read-only 0 No channel (n) event has occurred. #0 1 A channel (n) event has occurred. #1 TRIGMODE Trigger mode control 8 1 read-write 0 Channel outputs will generate the normal PWM outputs without generating a pulse. #0 1 If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle. #1 CHIS Channel (n) Input State 9 1 read-only 0 The channel (n) input is zero. #0 1 The channel (n) input is one. #1 CHOV Channel (n) Output Value 10 1 read-only 0 The channel (n) output is zero. #0 1 The channel (n) output is one. #1 C0V Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write C1SC Channel (n) Status And Control 0x14 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 ELSA Channel (n) Edge or Level Select 2 1 read-write ELSB Channel (n) Edge or Level Select 3 1 read-write MSA Channel (n) Mode Select 4 1 read-write MSB Channel (n) Mode Select 5 1 read-write CHIE Channel (n) Interrupt Enable 6 1 read-write 0 Disable channel (n) interrupt. Use software polling. #0 1 Enable channel (n) interrupt. #1 CHF Channel (n) Flag 7 1 read-only 0 No channel (n) event has occurred. #0 1 A channel (n) event has occurred. #1 TRIGMODE Trigger mode control 8 1 read-write 0 Channel outputs will generate the normal PWM outputs without generating a pulse. #0 1 If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle. #1 CHIS Channel (n) Input State 9 1 read-only 0 The channel (n) input is zero. #0 1 The channel (n) input is one. #1 CHOV Channel (n) Output Value 10 1 read-only 0 The channel (n) output is zero. #0 1 The channel (n) output is one. #1 C1V Channel (n) Value 0x18 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write C2SC Channel (n) Status And Control 0x1C 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 ELSA Channel (n) Edge or Level Select 2 1 read-write ELSB Channel (n) Edge or Level Select 3 1 read-write MSA Channel (n) Mode Select 4 1 read-write MSB Channel (n) Mode Select 5 1 read-write CHIE Channel (n) Interrupt Enable 6 1 read-write 0 Disable channel (n) interrupt. Use software polling. #0 1 Enable channel (n) interrupt. #1 CHF Channel (n) Flag 7 1 read-only 0 No channel (n) event has occurred. #0 1 A channel (n) event has occurred. #1 TRIGMODE Trigger mode control 8 1 read-write 0 Channel outputs will generate the normal PWM outputs without generating a pulse. #0 1 If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle. #1 CHIS Channel (n) Input State 9 1 read-only 0 The channel (n) input is zero. #0 1 The channel (n) input is one. #1 CHOV Channel (n) Output Value 10 1 read-only 0 The channel (n) output is zero. #0 1 The channel (n) output is one. #1 C2V Channel (n) Value 0x20 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write C3SC Channel (n) Status And Control 0x24 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 ELSA Channel (n) Edge or Level Select 2 1 read-write ELSB Channel (n) Edge or Level Select 3 1 read-write MSA Channel (n) Mode Select 4 1 read-write MSB Channel (n) Mode Select 5 1 read-write CHIE Channel (n) Interrupt Enable 6 1 read-write 0 Disable channel (n) interrupt. Use software polling. #0 1 Enable channel (n) interrupt. #1 CHF Channel (n) Flag 7 1 read-only 0 No channel (n) event has occurred. #0 1 A channel (n) event has occurred. #1 TRIGMODE Trigger mode control 8 1 read-write 0 Channel outputs will generate the normal PWM outputs without generating a pulse. #0 1 If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle. #1 CHIS Channel (n) Input State 9 1 read-only 0 The channel (n) input is zero. #0 1 The channel (n) input is one. #1 CHOV Channel (n) Output Value 10 1 read-only 0 The channel (n) output is zero. #0 1 The channel (n) output is one. #1 C3V Channel (n) Value 0x28 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write C4SC Channel (n) Status And Control 0x2C 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 ELSA Channel (n) Edge or Level Select 2 1 read-write ELSB Channel (n) Edge or Level Select 3 1 read-write MSA Channel (n) Mode Select 4 1 read-write MSB Channel (n) Mode Select 5 1 read-write CHIE Channel (n) Interrupt Enable 6 1 read-write 0 Disable channel (n) interrupt. Use software polling. #0 1 Enable channel (n) interrupt. #1 CHF Channel (n) Flag 7 1 read-only 0 No channel (n) event has occurred. #0 1 A channel (n) event has occurred. #1 TRIGMODE Trigger mode control 8 1 read-write 0 Channel outputs will generate the normal PWM outputs without generating a pulse. #0 1 If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle. #1 CHIS Channel (n) Input State 9 1 read-only 0 The channel (n) input is zero. #0 1 The channel (n) input is one. #1 CHOV Channel (n) Output Value 10 1 read-only 0 The channel (n) output is zero. #0 1 The channel (n) output is one. #1 C4V Channel (n) Value 0x30 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write C5SC Channel (n) Status And Control 0x34 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 ELSA Channel (n) Edge or Level Select 2 1 read-write ELSB Channel (n) Edge or Level Select 3 1 read-write MSA Channel (n) Mode Select 4 1 read-write MSB Channel (n) Mode Select 5 1 read-write CHIE Channel (n) Interrupt Enable 6 1 read-write 0 Disable channel (n) interrupt. Use software polling. #0 1 Enable channel (n) interrupt. #1 CHF Channel (n) Flag 7 1 read-only 0 No channel (n) event has occurred. #0 1 A channel (n) event has occurred. #1 TRIGMODE Trigger mode control 8 1 read-write 0 Channel outputs will generate the normal PWM outputs without generating a pulse. #0 1 If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle. #1 CHIS Channel (n) Input State 9 1 read-only 0 The channel (n) input is zero. #0 1 The channel (n) input is one. #1 CHOV Channel (n) Output Value 10 1 read-only 0 The channel (n) output is zero. #0 1 The channel (n) output is one. #1 C5V Channel (n) Value 0x38 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write C6SC Channel (n) Status And Control 0x3C 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 ELSA Channel (n) Edge or Level Select 2 1 read-write ELSB Channel (n) Edge or Level Select 3 1 read-write MSA Channel (n) Mode Select 4 1 read-write MSB Channel (n) Mode Select 5 1 read-write CHIE Channel (n) Interrupt Enable 6 1 read-write 0 Disable channel (n) interrupt. Use software polling. #0 1 Enable channel (n) interrupt. #1 CHF Channel (n) Flag 7 1 read-only 0 No channel (n) event has occurred. #0 1 A channel (n) event has occurred. #1 TRIGMODE Trigger mode control 8 1 read-write 0 Channel outputs will generate the normal PWM outputs without generating a pulse. #0 1 If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle. #1 CHIS Channel (n) Input State 9 1 read-only 0 The channel (n) input is zero. #0 1 The channel (n) input is one. #1 CHOV Channel (n) Output Value 10 1 read-only 0 The channel (n) output is zero. #0 1 The channel (n) output is one. #1 C6V Channel (n) Value 0x40 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write C7SC Channel (n) Status And Control 0x44 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 ELSA Channel (n) Edge or Level Select 2 1 read-write ELSB Channel (n) Edge or Level Select 3 1 read-write MSA Channel (n) Mode Select 4 1 read-write MSB Channel (n) Mode Select 5 1 read-write CHIE Channel (n) Interrupt Enable 6 1 read-write 0 Disable channel (n) interrupt. Use software polling. #0 1 Enable channel (n) interrupt. #1 CHF Channel (n) Flag 7 1 read-only 0 No channel (n) event has occurred. #0 1 A channel (n) event has occurred. #1 TRIGMODE Trigger mode control 8 1 read-write 0 Channel outputs will generate the normal PWM outputs without generating a pulse. #0 1 If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle. #1 CHIS Channel (n) Input State 9 1 read-only 0 The channel (n) input is zero. #0 1 The channel (n) input is one. #1 CHOV Channel (n) Output Value 10 1 read-only 0 The channel (n) output is zero. #0 1 The channel (n) output is one. #1 C7V Channel (n) Value 0x48 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write CNTIN Counter Initial Value 0x4C 32 read-write 0 0xFFFFFFFF INIT INIT 0 16 read-write STATUS Capture And Compare Status 0x50 32 read-only 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH6F Channel 6 Flag 6 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH7F Channel 7 Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 MODE Features Mode Selection 0x54 32 read-write 0x4 0xFFFFFFFF FTMEN FTM Enable 0 1 read-write 0 TPM compatibility. Free running counter and synchronization compatible with TPM. #0 1 Free running counter and synchronization are different from TPM behavior. #1 INIT Initialize The Channels Output 1 1 write-only WPDIS Write Protection Disable 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. #1 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTM Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 SYNC Synchronization 0x58 32 read-write 0 0xFFFFFFFF CNTMIN Minimum Loading Point Enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 CNTMAX Maximum Loading Point Enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 REINIT FTM Counter Reinitialization by Synchronization 2 1 read-write 0 FTM counter continues to count normally. #0 1 FTM counter is updated with its initial value when the selected trigger is detected. #1 SYNCHOM Output Mask Synchronization 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the FTM input clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 OUTINIT Initial State For Channels Output 0x5C 32 read-write 0 0xFFFFFFFF CH0OI Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OI Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OI Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OI Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OI Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OI Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH6OI Channel 6 Output Initialization Value 6 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH7OI Channel 7 Output Initialization Value 7 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 OUTMASK Output Mask 0x60 32 read-write 0 0xFFFFFFFF CH0OM Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OM Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OM Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OM Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OM Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OM Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH6OM Channel 6 Output Mask 6 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH7OM Channel 7 Output Mask 7 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 COMBINE Function For Linked Channels 0x64 32 read-write 0 0xFFFFFFFF COMBINE0 Combine Channels For n = 0 0 1 read-write COMP0 Complement Of Channel (n) For n = 0 1 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN0 Dual Edge Capture Mode Enable For n = 0 2 1 read-write DECAP0 Dual Edge Capture Mode Captures For n = 0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN0 Deadtime Enable For n = 0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN0 Synchronization Enable For n = 0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN0 Fault Control Enable For n = 0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 MCOMBINE0 Modified Combine Mode For n = 0 7 1 read-write COMBINE1 Combine Channels For n = 2 8 1 read-write COMP1 Complement Of Channel (n) For n = 2 9 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN1 Dual Edge Capture Mode Enable For n = 2 10 1 read-write DECAP1 Dual Edge Capture Mode Captures For n = 2 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN1 Deadtime Enable For n = 2 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN1 Synchronization Enable For n = 2 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN1 Fault Control Enable For n = 2 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 MCOMBINE1 Modified Combine Mode For n = 2 15 1 read-write COMBINE2 Combine Channels For n = 4 16 1 read-write COMP2 Complement Of Channel (n) For n = 4 17 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN2 Dual Edge Capture Mode Enable For n = 4 18 1 read-write DECAP2 Dual Edge Capture Mode Captures For n = 4 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN2 Deadtime Enable For n = 4 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN2 Synchronization Enable For n = 4 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN2 Fault Control Enable For n = 4 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 MCOMBINE2 Modified Combine Mode For n = 4 23 1 read-write COMBINE3 Combine Channels For n = 6 24 1 read-write COMP3 Complement Of Channel (n) for n = 6 25 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN3 Dual Edge Capture Mode Enable For n = 6 26 1 read-write DECAP3 Dual Edge Capture Mode Captures For n = 6 27 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN3 Deadtime Enable For n = 6 28 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN3 Synchronization Enable For n = 6 29 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN3 Fault Control Enable For n = 6 30 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 MCOMBINE3 Modified Combine Mode For n = 6 31 1 read-write DEADTIME Deadtime Configuration 0x68 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the FTM input clock by 1. #0x 10 Divide the FTM input clock by 4. #10 11 Divide the FTM input clock by 16. #11 DTVALEX Extended Deadtime Value 16 4 read-write EXTTRIG FTM External Trigger 0x6C 32 read-write 0 0xFFFFFFFF CH2TRIG Channel 2 External Trigger Enable 0 1 read-write 0 The generation of this external trigger is disabled. #0 1 The generation of this external trigger is enabled. #1 CH3TRIG Channel 3 External Trigger Enable 1 1 read-write 0 The generation of this external trigger is disabled. #0 1 The generation of this external trigger is enabled. #1 CH4TRIG Channel 4 External Trigger Enable 2 1 read-write 0 The generation of this external trigger is disabled. #0 1 The generation of this external trigger is enabled. #1 CH5TRIG Channel 5 External Trigger Enable 3 1 read-write 0 The generation of this external trigger is disabled. #0 1 The generation of this external trigger is enabled. #1 CH0TRIG Channel 0 External Trigger Enable 4 1 read-write 0 The generation of this external trigger is disabled. #0 1 The generation of this external trigger is enabled. #1 CH1TRIG Channel 1 External Trigger Enable 5 1 read-write 0 The generation of this external trigger is disabled. #0 1 The generation of this external trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 TRIGF Channel Trigger Flag 7 1 read-only 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 CH6TRIG Channel 6 External Trigger Enable 8 1 read-write 0 The generation of this external trigger is disabled. #0 1 The generation of this external trigger is enabled. #1 CH7TRIG Channel 7 External Trigger Enable 9 1 read-write 0 The generation of this external trigger is disabled. #0 1 The generation of this external trigger is enabled. #1 POL Channels Polarity 0x70 32 read-write 0 0xFFFFFFFF POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL6 Channel 6 Polarity 6 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL7 Channel 7 Polarity 7 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 FMS Fault Mode Status 0x74 32 read-write 0 0xFFFFFFFF FAULTF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 FAULTF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 FILTER Input Capture Filter Control 0x78 32 read-write 0 0xFFFFFFFF CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write FLTCTRL Fault Control 0x7C 32 read-write 0 0xFFFFFFFF FAULT0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write FSTATE Fault output state 15 1 read-write 0 FTM outputs will be placed into safe values when fault events in ongoing (defined by POL bits). #0 1 FTM outputs will be tri-stated when fault event is ongoing #1 QDCTRL Quadrature Decoder Control And Status 0x80 32 read-write 0 0xFFFFFFFF QUADEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature Decoder mode is disabled. #0 1 Quadrature Decoder mode is enabled. #1 TOFDIR Timer Overflow Direction In Quadrature Decoder Mode 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). #1 QUADIR FTM Counter Direction In Quadrature Decoder Mode 2 1 read-only 0 Counting direction is decreasing (FTM counter decrement). #0 1 Counting direction is increasing (FTM counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode. #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. #1 PHBFLTREN Phase B Input Filter Enable 6 1 read-write 0 Phase B input filter is disabled. #0 1 Phase B input filter is enabled. #1 PHAFLTREN Phase A Input Filter Enable 7 1 read-write 0 Phase A input filter is disabled. #0 1 Phase A input filter is enabled. #1 CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF LDFQ Frequency of the Reload Opportunities 0 5 read-write BDMMODE Debug Mode 6 2 read-write GTBEEN Global Time Base Enable 9 1 read-write GTBEOUT Global Time Base Output 10 1 read-write ITRIGR Initialization trigger on Reload Point 11 1 read-write 0 Initialization trigger is generated on counter wrap events. #0 1 Initialization trigger is generated when a reload point is reached. #1 FLTPOL FTM Fault Input Polarity 0x88 32 read-write 0 0xFFFFFFFF FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 SYNCONF Synchronization Configuration 0x8C 32 read-write 0 0xFFFFFFFF HWTRIGMODE Hardware Trigger Mode 0 1 read-write 0 FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #0 1 FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #1 CNTINC CNTIN Register Synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of FTM input clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 INVC INVCTRL Register Synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of FTM input clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 SWOC SWOCTRL Register Synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of FTM input clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 SWRSTCNT FTM counter synchronization is activated by the software trigger 8 1 read-write 0 The software trigger does not activate the FTM counter synchronization. #0 1 The software trigger activates the FTM counter synchronization. #1 SWWRBUF MOD, HCR, CNTIN, and CV registers synchronization is activated by the software trigger 9 1 read-write 0 The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization. #1 SWOM Output mask synchronization is activated by the software trigger 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 SWINVC Inverting control synchronization is activated by the software trigger 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 SWSOC Software output control synchronization is activated by the software trigger 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 HWRSTCNT FTM counter synchronization is activated by a hardware trigger 16 1 read-write 0 A hardware trigger does not activate the FTM counter synchronization. #0 1 A hardware trigger activates the FTM counter synchronization. #1 HWWRBUF MOD, HCR, CNTIN, and CV registers synchronization is activated by a hardware trigger 17 1 read-write 0 A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization. #1 HWOM Output mask synchronization is activated by a hardware trigger 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 HWINVC Inverting control synchronization is activated by a hardware trigger 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 HWSOC Software output control synchronization is activated by a hardware trigger 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 INVCTRL FTM Inverting Control 0x90 32 read-write 0 0xFFFFFFFF INV0EN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 SWOCTRL FTM Software Output Control 0x94 32 read-write 0 0xFFFFFFFF CH0OC Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 PWMLOAD FTM PWM Load 0x98 32 read-write 0 0xFFFFFFFF CH0SEL Channel 0 Select 0 1 read-write 0 Channel match is not included as a reload opportunity. #0 1 Channel match is included as a reload opportunity. #1 CH1SEL Channel 1 Select 1 1 read-write 0 Channel match is not included as a reload opportunity. #0 1 Channel match is included as a reload opportunity. #1 CH2SEL Channel 2 Select 2 1 read-write 0 Channel match is not included as a reload opportunity. #0 1 Channel match is included as a reload opportunity. #1 CH3SEL Channel 3 Select 3 1 read-write 0 Channel match is not included as a reload opportunity. #0 1 Channel match is included as a reload opportunity. #1 CH4SEL Channel 4 Select 4 1 read-write 0 Channel match is not included as a reload opportunity. #0 1 Channel match is included as a reload opportunity. #1 CH5SEL Channel 5 Select 5 1 read-write 0 Channel match is not included as a reload opportunity. #0 1 Channel match is included as a reload opportunity. #1 CH6SEL Channel 6 Select 6 1 read-write 0 Channel match is not included as a reload opportunity. #0 1 Channel match is included as a reload opportunity. #1 CH7SEL Channel 7 Select 7 1 read-write 0 Channel match is not included as a reload opportunity. #0 1 Channel match is included as a reload opportunity. #1 HCSEL Half Cycle Select 8 1 read-write 0 Half cycle reload is disabled and it is not considered as a reload opportunity. #0 1 Half cycle reload is enabled and it is considered as a reload opportunity. #1 LDOK Load Enable 9 1 read-write 0 Loading updated values is disabled. #0 1 Loading updated values is enabled. #1 GLEN Global Load Enable 10 1 read-write 0 Global Load Ok disabled. #0 1 Global Load OK enabled. A pulse event on the module global load input sets the LDOK bit. #1 GLDOK Global Load OK 11 1 write-only 0 No action. #0 1 LDOK bit is set. #1 HCR Half Cycle Register 0x9C 32 read-write 0 0xFFFFFFFF HCVAL Half Cycle Value 0 16 read-write PAIR0DEADTIME Pair 0 Deadtime Configuration 0xA0 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the FTM input clock by 1. #0x 10 Divide the FTM input clock by 4. #10 11 Divide the FTM input clock by 16. #11 DTVALEX Extended Deadtime Value 16 4 read-write PAIR1DEADTIME Pair 1 Deadtime Configuration 0xA8 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the FTM input clock by 1. #0x 10 Divide the FTM input clock by 4. #10 11 Divide the FTM input clock by 16. #11 DTVALEX Extended Deadtime Value 16 4 read-write PAIR2DEADTIME Pair 2 Deadtime Configuration 0xB0 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the FTM input clock by 1. #0x 10 Divide the FTM input clock by 4. #10 11 Divide the FTM input clock by 16. #11 DTVALEX Extended Deadtime Value 16 4 read-write PAIR3DEADTIME Pair 3 Deadtime Configuration 0xB8 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the FTM input clock by 1. #0x 10 Divide the FTM input clock by 4. #10 11 Divide the FTM input clock by 16. #11 DTVALEX Extended Deadtime Value 16 4 read-write MOD_MIRROR Mirror of Modulo Value 0x200 32 read-write 0 0xFFFFFFFF FRACMOD Modulo Fractional Value 11 5 read-write MOD Mirror of the Modulo Integer Value 16 16 read-write C0V_MIRROR Mirror of Channel (n) Match Value 0x204 32 read-write 0 0xFFFFFFFF FRACVAL Channel (n) Match Fractional Value 11 5 read-write VAL Mirror of the Channel (n) Match Integer Value 16 16 read-write C1V_MIRROR Mirror of Channel (n) Match Value 0x208 32 read-write 0 0xFFFFFFFF FRACVAL Channel (n) Match Fractional Value 11 5 read-write VAL Mirror of the Channel (n) Match Integer Value 16 16 read-write C2V_MIRROR Mirror of Channel (n) Match Value 0x20C 32 read-write 0 0xFFFFFFFF FRACVAL Channel (n) Match Fractional Value 11 5 read-write VAL Mirror of the Channel (n) Match Integer Value 16 16 read-write C3V_MIRROR Mirror of Channel (n) Match Value 0x210 32 read-write 0 0xFFFFFFFF FRACVAL Channel (n) Match Fractional Value 11 5 read-write VAL Mirror of the Channel (n) Match Integer Value 16 16 read-write C4V_MIRROR Mirror of Channel (n) Match Value 0x214 32 read-write 0 0xFFFFFFFF FRACVAL Channel (n) Match Fractional Value 11 5 read-write VAL Mirror of the Channel (n) Match Integer Value 16 16 read-write C5V_MIRROR Mirror of Channel (n) Match Value 0x218 32 read-write 0 0xFFFFFFFF FRACVAL Channel (n) Match Fractional Value 11 5 read-write VAL Mirror of the Channel (n) Match Integer Value 16 16 read-write C6V_MIRROR Mirror of Channel (n) Match Value 0x21C 32 read-write 0 0xFFFFFFFF FRACVAL Channel (n) Match Fractional Value 11 5 read-write VAL Mirror of the Channel (n) Match Integer Value 16 16 read-write C7V_MIRROR Mirror of Channel (n) Match Value 0x220 32 read-write 0 0xFFFFFFFF FRACVAL Channel (n) Match Fractional Value 11 5 read-write VAL Mirror of the Channel (n) Match Integer Value 16 16 read-write FTM1 FlexTimer Module FTM FTM1_ 0x40039000 0 0x224 registers FTM1_Ch0_7 15 FTM1_Fault 16 FTM1_Ovf_Reload 17 SC Status And Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CLKS Clock Source Selection 3 2 read-write 00 No clock selected. This in effect disables the FTM counter. #00 01 FTM input clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-Aligned PWM Select 5 1 read-write 0 FTM counter operates in Up Counting mode. #0 1 FTM counter operates in Up-Down Counting mode. #1 RIE Reload Point Interrupt Enable 6 1 read-write 0 Reload point interrupt is disabled. #0 1 Reload point interrupt is enabled. #1 RF Reload Flag 7 1 read-only 0 A selected reload point did not happen. #0 1 A selected reload point happened. #1 TOIE Timer Overflow Interrupt Enable 8 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 9 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 PWMEN0 Channel 0 PWM enable bit 16 1 read-write 0 Channel output port is disabled #0 1 Channel output port is enabled #1 PWMEN1 Channel 1 PWM enable bit 17 1 read-write 0 Channel output port is disabled #0 1 Channel output port is enabled #1 PWMEN2 Channel 2 PWM enable bit 18 1 read-write 0 Channel output port is disabled #0 1 Channel output port is enabled #1 PWMEN3 Channel 3 PWM enable bit 19 1 read-write 0 Channel output port is disabled #0 1 Channel output port is enabled #1 PWMEN4 Channel 4 PWM enable bit 20 1 read-write 0 Channel output port is disabled #0 1 Channel output port is enabled #1 PWMEN5 Channel 5 PWM enable bit 21 1 read-write 0 Channel output port is disabled #0 1 Channel output port is enabled #1 PWMEN6 Channel 6 PWM enable bit 22 1 read-write 0 Channel output port is disabled #0 1 Channel output port is enabled #1 PWMEN7 Channel 7 PWM enable bit 23 1 read-write 0 Channel output port is disabled #0 1 Channel output port is enabled #1 FLTPS Filter Prescaler 24 4 read-write 0000 Divide by 1 #0000 0001 Divide by 2 #0001 0010 Divide by 3 #0010 0011 Divide by 4 #0011 0100 Divide by 5 #0100 0101 Divide by 6 #0101 0110 Divide by 7 #0110 0111 Divide by 8 #0111 1000 Divide by 9 #1000 1001 Divide by 10 #1001 1010 Divide by 11 #1010 1011 Divide by 12 #1011 1100 Divide by 13 #1100 1101 Divide by 14 #1101 1110 Divide by 15 #1110 1111 Divide by 16 #1111 CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter Value 0 16 read-write MOD Modulo 0x8 32 read-write 0 0xFFFFFFFF MOD MOD 0 16 read-write C0SC Channel (n) Status And Control 0xC 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 ELSA Channel (n) Edge or Level Select 2 1 read-write ELSB Channel (n) Edge or Level Select 3 1 read-write MSA Channel (n) Mode Select 4 1 read-write MSB Channel (n) Mode Select 5 1 read-write CHIE Channel (n) Interrupt Enable 6 1 read-write 0 Disable channel (n) interrupt. Use software polling. #0 1 Enable channel (n) interrupt. #1 CHF Channel (n) Flag 7 1 read-only 0 No channel (n) event has occurred. #0 1 A channel (n) event has occurred. #1 TRIGMODE Trigger mode control 8 1 read-write 0 Channel outputs will generate the normal PWM outputs without generating a pulse. #0 1 If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle. #1 CHIS Channel (n) Input State 9 1 read-only 0 The channel (n) input is zero. #0 1 The channel (n) input is one. #1 CHOV Channel (n) Output Value 10 1 read-only 0 The channel (n) output is zero. #0 1 The channel (n) output is one. #1 C0V Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write C1SC Channel (n) Status And Control 0x14 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 ELSA Channel (n) Edge or Level Select 2 1 read-write ELSB Channel (n) Edge or Level Select 3 1 read-write MSA Channel (n) Mode Select 4 1 read-write MSB Channel (n) Mode Select 5 1 read-write CHIE Channel (n) Interrupt Enable 6 1 read-write 0 Disable channel (n) interrupt. Use software polling. #0 1 Enable channel (n) interrupt. #1 CHF Channel (n) Flag 7 1 read-only 0 No channel (n) event has occurred. #0 1 A channel (n) event has occurred. #1 TRIGMODE Trigger mode control 8 1 read-write 0 Channel outputs will generate the normal PWM outputs without generating a pulse. #0 1 If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle. #1 CHIS Channel (n) Input State 9 1 read-only 0 The channel (n) input is zero. #0 1 The channel (n) input is one. #1 CHOV Channel (n) Output Value 10 1 read-only 0 The channel (n) output is zero. #0 1 The channel (n) output is one. #1 C1V Channel (n) Value 0x18 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write C2SC Channel (n) Status And Control 0x1C 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 ELSA Channel (n) Edge or Level Select 2 1 read-write ELSB Channel (n) Edge or Level Select 3 1 read-write MSA Channel (n) Mode Select 4 1 read-write MSB Channel (n) Mode Select 5 1 read-write CHIE Channel (n) Interrupt Enable 6 1 read-write 0 Disable channel (n) interrupt. Use software polling. #0 1 Enable channel (n) interrupt. #1 CHF Channel (n) Flag 7 1 read-only 0 No channel (n) event has occurred. #0 1 A channel (n) event has occurred. #1 TRIGMODE Trigger mode control 8 1 read-write 0 Channel outputs will generate the normal PWM outputs without generating a pulse. #0 1 If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle. #1 CHIS Channel (n) Input State 9 1 read-only 0 The channel (n) input is zero. #0 1 The channel (n) input is one. #1 CHOV Channel (n) Output Value 10 1 read-only 0 The channel (n) output is zero. #0 1 The channel (n) output is one. #1 C2V Channel (n) Value 0x20 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write C3SC Channel (n) Status And Control 0x24 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 ELSA Channel (n) Edge or Level Select 2 1 read-write ELSB Channel (n) Edge or Level Select 3 1 read-write MSA Channel (n) Mode Select 4 1 read-write MSB Channel (n) Mode Select 5 1 read-write CHIE Channel (n) Interrupt Enable 6 1 read-write 0 Disable channel (n) interrupt. Use software polling. #0 1 Enable channel (n) interrupt. #1 CHF Channel (n) Flag 7 1 read-only 0 No channel (n) event has occurred. #0 1 A channel (n) event has occurred. #1 TRIGMODE Trigger mode control 8 1 read-write 0 Channel outputs will generate the normal PWM outputs without generating a pulse. #0 1 If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle. #1 CHIS Channel (n) Input State 9 1 read-only 0 The channel (n) input is zero. #0 1 The channel (n) input is one. #1 CHOV Channel (n) Output Value 10 1 read-only 0 The channel (n) output is zero. #0 1 The channel (n) output is one. #1 C3V Channel (n) Value 0x28 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write C4SC Channel (n) Status And Control 0x2C 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 ELSA Channel (n) Edge or Level Select 2 1 read-write ELSB Channel (n) Edge or Level Select 3 1 read-write MSA Channel (n) Mode Select 4 1 read-write MSB Channel (n) Mode Select 5 1 read-write CHIE Channel (n) Interrupt Enable 6 1 read-write 0 Disable channel (n) interrupt. Use software polling. #0 1 Enable channel (n) interrupt. #1 CHF Channel (n) Flag 7 1 read-only 0 No channel (n) event has occurred. #0 1 A channel (n) event has occurred. #1 TRIGMODE Trigger mode control 8 1 read-write 0 Channel outputs will generate the normal PWM outputs without generating a pulse. #0 1 If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle. #1 CHIS Channel (n) Input State 9 1 read-only 0 The channel (n) input is zero. #0 1 The channel (n) input is one. #1 CHOV Channel (n) Output Value 10 1 read-only 0 The channel (n) output is zero. #0 1 The channel (n) output is one. #1 C4V Channel (n) Value 0x30 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write C5SC Channel (n) Status And Control 0x34 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 ELSA Channel (n) Edge or Level Select 2 1 read-write ELSB Channel (n) Edge or Level Select 3 1 read-write MSA Channel (n) Mode Select 4 1 read-write MSB Channel (n) Mode Select 5 1 read-write CHIE Channel (n) Interrupt Enable 6 1 read-write 0 Disable channel (n) interrupt. Use software polling. #0 1 Enable channel (n) interrupt. #1 CHF Channel (n) Flag 7 1 read-only 0 No channel (n) event has occurred. #0 1 A channel (n) event has occurred. #1 TRIGMODE Trigger mode control 8 1 read-write 0 Channel outputs will generate the normal PWM outputs without generating a pulse. #0 1 If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle. #1 CHIS Channel (n) Input State 9 1 read-only 0 The channel (n) input is zero. #0 1 The channel (n) input is one. #1 CHOV Channel (n) Output Value 10 1 read-only 0 The channel (n) output is zero. #0 1 The channel (n) output is one. #1 C5V Channel (n) Value 0x38 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write C6SC Channel (n) Status And Control 0x3C 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 ELSA Channel (n) Edge or Level Select 2 1 read-write ELSB Channel (n) Edge or Level Select 3 1 read-write MSA Channel (n) Mode Select 4 1 read-write MSB Channel (n) Mode Select 5 1 read-write CHIE Channel (n) Interrupt Enable 6 1 read-write 0 Disable channel (n) interrupt. Use software polling. #0 1 Enable channel (n) interrupt. #1 CHF Channel (n) Flag 7 1 read-only 0 No channel (n) event has occurred. #0 1 A channel (n) event has occurred. #1 TRIGMODE Trigger mode control 8 1 read-write 0 Channel outputs will generate the normal PWM outputs without generating a pulse. #0 1 If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle. #1 CHIS Channel (n) Input State 9 1 read-only 0 The channel (n) input is zero. #0 1 The channel (n) input is one. #1 CHOV Channel (n) Output Value 10 1 read-only 0 The channel (n) output is zero. #0 1 The channel (n) output is one. #1 C6V Channel (n) Value 0x40 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write C7SC Channel (n) Status And Control 0x44 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 ELSA Channel (n) Edge or Level Select 2 1 read-write ELSB Channel (n) Edge or Level Select 3 1 read-write MSA Channel (n) Mode Select 4 1 read-write MSB Channel (n) Mode Select 5 1 read-write CHIE Channel (n) Interrupt Enable 6 1 read-write 0 Disable channel (n) interrupt. Use software polling. #0 1 Enable channel (n) interrupt. #1 CHF Channel (n) Flag 7 1 read-only 0 No channel (n) event has occurred. #0 1 A channel (n) event has occurred. #1 TRIGMODE Trigger mode control 8 1 read-write 0 Channel outputs will generate the normal PWM outputs without generating a pulse. #0 1 If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle. #1 CHIS Channel (n) Input State 9 1 read-only 0 The channel (n) input is zero. #0 1 The channel (n) input is one. #1 CHOV Channel (n) Output Value 10 1 read-only 0 The channel (n) output is zero. #0 1 The channel (n) output is one. #1 C7V Channel (n) Value 0x48 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write CNTIN Counter Initial Value 0x4C 32 read-write 0 0xFFFFFFFF INIT INIT 0 16 read-write STATUS Capture And Compare Status 0x50 32 read-only 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH6F Channel 6 Flag 6 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH7F Channel 7 Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 MODE Features Mode Selection 0x54 32 read-write 0x4 0xFFFFFFFF FTMEN FTM Enable 0 1 read-write 0 TPM compatibility. Free running counter and synchronization compatible with TPM. #0 1 Free running counter and synchronization are different from TPM behavior. #1 INIT Initialize The Channels Output 1 1 write-only WPDIS Write Protection Disable 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. #1 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTM Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 SYNC Synchronization 0x58 32 read-write 0 0xFFFFFFFF CNTMIN Minimum Loading Point Enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 CNTMAX Maximum Loading Point Enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 REINIT FTM Counter Reinitialization by Synchronization 2 1 read-write 0 FTM counter continues to count normally. #0 1 FTM counter is updated with its initial value when the selected trigger is detected. #1 SYNCHOM Output Mask Synchronization 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the FTM input clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 OUTINIT Initial State For Channels Output 0x5C 32 read-write 0 0xFFFFFFFF CH0OI Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OI Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OI Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OI Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OI Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OI Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH6OI Channel 6 Output Initialization Value 6 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH7OI Channel 7 Output Initialization Value 7 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 OUTMASK Output Mask 0x60 32 read-write 0 0xFFFFFFFF CH0OM Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OM Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OM Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OM Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OM Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OM Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH6OM Channel 6 Output Mask 6 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH7OM Channel 7 Output Mask 7 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 COMBINE Function For Linked Channels 0x64 32 read-write 0 0xFFFFFFFF COMBINE0 Combine Channels For n = 0 0 1 read-write COMP0 Complement Of Channel (n) For n = 0 1 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN0 Dual Edge Capture Mode Enable For n = 0 2 1 read-write DECAP0 Dual Edge Capture Mode Captures For n = 0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN0 Deadtime Enable For n = 0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN0 Synchronization Enable For n = 0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN0 Fault Control Enable For n = 0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 MCOMBINE0 Modified Combine Mode For n = 0 7 1 read-write COMBINE1 Combine Channels For n = 2 8 1 read-write COMP1 Complement Of Channel (n) For n = 2 9 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN1 Dual Edge Capture Mode Enable For n = 2 10 1 read-write DECAP1 Dual Edge Capture Mode Captures For n = 2 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN1 Deadtime Enable For n = 2 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN1 Synchronization Enable For n = 2 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN1 Fault Control Enable For n = 2 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 MCOMBINE1 Modified Combine Mode For n = 2 15 1 read-write COMBINE2 Combine Channels For n = 4 16 1 read-write COMP2 Complement Of Channel (n) For n = 4 17 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN2 Dual Edge Capture Mode Enable For n = 4 18 1 read-write DECAP2 Dual Edge Capture Mode Captures For n = 4 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN2 Deadtime Enable For n = 4 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN2 Synchronization Enable For n = 4 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN2 Fault Control Enable For n = 4 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 MCOMBINE2 Modified Combine Mode For n = 4 23 1 read-write COMBINE3 Combine Channels For n = 6 24 1 read-write COMP3 Complement Of Channel (n) for n = 6 25 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN3 Dual Edge Capture Mode Enable For n = 6 26 1 read-write DECAP3 Dual Edge Capture Mode Captures For n = 6 27 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN3 Deadtime Enable For n = 6 28 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN3 Synchronization Enable For n = 6 29 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN3 Fault Control Enable For n = 6 30 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 MCOMBINE3 Modified Combine Mode For n = 6 31 1 read-write DEADTIME Deadtime Configuration 0x68 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the FTM input clock by 1. #0x 10 Divide the FTM input clock by 4. #10 11 Divide the FTM input clock by 16. #11 DTVALEX Extended Deadtime Value 16 4 read-write EXTTRIG FTM External Trigger 0x6C 32 read-write 0 0xFFFFFFFF CH2TRIG Channel 2 External Trigger Enable 0 1 read-write 0 The generation of this external trigger is disabled. #0 1 The generation of this external trigger is enabled. #1 CH3TRIG Channel 3 External Trigger Enable 1 1 read-write 0 The generation of this external trigger is disabled. #0 1 The generation of this external trigger is enabled. #1 CH4TRIG Channel 4 External Trigger Enable 2 1 read-write 0 The generation of this external trigger is disabled. #0 1 The generation of this external trigger is enabled. #1 CH5TRIG Channel 5 External Trigger Enable 3 1 read-write 0 The generation of this external trigger is disabled. #0 1 The generation of this external trigger is enabled. #1 CH0TRIG Channel 0 External Trigger Enable 4 1 read-write 0 The generation of this external trigger is disabled. #0 1 The generation of this external trigger is enabled. #1 CH1TRIG Channel 1 External Trigger Enable 5 1 read-write 0 The generation of this external trigger is disabled. #0 1 The generation of this external trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 TRIGF Channel Trigger Flag 7 1 read-only 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 CH6TRIG Channel 6 External Trigger Enable 8 1 read-write 0 The generation of this external trigger is disabled. #0 1 The generation of this external trigger is enabled. #1 CH7TRIG Channel 7 External Trigger Enable 9 1 read-write 0 The generation of this external trigger is disabled. #0 1 The generation of this external trigger is enabled. #1 POL Channels Polarity 0x70 32 read-write 0 0xFFFFFFFF POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL6 Channel 6 Polarity 6 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL7 Channel 7 Polarity 7 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 FMS Fault Mode Status 0x74 32 read-write 0 0xFFFFFFFF FAULTF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 FAULTF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 FILTER Input Capture Filter Control 0x78 32 read-write 0 0xFFFFFFFF CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write FLTCTRL Fault Control 0x7C 32 read-write 0 0xFFFFFFFF FAULT0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write FSTATE Fault output state 15 1 read-write 0 FTM outputs will be placed into safe values when fault events in ongoing (defined by POL bits). #0 1 FTM outputs will be tri-stated when fault event is ongoing #1 QDCTRL Quadrature Decoder Control And Status 0x80 32 read-write 0 0xFFFFFFFF QUADEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature Decoder mode is disabled. #0 1 Quadrature Decoder mode is enabled. #1 TOFDIR Timer Overflow Direction In Quadrature Decoder Mode 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). #1 QUADIR FTM Counter Direction In Quadrature Decoder Mode 2 1 read-only 0 Counting direction is decreasing (FTM counter decrement). #0 1 Counting direction is increasing (FTM counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode. #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. #1 PHBFLTREN Phase B Input Filter Enable 6 1 read-write 0 Phase B input filter is disabled. #0 1 Phase B input filter is enabled. #1 PHAFLTREN Phase A Input Filter Enable 7 1 read-write 0 Phase A input filter is disabled. #0 1 Phase A input filter is enabled. #1 CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF LDFQ Frequency of the Reload Opportunities 0 5 read-write BDMMODE Debug Mode 6 2 read-write GTBEEN Global Time Base Enable 9 1 read-write GTBEOUT Global Time Base Output 10 1 read-write ITRIGR Initialization trigger on Reload Point 11 1 read-write 0 Initialization trigger is generated on counter wrap events. #0 1 Initialization trigger is generated when a reload point is reached. #1 FLTPOL FTM Fault Input Polarity 0x88 32 read-write 0 0xFFFFFFFF FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 SYNCONF Synchronization Configuration 0x8C 32 read-write 0 0xFFFFFFFF HWTRIGMODE Hardware Trigger Mode 0 1 read-write 0 FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #0 1 FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #1 CNTINC CNTIN Register Synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of FTM input clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 INVC INVCTRL Register Synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of FTM input clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 SWOC SWOCTRL Register Synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of FTM input clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 SWRSTCNT FTM counter synchronization is activated by the software trigger 8 1 read-write 0 The software trigger does not activate the FTM counter synchronization. #0 1 The software trigger activates the FTM counter synchronization. #1 SWWRBUF MOD, HCR, CNTIN, and CV registers synchronization is activated by the software trigger 9 1 read-write 0 The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization. #1 SWOM Output mask synchronization is activated by the software trigger 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 SWINVC Inverting control synchronization is activated by the software trigger 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 SWSOC Software output control synchronization is activated by the software trigger 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 HWRSTCNT FTM counter synchronization is activated by a hardware trigger 16 1 read-write 0 A hardware trigger does not activate the FTM counter synchronization. #0 1 A hardware trigger activates the FTM counter synchronization. #1 HWWRBUF MOD, HCR, CNTIN, and CV registers synchronization is activated by a hardware trigger 17 1 read-write 0 A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization. #1 HWOM Output mask synchronization is activated by a hardware trigger 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 HWINVC Inverting control synchronization is activated by a hardware trigger 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 HWSOC Software output control synchronization is activated by a hardware trigger 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 INVCTRL FTM Inverting Control 0x90 32 read-write 0 0xFFFFFFFF INV0EN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 SWOCTRL FTM Software Output Control 0x94 32 read-write 0 0xFFFFFFFF CH0OC Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 PWMLOAD FTM PWM Load 0x98 32 read-write 0 0xFFFFFFFF CH0SEL Channel 0 Select 0 1 read-write 0 Channel match is not included as a reload opportunity. #0 1 Channel match is included as a reload opportunity. #1 CH1SEL Channel 1 Select 1 1 read-write 0 Channel match is not included as a reload opportunity. #0 1 Channel match is included as a reload opportunity. #1 CH2SEL Channel 2 Select 2 1 read-write 0 Channel match is not included as a reload opportunity. #0 1 Channel match is included as a reload opportunity. #1 CH3SEL Channel 3 Select 3 1 read-write 0 Channel match is not included as a reload opportunity. #0 1 Channel match is included as a reload opportunity. #1 CH4SEL Channel 4 Select 4 1 read-write 0 Channel match is not included as a reload opportunity. #0 1 Channel match is included as a reload opportunity. #1 CH5SEL Channel 5 Select 5 1 read-write 0 Channel match is not included as a reload opportunity. #0 1 Channel match is included as a reload opportunity. #1 CH6SEL Channel 6 Select 6 1 read-write 0 Channel match is not included as a reload opportunity. #0 1 Channel match is included as a reload opportunity. #1 CH7SEL Channel 7 Select 7 1 read-write 0 Channel match is not included as a reload opportunity. #0 1 Channel match is included as a reload opportunity. #1 HCSEL Half Cycle Select 8 1 read-write 0 Half cycle reload is disabled and it is not considered as a reload opportunity. #0 1 Half cycle reload is enabled and it is considered as a reload opportunity. #1 LDOK Load Enable 9 1 read-write 0 Loading updated values is disabled. #0 1 Loading updated values is enabled. #1 GLEN Global Load Enable 10 1 read-write 0 Global Load Ok disabled. #0 1 Global Load OK enabled. A pulse event on the module global load input sets the LDOK bit. #1 GLDOK Global Load OK 11 1 write-only 0 No action. #0 1 LDOK bit is set. #1 HCR Half Cycle Register 0x9C 32 read-write 0 0xFFFFFFFF HCVAL Half Cycle Value 0 16 read-write PAIR0DEADTIME Pair 0 Deadtime Configuration 0xA0 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the FTM input clock by 1. #0x 10 Divide the FTM input clock by 4. #10 11 Divide the FTM input clock by 16. #11 DTVALEX Extended Deadtime Value 16 4 read-write PAIR1DEADTIME Pair 1 Deadtime Configuration 0xA8 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the FTM input clock by 1. #0x 10 Divide the FTM input clock by 4. #10 11 Divide the FTM input clock by 16. #11 DTVALEX Extended Deadtime Value 16 4 read-write PAIR2DEADTIME Pair 2 Deadtime Configuration 0xB0 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the FTM input clock by 1. #0x 10 Divide the FTM input clock by 4. #10 11 Divide the FTM input clock by 16. #11 DTVALEX Extended Deadtime Value 16 4 read-write PAIR3DEADTIME Pair 3 Deadtime Configuration 0xB8 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the FTM input clock by 1. #0x 10 Divide the FTM input clock by 4. #10 11 Divide the FTM input clock by 16. #11 DTVALEX Extended Deadtime Value 16 4 read-write MOD_MIRROR Mirror of Modulo Value 0x200 32 read-write 0 0xFFFFFFFF FRACMOD Modulo Fractional Value 11 5 read-write MOD Mirror of the Modulo Integer Value 16 16 read-write C0V_MIRROR Mirror of Channel (n) Match Value 0x204 32 read-write 0 0xFFFFFFFF FRACVAL Channel (n) Match Fractional Value 11 5 read-write VAL Mirror of the Channel (n) Match Integer Value 16 16 read-write C1V_MIRROR Mirror of Channel (n) Match Value 0x208 32 read-write 0 0xFFFFFFFF FRACVAL Channel (n) Match Fractional Value 11 5 read-write VAL Mirror of the Channel (n) Match Integer Value 16 16 read-write C2V_MIRROR Mirror of Channel (n) Match Value 0x20C 32 read-write 0 0xFFFFFFFF FRACVAL Channel (n) Match Fractional Value 11 5 read-write VAL Mirror of the Channel (n) Match Integer Value 16 16 read-write C3V_MIRROR Mirror of Channel (n) Match Value 0x210 32 read-write 0 0xFFFFFFFF FRACVAL Channel (n) Match Fractional Value 11 5 read-write VAL Mirror of the Channel (n) Match Integer Value 16 16 read-write C4V_MIRROR Mirror of Channel (n) Match Value 0x214 32 read-write 0 0xFFFFFFFF FRACVAL Channel (n) Match Fractional Value 11 5 read-write VAL Mirror of the Channel (n) Match Integer Value 16 16 read-write C5V_MIRROR Mirror of Channel (n) Match Value 0x218 32 read-write 0 0xFFFFFFFF FRACVAL Channel (n) Match Fractional Value 11 5 read-write VAL Mirror of the Channel (n) Match Integer Value 16 16 read-write C6V_MIRROR Mirror of Channel (n) Match Value 0x21C 32 read-write 0 0xFFFFFFFF FRACVAL Channel (n) Match Fractional Value 11 5 read-write VAL Mirror of the Channel (n) Match Integer Value 16 16 read-write C7V_MIRROR Mirror of Channel (n) Match Value 0x220 32 read-write 0 0xFFFFFFFF FRACVAL Channel (n) Match Fractional Value 11 5 read-write VAL Mirror of the Channel (n) Match Integer Value 16 16 read-write ADC0 Analog-to-Digital Converter ADC0_ 0x4003B000 0 0xEC registers ADC0 28 16 0x4 A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P SC1%s ADC Status and Control Register 1 0 32 read-write 0x1F 0xFFFFFFFF ADCH Input channel select 0 5 read-write 00000 Exernal channel 0 is selected as input. #00000 00001 Exernal channel 1 is selected as input. #00001 00010 Exernal channel 2 is selected as input. #00010 00011 Exernal channel 3 is selected as input. #00011 00100 Exernal channel 4 is selected as input. #00100 00101 Exernal channel 5 is selected as input. #00101 00110 Exernal channel 6 is selected as input. #00110 00111 Exernal channel 7 is selected as input. #00111 01000 Exernal channel 8 is selected as input. #01000 01001 Exernal channel 9 is selected as input. #01001 01010 Exernal channel 10 is selected as input. #01010 01011 Exernal channel 11 is selected as input. #01011 01100 Exernal channel 12 is selected as input. #01100 01101 Exernal channel 13 is selected as input. #01101 01110 Exernal channel 14 is selected as input. #01110 01111 Exernal channel 15 is selected as input. #01111 10010 Exernal channel 18 is selected as input. #10010 10011 Exernal channel 19 is selected as input. #10011 10101 Internal channel 0 is selected as input. #10101 10110 Internal channel 1 is selected as input. #10110 10111 Internal channel 2 is selected as input. #10111 11010 Temp Sensor #11010 11011 Band Gap #11011 11100 Internal channel 3 is selected as input. #11100 11101 VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL]. #11101 11110 VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL]. #11110 11111 Module is disabled #11111 AIEN Interrupt Enable 6 1 read-write 0 Conversion complete interrupt is disabled. #0 1 Conversion complete interrupt is enabled. #1 COCO Conversion Complete Flag 7 1 read-only 0 Conversion is not completed. #0 1 Conversion is completed. #1 CFG1 ADC Configuration Register 1 0x40 32 read-write 0 0xFFFFFFFF ADICLK Input Clock Select 0 2 read-write 00 Alternate clock 1 (ADC_ALTCLK1) #00 01 Alternate clock 2 (ADC_ALTCLK2) #01 10 Alternate clock 3 (ADC_ALTCLK3) #10 11 Alternate clock 4 (ADC_ALTCLK4) #11 MODE Conversion mode selection 2 2 read-write 00 8-bit conversion. #00 01 12-bit conversion. #01 10 10-bit conversion. #10 ADIV Clock Divide Select 5 2 read-write 00 The divide ratio is 1 and the clock rate is input clock. #00 01 The divide ratio is 2 and the clock rate is (input clock)/2. #01 10 The divide ratio is 4 and the clock rate is (input clock)/4. #10 11 The divide ratio is 8 and the clock rate is (input clock)/8. #11 CLRLTRG Clear Latch Trigger in Trigger Handler Block 8 1 write-only CFG2 ADC Configuration Register 2 0x44 32 read-write 0xC 0xFFFFFFFF SMPLTS Sample Time Select 0 8 read-write 16 0x4 A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P R%s ADC Data Result Registers 0x48 32 read-only 0 0xFFFFFFFF D Data result 0 12 read-only 2 0x4 1,2 CV%s Compare Value Registers 0x88 32 read-write 0 0xFFFFFFFF CV Compare Value. 0 16 read-write SC2 Status and Control Register 2 0x90 32 read-write 0 0xFFFFFFFF REFSEL Voltage Reference Selection 0 2 read-write 00 Default voltage reference pin pair, that is, external pins VREFH and VREFL #00 01 Alternate reference voltage, that is, VALTH. This voltage may be additional external pin or internal source depending on the MCU configuration. See the chip configuration information for details specific to this MCU. #01 DMAEN DMA Enable 2 1 read-write 0 DMA is disabled. #0 1 DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n[COCO] flag is asserted. #1 ACREN Compare Function Range Enable 3 1 read-write ACFGT Compare Function Greater Than Enable 4 1 read-write ACFE Compare Function Enable 5 1 read-write 0 Compare function disabled. #0 1 Compare function enabled. #1 ADTRG Conversion Trigger Select 6 1 read-write 0 Software trigger selected. #0 1 Hardware trigger selected. #1 ADACT Conversion Active 7 1 read-only 0 Conversion not in progress. #0 1 Conversion in progress. #1 TRGPRNUM Trigger Process Number 13 2 read-only TRGSTLAT Trigger Status 16 4 read-only 0 No trigger request has been latched #0000 1 A trigger request has been latched #0001 TRGSTERR Error in Multiplexed Trigger Request 24 4 read-only 0 No error has occurred #0000 1 An error has occurred #0001 SC3 Status and Control Register 3 0x94 32 read-write 0 0xFFFFFFFF AVGS Hardware Average Select 0 2 read-write 00 4 samples averaged. #00 01 8 samples averaged. #01 10 16 samples averaged. #10 11 32 samples averaged. #11 AVGE Hardware Average Enable 2 1 read-write 0 Hardware average function disabled. #0 1 Hardware average function enabled. #1 ADCO Continuous Conversion Enable 3 1 read-write 0 One conversion will be performed (or one set of conversions, if AVGE is set) after a conversion is initiated. #0 1 Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated. #1 CAL Calibration 7 1 read-write BASE_OFS BASE Offset Register 0x98 32 read-write 0x40 0xFFFFFFFF BA_OFS Base Offset Error Correction Value 0 8 read-write OFS ADC Offset Correction Register 0x9C 32 read-write 0 0xFFFFFFFF OFS Offset Error Correction Value 0 16 read-write USR_OFS USER Offset Correction Register 0xA0 32 read-write 0 0xFFFFFFFF USR_OFS USER Offset Error Correction Value 0 8 read-write XOFS ADC X Offset Correction Register 0xA4 32 read-write 0x30 0xFFFFFFFF XOFS X offset error correction value 0 6 read-write YOFS ADC Y Offset Correction Register 0xA8 32 read-write 0x37 0xFFFFFFFF YOFS Y offset error correction value 0 8 read-write G ADC Gain Register 0xAC 32 read-write 0x2F0 0xFFFFFFFF G Gain error adjustment factor for the overall conversion 0 11 read-write UG ADC User Gain Register 0xB0 32 read-write 0x4 0xFFFFFFFF UG User gain error correction value 0 10 read-write CLPS ADC General Calibration Value Register S 0xB4 32 read-write 0x2E 0xFFFFFFFF CLPS Calibration Value 0 7 read-write CLP3 ADC Plus-Side General Calibration Value Register 3 0xB8 32 read-write 0x180 0xFFFFFFFF CLP3 Calibration Value 0 10 read-write CLP2 ADC Plus-Side General Calibration Value Register 2 0xBC 32 read-write 0xB8 0xFFFFFFFF CLP2 Calibration Value 0 10 read-write CLP1 ADC Plus-Side General Calibration Value Register 1 0xC0 32 read-write 0x5C 0xFFFFFFFF CLP1 Calibration Value 0 9 read-write CLP0 ADC Plus-Side General Calibration Value Register 0 0xC4 32 read-write 0x2E 0xFFFFFFFF CLP0 Calibration Value 0 8 read-write CLPX ADC Plus-Side General Calibration Value Register X 0xC8 32 read-write 0 0xFFFFFFFF CLPX Calibration Value 0 7 read-write CLP9 ADC Plus-Side General Calibration Value Register 9 0xCC 32 read-write 0 0xFFFFFFFF CLP9 Calibration Value 0 7 read-write CLPS_OFS ADC General Calibration Offset Value Register S 0xD0 32 read-write 0 0xFFFFFFFF CLPS_OFS CLPS Offset 0 4 read-write CLP3_OFS ADC Plus-Side General Calibration Offset Value Register 3 0xD4 32 read-write 0 0xFFFFFFFF CLP3_OFS CLP3 Offset 0 4 read-write CLP2_OFS ADC Plus-Side General Calibration Offset Value Register 2 0xD8 32 read-write 0 0xFFFFFFFF CLP2_OFS CLP2 Offset 0 4 read-write CLP1_OFS ADC Plus-Side General Calibration Offset Value Register 1 0xDC 32 read-write 0 0xFFFFFFFF CLP1_OFS CLP1 Offset 0 4 read-write CLP0_OFS ADC Plus-Side General Calibration Offset Value Register 0 0xE0 32 read-write 0 0xFFFFFFFF CLP0_OFS CLP0 Offset 0 4 read-write CLPX_OFS ADC Plus-Side General Calibration Offset Value Register X 0xE4 32 read-write 0x440 0xFFFFFFFF CLPX_OFS CLPX Offset 0 12 read-write CLP9_OFS ADC Plus-Side General Calibration Offset Value Register 9 0xE8 32 read-write 0x240 0xFFFFFFFF CLP9_OFS CLP9 Offset 0 12 read-write RTC Secure Real Time Clock RTC_ 0x4003D000 0 0x20 registers RTC 6 RTC_Seconds 7 TSR RTC Time Seconds Register 0 32 read-write 0 0xFFFFFFFF TSR Time Seconds Register 0 32 read-write TPR RTC Time Prescaler Register 0x4 32 read-write 0 0xFFFFFFFF TPR Time Prescaler Register 0 16 read-write TAR RTC Time Alarm Register 0x8 32 read-write 0 0xFFFFFFFF TAR Time Alarm Register 0 32 read-write TCR RTC Time Compensation Register 0xC 32 read-write 0 0xFFFFFFFF TCR Time Compensation Register 0 8 read-write 10000000 Time Prescaler Register overflows every 32896 clock cycles. #10000000 10000001 Time Prescaler Register overflows every 32895 clock cycles. #10000001 11111111 Time Prescaler Register overflows every 32769 clock cycles. #11111111 00000000 Time Prescaler Register overflows every 32768 clock cycles. #0 00000001 Time Prescaler Register overflows every 32767 clock cycles. #1 01111110 Time Prescaler Register overflows every 32642 clock cycles. #1111110 01111111 Time Prescaler Register overflows every 32641 clock cycles. #1111111 CIR Compensation Interval Register 8 8 read-write TCV Time Compensation Value 16 8 read-only CIC Compensation Interval Counter 24 8 read-only CR RTC Control Register 0x10 32 read-write 0 0xFFFFFFFF SWR Software Reset 0 1 read-write 0 No effect. #0 SUP Supervisor Access 2 1 read-write 0 Non-supervisor mode write accesses are not supported and generate a bus error. #0 1 Non-supervisor mode write accesses are supported. #1 UM Update Mode 3 1 read-write 0 Registers cannot be written when locked. #0 1 Registers can be written when locked under limited conditions. #1 CPS Clock Pin Select 5 1 read-write 0 The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT. #0 1 The RTC 32.768 kHz clock is output on RTC_CLKOUT, provided it is output to other peripherals. #1 LPOS LPO Select 7 1 read-write 0 RTC prescaler increments using 32.768 kHz clock. #0 1 RTC prescaler increments using 1 kHz LPO, bits [4:0] of the prescaler are ignored. #1 CLKO Clock Output 9 1 read-write 0 The 32 kHz clock is output to other peripherals. #0 1 The 32 kHz clock is not output to other peripherals. #1 CPE Clock Pin Enable 24 1 read-write 0 The RTC_CLKOUT function is disabled. #0 1 Enable RTC_CLKOUT function. #1 SR RTC Status Register 0x14 32 read-write 0x1 0xFFFFFFFF TIF Time Invalid Flag 0 1 read-only 0 Time is valid. #0 1 Time is invalid and time counter is read as zero. #1 TOF Time Overflow Flag 1 1 read-only 0 Time overflow has not occurred. #0 1 Time overflow has occurred and time counter is read as zero. #1 TAF Time Alarm Flag 2 1 read-only 0 Time alarm has not occurred. #0 1 Time alarm has occurred. #1 TCE Time Counter Enable 4 1 read-write 0 Time counter is disabled. #0 1 Time counter is enabled. #1 LR RTC Lock Register 0x18 32 read-write 0xFF 0xFFFFFFFF TCL Time Compensation Lock 3 1 read-write 0 Time Compensation Register is locked and writes are ignored. #0 1 Time Compensation Register is not locked and writes complete as normal. #1 CRL Control Register Lock 4 1 read-write 0 Control Register is locked and writes are ignored. #0 1 Control Register is not locked and writes complete as normal. #1 SRL Status Register Lock 5 1 read-write 0 Status Register is locked and writes are ignored. #0 1 Status Register is not locked and writes complete as normal. #1 LRL Lock Register Lock 6 1 read-write 0 Lock Register is locked and writes are ignored. #0 1 Lock Register is not locked and writes complete as normal. #1 IER RTC Interrupt Enable Register 0x1C 32 read-write 0x7 0xFFFFFFFF TIIE Time Invalid Interrupt Enable 0 1 read-write 0 Time invalid flag does not generate an interrupt. #0 1 Time invalid flag does generate an interrupt. #1 TOIE Time Overflow Interrupt Enable 1 1 read-write 0 Time overflow flag does not generate an interrupt. #0 1 Time overflow flag does generate an interrupt. #1 TAIE Time Alarm Interrupt Enable 2 1 read-write 0 Time alarm flag does not generate an interrupt. #0 1 Time alarm flag does generate an interrupt. #1 TSIE Time Seconds Interrupt Enable 4 1 read-write 0 Seconds interrupt is disabled. #0 1 Seconds interrupt is enabled. #1 TSIC Timer Seconds Interrupt Configuration 16 3 read-write 000 1 Hz. #000 001 2 Hz. #001 010 4 Hz. #010 011 8 Hz. #011 100 16 Hz. #100 101 32 Hz. #101 110 64 Hz. #110 111 128 Hz. #111 CMU_FC_0 CMU_FC CMU_FC CMU_FC_0_ 0x4003E000 0 0x18 registers GCR CMU Frequency Check Global Configuration Register 0 32 read-write 0 0xFFFFFFFF FCE Frequency Check Enable 0 1 read-write 0 Frequency Check Disabled #0 1 Frequency Check Enabled #1 RCCR CMU Frequency Check Reference Count Configuration Register 0x4 32 read-write 0 0xFFFFFFFF REF_CNT Reference Clock Count 0 16 read-write HTCR CMU Frequency Check High Threshold Configuration Register 0x8 32 read-write 0xFFFFFF 0xFFFFFFFF HFREF High Frequency Reference Threshold 0 24 read-write LTCR CMU Frequency Check Low Threshold Configuration Register 0xC 32 read-write 0 0xFFFFFFFF LFREF Low Frequency Reference Threshold 0 24 read-write SR CMU Frequency Check Status Register 0x10 32 read-write 0 0xFFFFFFFF FLL Frequency Lower than Low Frequency Reference Threshold Event Status 0 1 read-write 0 No FLL Event #0 1 FLL Event Occured #1 FHH Frequency Higher than High Frequency Reference Threshold Event Status 1 1 read-write 0 No FHH Event #0 1 FHH Event Occured #1 STATE Module State 2 2 read-only 00 Configure State- Configuration registers and CMU_FC_IER programming is getting done #00 01 Initialization State- Register configurations are getting loaded internally. #01 10 Initialization Wait State- The module stays in this state for 1 bus clock cycle. #10 11 Frequency Check State- The module is ready to start frequency check operation in this state. #11 RS Run Status 4 1 read-only 0 Frequency Check Stopped #0 1 Frequency Check Running #1 IER CMU Frequency Check Interrupt/Event Enable Register 0x14 32 read-write 0 0xFFFFFFFF FLLIE Frequency Lower than Low Frequency Reference Threshold Interrupt Enable 0 1 read-write 0 FLL Interrupt is Disabled #0 1 FLL Interrupt is Enabled #1 FHHIE Frequency Higher than High Frequency Reference Threshold Interrupt Enable 1 1 read-write 0 FHH Interrupt is Disabled #0 1 FHH Interrupt is Enabled #1 FLLAEE Frequency Lower than Low Frequency Reference Threshold Asynchronous Event Enable 2 1 read-write 0 Asynchronous FLL Event is Disabled #0 1 Asynchronous FLL Event is Enabled #1 FHHAEE Frequency Higher than High Frequency Reference Threshold Asynchronous Event Enable 3 1 read-write 0 Asynchronous FHH Event is Disabled #0 1 Asynchronous FHH Event is Enabled #1 CMU_FC_1 CMU_FC CMU_FC CMU_FC_1_ 0x4003F000 0 0x18 registers GCR CMU Frequency Check Global Configuration Register 0 32 read-write 0 0xFFFFFFFF FCE Frequency Check Enable 0 1 read-write 0 Frequency Check Disabled #0 1 Frequency Check Enabled #1 RCCR CMU Frequency Check Reference Count Configuration Register 0x4 32 read-write 0 0xFFFFFFFF REF_CNT Reference Clock Count 0 16 read-write HTCR CMU Frequency Check High Threshold Configuration Register 0x8 32 read-write 0xFFFFFF 0xFFFFFFFF HFREF High Frequency Reference Threshold 0 24 read-write LTCR CMU Frequency Check Low Threshold Configuration Register 0xC 32 read-write 0 0xFFFFFFFF LFREF Low Frequency Reference Threshold 0 24 read-write SR CMU Frequency Check Status Register 0x10 32 read-write 0 0xFFFFFFFF FLL Frequency Lower than Low Frequency Reference Threshold Event Status 0 1 read-write 0 No FLL Event #0 1 FLL Event Occured #1 FHH Frequency Higher than High Frequency Reference Threshold Event Status 1 1 read-write 0 No FHH Event #0 1 FHH Event Occured #1 STATE Module State 2 2 read-only 00 Configure State- Configuration registers and CMU_FC_IER programming is getting done #00 01 Initialization State- Register configurations are getting loaded internally. #01 10 Initialization Wait State- The module stays in this state for 1 bus clock cycle. #10 11 Frequency Check State- The module is ready to start frequency check operation in this state. #11 RS Run Status 4 1 read-only 0 Frequency Check Stopped #0 1 Frequency Check Running #1 IER CMU Frequency Check Interrupt/Event Enable Register 0x14 32 read-write 0 0xFFFFFFFF FLLIE Frequency Lower than Low Frequency Reference Threshold Interrupt Enable 0 1 read-write 0 FLL Interrupt is Disabled #0 1 FLL Interrupt is Enabled #1 FHHIE Frequency Higher than High Frequency Reference Threshold Interrupt Enable 1 1 read-write 0 FHH Interrupt is Disabled #0 1 FHH Interrupt is Enabled #1 FLLAEE Frequency Lower than Low Frequency Reference Threshold Asynchronous Event Enable 2 1 read-write 0 Asynchronous FLL Event is Disabled #0 1 Asynchronous FLL Event is Enabled #1 FHHAEE Frequency Higher than High Frequency Reference Threshold Asynchronous Event Enable 3 1 read-write 0 Asynchronous FHH Event is Disabled #0 1 Asynchronous FHH Event is Enabled #1 LPTMR0 Low Power Timer LPTMR0_ 0x40040000 0 0x10 registers LPTMR0 8 CSR Low Power Timer Control Status Register 0 32 read-write 0 0xFFFFFFFF TEN Timer Enable 0 1 read-write 0 LPTMR is disabled and internal logic is reset. #0 1 LPTMR is enabled. #1 TMS Timer Mode Select 1 1 read-write 0 Time Counter mode. #0 1 Pulse Counter mode. #1 TFC Timer Free-Running Counter 2 1 read-write 0 CNR is reset whenever TCF is set. #0 1 CNR is reset on overflow. #1 TPP Timer Pin Polarity 3 1 read-write 0 Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. #0 1 Pulse Counter input source is active-low, and the CNR will increment on the falling-edge. #1 TPS Timer Pin Select 4 2 read-write 00 Pulse counter input 0 is selected. #00 01 Pulse counter input 1 is selected. #01 10 Pulse counter input 2 is selected. #10 11 Pulse counter input 3 is selected. #11 TIE Timer Interrupt Enable 6 1 read-write 0 Timer interrupt disabled. #0 1 Timer interrupt enabled. #1 TCF Timer Compare Flag 7 1 read-write 0 The value of CNR is not equal to CMR and increments. #0 1 The value of CNR is equal to CMR and increments. #1 TDRE Timer DMA Request Enable 8 1 read-write 0 Timer DMA Request disabled. #0 1 Timer DMA Request enabled. #1 PSR Low Power Timer Prescale Register 0x4 32 read-write 0 0xFFFFFFFF PCS Prescaler Clock Select 0 2 read-write 00 Prescaler/glitch filter clock 0 selected. #00 01 Prescaler/glitch filter clock 1 selected. #01 10 Prescaler/glitch filter clock 2 selected. #10 11 Prescaler/glitch filter clock 3 selected. #11 PBYP Prescaler Bypass 2 1 read-write 0 Prescaler/glitch filter is enabled. #0 1 Prescaler/glitch filter is bypassed. #1 PRESCALE Prescale Value 3 4 read-write 0000 Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. #0000 0001 Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. #0001 0010 Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. #0010 0011 Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. #0011 0100 Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. #0100 0101 Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. #0101 0110 Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. #0110 0111 Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. #0111 1000 Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. #1000 1001 Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. #1001 1010 Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. #1010 1011 Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. #1011 1100 Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. #1100 1101 Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. #1101 1110 Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. #1110 1111 Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges. #1111 CMR Low Power Timer Compare Register 0x8 32 read-write 0 0xFFFFFFFF COMPARE Compare Value 0 16 read-write CNR Low Power Timer Counter Register 0xC 32 read-write 0 0xFFFFFFFF COUNTER Counter Value 0 16 read-write SIM System Integration Module SIM_ 0x40048000 0x4 0x6C registers CHIPCTL Chip Control register 0x4 32 read-write 0x300000 0xFFFFFFFF ADC_INTERLEAVE_EN ADC interleave channel enable 0 4 read-write 0000 Interleaving disabled. No channel pair interleaved. Interleaved channels are individually connected to pins. PTC0 is connected to ADC0_SE8. PTC1 is connected to ADC0_SE9. PTB15 is connected to ADC1_SE14. PTB16 is connected to ADC1_SE15. PTB0 is connected to ADC0_SE4. PTB1 is connected to ADC0_SE5. PTB13 is connected to ADC1_SE8. PTB14 is connected to ADC1_SE9. #0000 1xxx PTB14 to ADC1_SE9 and ADC0_SE9 #1xxx x1xx PTB13 to ADC1_SE8 and ADC0_SE8 #x1xx xx1x PTB1 to ADC0_SE5 and ADC1_SE15 #xx1x xxx1 PTB0 to ADC0_SE4 and ADC1_SE14 #xxx1 CLKOUTSEL CLKOUT Select 4 4 read-write 0000 SCG CLKOUT #0000 0010 SOSC DIV2 CLK #0010 0100 SIRC DIV2 CLK #0100 0101 For S32K148: QSPI SFIF_CLK_HYP: Divide by 2 clock (configured through SCLKCONFIG[5]) for HyperRAM going to sfif clock to QSPI; For others: Reserved #0101 0110 FIRC DIV2 CLK #0110 0111 HCLK #0111 1000 SPLL DIV2 CLK #1000 1001 BUS_CLK #1001 1010 LPO128K_CLK #1010 1011 For S32K148: QSPI IPG_CLK; For others: Reserved #1011 1100 LPO_CLK as selected by SIM_LPOCLKS[LPOCLKSEL] #1100 1101 For S32K148: QSPI IPG_CLK_SFIF; For others: Reserved #1101 1110 RTC_CLK as selected by SIM_LPOCLKS[RTCCLKSEL] #1110 1111 For S32K148: QSPI IPG_CLK_2XSFIF; For others: Reserved #1111 CLKOUTDIV CLKOUT Divide Ratio 8 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 3 #010 011 Divide by 4 #011 100 Divide by 5 #100 101 Divide by 6 #101 110 Divide by 7 #110 111 Divide by 8 #111 CLKOUTEN CLKOUT enable 11 1 read-write 0 Clockout disable #0 1 Clockout enable #1 TRACECLK_SEL Debug trace clock select 12 1 read-write 0 Core clock #0 1 Platform clock #1 PDB_BB_SEL PDB back-to-back select 13 1 read-write 0 PDB0 channel 0 back-to-back operation with ADC0 COCO[7:0] and PDB1 channel 0 back-to-back operation with ADC1 COCO[7:0] #0 1 Channel 0 of PDB0 and PDB1 back-to-back operation with COCO[7:0] of ADC0 and ADC1. #1 ADC_SUPPLY ADC_SUPPLY 16 3 read-write 000 5 V input VDD supply (VDD) #000 001 5 V input analog supply (VDDA) #001 010 ADC Reference Supply (VREFH) #010 011 3.3 V Oscillator Regulator Output (VDD_3V) #011 100 3.3 V flash regulator output (VDD_flash_3V) #100 101 1.2 V core regulator output (VDD_LV) #101 ADC_SUPPLYEN ADC_SUPPLYEN 19 1 read-write 0 Disable internal supply monitoring #0 1 Enable internal supply monitoring #1 SRAMU_RETEN SRAMU_RETEN 20 1 read-write 0 SRAMU contents are retained across resets #0 1 No SRAMU retention #1 SRAML_RETEN SRAML_RETEN 21 1 read-write 0 SRAML contents are retained across resets #0 1 No SRAML retention #1 FTMOPT0 FTM Option Register 0 0xC 32 read-write 0 0xFFFFFFFF FTM0FLTxSEL FTM0 Fault X Select 0 3 read-write 000 FTM0_FLTx pin #000 001 TRGMUX_FTM0 out #001 FTM1FLTxSEL FTM1 Fault X Select 4 3 read-write 000 FTM1_FLTx pin #000 001 TRGMUX_FTM1 out #001 FTM2FLTxSEL FTM2 Fault X Select 8 3 read-write 000 FTM2_FLTx pin #000 001 TRGMUX_FTM2 out #001 FTM3FLTxSEL FTM3 Fault X Select 12 3 read-write 000 FTM3_FLTx pin #000 001 TRGMUX_FTM3 out #001 FTM0CLKSEL FTM0 External Clock Pin Select 24 2 read-write 00 FTM0 external clock driven by TCLK0 pin. #00 01 FTM0 external clock driven by TCLK1 pin. #01 10 FTM0 external clock driven by TCLK2 pin. #10 11 No clock input #11 FTM1CLKSEL FTM1 External Clock Pin Select 26 2 read-write 00 FTM1 external clock driven by TCLK0 pin. #00 01 FTM1 external clock driven by TCLK1 pin. #01 10 FTM1 external clock driven by TCLK2 pin. #10 11 No clock input #11 FTM2CLKSEL FTM2 External Clock Pin Select 28 2 read-write 00 FTM2 external clock driven by TCLK0 pin. #00 01 FTM2 external clock driven by TCLK1 pin. #01 10 FTM2 external clock driven by TCLK2 pin. #10 11 No clock input #11 FTM3CLKSEL FTM3 External Clock Pin Select 30 2 read-write 00 FTM3 external clock driven by TCLK0 pin. #00 01 FTM3 external clock driven by TCLK1 pin. #01 10 FTM3 external clock driven by TCLK2 pin. #10 11 No clock input #11 LPOCLKS LPO Clock Select Register 0x10 32 read-write 0x3 0xFFFFFFFF LPO1KCLKEN 1 kHz LPO_CLK enable 0 1 read-write 0 Disable 1 kHz LPO_CLK output #0 1 Enable 1 kHz LPO_CLK output #1 LPO32KCLKEN 32 kHz LPO_CLK enable 1 1 read-write 0 Disable 32 kHz LPO_CLK output #0 1 Enable 32 kHz LPO_CLK output #1 LPOCLKSEL LPO clock source select 2 2 read-write 00 128 kHz LPO_CLK #00 01 No clock #01 10 32 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK #10 11 1 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK #11 RTCCLKSEL 32 kHz clock source select 4 2 read-write 00 SOSCDIV1_CLK #00 01 32 kHz LPO_CLK #01 10 RTC_CLKIN clock #10 11 FIRCDIV1_CLK #11 ADCOPT ADC Options Register 0x18 32 read-write 0 0xFFFFFFFF ADC0TRGSEL ADC0 trigger source select 0 1 read-write 0 PDB output #0 1 TRGMUX output #1 ADC0SWPRETRG ADC0 software pretrigger sources 1 3 read-write 000 Software pretrigger disabled #000 001 Reserved (do not use) #001 010 Reserved (do not use) #010 011 Reserved (do not use) #011 100 Software pretrigger 0 #100 101 Software pretrigger 1 #101 110 Software pretrigger 2 #110 111 Software pretrigger 3 #111 ADC0PRETRGSEL ADC0 pretrigger source select 4 2 read-write 00 PDB pretrigger (default) #00 01 TRGMUX pretrigger #01 10 Software pretrigger #10 ADC1TRGSEL ADC1 trigger source select 8 1 read-write 0 PDB output #0 1 TRGMUX output #1 ADC1SWPRETRG ADC1 software pretrigger sources 9 3 read-write 000 Software pretrigger disabled #000 001 Reserved (do not use) #001 010 Reserved (do not use) #010 011 Reserved (do not use) #011 100 Software pretrigger 0 #100 101 Software pretrigger 1 #101 110 Software pretrigger 2 #110 111 Software pretrigger 3 #111 ADC1PRETRGSEL ADC1 pretrigger source select 12 2 read-write 00 PDB pretrigger (default) #00 01 TRGMUX pretrigger #01 10 Software pretrigger #10 FTMOPT1 FTM Option Register 1 0x1C 32 read-write 0 0xFFFFFFFF FTM0SYNCBIT FTM0 Sync Bit 0 1 read-write FTM1SYNCBIT FTM1 Sync Bit 1 1 read-write FTM2SYNCBIT FTM2 Sync Bit 2 1 read-write FTM3SYNCBIT FTM3 Sync Bit 3 1 read-write FTM1CH0SEL FTM1 CH0 Select 4 2 read-write 00 FTM1_CH0 input #00 01 CMP0 output #01 FTM2CH0SEL FTM2 CH0 Select 6 2 read-write 00 FTM2_CH0 input #00 01 CMP0 output #01 FTM2CH1SEL FTM2 CH1 Select 8 1 read-write 0 FTM2_CH1 input #0 1 exclusive OR of FTM2_CH0,FTM2_CH1,and FTM1_CH1 #1 FTMGLDOK FTM global load enable 15 1 read-write 0 FTM Global load mechanism disabled. #0 1 FTM Global load mechanism enabled #1 FTM0_OUTSEL FTM0 channel modulation select with FTM1_CH1 16 8 read-write 00000000 No modulation with FTM1_CH1 #0 00000001 Modulation with FTM1_CH1 #1 FTM3_OUTSEL FTM3 channel modulation select with FTM2_CH1 24 8 read-write 00000000 No modulation with FTM2_CH1 #0 00000001 Modulation with FTM2_CH1 #1 MISCTRL0 Miscellaneous control register 0 0x20 32 read-write 0 0xFFFFFFFF FTM0_OBE_CTRL FTM0 OBE CTRL bit 16 1 read-write 0 The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated. #0 1 The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]. #1 FTM1_OBE_CTRL FTM1 OBE CTRL bit 17 1 read-write 0 The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated. #0 1 The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]. #1 FTM2_OBE_CTRL FTM2 OBE CTRL bit 18 1 read-write 0 The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated. #0 1 The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]. #1 FTM3_OBE_CTRL FTM3 OBE CTRL bit 19 1 read-write 0 The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated. #0 1 The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]. #1 SDID System Device Identification Register 0x24 32 read-only 0 0 FEATURES Features 0 8 read-only PACKAGE Package 8 4 read-only 0010 48 LQFP #0010 0011 64 LQFP #0011 0100 100 LQFP #0100 0110 144 LQFP #0110 0111 176 LQFP #0111 1000 100 MAP BGA #1000 REVID Device revision number 12 4 read-only RAMSIZE RAM size 16 4 read-only 0111 128 KB (S32K148), Reserved (others) #0111 1001 160 KB (S32K148) , Reserved (others) #1001 1011 192 KB (S32K148), 16 KB (S32K142), Reserved (others) #1011 1101 48 KB (S32K144), 24 KB (S32K142), Reserved (others) #1101 1111 256 KB (S32K148), 64 KB (S32K144), 32 KB (S32K142) #1111 DERIVATE Derivate 20 4 read-only SUBSERIES Subseries 24 4 read-only GENERATION S32K product series generation 28 4 read-only PLATCGC Platform Clock Gating Control Register 0x40 32 read-write 0x1F 0xFFFFFFFF CGCMSCM MSCM Clock Gating Control 0 1 read-write 0 Clock disabled #0 1 Clock enabled #1 CGCMPU MPU Clock Gating Control 1 1 read-write 0 Clock disabled #0 1 Clock enabled #1 CGCDMA DMA Clock Gating Control 2 1 read-write 0 Clock disabled #0 1 Clock enabled #1 CGCERM ERM Clock Gating Control 3 1 read-write 0 Clock disabled #0 1 Clock enabled #1 CGCEIM EIM Clock Gating Control 4 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FCFG1 Flash Configuration Register 1 0x4C 32 read-write 0 0 DEPART FlexNVM partition 12 4 read-only EEERAMSIZE EEE SRAM SIZE 16 4 read-only 0010 4 KB #0010 0011 2 KB #0011 0100 1 KB #0100 0101 512 Bytes #0101 0110 256 Bytes #0110 0111 128 Bytes #0111 1000 64 Bytes #1000 1001 32 Bytes #1001 1111 0 Bytes #1111 UIDH Unique Identification Register High 0x54 32 read-only 0 0 UID127_96 Unique Identification 0 32 read-only UIDMH Unique Identification Register Mid-High 0x58 32 read-only 0 0 UID95_64 Unique Identification 0 32 read-only UIDML Unique Identification Register Mid Low 0x5C 32 read-only 0 0 UID63_32 Unique Identification 0 32 read-only UIDL Unique Identification Register Low 0x60 32 read-only 0 0 UID31_0 Unique Identification 0 32 read-only CLKDIV4 System Clock Divider Register 4 0x68 32 read-write 0x10000000 0xFFFFFFFF TRACEFRAC Trace Clock Divider fraction To configure TRACEDIV and TRACEFRAC, you must first clear TRACEDIVEN to disable the trace clock divide function. 0 1 read-write TRACEDIV Trace Clock Divider value To configure TRACEDIV, you must first disable TRACEDIVEN, then enable it after setting TRACEDIV. 1 3 read-write TRACEDIVEN Debug Trace Divider control 28 1 read-write 0 Debug trace divider disabled #0 1 Debug trace divider enabled #1 MISCTRL1 Miscellaneous Control register 1 0x6C 32 read-write 0 0xFFFFFFFF SW_TRG Software trigger to TRGMUX. Writing to this bit generates software trigger to peripherals through TRGMUX (Refer to Figure: Trigger interconnectivity). 0 1 read-write PORTA Pin Control and Interrupts PORT PORTA_ 0x40049000 0 0xCC registers PCR0 Pin Control Register n 0 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR1 Pin Control Register n 0x4 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR2 Pin Control Register n 0x8 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR3 Pin Control Register n 0xC 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR4 Pin Control Register n 0x10 32 read-write 0x703 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR5 Pin Control Register n 0x14 32 read-write 0x713 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR6 Pin Control Register n 0x18 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR7 Pin Control Register n 0x1C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR8 Pin Control Register n 0x20 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR9 Pin Control Register n 0x24 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR10 Pin Control Register n 0x28 32 read-write 0x740 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR11 Pin Control Register n 0x2C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR12 Pin Control Register n 0x30 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR13 Pin Control Register n 0x34 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR14 Pin Control Register n 0x38 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR15 Pin Control Register n 0x3C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR16 Pin Control Register n 0x40 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR17 Pin Control Register n 0x44 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR18 Pin Control Register n 0x48 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR19 Pin Control Register n 0x4C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR20 Pin Control Register n 0x50 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR21 Pin Control Register n 0x54 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR22 Pin Control Register n 0x58 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR23 Pin Control Register n 0x5C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR24 Pin Control Register n 0x60 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR25 Pin Control Register n 0x64 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR26 Pin Control Register n 0x68 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR27 Pin Control Register n 0x6C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR28 Pin Control Register n 0x70 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR29 Pin Control Register n 0x74 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR30 Pin Control Register n 0x78 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR31 Pin Control Register n 0x7C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GICLR Global Interrupt Control Low Register 0x88 32 write-only 0 0xFFFFFFFF GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GIWD Global Interrupt Write Data 16 16 write-only GICHR Global Interrupt Control High Register 0x8C 32 write-only 0 0xFFFFFFFF GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GIWD Global Interrupt Write Data 16 16 write-only ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 DFER Digital Filter Enable Register 0xC0 32 read-write 0 0xFFFFFFFF DFE Digital Filter Enable 0 32 read-write 0 Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. #0 1 Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DFCR Digital Filter Clock Register 0xC4 32 read-write 0 0xFFFFFFFF CS Clock Source 0 1 read-write 0 Digital filters are clocked by the bus clock. #0 1 Digital filters are clocked by the LPO clock. #1 DFWR Digital Filter Width Register 0xC8 32 read-write 0 0xFFFFFFFF FILT Filter Length 0 5 read-write PORTB Pin Control and Interrupts PORT PORTB_ 0x4004A000 0 0xCC registers PCR0 Pin Control Register n 0 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR1 Pin Control Register n 0x4 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR2 Pin Control Register n 0x8 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR3 Pin Control Register n 0xC 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR4 Pin Control Register n 0x10 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR5 Pin Control Register n 0x14 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR6 Pin Control Register n 0x18 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR7 Pin Control Register n 0x1C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR8 Pin Control Register n 0x20 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR9 Pin Control Register n 0x24 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR10 Pin Control Register n 0x28 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR11 Pin Control Register n 0x2C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR12 Pin Control Register n 0x30 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR13 Pin Control Register n 0x34 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR14 Pin Control Register n 0x38 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR15 Pin Control Register n 0x3C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR16 Pin Control Register n 0x40 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR17 Pin Control Register n 0x44 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR18 Pin Control Register n 0x48 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR19 Pin Control Register n 0x4C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR20 Pin Control Register n 0x50 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR21 Pin Control Register n 0x54 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR22 Pin Control Register n 0x58 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR23 Pin Control Register n 0x5C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR24 Pin Control Register n 0x60 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR25 Pin Control Register n 0x64 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR26 Pin Control Register n 0x68 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR27 Pin Control Register n 0x6C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR28 Pin Control Register n 0x70 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR29 Pin Control Register n 0x74 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR30 Pin Control Register n 0x78 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR31 Pin Control Register n 0x7C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GICLR Global Interrupt Control Low Register 0x88 32 write-only 0 0xFFFFFFFF GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GIWD Global Interrupt Write Data 16 16 write-only GICHR Global Interrupt Control High Register 0x8C 32 write-only 0 0xFFFFFFFF GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GIWD Global Interrupt Write Data 16 16 write-only ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 DFER Digital Filter Enable Register 0xC0 32 read-write 0 0xFFFFFFFF DFE Digital Filter Enable 0 32 read-write 0 Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. #0 1 Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DFCR Digital Filter Clock Register 0xC4 32 read-write 0 0xFFFFFFFF CS Clock Source 0 1 read-write 0 Digital filters are clocked by the bus clock. #0 1 Digital filters are clocked by the LPO clock. #1 DFWR Digital Filter Width Register 0xC8 32 read-write 0 0xFFFFFFFF FILT Filter Length 0 5 read-write PORTC Pin Control and Interrupts PORT PORTC_ 0x4004B000 0 0xCC registers PCR0 Pin Control Register n 0 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR1 Pin Control Register n 0x4 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR2 Pin Control Register n 0x8 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR3 Pin Control Register n 0xC 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR4 Pin Control Register n 0x10 32 read-write 0x702 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR5 Pin Control Register n 0x14 32 read-write 0x703 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR6 Pin Control Register n 0x18 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR7 Pin Control Register n 0x1C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR8 Pin Control Register n 0x20 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR9 Pin Control Register n 0x24 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR10 Pin Control Register n 0x28 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR11 Pin Control Register n 0x2C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR12 Pin Control Register n 0x30 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR13 Pin Control Register n 0x34 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR14 Pin Control Register n 0x38 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR15 Pin Control Register n 0x3C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR16 Pin Control Register n 0x40 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR17 Pin Control Register n 0x44 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR18 Pin Control Register n 0x48 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR19 Pin Control Register n 0x4C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR20 Pin Control Register n 0x50 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR21 Pin Control Register n 0x54 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR22 Pin Control Register n 0x58 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR23 Pin Control Register n 0x5C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR24 Pin Control Register n 0x60 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR25 Pin Control Register n 0x64 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR26 Pin Control Register n 0x68 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR27 Pin Control Register n 0x6C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR28 Pin Control Register n 0x70 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR29 Pin Control Register n 0x74 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR30 Pin Control Register n 0x78 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR31 Pin Control Register n 0x7C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GICLR Global Interrupt Control Low Register 0x88 32 write-only 0 0xFFFFFFFF GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GIWD Global Interrupt Write Data 16 16 write-only GICHR Global Interrupt Control High Register 0x8C 32 write-only 0 0xFFFFFFFF GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GIWD Global Interrupt Write Data 16 16 write-only ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 DFER Digital Filter Enable Register 0xC0 32 read-write 0 0xFFFFFFFF DFE Digital Filter Enable 0 32 read-write 0 Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. #0 1 Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DFCR Digital Filter Clock Register 0xC4 32 read-write 0 0xFFFFFFFF CS Clock Source 0 1 read-write 0 Digital filters are clocked by the bus clock. #0 1 Digital filters are clocked by the LPO clock. #1 DFWR Digital Filter Width Register 0xC8 32 read-write 0 0xFFFFFFFF FILT Filter Length 0 5 read-write PORTD Pin Control and Interrupts PORT PORTD_ 0x4004C000 0 0xCC registers PCR0 Pin Control Register n 0 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR1 Pin Control Register n 0x4 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR2 Pin Control Register n 0x8 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR3 Pin Control Register n 0xC 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR4 Pin Control Register n 0x10 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR5 Pin Control Register n 0x14 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR6 Pin Control Register n 0x18 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR7 Pin Control Register n 0x1C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR8 Pin Control Register n 0x20 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR9 Pin Control Register n 0x24 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR10 Pin Control Register n 0x28 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR11 Pin Control Register n 0x2C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR12 Pin Control Register n 0x30 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR13 Pin Control Register n 0x34 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR14 Pin Control Register n 0x38 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR15 Pin Control Register n 0x3C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR16 Pin Control Register n 0x40 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR17 Pin Control Register n 0x44 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR18 Pin Control Register n 0x48 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR19 Pin Control Register n 0x4C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR20 Pin Control Register n 0x50 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR21 Pin Control Register n 0x54 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR22 Pin Control Register n 0x58 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR23 Pin Control Register n 0x5C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR24 Pin Control Register n 0x60 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR25 Pin Control Register n 0x64 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR26 Pin Control Register n 0x68 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR27 Pin Control Register n 0x6C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR28 Pin Control Register n 0x70 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR29 Pin Control Register n 0x74 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR30 Pin Control Register n 0x78 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR31 Pin Control Register n 0x7C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GICLR Global Interrupt Control Low Register 0x88 32 write-only 0 0xFFFFFFFF GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GIWD Global Interrupt Write Data 16 16 write-only GICHR Global Interrupt Control High Register 0x8C 32 write-only 0 0xFFFFFFFF GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GIWD Global Interrupt Write Data 16 16 write-only ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 DFER Digital Filter Enable Register 0xC0 32 read-write 0 0xFFFFFFFF DFE Digital Filter Enable 0 32 read-write 0 Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. #0 1 Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DFCR Digital Filter Clock Register 0xC4 32 read-write 0 0xFFFFFFFF CS Clock Source 0 1 read-write 0 Digital filters are clocked by the bus clock. #0 1 Digital filters are clocked by the LPO clock. #1 DFWR Digital Filter Width Register 0xC8 32 read-write 0 0xFFFFFFFF FILT Filter Length 0 5 read-write PORTE Pin Control and Interrupts PORT PORTE_ 0x4004D000 0 0xCC registers PCR0 Pin Control Register n 0 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR1 Pin Control Register n 0x4 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR2 Pin Control Register n 0x8 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR3 Pin Control Register n 0xC 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR4 Pin Control Register n 0x10 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR5 Pin Control Register n 0x14 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR6 Pin Control Register n 0x18 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR7 Pin Control Register n 0x1C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR8 Pin Control Register n 0x20 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR9 Pin Control Register n 0x24 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR10 Pin Control Register n 0x28 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR11 Pin Control Register n 0x2C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR12 Pin Control Register n 0x30 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR13 Pin Control Register n 0x34 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR14 Pin Control Register n 0x38 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR15 Pin Control Register n 0x3C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR16 Pin Control Register n 0x40 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR17 Pin Control Register n 0x44 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR18 Pin Control Register n 0x48 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR19 Pin Control Register n 0x4C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR20 Pin Control Register n 0x50 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR21 Pin Control Register n 0x54 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR22 Pin Control Register n 0x58 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR23 Pin Control Register n 0x5C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR24 Pin Control Register n 0x60 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR25 Pin Control Register n 0x64 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR26 Pin Control Register n 0x68 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR27 Pin Control Register n 0x6C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR28 Pin Control Register n 0x70 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR29 Pin Control Register n 0x74 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR30 Pin Control Register n 0x78 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR31 Pin Control Register n 0x7C 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GICLR Global Interrupt Control Low Register 0x88 32 write-only 0 0xFFFFFFFF GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GIWD Global Interrupt Write Data 16 16 write-only GICHR Global Interrupt Control High Register 0x8C 32 write-only 0 0xFFFFFFFF GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GIWD Global Interrupt Write Data 16 16 write-only ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 DFER Digital Filter Enable Register 0xC0 32 read-write 0 0xFFFFFFFF DFE Digital Filter Enable 0 32 read-write 0 Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. #0 1 Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DFCR Digital Filter Clock Register 0xC4 32 read-write 0 0xFFFFFFFF CS Clock Source 0 1 read-write 0 Digital filters are clocked by the bus clock. #0 1 Digital filters are clocked by the LPO clock. #1 DFWR Digital Filter Width Register 0xC8 32 read-write 0 0xFFFFFFFF FILT Filter Length 0 5 read-write WDOG Watchdog timer WDOG_ 0x40052000 0 0x10 registers WDOG 22 CS Watchdog Control and Status Register 0 32 read-write 0x2980 0xFFFFFFFF STOP Stop Enable 0 1 read-write 0 Watchdog disabled in chip stop mode. #0 1 Watchdog enabled in chip stop mode. #1 WAIT Wait Enable 1 1 read-write 0 Watchdog disabled in chip wait mode. #0 1 Watchdog enabled in chip wait mode. #1 DBG Debug Enable 2 1 read-write 0 Watchdog disabled in chip debug mode. #0 1 Watchdog enabled in chip debug mode. #1 TST Watchdog Test 3 2 read-write 00 Watchdog test mode disabled. #00 01 Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode. #01 10 Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]. #10 11 Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH]. #11 UPDATE Allow updates 5 1 read-write 0 Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. #0 1 Updates allowed. Software can modify the watchdog configuration registers within 8'd128 bus clocks after performing the unlock write sequence. #1 INT Watchdog Interrupt 6 1 read-write 0 Watchdog interrupts are disabled. Watchdog resets are not delayed. #0 1 Watchdog interrupts are enabled. Watchdog resets are delayed by 8'd128 bus clocks from the interrupt vector fetch. #1 EN Watchdog Enable 7 1 read-write 0 Watchdog disabled. #0 1 Watchdog enabled. #1 CLK Watchdog Clock 8 2 read-write 00 Bus clock #00 01 LPO clock #01 10 INTCLK (internal clock) #10 11 ERCLK (external reference clock) #11 RCS Reconfiguration Success 10 1 read-only 0 Reconfiguring WDOG. #0 1 Reconfiguration is successful. #1 ULK Unlock status 11 1 read-only 0 WDOG is locked. #0 1 WDOG is unlocked. #1 PRES Watchdog prescaler 12 1 read-write 0 256 prescaler disabled. #0 1 256 prescaler enabled. #1 CMD32EN Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words 13 1 read-write 0 Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported. #0 1 Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported. #1 FLG Watchdog Interrupt Flag 14 1 read-write 0 No interrupt occurred. #0 1 An interrupt occurred. #1 WIN Watchdog Window 15 1 read-write 0 Window mode disabled. #0 1 Window mode enabled. #1 CNT Watchdog Counter Register 0x4 32 read-write 0 0xFFFFFFFF CNTLOW Low byte of the Watchdog Counter 0 8 read-write CNTHIGH High byte of the Watchdog Counter 8 8 read-write TOVAL Watchdog Timeout Value Register 0x8 32 read-write 0x400 0xFFFFFFFF TOVALLOW Low byte of the timeout value 0 8 read-write TOVALHIGH High byte of the timeout value 8 8 read-write WIN Watchdog Window Register 0xC 32 read-write 0 0xFFFFFFFF WINLOW Low byte of Watchdog Window 0 8 read-write WINHIGH High byte of Watchdog Window 8 8 read-write FLEXIO The FLEXIO Memory Map/Register Definition can be found here. FLEXIO_ 0x4005A000 0 0x510 registers FLEXIO 25 VERID Version ID Register 0 32 read-only 0x1010000 0xFFFFFFFF FEATURE Feature Specification Number 0 16 read-only 0000000000000000 Standard features implemented. #0 0000000000000001 Supports state, logic and parallel modes. #1 MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM Parameter Register 0x4 32 read-only 0x4080404 0xFFFFFFFF SHIFTER Shifter Number 0 8 read-only TIMER Timer Number 8 8 read-only PIN Pin Number 16 8 read-only TRIGGER Trigger Number 24 8 read-only CTRL FlexIO Control Register 0x8 32 read-write 0 0xFFFFFFFF FLEXEN FlexIO Enable 0 1 read-write 0 FlexIO module is disabled. #0 1 FlexIO module is enabled. #1 SWRST Software Reset 1 1 read-write 0 Software reset is disabled #0 1 Software reset is enabled, all FlexIO registers except the Control Register are reset. #1 FASTACC Fast Access 2 1 read-write 0 Configures for normal register accesses to FlexIO #0 1 Configures for fast register accesses to FlexIO #1 DBGE Debug Enable 30 1 read-write 0 FlexIO is disabled in debug modes. #0 1 FlexIO is enabled in debug modes #1 DOZEN Doze Enable 31 1 read-write 0 FlexIO enabled in Doze modes. #0 1 FlexIO disabled in Doze modes. #1 PIN Pin State Register 0xC 32 read-only 0 0xFFFFFFFF PDI Pin Data Input 0 8 read-only SHIFTSTAT Shifter Status Register 0x10 32 read-write 0 0xFFFFFFFF SSF Shifter Status Flag 0 4 read-write SHIFTERR Shifter Error Register 0x14 32 read-write 0 0xFFFFFFFF SEF Shifter Error Flags 0 4 read-write TIMSTAT Timer Status Register 0x18 32 read-write 0 0xFFFFFFFF TSF Timer Status Flags 0 4 read-write SHIFTSIEN Shifter Status Interrupt Enable 0x20 32 read-write 0 0xFFFFFFFF SSIE Shifter Status Interrupt Enable 0 4 read-write SHIFTEIEN Shifter Error Interrupt Enable 0x24 32 read-write 0 0xFFFFFFFF SEIE Shifter Error Interrupt Enable 0 4 read-write TIMIEN Timer Interrupt Enable Register 0x28 32 read-write 0 0xFFFFFFFF TEIE Timer Status Interrupt Enable 0 4 read-write SHIFTSDEN Shifter Status DMA Enable 0x30 32 read-write 0 0xFFFFFFFF SSDE Shifter Status DMA Enable 0 4 read-write SHIFTCTL0 Shifter Control N Register 0x80 32 read-write 0 0xFFFFFFFF SMOD Shifter Mode 0 3 read-write 0 Disabled. #000 1 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. #001 10 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. #010 100 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. #100 101 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. #101 PINPOL Shifter Pin Polarity 7 1 read-write 0 Pin is active high #0 1 Pin is active low #1 PINSEL Shifter Pin Select 8 3 read-write PINCFG Shifter Pin Configuration 16 2 read-write 0 Shifter pin output disabled #00 1 Shifter pin open drain or bidirectional output enable #01 10 Shifter pin bidirectional output data #10 11 Shifter pin output #11 TIMPOL Timer Polarity 23 1 read-write 0 Shift on posedge of Shift clock #0 1 Shift on negedge of Shift clock #1 TIMSEL Timer Select 24 2 read-write SHIFTCTL1 Shifter Control N Register 0x84 32 read-write 0 0xFFFFFFFF SMOD Shifter Mode 0 3 read-write 0 Disabled. #000 1 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. #001 10 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. #010 100 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. #100 101 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. #101 PINPOL Shifter Pin Polarity 7 1 read-write 0 Pin is active high #0 1 Pin is active low #1 PINSEL Shifter Pin Select 8 3 read-write PINCFG Shifter Pin Configuration 16 2 read-write 0 Shifter pin output disabled #00 1 Shifter pin open drain or bidirectional output enable #01 10 Shifter pin bidirectional output data #10 11 Shifter pin output #11 TIMPOL Timer Polarity 23 1 read-write 0 Shift on posedge of Shift clock #0 1 Shift on negedge of Shift clock #1 TIMSEL Timer Select 24 2 read-write SHIFTCTL2 Shifter Control N Register 0x88 32 read-write 0 0xFFFFFFFF SMOD Shifter Mode 0 3 read-write 0 Disabled. #000 1 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. #001 10 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. #010 100 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. #100 101 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. #101 PINPOL Shifter Pin Polarity 7 1 read-write 0 Pin is active high #0 1 Pin is active low #1 PINSEL Shifter Pin Select 8 3 read-write PINCFG Shifter Pin Configuration 16 2 read-write 0 Shifter pin output disabled #00 1 Shifter pin open drain or bidirectional output enable #01 10 Shifter pin bidirectional output data #10 11 Shifter pin output #11 TIMPOL Timer Polarity 23 1 read-write 0 Shift on posedge of Shift clock #0 1 Shift on negedge of Shift clock #1 TIMSEL Timer Select 24 2 read-write SHIFTCTL3 Shifter Control N Register 0x8C 32 read-write 0 0xFFFFFFFF SMOD Shifter Mode 0 3 read-write 0 Disabled. #000 1 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. #001 10 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. #010 100 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. #100 101 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. #101 PINPOL Shifter Pin Polarity 7 1 read-write 0 Pin is active high #0 1 Pin is active low #1 PINSEL Shifter Pin Select 8 3 read-write PINCFG Shifter Pin Configuration 16 2 read-write 0 Shifter pin output disabled #00 1 Shifter pin open drain or bidirectional output enable #01 10 Shifter pin bidirectional output data #10 11 Shifter pin output #11 TIMPOL Timer Polarity 23 1 read-write 0 Shift on posedge of Shift clock #0 1 Shift on negedge of Shift clock #1 TIMSEL Timer Select 24 2 read-write SHIFTCFG0 Shifter Configuration N Register 0x100 32 read-write 0 0xFFFFFFFF SSTART Shifter Start bit 0 2 read-write 0 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable #00 1 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift #01 10 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 #10 11 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 #11 SSTOP Shifter Stop bit 4 2 read-write 0 Stop bit disabled for transmitter/receiver/match store #00 1 Reserved for transmitter/receiver/match store #01 10 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 #10 11 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 #11 INSRC Input Source 8 1 read-write 0 Pin #0 1 Shifter N+1 Output #1 SHIFTCFG1 Shifter Configuration N Register 0x104 32 read-write 0 0xFFFFFFFF SSTART Shifter Start bit 0 2 read-write 0 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable #00 1 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift #01 10 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 #10 11 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 #11 SSTOP Shifter Stop bit 4 2 read-write 0 Stop bit disabled for transmitter/receiver/match store #00 1 Reserved for transmitter/receiver/match store #01 10 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 #10 11 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 #11 INSRC Input Source 8 1 read-write 0 Pin #0 1 Shifter N+1 Output #1 SHIFTCFG2 Shifter Configuration N Register 0x108 32 read-write 0 0xFFFFFFFF SSTART Shifter Start bit 0 2 read-write 0 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable #00 1 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift #01 10 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 #10 11 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 #11 SSTOP Shifter Stop bit 4 2 read-write 0 Stop bit disabled for transmitter/receiver/match store #00 1 Reserved for transmitter/receiver/match store #01 10 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 #10 11 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 #11 INSRC Input Source 8 1 read-write 0 Pin #0 1 Shifter N+1 Output #1 SHIFTCFG3 Shifter Configuration N Register 0x10C 32 read-write 0 0xFFFFFFFF SSTART Shifter Start bit 0 2 read-write 0 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable #00 1 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift #01 10 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 #10 11 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 #11 SSTOP Shifter Stop bit 4 2 read-write 0 Stop bit disabled for transmitter/receiver/match store #00 1 Reserved for transmitter/receiver/match store #01 10 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 #10 11 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 #11 INSRC Input Source 8 1 read-write 0 Pin #0 1 Shifter N+1 Output #1 SHIFTBUF0 Shifter Buffer N Register 0x200 32 read-write 0 0xFFFFFFFF SHIFTBUF Shift Buffer 0 32 read-write SHIFTBUF1 Shifter Buffer N Register 0x204 32 read-write 0 0xFFFFFFFF SHIFTBUF Shift Buffer 0 32 read-write SHIFTBUF2 Shifter Buffer N Register 0x208 32 read-write 0 0xFFFFFFFF SHIFTBUF Shift Buffer 0 32 read-write SHIFTBUF3 Shifter Buffer N Register 0x20C 32 read-write 0 0xFFFFFFFF SHIFTBUF Shift Buffer 0 32 read-write SHIFTBUFBIS0 Shifter Buffer N Bit Swapped Register 0x280 32 read-write 0 0xFFFFFFFF SHIFTBUFBIS Shift Buffer 0 32 read-write SHIFTBUFBIS1 Shifter Buffer N Bit Swapped Register 0x284 32 read-write 0 0xFFFFFFFF SHIFTBUFBIS Shift Buffer 0 32 read-write SHIFTBUFBIS2 Shifter Buffer N Bit Swapped Register 0x288 32 read-write 0 0xFFFFFFFF SHIFTBUFBIS Shift Buffer 0 32 read-write SHIFTBUFBIS3 Shifter Buffer N Bit Swapped Register 0x28C 32 read-write 0 0xFFFFFFFF SHIFTBUFBIS Shift Buffer 0 32 read-write SHIFTBUFBYS0 Shifter Buffer N Byte Swapped Register 0x300 32 read-write 0 0xFFFFFFFF SHIFTBUFBYS Shift Buffer 0 32 read-write SHIFTBUFBYS1 Shifter Buffer N Byte Swapped Register 0x304 32 read-write 0 0xFFFFFFFF SHIFTBUFBYS Shift Buffer 0 32 read-write SHIFTBUFBYS2 Shifter Buffer N Byte Swapped Register 0x308 32 read-write 0 0xFFFFFFFF SHIFTBUFBYS Shift Buffer 0 32 read-write SHIFTBUFBYS3 Shifter Buffer N Byte Swapped Register 0x30C 32 read-write 0 0xFFFFFFFF SHIFTBUFBYS Shift Buffer 0 32 read-write SHIFTBUFBBS0 Shifter Buffer N Bit Byte Swapped Register 0x380 32 read-write 0 0xFFFFFFFF SHIFTBUFBBS Shift Buffer 0 32 read-write SHIFTBUFBBS1 Shifter Buffer N Bit Byte Swapped Register 0x384 32 read-write 0 0xFFFFFFFF SHIFTBUFBBS Shift Buffer 0 32 read-write SHIFTBUFBBS2 Shifter Buffer N Bit Byte Swapped Register 0x388 32 read-write 0 0xFFFFFFFF SHIFTBUFBBS Shift Buffer 0 32 read-write SHIFTBUFBBS3 Shifter Buffer N Bit Byte Swapped Register 0x38C 32 read-write 0 0xFFFFFFFF SHIFTBUFBBS Shift Buffer 0 32 read-write TIMCTL0 Timer Control N Register 0x400 32 read-write 0 0xFFFFFFFF TIMOD Timer Mode 0 2 read-write 0 Timer Disabled. #00 1 Dual 8-bit counters baud/bit mode. #01 10 Dual 8-bit counters PWM mode. #10 11 Single 16-bit counter mode. #11 PINPOL Timer Pin Polarity 7 1 read-write 0 Pin is active high #0 1 Pin is active low #1 PINSEL Timer Pin Select 8 3 read-write PINCFG Timer Pin Configuration 16 2 read-write 0 Timer pin output disabled #00 1 Timer pin open drain or bidirectional output enable #01 10 Timer pin bidirectional output data #10 11 Timer pin output #11 TRGSRC Trigger Source 22 1 read-write 0 External trigger selected #0 1 Internal trigger selected #1 TRGPOL Trigger Polarity 23 1 read-write 0 Trigger active high #0 1 Trigger active low #1 TRGSEL Trigger Select 24 4 read-write TIMCTL1 Timer Control N Register 0x404 32 read-write 0 0xFFFFFFFF TIMOD Timer Mode 0 2 read-write 0 Timer Disabled. #00 1 Dual 8-bit counters baud/bit mode. #01 10 Dual 8-bit counters PWM mode. #10 11 Single 16-bit counter mode. #11 PINPOL Timer Pin Polarity 7 1 read-write 0 Pin is active high #0 1 Pin is active low #1 PINSEL Timer Pin Select 8 3 read-write PINCFG Timer Pin Configuration 16 2 read-write 0 Timer pin output disabled #00 1 Timer pin open drain or bidirectional output enable #01 10 Timer pin bidirectional output data #10 11 Timer pin output #11 TRGSRC Trigger Source 22 1 read-write 0 External trigger selected #0 1 Internal trigger selected #1 TRGPOL Trigger Polarity 23 1 read-write 0 Trigger active high #0 1 Trigger active low #1 TRGSEL Trigger Select 24 4 read-write TIMCTL2 Timer Control N Register 0x408 32 read-write 0 0xFFFFFFFF TIMOD Timer Mode 0 2 read-write 0 Timer Disabled. #00 1 Dual 8-bit counters baud/bit mode. #01 10 Dual 8-bit counters PWM mode. #10 11 Single 16-bit counter mode. #11 PINPOL Timer Pin Polarity 7 1 read-write 0 Pin is active high #0 1 Pin is active low #1 PINSEL Timer Pin Select 8 3 read-write PINCFG Timer Pin Configuration 16 2 read-write 0 Timer pin output disabled #00 1 Timer pin open drain or bidirectional output enable #01 10 Timer pin bidirectional output data #10 11 Timer pin output #11 TRGSRC Trigger Source 22 1 read-write 0 External trigger selected #0 1 Internal trigger selected #1 TRGPOL Trigger Polarity 23 1 read-write 0 Trigger active high #0 1 Trigger active low #1 TRGSEL Trigger Select 24 4 read-write TIMCTL3 Timer Control N Register 0x40C 32 read-write 0 0xFFFFFFFF TIMOD Timer Mode 0 2 read-write 0 Timer Disabled. #00 1 Dual 8-bit counters baud/bit mode. #01 10 Dual 8-bit counters PWM mode. #10 11 Single 16-bit counter mode. #11 PINPOL Timer Pin Polarity 7 1 read-write 0 Pin is active high #0 1 Pin is active low #1 PINSEL Timer Pin Select 8 3 read-write PINCFG Timer Pin Configuration 16 2 read-write 0 Timer pin output disabled #00 1 Timer pin open drain or bidirectional output enable #01 10 Timer pin bidirectional output data #10 11 Timer pin output #11 TRGSRC Trigger Source 22 1 read-write 0 External trigger selected #0 1 Internal trigger selected #1 TRGPOL Trigger Polarity 23 1 read-write 0 Trigger active high #0 1 Trigger active low #1 TRGSEL Trigger Select 24 4 read-write TIMCFG0 Timer Configuration N Register 0x480 32 read-write 0 0xFFFFFFFF TSTART Timer Start Bit 1 1 read-write 0 Start bit disabled #0 1 Start bit enabled #1 TSTOP Timer Stop Bit 4 2 read-write 0 Stop bit disabled #00 1 Stop bit is enabled on timer compare #01 10 Stop bit is enabled on timer disable #10 11 Stop bit is enabled on timer compare and timer disable #11 TIMENA Timer Enable 8 3 read-write 0 Timer always enabled #000 1 Timer enabled on Timer N-1 enable #001 10 Timer enabled on Trigger high #010 11 Timer enabled on Trigger high and Pin high #011 100 Timer enabled on Pin rising edge #100 101 Timer enabled on Pin rising edge and Trigger high #101 110 Timer enabled on Trigger rising edge #110 111 Timer enabled on Trigger rising or falling edge #111 TIMDIS Timer Disable 12 3 read-write 0 Timer never disabled #000 1 Timer disabled on Timer N-1 disable #001 10 Timer disabled on Timer compare #010 11 Timer disabled on Timer compare and Trigger Low #011 100 Timer disabled on Pin rising or falling edge #100 101 Timer disabled on Pin rising or falling edge provided Trigger is high #101 110 Timer disabled on Trigger falling edge #110 TIMRST Timer Reset 16 3 read-write 0 Timer never reset #000 10 Timer reset on Timer Pin equal to Timer Output #010 11 Timer reset on Timer Trigger equal to Timer Output #011 100 Timer reset on Timer Pin rising edge #100 110 Timer reset on Trigger rising edge #110 111 Timer reset on Trigger rising or falling edge #111 TIMDEC Timer Decrement 20 2 read-write 0 Decrement counter on FlexIO clock, Shift clock equals Timer output. #00 1 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. #01 10 Decrement counter on Pin input (both edges), Shift clock equals Pin input. #10 11 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. #11 TIMOUT Timer Output 24 2 read-write 0 Timer output is logic one when enabled and is not affected by timer reset #00 1 Timer output is logic zero when enabled and is not affected by timer reset #01 10 Timer output is logic one when enabled and on timer reset #10 11 Timer output is logic zero when enabled and on timer reset #11 TIMCFG1 Timer Configuration N Register 0x484 32 read-write 0 0xFFFFFFFF TSTART Timer Start Bit 1 1 read-write 0 Start bit disabled #0 1 Start bit enabled #1 TSTOP Timer Stop Bit 4 2 read-write 0 Stop bit disabled #00 1 Stop bit is enabled on timer compare #01 10 Stop bit is enabled on timer disable #10 11 Stop bit is enabled on timer compare and timer disable #11 TIMENA Timer Enable 8 3 read-write 0 Timer always enabled #000 1 Timer enabled on Timer N-1 enable #001 10 Timer enabled on Trigger high #010 11 Timer enabled on Trigger high and Pin high #011 100 Timer enabled on Pin rising edge #100 101 Timer enabled on Pin rising edge and Trigger high #101 110 Timer enabled on Trigger rising edge #110 111 Timer enabled on Trigger rising or falling edge #111 TIMDIS Timer Disable 12 3 read-write 0 Timer never disabled #000 1 Timer disabled on Timer N-1 disable #001 10 Timer disabled on Timer compare #010 11 Timer disabled on Timer compare and Trigger Low #011 100 Timer disabled on Pin rising or falling edge #100 101 Timer disabled on Pin rising or falling edge provided Trigger is high #101 110 Timer disabled on Trigger falling edge #110 TIMRST Timer Reset 16 3 read-write 0 Timer never reset #000 10 Timer reset on Timer Pin equal to Timer Output #010 11 Timer reset on Timer Trigger equal to Timer Output #011 100 Timer reset on Timer Pin rising edge #100 110 Timer reset on Trigger rising edge #110 111 Timer reset on Trigger rising or falling edge #111 TIMDEC Timer Decrement 20 2 read-write 0 Decrement counter on FlexIO clock, Shift clock equals Timer output. #00 1 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. #01 10 Decrement counter on Pin input (both edges), Shift clock equals Pin input. #10 11 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. #11 TIMOUT Timer Output 24 2 read-write 0 Timer output is logic one when enabled and is not affected by timer reset #00 1 Timer output is logic zero when enabled and is not affected by timer reset #01 10 Timer output is logic one when enabled and on timer reset #10 11 Timer output is logic zero when enabled and on timer reset #11 TIMCFG2 Timer Configuration N Register 0x488 32 read-write 0 0xFFFFFFFF TSTART Timer Start Bit 1 1 read-write 0 Start bit disabled #0 1 Start bit enabled #1 TSTOP Timer Stop Bit 4 2 read-write 0 Stop bit disabled #00 1 Stop bit is enabled on timer compare #01 10 Stop bit is enabled on timer disable #10 11 Stop bit is enabled on timer compare and timer disable #11 TIMENA Timer Enable 8 3 read-write 0 Timer always enabled #000 1 Timer enabled on Timer N-1 enable #001 10 Timer enabled on Trigger high #010 11 Timer enabled on Trigger high and Pin high #011 100 Timer enabled on Pin rising edge #100 101 Timer enabled on Pin rising edge and Trigger high #101 110 Timer enabled on Trigger rising edge #110 111 Timer enabled on Trigger rising or falling edge #111 TIMDIS Timer Disable 12 3 read-write 0 Timer never disabled #000 1 Timer disabled on Timer N-1 disable #001 10 Timer disabled on Timer compare #010 11 Timer disabled on Timer compare and Trigger Low #011 100 Timer disabled on Pin rising or falling edge #100 101 Timer disabled on Pin rising or falling edge provided Trigger is high #101 110 Timer disabled on Trigger falling edge #110 TIMRST Timer Reset 16 3 read-write 0 Timer never reset #000 10 Timer reset on Timer Pin equal to Timer Output #010 11 Timer reset on Timer Trigger equal to Timer Output #011 100 Timer reset on Timer Pin rising edge #100 110 Timer reset on Trigger rising edge #110 111 Timer reset on Trigger rising or falling edge #111 TIMDEC Timer Decrement 20 2 read-write 0 Decrement counter on FlexIO clock, Shift clock equals Timer output. #00 1 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. #01 10 Decrement counter on Pin input (both edges), Shift clock equals Pin input. #10 11 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. #11 TIMOUT Timer Output 24 2 read-write 0 Timer output is logic one when enabled and is not affected by timer reset #00 1 Timer output is logic zero when enabled and is not affected by timer reset #01 10 Timer output is logic one when enabled and on timer reset #10 11 Timer output is logic zero when enabled and on timer reset #11 TIMCFG3 Timer Configuration N Register 0x48C 32 read-write 0 0xFFFFFFFF TSTART Timer Start Bit 1 1 read-write 0 Start bit disabled #0 1 Start bit enabled #1 TSTOP Timer Stop Bit 4 2 read-write 0 Stop bit disabled #00 1 Stop bit is enabled on timer compare #01 10 Stop bit is enabled on timer disable #10 11 Stop bit is enabled on timer compare and timer disable #11 TIMENA Timer Enable 8 3 read-write 0 Timer always enabled #000 1 Timer enabled on Timer N-1 enable #001 10 Timer enabled on Trigger high #010 11 Timer enabled on Trigger high and Pin high #011 100 Timer enabled on Pin rising edge #100 101 Timer enabled on Pin rising edge and Trigger high #101 110 Timer enabled on Trigger rising edge #110 111 Timer enabled on Trigger rising or falling edge #111 TIMDIS Timer Disable 12 3 read-write 0 Timer never disabled #000 1 Timer disabled on Timer N-1 disable #001 10 Timer disabled on Timer compare #010 11 Timer disabled on Timer compare and Trigger Low #011 100 Timer disabled on Pin rising or falling edge #100 101 Timer disabled on Pin rising or falling edge provided Trigger is high #101 110 Timer disabled on Trigger falling edge #110 TIMRST Timer Reset 16 3 read-write 0 Timer never reset #000 10 Timer reset on Timer Pin equal to Timer Output #010 11 Timer reset on Timer Trigger equal to Timer Output #011 100 Timer reset on Timer Pin rising edge #100 110 Timer reset on Trigger rising edge #110 111 Timer reset on Trigger rising or falling edge #111 TIMDEC Timer Decrement 20 2 read-write 0 Decrement counter on FlexIO clock, Shift clock equals Timer output. #00 1 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. #01 10 Decrement counter on Pin input (both edges), Shift clock equals Pin input. #10 11 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. #11 TIMOUT Timer Output 24 2 read-write 0 Timer output is logic one when enabled and is not affected by timer reset #00 1 Timer output is logic zero when enabled and is not affected by timer reset #01 10 Timer output is logic one when enabled and on timer reset #10 11 Timer output is logic zero when enabled and on timer reset #11 TIMCMP0 Timer Compare N Register 0x500 32 read-write 0 0xFFFFFFFF CMP Timer Compare Value 0 16 read-write TIMCMP1 Timer Compare N Register 0x504 32 read-write 0 0xFFFFFFFF CMP Timer Compare Value 0 16 read-write TIMCMP2 Timer Compare N Register 0x508 32 read-write 0 0xFFFFFFFF CMP Timer Compare Value 0 16 read-write TIMCMP3 Timer Compare N Register 0x50C 32 read-write 0 0xFFFFFFFF CMP Timer Compare Value 0 16 read-write TRGMUX TRGMUX 0x40063000 0 0x68 registers TRGMUX_DMAMUX0 TRGMUX DMAMUX0 Register 0 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write LK TRGMUX register lock. 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 TRGMUX_EXTOUT0 TRGMUX EXTOUT0 Register 0x4 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write LK TRGMUX register lock. 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 TRGMUX_EXTOUT1 TRGMUX EXTOUT1 Register 0x8 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write LK TRGMUX register lock. 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 TRGMUX_ADC0 TRGMUX ADC0 Register 0xC 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write LK TRGMUX register lock. 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 TRGMUX_CMP0 TRGMUX CMP0 Register 0x1C 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LK TRGMUX register lock. 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 TRGMUX_FTM0 TRGMUX FTM0 Register 0x28 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write LK TRGMUX register lock. 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 TRGMUX_FTM1 TRGMUX FTM1 Register 0x2C 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write LK TRGMUX register lock. 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 TRGMUX_PDB0 TRGMUX PDB0 Register 0x38 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LK TRGMUX register lock. 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 TRGMUX_FLEXIO TRGMUX FLEXIO Register 0x44 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write LK TRGMUX register lock. 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 TRGMUX_LPIT0 TRGMUX LPIT0 Register 0x48 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write LK TRGMUX register lock. 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 TRGMUX_LPUART0 TRGMUX LPUART0 Register 0x4C 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LK TRGMUX register lock. 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 TRGMUX_LPUART1 TRGMUX LPUART1 Register 0x50 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LK TRGMUX register lock. 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 TRGMUX_LPI2C0 TRGMUX LPI2C0 Register 0x54 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LK TRGMUX register lock. 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 TRGMUX_LPSPI0 TRGMUX LPSPI0 Register 0x5C 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LK TRGMUX register lock. 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 TRGMUX_LPSPI1 TRGMUX LPSPI1 Register 0x60 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LK TRGMUX register lock. 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 TRGMUX_LPTMR0 TRGMUX LPTMR0 Register 0x64 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LK TRGMUX register lock. 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 SCG System Clock Generator SCG_ 0x40064000 0 0x30C registers SCG_CMU_LVD_LVWSCG 21 VERID Version ID Register 0 32 read-only 0x1000000 0xFFFFFFFF VERSION SCG Version Number 0 32 read-only PARAM Parameter Register 0x4 32 read-only 0xF80000FE 0xFFFFFFFF CLKPRES Clock Present 0 8 read-only DIVPRES Divider Present 27 5 read-only CSR Clock Status Register 0x10 32 read-only 0x3000001 0xFFFFFFFF DIVSLOW Slow Clock Divide Ratio 0 4 read-only 0000 Divide-by-1 #0000 0001 Divide-by-2 #0001 0010 Divide-by-3 #0010 0011 Divide-by-4 #0011 0100 Divide-by-5 #0100 0101 Divide-by-6 #0101 0110 Divide-by-7 #0110 0111 Divide-by-8 #0111 DIVBUS Bus Clock Divide Ratio 4 4 read-only 0000 Divide-by-1 #0000 0001 Divide-by-2 #0001 0010 Divide-by-3 #0010 0011 Divide-by-4 #0011 0100 Divide-by-5 #0100 0101 Divide-by-6 #0101 0110 Divide-by-7 #0110 0111 Divide-by-8 #0111 1000 Divide-by-9 #1000 1001 Divide-by-10 #1001 1010 Divide-by-11 #1010 1011 Divide-by-12 #1011 1100 Divide-by-13 #1100 1101 Divide-by-14 #1101 1110 Divide-by-15 #1110 1111 Divide-by-16 #1111 DIVCORE Core Clock Divide Ratio 16 4 read-only 0000 Divide-by-1 #0000 0001 Divide-by-2 #0001 0010 Divide-by-3 #0010 0011 Divide-by-4 #0011 0100 Divide-by-5 #0100 0101 Divide-by-6 #0101 0110 Divide-by-7 #0110 0111 Divide-by-8 #0111 1000 Divide-by-9 #1000 1001 Divide-by-10 #1001 1010 Divide-by-11 #1010 1011 Divide-by-12 #1011 1100 Divide-by-13 #1100 1101 Divide-by-14 #1101 1110 Divide-by-15 #1110 1111 Divide-by-16 #1111 SCS System Clock Source 24 4 read-only 0001 System OSC (SOSC_CLK) #0001 0010 Slow IRC (SIRC_CLK) #0010 0011 Fast IRC (FIRC_CLK) #0011 RCCR Run Clock Control Register 0x14 32 read-write 0x3000001 0xFFFFFFFF DIVSLOW Slow Clock Divide Ratio 0 4 read-write 0000 Divide-by-1 #0000 0001 Divide-by-2 #0001 0010 Divide-by-3 #0010 0011 Divide-by-4 #0011 0100 Divide-by-5 #0100 0101 Divide-by-6 #0101 0110 Divide-by-7 #0110 0111 Divide-by-8 #0111 DIVBUS Bus Clock Divide Ratio 4 4 read-write 0000 Divide-by-1 #0000 0001 Divide-by-2 #0001 0010 Divide-by-3 #0010 0011 Divide-by-4 #0011 0100 Divide-by-5 #0100 0101 Divide-by-6 #0101 0110 Divide-by-7 #0110 0111 Divide-by-8 #0111 1000 Divide-by-9 #1000 1001 Divide-by-10 #1001 1010 Divide-by-11 #1010 1011 Divide-by-12 #1011 1100 Divide-by-13 #1100 1101 Divide-by-14 #1101 1110 Divide-by-15 #1110 1111 Divide-by-16 #1111 DIVCORE Core Clock Divide Ratio 16 4 read-write 0000 Divide-by-1 #0000 0001 Divide-by-2 #0001 0010 Divide-by-3 #0010 0011 Divide-by-4 #0011 0100 Divide-by-5 #0100 0101 Divide-by-6 #0101 0110 Divide-by-7 #0110 0111 Divide-by-8 #0111 1000 Divide-by-9 #1000 1001 Divide-by-10 #1001 1010 Divide-by-11 #1010 1011 Divide-by-12 #1011 1100 Divide-by-13 #1100 1101 Divide-by-14 #1101 1110 Divide-by-15 #1110 1111 Divide-by-16 #1111 SCS System Clock Source 24 4 read-write 0001 System OSC (SOSC_CLK) #0001 0010 Slow IRC (SIRC_CLK) #0010 0011 Fast IRC (FIRC_CLK) #0011 VCCR VLPR Clock Control Register 0x18 32 read-write 0x2000001 0xFFFFFFFF DIVSLOW Slow Clock Divide Ratio 0 4 read-write 0000 Divide-by-1 #0000 0001 Divide-by-2 #0001 0010 Divide-by-3 #0010 0011 Divide-by-4 #0011 0100 Divide-by-5 #0100 0101 Divide-by-6 #0101 0110 Divide-by-7 #0110 0111 Divide-by-8 #0111 DIVBUS Bus Clock Divide Ratio 4 4 read-write 0000 Divide-by-1 #0000 0001 Divide-by-2 #0001 0010 Divide-by-3 #0010 0011 Divide-by-4 #0011 0100 Divide-by-5 #0100 0101 Divide-by-6 #0101 0110 Divide-by-7 #0110 0111 Divide-by-8 #0111 1000 Divide-by-9 #1000 1001 Divide-by-10 #1001 1010 Divide-by-11 #1010 1011 Divide-by-12 #1011 1100 Divide-by-13 #1100 1101 Divide-by-14 #1101 1110 Divide-by-15 #1110 1111 Divide-by-16 #1111 DIVCORE Core Clock Divide Ratio 16 4 read-write 0000 Divide-by-1 #0000 0001 Divide-by-2 #0001 0010 Divide-by-3 #0010 0011 Divide-by-4 #0011 0100 Divide-by-5 #0100 0101 Divide-by-6 #0101 0110 Divide-by-7 #0110 0111 Divide-by-8 #0111 1000 Divide-by-9 #1000 1001 Divide-by-10 #1001 1010 Divide-by-11 #1010 1011 Divide-by-12 #1011 1100 Divide-by-13 #1100 1101 Divide-by-14 #1101 1110 Divide-by-15 #1110 1111 Divide-by-16 #1111 SCS System Clock Source 24 4 read-write 0010 Slow IRC (SIRC_CLK) #0010 CLKOUTCNFG SCG CLKOUT Configuration Register 0x20 32 read-write 0x3000000 0xFFFFFFFF CLKOUTSEL SCG Clkout Select 24 4 read-write 0000 SCG SLOW Clock #0000 0001 System OSC (SOSC_CLK) #0001 0010 Slow IRC (SIRC_CLK) #0010 0011 Fast IRC (FIRC_CLK) #0011 SOSCCSR System OSC Control Status Register 0x100 32 read-write 0 0xFFFFFFFF SOSCEN System OSC Enable 0 1 read-write 0 System OSC is disabled #0 1 System OSC is enabled #1 SOSCCM System OSC Clock Monitor 16 1 read-write 0 System OSC Clock Monitor is disabled #0 1 System OSC Clock Monitor is enabled #1 SOSCCMRE System OSC Clock Monitor Reset Enable 17 1 read-write 0 Clock Monitor generates interrupt when error detected #0 1 Clock Monitor generates reset when error detected #1 LK Lock Register 23 1 read-write 0 This Control Status Register can be written. #0 1 This Control Status Register cannot be written. #1 SOSCVLD System OSC Valid 24 1 read-only 0 System OSC is not enabled or clock is not valid #0 1 System OSC is enabled and output clock is valid #1 SOSCSEL System OSC Selected 25 1 read-only 0 System OSC is not the system clock source #0 1 System OSC is the system clock source #1 SOSCERR System OSC Clock Error 26 1 read-write 0 System OSC Clock Monitor is disabled or has not detected an error #0 1 System OSC Clock Monitor is enabled and detected an error #1 SOSCDIV System OSC Divide Register 0x104 32 read-write 0 0xFFFFFFFF SOSCDIV1 System OSC Clock Divide 1 0 3 read-write 000 Output disabled #000 001 Divide by 1 #001 010 Divide by 2 #010 011 Divide by 4 #011 100 Divide by 8 #100 101 Divide by 16 #101 110 Divide by 32 #110 111 Divide by 64 #111 SOSCDIV2 System OSC Clock Divide 2 8 3 read-write 000 Output disabled #000 001 Divide by 1 #001 010 Divide by 2 #010 011 Divide by 4 #011 100 Divide by 8 #100 101 Divide by 16 #101 110 Divide by 32 #110 111 Divide by 64 #111 SOSCCFG System Oscillator Configuration Register 0x108 32 read-write 0x10 0xFFFFFFFF EREFS External Reference Select 2 1 read-write 0 External reference clock selected #0 1 Internal crystal oscillator of OSC selected. #1 HGO High Gain Oscillator Select 3 1 read-write 0 Configure crystal oscillator for low-gain operation #0 1 Configure crystal oscillator for high-gain operation #1 RANGE System OSC Range Select 4 2 read-write 01 Low frequency range selected for the crystal oscillator #01 10 Medium frequency range selected for the crytstal oscillator #10 11 High frequency range selected for the crystal oscillator #11 SIRCCSR Slow IRC Control Status Register 0x200 32 read-write 0x1000005 0xFFFFFFFF SIRCEN Slow IRC Enable 0 1 read-write 0 Slow IRC is disabled #0 1 Slow IRC is enabled #1 SIRCSTEN Slow IRC Stop Enable 1 1 read-write 0 Slow IRC is disabled in supported Stop modes #0 1 Slow IRC is enabled in supported Stop modes #1 SIRCLPEN Slow IRC Low Power Enable 2 1 read-write 0 Slow IRC is disabled in VLP modes #0 1 Slow IRC is enabled in VLP modes #1 LK Lock Register 23 1 read-write 0 Control Status Register can be written. #0 1 Control Status Register cannot be written. #1 SIRCVLD Slow IRC Valid 24 1 read-only 0 Slow IRC is not enabled or clock is not valid #0 1 Slow IRC is enabled and output clock is valid #1 SIRCSEL Slow IRC Selected 25 1 read-only 0 Slow IRC is not the system clock source #0 1 Slow IRC is the system clock source #1 SIRCDIV Slow IRC Divide Register 0x204 32 read-write 0 0xFFFFFFFF SIRCDIV1 Slow IRC Clock Divide 1 0 3 read-write 000 Output disabled #000 001 Divide by 1 #001 010 Divide by 2 #010 011 Divide by 4 #011 100 Divide by 8 #100 101 Divide by 16 #101 110 Divide by 32 #110 111 Divide by 64 #111 SIRCDIV2 Slow IRC Clock Divide 2 8 3 read-write 000 Output disabled #000 001 Divide by 1 #001 010 Divide by 2 #010 011 Divide by 4 #011 100 Divide by 8 #100 101 Divide by 16 #101 110 Divide by 32 #110 111 Divide by 64 #111 SIRCCFG Slow IRC Configuration Register 0x208 32 read-write 0x1 0xFFFFFFFF RANGE Frequency Range 0 1 read-write 0 Slow IRC low range clock (2 MHz) #0 1 Slow IRC high range clock (8 MHz ) #1 FIRCCSR Fast IRC Control Status Register 0x300 32 read-write 0x3000001 0xFFFFFFFF FIRCEN Fast IRC Enable 0 1 read-write 0 Fast IRC is disabled #0 1 Fast IRC is enabled #1 FIRCREGOFF Fast IRC Regulator Enable 3 1 read-write 0 Fast IRC Regulator is enabled. #0 1 Fast IRC Regulator is disabled. #1 LK Lock Register 23 1 read-write 0 Control Status Register can be written. #0 1 Control Status Register cannot be written. #1 FIRCVLD Fast IRC Valid status 24 1 read-only 0 Fast IRC is not enabled or clock is not valid. #0 1 Fast IRC is enabled and output clock is valid. The clock is valid once there is an output clock from the FIRC analog. #1 FIRCSEL Fast IRC Selected status 25 1 read-only 0 Fast IRC is not the system clock source #0 1 Fast IRC is the system clock source #1 FIRCERR Fast IRC Clock Error 26 1 read-write 0 Error not detected with the Fast IRC trimming. #0 1 Error detected with the Fast IRC trimming. #1 FIRCDIV Fast IRC Divide Register 0x304 32 read-write 0 0xFFFFFFFF FIRCDIV1 Fast IRC Clock Divide 1 0 3 read-write 000 Output disabled #000 001 Divide by 1 #001 010 Divide by 2 #010 011 Divide by 4 #011 100 Divide by 8 #100 101 Divide by 16 #101 110 Divide by 32 #110 111 Divide by 64 #111 FIRCDIV2 Fast IRC Clock Divide 2 8 3 read-write 000 Output disabled #000 001 Divide by 1 #001 010 Divide by 2 #010 011 Divide by 4 #011 100 Divide by 8 #100 101 Divide by 16 #101 110 Divide by 32 #110 111 Divide by 64 #111 FIRCCFG Fast IRC Configuration Register 0x308 32 read-write 0 0xFFFFFFFF RANGE Frequency Range 0 2 read-write 00 Fast IRC is trimmed to 48 MHz #00 01 Fast IRC is trimmed to 52 MHz #01 10 Fast IRC is trimmed to 56 MHz #10 11 Fast IRC is trimmed to 60 MHz #11 PCC PCC 0x40065000 0 0x1D0 registers PCC_FTFC PCC FTFC Register 0x80 32 read-write 0xC0000000 0xFFFFFFFF CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled. The current clock selection and divider options are locked. #1 PR Present 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_DMAMUX PCC DMAMUX Register 0x84 32 read-write 0x80000000 0xFFFFFFFF CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled. The current clock selection and divider options are locked. #1 PR Present 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_FlexCAN0 PCC FlexCAN0 Register 0x90 32 read-write 0x80000000 0xFFFFFFFF CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled. The current clock selection and divider options are locked. #1 PR Present 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_LPSPI0 PCC LPSPI0 Register 0xB0 32 read-write 0x80000000 0xFFFFFFFF PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off. #000 001 Clock option 1 #001 010 Clock option 2 #010 011 Clock option 3 #011 100 Clock option 4 #100 101 Clock option 5 #101 110 Clock option 6 #110 111 Clock option 7 #111 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled. The current clock selection and divider options are locked. #1 PR Present 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_LPSPI1 PCC LPSPI1 Register 0xB4 32 read-write 0x80000000 0xFFFFFFFF PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off. #000 001 Clock option 1 #001 010 Clock option 2 #010 011 Clock option 3 #011 100 Clock option 4 #100 101 Clock option 5 #101 110 Clock option 6 #110 111 Clock option 7 #111 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled. The current clock selection and divider options are locked. #1 PR Present 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_CRC PCC CRC Register 0xC8 32 read-write 0x80000000 0xFFFFFFFF CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled. The current clock selection and divider options are locked. #1 PR Present 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_PDB0 PCC PDB0 Register 0xD8 32 read-write 0x80000000 0xFFFFFFFF CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled. The current clock selection and divider options are locked. #1 PR Present 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_LPIT PCC LPIT Register 0xDC 32 read-write 0x80000000 0xFFFFFFFF PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off. #000 001 Clock option 1 #001 010 Clock option 2 #010 011 Clock option 3 #011 100 Clock option 4 #100 101 Clock option 5 #101 110 Clock option 6 #110 111 Clock option 7 #111 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled. The current clock selection and divider options are locked. #1 PR Present 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_FTM0 PCC FTM0 Register 0xE0 32 read-write 0x80000000 0xFFFFFFFF PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off. An external clock can be enabled for this peripheral. #000 001 Clock option 1 #001 010 Clock option 2 #010 011 Clock option 3 #011 100 Clock option 4 #100 101 Clock option 5 #101 110 Clock option 6 #110 111 Clock option 7 #111 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled. The current clock selection and divider options are locked. #1 PR Present 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_FTM1 PCC FTM1 Register 0xE4 32 read-write 0x80000000 0xFFFFFFFF PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off. An external clock can be enabled for this peripheral. #000 001 Clock option 1 #001 010 Clock option 2 #010 011 Clock option 3 #011 100 Clock option 4 #100 101 Clock option 5 #101 110 Clock option 6 #110 111 Clock option 7 #111 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled. The current clock selection and divider options are locked. #1 PR Present 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_ADC0 PCC ADC0 Register 0xEC 32 read-write 0x80000000 0xFFFFFFFF PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off. #000 001 Clock option 1 #001 010 Clock option 2 #010 011 Clock option 3 #011 100 Clock option 4 #100 101 Clock option 5 #101 110 Clock option 6 #110 111 Clock option 7 #111 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled. The current clock selection and divider options are locked. #1 PR Present 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_RTC PCC RTC Register 0xF4 32 read-write 0x80000000 0xFFFFFFFF CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled. The current clock selection and divider options are locked. #1 PR Present 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_CMU0 PCC CMU0 Register 0xF8 32 read-write 0x80000000 0xFFFFFFFF CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled. The current clock selection and divider options are locked. #1 PR Present 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_CMU1 PCC CMU1 Register 0xFC 32 read-write 0x80000000 0xFFFFFFFF CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled. The current clock selection and divider options are locked. #1 PR Present 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_LPTMR0 PCC LPTMR0 Register 0x100 32 read-write 0x80000000 0xFFFFFFFF PCD Peripheral Clock Divider Select 0 4 read-write 0000 Divide by 1. #0000 0001 Divide by 2. #0001 0010 Divide by 3. #0010 0011 Divide by 4. #0011 0100 Divide by 5. #0100 0101 Divide by 6. #0101 0110 Divide by 7. #0110 0111 Divide by 8. #0111 FRAC Peripheral Clock Divider Fraction 4 1 read-write 0 Fractional value is 0. #0 1 Fractional value is 1. #1 PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off. #000 001 Clock option 1 #001 010 Clock option 2 #010 011 Clock option 3 #011 100 Clock option 4 #100 101 Clock option 5 #101 110 Clock option 6 #110 111 Clock option 7 #111 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled. The current clock selection and divider options are locked. #1 PR Present 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_PORTA PCC PORTA Register 0x124 32 read-write 0x80000000 0xFFFFFFFF CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled. The current clock selection and divider options are locked. #1 PR Present 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_PORTB PCC PORTB Register 0x128 32 read-write 0x80000000 0xFFFFFFFF CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled. The current clock selection and divider options are locked. #1 PR Present 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_PORTC PCC PORTC Register 0x12C 32 read-write 0x80000000 0xFFFFFFFF CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled. The current clock selection and divider options are locked. #1 PR Present 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_PORTD PCC PORTD Register 0x130 32 read-write 0x80000000 0xFFFFFFFF CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled. The current clock selection and divider options are locked. #1 PR Present 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_PORTE PCC PORTE Register 0x134 32 read-write 0x80000000 0xFFFFFFFF CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled. The current clock selection and divider options are locked. #1 PR Present 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_FlexIO PCC FlexIO Register 0x168 32 read-write 0x80000000 0xFFFFFFFF PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off. #000 001 Clock option 1 #001 010 Clock option 2 #010 011 Clock option 3 #011 100 Clock option 4 #100 101 Clock option 5 #101 110 Clock option 6 #110 111 Clock option 7 #111 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled. The current clock selection and divider options are locked. #1 PR Present 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_LPI2C0 PCC LPI2C0 Register 0x198 32 read-write 0x80000000 0xFFFFFFFF PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off. #000 001 Clock option 1 #001 010 Clock option 2 #010 011 Clock option 3 #011 100 Clock option 4 #100 101 Clock option 5 #101 110 Clock option 6 #110 111 Clock option 7 #111 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled. The current clock selection and divider options are locked. #1 PR Present 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_LPUART0 PCC LPUART0 Register 0x1A8 32 read-write 0x80000000 0xFFFFFFFF PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off. #000 001 Clock option 1 #001 010 Clock option 2 #010 011 Clock option 3 #011 100 Clock option 4 #100 101 Clock option 5 #101 110 Clock option 6 #110 111 Clock option 7 #111 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled. The current clock selection and divider options are locked. #1 PR Present 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_LPUART1 PCC LPUART1 Register 0x1AC 32 read-write 0x80000000 0xFFFFFFFF PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off. #000 001 Clock option 1 #001 010 Clock option 2 #010 011 Clock option 3 #011 100 Clock option 4 #100 101 Clock option 5 #101 110 Clock option 6 #110 111 Clock option 7 #111 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled. The current clock selection and divider options are locked. #1 PR Present 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_CMP0 PCC CMP0 Register 0x1CC 32 read-write 0x80000000 0xFFFFFFFF CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled. The current clock selection and divider options are locked. #1 PR Present 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 LPI2C0 The LPI2C Memory Map/Register Definition can be found here. LPI2C0_ 0x40066000 0 0x174 registers LPI2C0_Master_Slave 24 VERID Version ID Register 0 32 read-only 0x1000003 0xFFFFFFFF FEATURE Feature Specification Number 0 16 read-only 0000000000000010 Master only with standard feature set. #10 0000000000000011 Master and slave with standard feature set. #11 MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM Parameter Register 0x4 32 read-only 0x202 0xFFFFFFFF MTXFIFO Master Transmit FIFO Size 0 4 read-only MRXFIFO Master Receive FIFO Size 8 4 read-only MCR Master Control Register 0x10 32 read-write 0 0xFFFFFFFF MEN Master Enable 0 1 read-write 0 Master logic is disabled. #0 1 Master logic is enabled. #1 RST Software Reset 1 1 read-write 0 Master logic is not reset. #0 1 Master logic is reset. #1 DOZEN Doze mode enable 2 1 read-write 0 Master is enabled in Doze mode. #0 1 Master is disabled in Doze mode. #1 DBGEN Debug Enable 3 1 read-write 0 Master is disabled in debug mode. #0 1 Master is enabled in debug mode. #1 RTF Reset Transmit FIFO 8 1 write-only 0 No effect. #0 1 Transmit FIFO is reset. #1 RRF Reset Receive FIFO 9 1 write-only 0 No effect. #0 1 Receive FIFO is reset. #1 MSR Master Status Register 0x14 32 read-write 0x1 0xFFFFFFFF TDF Transmit Data Flag 0 1 read-only 0 Transmit data not requested. #0 1 Transmit data is requested. #1 RDF Receive Data Flag 1 1 read-only 0 Receive Data is not ready. #0 1 Receive data is ready. #1 EPF End Packet Flag 8 1 read-write 0 Master has not generated a STOP or Repeated START condition. #0 1 Master has generated a STOP or Repeated START condition. #1 SDF STOP Detect Flag 9 1 read-write 0 Master has not generated a STOP condition. #0 1 Master has generated a STOP condition. #1 NDF NACK Detect Flag 10 1 read-write 0 Unexpected NACK not detected. #0 1 Unexpected NACK was detected. #1 ALF Arbitration Lost Flag 11 1 read-write 0 Master has not lost arbitration. #0 1 Master has lost arbitration. #1 FEF FIFO Error Flag 12 1 read-write 0 No error. #0 1 Master sending or receiving data without START condition. #1 PLTF Pin Low Timeout Flag 13 1 read-write 0 Pin low timeout has not occurred or is disabled. #0 1 Pin low timeout has occurred. #1 DMF Data Match Flag 14 1 read-write 0 Have not received matching data. #0 1 Have received matching data. #1 MBF Master Busy Flag 24 1 read-only 0 I2C Master is idle. #0 1 I2C Master is busy. #1 BBF Bus Busy Flag 25 1 read-only 0 I2C Bus is idle. #0 1 I2C Bus is busy. #1 MIER Master Interrupt Enable Register 0x18 32 read-write 0 0xFFFFFFFF TDIE Transmit Data Interrupt Enable 0 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled #1 RDIE Receive Data Interrupt Enable 1 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 EPIE End Packet Interrupt Enable 8 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 SDIE STOP Detect Interrupt Enable 9 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 NDIE NACK Detect Interrupt Enable 10 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 ALIE Arbitration Lost Interrupt Enable 11 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 FEIE FIFO Error Interrupt Enable 12 1 read-write 0 Interrupt enabled. #0 1 Interrupt disabled. #1 PLTIE Pin Low Timeout Interrupt Enable 13 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 DMIE Data Match Interrupt Enable 14 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 MDER Master DMA Enable Register 0x1C 32 read-write 0 0xFFFFFFFF TDDE Transmit Data DMA Enable 0 1 read-write 0 DMA request disabled. #0 1 DMA request enabled #1 RDDE Receive Data DMA Enable 1 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 MCFGR0 Master Configuration Register 0 0x20 32 read-write 0 0xFFFFFFFF HREN Host Request Enable 0 1 read-write 0 Host request input is disabled. #0 1 Host request input is enabled. #1 HRPOL Host Request Polarity 1 1 read-write 0 Active low. #0 1 Active high. #1 HRSEL Host Request Select 2 1 read-write 0 Host request input is pin HREQ. #0 1 Host request input is input trigger. #1 CIRFIFO Circular FIFO Enable 8 1 read-write 0 Circular FIFO is disabled. #0 1 Circular FIFO is enabled. #1 RDMO Receive Data Match Only 9 1 read-write 0 Received data is stored in the receive FIFO as normal. #0 1 Received data is discarded unless the RMF is set. #1 MCFGR1 Master Configuration Register 1 0x24 32 read-write 0 0xFFFFFFFF PRESCALE Prescaler 0 3 read-write 000 Divide by 1. #000 001 Divide by 2. #001 010 Divide by 4. #010 011 Divide by 8. #011 100 Divide by 16. #100 101 Divide by 32. #101 110 Divide by 64. #110 111 Divide by 128. #111 AUTOSTOP Automatic STOP Generation 8 1 read-write 0 No effect. #0 1 STOP condition is automatically generated whenever the transmit FIFO is empty and LPI2C master is busy. #1 IGNACK IGNACK 9 1 read-write 0 LPI2C Master will receive ACK and NACK normally. #0 1 LPI2C Master will treat a received NACK as if it was an ACK. #1 TIMECFG Timeout Configuration 10 1 read-write 0 Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout. #0 1 Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout. #1 MATCFG Match Configuration 16 3 read-write 000 Match disabled. #000 010 Match enabled (1st data word equals MATCH0 OR MATCH1). #010 011 Match enabled (any data word equals MATCH0 OR MATCH1). #011 100 Match enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1). #100 101 Match enabled (any data word equals MATCH0 AND next data word equals MATCH1). #101 110 Match enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1). #110 111 Match enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1). #111 PINCFG Pin Configuration 24 3 read-write 000 LPI2C configured for 2-pin open drain mode. #000 001 LPI2C configured for 2-pin output only mode (ultra-fast mode). #001 010 LPI2C configured for 2-pin push-pull mode. #010 011 LPI2C configured for 4-pin push-pull mode. #011 100 LPI2C configured for 2-pin open drain mode with separate LPI2C slave. #100 101 LPI2C configured for 2-pin output only mode (ultra-fast mode) with separate LPI2C slave. #101 110 LPI2C configured for 2-pin push-pull mode with separate LPI2C slave. #110 111 LPI2C configured for 4-pin push-pull mode (inverted outputs). #111 MCFGR2 Master Configuration Register 2 0x28 32 read-write 0 0xFFFFFFFF BUSIDLE Bus Idle Timeout 0 12 read-write FILTSCL Glitch Filter SCL 16 4 read-write FILTSDA Glitch Filter SDA 24 4 read-write MCFGR3 Master Configuration Register 3 0x2C 32 read-write 0 0xFFFFFFFF PINLOW Pin Low Timeout 8 12 read-write MDMR Master Data Match Register 0x40 32 read-write 0 0xFFFFFFFF MATCH0 Match 0 Value 0 8 read-write MATCH1 Match 1 Value 16 8 read-write MCCR0 Master Clock Configuration Register 0 0x48 32 read-write 0 0xFFFFFFFF CLKLO Clock Low Period 0 6 read-write CLKHI Clock High Period 8 6 read-write SETHOLD Setup Hold Delay 16 6 read-write DATAVD Data Valid Delay 24 6 read-write MCCR1 Master Clock Configuration Register 1 0x50 32 read-write 0 0xFFFFFFFF CLKLO Clock Low Period 0 6 read-write CLKHI Clock High Period 8 6 read-write SETHOLD Setup Hold Delay 16 6 read-write DATAVD Data Valid Delay 24 6 read-write MFCR Master FIFO Control Register 0x58 32 read-write 0 0xFFFFFFFF TXWATER Transmit FIFO Watermark 0 2 read-write RXWATER Receive FIFO Watermark 16 2 read-write MFSR Master FIFO Status Register 0x5C 32 read-only 0 0xFFFFFFFF TXCOUNT Transmit FIFO Count 0 3 read-only RXCOUNT Receive FIFO Count 16 3 read-only MTDR Master Transmit Data Register 0x60 32 read-write 0 0xFFFFFFFF DATA Transmit Data 0 8 write-only CMD Command Data 8 3 write-only 000 Transmit DATA[7:0]. #000 001 Receive (DATA[7:0] + 1) bytes. #001 010 Generate STOP condition. #010 011 Receive and discard (DATA[7:0] + 1) bytes. #011 100 Generate (repeated) START and transmit address in DATA[7:0]. #100 101 Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. #101 110 Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. #110 111 Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned. #111 MRDR Master Receive Data Register 0x70 32 read-only 0x4000 0xFFFFFFFF DATA Receive Data 0 8 read-only RXEMPTY RX Empty 14 1 read-only 0 Receive FIFO is not empty. #0 1 Receive FIFO is empty. #1 SCR Slave Control Register 0x110 32 read-write 0 0xFFFFFFFF SEN Slave Enable 0 1 read-write 0 Slave mode is disabled. #0 1 Slave mode is enabled. #1 RST Software Reset 1 1 read-write 0 Slave logic is not reset. #0 1 Slave logic is reset. #1 FILTEN Filter Enable 4 1 read-write 0 Disable digital filter and output delay counter for slave mode. #0 1 Enable digital filter and output delay counter for slave mode. #1 FILTDZ Filter Doze Enable 5 1 read-write 0 Filter remains enabled in Doze mode. #0 1 Filter is disabled in Doze mode. #1 SSR Slave Status Register 0x114 32 read-write 0 0xFFFFFFFF TDF Transmit Data Flag 0 1 read-only 0 Transmit data not requested. #0 1 Transmit data is requested. #1 RDF Receive Data Flag 1 1 read-only 0 Receive Data is not ready. #0 1 Receive data is ready. #1 AVF Address Valid Flag 2 1 read-only 0 Address Status Register is not valid. #0 1 Address Status Register is valid. #1 TAF Transmit ACK Flag 3 1 read-only 0 Transmit ACK/NACK is not required. #0 1 Transmit ACK/NACK is required. #1 RSF Repeated Start Flag 8 1 read-write 0 Slave has not detected a Repeated START condition. #0 1 Slave has detected a Repeated START condition. #1 SDF STOP Detect Flag 9 1 read-write 0 Slave has not detected a STOP condition. #0 1 Slave has detected a STOP condition. #1 BEF Bit Error Flag 10 1 read-write 0 Slave has not detected a bit error. #0 1 Slave has detected a bit error. #1 FEF FIFO Error Flag 11 1 read-write 0 FIFO underflow or overflow not detected. #0 1 FIFO underflow or overflow detected. #1 AM0F Address Match 0 Flag 12 1 read-only 0 Have not received ADDR0 matching address. #0 1 Have received ADDR0 matching address. #1 AM1F Address Match 1 Flag 13 1 read-only 0 Have not received ADDR1 or ADDR0/ADDR1 range matching address. #0 1 Have received ADDR1 or ADDR0/ADDR1 range matching address. #1 GCF General Call Flag 14 1 read-only 0 Slave has not detected the General Call Address or General Call Address disabled. #0 1 Slave has detected the General Call Address. #1 SARF SMBus Alert Response Flag 15 1 read-only 0 SMBus Alert Response disabled or not detected. #0 1 SMBus Alert Response enabled and detected. #1 SBF Slave Busy Flag 24 1 read-only 0 I2C Slave is idle. #0 1 I2C Slave is busy. #1 BBF Bus Busy Flag 25 1 read-only 0 I2C Bus is idle. #0 1 I2C Bus is busy. #1 SIER Slave Interrupt Enable Register 0x118 32 read-write 0 0xFFFFFFFF TDIE Transmit Data Interrupt Enable 0 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled #1 RDIE Receive Data Interrupt Enable 1 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 AVIE Address Valid Interrupt Enable 2 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 TAIE Transmit ACK Interrupt Enable 3 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 RSIE Repeated Start Interrupt Enable 8 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 SDIE STOP Detect Interrupt Enable 9 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 BEIE Bit Error Interrupt Enable 10 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 FEIE FIFO Error Interrupt Enable 11 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 AM0IE Address Match 0 Interrupt Enable 12 1 read-write 0 Interrupt enabled. #0 1 Interrupt disabled. #1 AM1F Address Match 1 Interrupt Enable 13 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 GCIE General Call Interrupt Enable 14 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 SARIE SMBus Alert Response Interrupt Enable 15 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 SDER Slave DMA Enable Register 0x11C 32 read-write 0 0xFFFFFFFF TDDE Transmit Data DMA Enable 0 1 read-write 0 DMA request disabled. #0 1 DMA request enabled #1 RDDE Receive Data DMA Enable 1 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 AVDE Address Valid DMA Enable 2 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 SCFGR1 Slave Configuration Register 1 0x124 32 read-write 0 0xFFFFFFFF ADRSTALL Address SCL Stall 0 1 read-write 0 Clock stretching disabled. #0 1 Clock stretching enabled. #1 RXSTALL RX SCL Stall 1 1 read-write 0 Clock stretching disabled. #0 1 Clock stretching enabled. #1 TXDSTALL TX Data SCL Stall 2 1 read-write 0 Clock stretching disabled. #0 1 Clock stretching enabled. #1 ACKSTALL ACK SCL Stall 3 1 read-write 0 Clock stretching disabled. #0 1 Clock stretching enabled. #1 GCEN General Call Enable 8 1 read-write 0 General Call address is disabled. #0 1 General call address is enabled. #1 SAEN SMBus Alert Enable 9 1 read-write 0 Disables match on SMBus Alert. #0 1 Enables match on SMBus Alert. #1 TXCFG Transmit Flag Configuration 10 1 read-write 0 Transmit Data Flag will only assert during a slave-transmit transfer when the transmit data register is empty. #0 1 Transmit Data Flag will assert whenever the transmit data register is empty. #1 RXCFG Receive Data Configuration 11 1 read-write 0 Reading the receive data register will return receive data and clear the receive data flag. #0 1 Reading the receive data register when the address valid flag is set will return the address status register and clear the address valid flag. Reading the receive data register when the address valid flag is clear will return receive data and clear the receive data flag. #1 IGNACK Ignore NACK 12 1 read-write 0 Slave will end transfer when NACK detected. #0 1 Slave will not end transfer when NACK detected. #1 HSMEN High Speed Mode Enable 13 1 read-write 0 Disables detection of Hs-mode master code. #0 1 Enables detection of Hs-mode master code. #1 ADDRCFG Address Configuration 16 3 read-write 000 Address match 0 (7-bit). #000 001 Address match 0 (10-bit). #001 010 Address match 0 (7-bit) or Address match 1 (7-bit). #010 011 Address match 0 (10-bit) or Address match 1 (10-bit). #011 100 Address match 0 (7-bit) or Address match 1 (10-bit). #100 101 Address match 0 (10-bit) or Address match 1 (7-bit). #101 110 From Address match 0 (7-bit) to Address match 1 (7-bit). #110 111 From Address match 0 (10-bit) to Address match 1 (10-bit). #111 SCFGR2 Slave Configuration Register 2 0x128 32 read-write 0 0xFFFFFFFF CLKHOLD Clock Hold Time 0 4 read-write DATAVD Data Valid Delay 8 6 read-write FILTSCL Glitch Filter SCL 16 4 read-write FILTSDA Glitch Filter SDA 24 4 read-write SAMR Slave Address Match Register 0x140 32 read-write 0 0xFFFFFFFF ADDR0 Address 0 Value 1 10 read-write ADDR1 Address 1 Value 17 10 read-write SASR Slave Address Status Register 0x150 32 read-only 0x4000 0xFFFFFFFF RADDR Received Address 0 11 read-only ANV Address Not Valid 14 1 read-only 0 RADDR is valid. #0 1 RADDR is not valid. #1 STAR Slave Transmit ACK Register 0x154 32 read-write 0 0xFFFFFFFF TXNACK Transmit NACK 0 1 read-write 0 Transmit ACK for received word. #0 1 Transmit NACK for received word. #1 STDR Slave Transmit Data Register 0x160 32 read-write 0 0xFFFFFFFF DATA Transmit Data 0 8 write-only SRDR Slave Receive Data Register 0x170 32 read-only 0x4000 0xFFFFFFFF DATA Receive Data 0 8 read-only RXEMPTY RX Empty 14 1 read-only 0 The Receive Data Register is not empty. #0 1 The Receive Data Register is empty. #1 SOF Start Of Frame 15 1 read-only 0 Indicates this is not the first data word since a (repeated) START or STOP condition. #0 1 Indicates this is the first data word since a (repeated) START or STOP condition. #1 LPUART0 Universal Asynchronous Receiver/Transmitter LPUART LPUART0_ 0x4006A000 0 0x30 registers LPUART0_RxTx 31 VERID Version ID Register 0 32 read-only 0x4010003 0xFFFFFFFF FEATURE Feature Identification Number 0 16 read-only 0000000000000001 Standard feature set. #1 0000000000000011 Standard feature set with MODEM/IrDA support. #11 MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM Parameter Register 0x4 32 read-only 0x202 0xFFFFFFFF TXFIFO Transmit FIFO Size 0 8 read-only RXFIFO Receive FIFO Size 8 8 read-only GLOBAL LPUART Global Register 0x8 32 read-write 0 0xFFFFFFFF RST Software Reset 1 1 read-write 0 Module is not reset. #0 1 Module is reset. #1 PINCFG LPUART Pin Configuration Register 0xC 32 read-write 0 0xFFFFFFFF TRGSEL Trigger Select 0 2 read-write 00 Input trigger is disabled. #00 01 Input trigger is used instead of RXD pin input. #01 10 Input trigger is used instead of CTS_B pin input. #10 11 Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger. #11 BAUD LPUART Baud Rate Register 0x10 32 read-write 0xF000004 0xFFFFFFFF SBR Baud Rate Modulo Divisor. 0 13 read-write SBNS Stop Bit Number Select 13 1 read-write 0 One stop bit. #0 1 Two stop bits. #1 RXEDGIE RX Input Active Edge Interrupt Enable 14 1 read-write 0 Hardware interrupts from LPUART_STAT[RXEDGIF] disabled. #0 1 Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1. #1 LBKDIE LIN Break Detect Interrupt Enable 15 1 read-write 0 Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling). #0 1 Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1. #1 RESYNCDIS Resynchronization Disable 16 1 read-write 0 Resynchronization during received data word is supported #0 1 Resynchronization during received data word is disabled #1 BOTHEDGE Both Edge Sampling 17 1 read-write 0 Receiver samples input data using the rising edge of the baud rate clock. #0 1 Receiver samples input data using the rising and falling edge of the baud rate clock. #1 MATCFG Match Configuration 18 2 read-write 00 Address Match Wakeup #00 01 Idle Match Wakeup #01 10 Match On and Match Off #10 RIDMAE Receiver Idle DMA Enable 20 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 RDMAE Receiver Full DMA Enable 21 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 TDMAE Transmitter DMA Enable 23 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 OSR Oversampling Ratio 24 5 read-write 00000 Writing 0 to this field will result in an oversampling ratio of 16 #00000 00011 Oversampling ratio of 4, requires BOTHEDGE to be set. #00011 00100 Oversampling ratio of 5, requires BOTHEDGE to be set. #00100 00101 Oversampling ratio of 6, requires BOTHEDGE to be set. #00101 00110 Oversampling ratio of 7, requires BOTHEDGE to be set. #00110 00111 Oversampling ratio of 8. #00111 01000 Oversampling ratio of 9. #01000 01001 Oversampling ratio of 10. #01001 01010 Oversampling ratio of 11. #01010 01011 Oversampling ratio of 12. #01011 01100 Oversampling ratio of 13. #01100 01101 Oversampling ratio of 14. #01101 01110 Oversampling ratio of 15. #01110 01111 Oversampling ratio of 16. #01111 10000 Oversampling ratio of 17. #10000 10001 Oversampling ratio of 18. #10001 10010 Oversampling ratio of 19. #10010 10011 Oversampling ratio of 20. #10011 10100 Oversampling ratio of 21. #10100 10101 Oversampling ratio of 22. #10101 10110 Oversampling ratio of 23. #10110 10111 Oversampling ratio of 24. #10111 11000 Oversampling ratio of 25. #11000 11001 Oversampling ratio of 26. #11001 11010 Oversampling ratio of 27. #11010 11011 Oversampling ratio of 28. #11011 11100 Oversampling ratio of 29. #11100 11101 Oversampling ratio of 30. #11101 11110 Oversampling ratio of 31. #11110 11111 Oversampling ratio of 32. #11111 M10 10-bit Mode select 29 1 read-write 0 Receiver and transmitter use 7-bit to 9-bit data characters. #0 1 Receiver and transmitter use 10-bit data characters. #1 MAEN2 Match Address Mode Enable 2 30 1 read-write 0 Normal operation. #0 1 Enables automatic address matching or data matching mode for MATCH[MA2]. #1 MAEN1 Match Address Mode Enable 1 31 1 read-write 0 Normal operation. #0 1 Enables automatic address matching or data matching mode for MATCH[MA1]. #1 STAT LPUART Status Register 0x14 32 read-write 0xC00000 0xFFFFFFFF MA2F Match 2 Flag 14 1 read-write 0 Received data is not equal to MA2 #0 1 Received data is equal to MA2 #1 MA1F Match 1 Flag 15 1 read-write 0 Received data is not equal to MA1 #0 1 Received data is equal to MA1 #1 PF Parity Error Flag 16 1 read-write 0 No parity error. #0 1 Parity error. #1 FE Framing Error Flag 17 1 read-write 0 No framing error detected. This does not guarantee the framing is correct. #0 1 Framing error. #1 NF Noise Flag 18 1 read-write 0 No noise detected. #0 1 Noise detected in the received character in LPUART_DATA. #1 OR Receiver Overrun Flag 19 1 read-write 0 No overrun. #0 1 Receive overrun (new LPUART data lost). #1 IDLE Idle Line Flag 20 1 read-write 0 No idle line detected. #0 1 Idle line was detected. #1 RDRF Receive Data Register Full Flag 21 1 read-only 0 Receive data buffer empty. #0 1 Receive data buffer full. #1 TC Transmission Complete Flag 22 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 23 1 read-only 0 Transmit data buffer full. #0 1 Transmit data buffer empty. #1 RAF Receiver Active Flag 24 1 read-only 0 LPUART receiver idle waiting for a start bit. #0 1 LPUART receiver active (RXD input not idle). #1 LBKDE LIN Break Detection Enable 25 1 read-write 0 LIN break detect is disabled, normal break character can be detected. #0 1 LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1). #1 BRK13 Break Character Generation Length 26 1 read-write 0 Break character is transmitted with length of 9 to 13 bit times. #0 1 Break character is transmitted with length of 12 to 15 bit times. #1 RWUID Receive Wake Up Idle Detect 27 1 read-write 0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not set when an address does not match. #0 1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does set when an address does not match. #1 RXINV Receive Data Inversion 28 1 read-write 0 Receive data not inverted. #0 1 Receive data inverted. #1 MSBF MSB First 29 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. #1 RXEDGIF RXD Pin Active Edge Interrupt Flag 30 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 LBKDIF LIN Break Detect Interrupt Flag 31 1 read-write 0 No LIN break character has been detected. #0 1 LIN break character has been detected. #1 CTRL LPUART Control Register 0x18 32 read-write 0 0xFFFFFFFF PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 PE Parity Enable 1 1 read-write 0 No hardware parity generation or checking. #0 1 Parity enabled. #1 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Configures RWU for idle-line wakeup. #0 1 Configures RWU with address-mark wakeup. #1 M 9-Bit or 8-Bit Mode Select 4 1 read-write 0 Receiver and transmitter use 8-bit data characters. #0 1 Receiver and transmitter use 9-bit data characters. #1 RSRC Receiver Source Select 5 1 read-write 0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin. #0 1 Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input. #1 DOZEEN Doze Enable 6 1 read-write 0 LPUART is enabled in Doze mode. #0 1 LPUART is disabled in Doze mode. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation - RXD and TXD use separate pins. #0 1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). #1 IDLECFG Idle Configuration 8 3 read-write 000 1 idle character #000 001 2 idle characters #001 010 4 idle characters #010 011 8 idle characters #011 100 16 idle characters #100 101 32 idle characters #101 110 64 idle characters #110 111 128 idle characters #111 M7 7-Bit Mode Select 11 1 read-write 0 Receiver and transmitter use 8-bit to 10-bit data characters. #0 1 Receiver and transmitter use 7-bit data characters. #1 MA2IE Match 2 Interrupt Enable 14 1 read-write 0 MA2F interrupt disabled #0 1 MA2F interrupt enabled #1 MA1IE Match 1 Interrupt Enable 15 1 read-write 0 MA1F interrupt disabled #0 1 MA1F interrupt enabled #1 SBK Send Break 16 1 read-write 0 Normal transmitter operation. #0 1 Queue break character(s) to be sent. #1 RWU Receiver Wakeup Control 17 1 read-write 0 Normal receiver operation. #0 1 LPUART receiver in standby waiting for wakeup condition. #1 RE Receiver Enable 18 1 read-write 0 Receiver disabled. #0 1 Receiver enabled. #1 TE Transmitter Enable 19 1 read-write 0 Transmitter disabled. #0 1 Transmitter enabled. #1 ILIE Idle Line Interrupt Enable 20 1 read-write 0 Hardware interrupts from IDLE disabled; use polling. #0 1 Hardware interrupt requested when IDLE flag is 1. #1 RIE Receiver Interrupt Enable 21 1 read-write 0 Hardware interrupts from RDRF disabled; use polling. #0 1 Hardware interrupt requested when RDRF flag is 1. #1 TCIE Transmission Complete Interrupt Enable for 22 1 read-write 0 Hardware interrupts from TC disabled; use polling. #0 1 Hardware interrupt requested when TC flag is 1. #1 TIE Transmit Interrupt Enable 23 1 read-write 0 Hardware interrupts from TDRE disabled; use polling. #0 1 Hardware interrupt requested when TDRE flag is 1. #1 PEIE Parity Error Interrupt Enable 24 1 read-write 0 PF interrupts disabled; use polling). #0 1 Hardware interrupt requested when PF is set. #1 FEIE Framing Error Interrupt Enable 25 1 read-write 0 FE interrupts disabled; use polling. #0 1 Hardware interrupt requested when FE is set. #1 NEIE Noise Error Interrupt Enable 26 1 read-write 0 NF interrupts disabled; use polling. #0 1 Hardware interrupt requested when NF is set. #1 ORIE Overrun Interrupt Enable 27 1 read-write 0 OR interrupts disabled; use polling. #0 1 Hardware interrupt requested when OR is set. #1 TXINV Transmit Data Inversion 28 1 read-write 0 Transmit data not inverted. #0 1 Transmit data inverted. #1 TXDIR TXD Pin Direction in Single-Wire Mode 29 1 read-write 0 TXD pin is an input in single-wire mode. #0 1 TXD pin is an output in single-wire mode. #1 R9T8 Receive Bit 9 / Transmit Bit 8 30 1 read-write R8T9 Receive Bit 8 / Transmit Bit 9 31 1 read-write DATA LPUART Data Register 0x1C 32 read-write 0x1000 0xFFFFFFFF R0T0 R0T0 0 1 read-write R1T1 R1T1 1 1 read-write R2T2 R2T2 2 1 read-write R3T3 R3T3 3 1 read-write R4T4 R4T4 4 1 read-write R5T5 R5T5 5 1 read-write R6T6 R6T6 6 1 read-write R7T7 R7T7 7 1 read-write R8T8 R8T8 8 1 read-write R9T9 R9T9 9 1 read-write IDLINE Idle Line 11 1 read-only 0 Receiver was not idle before receiving this character. #0 1 Receiver was idle before receiving this character. #1 RXEMPT Receive Buffer Empty 12 1 read-only 0 Receive buffer contains valid data. #0 1 Receive buffer is empty, data returned on read is not valid. #1 FRETSC Frame Error / Transmit Special Character 13 1 read-write 0 The dataword was received without a frame error on read, or transmit a normal character on write. #0 1 The dataword was received with a frame error, or transmit an idle or break character on transmit. #1 PARITYE PARITYE 14 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 NOISY NOISY 15 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 MATCH LPUART Match Address Register 0x20 32 read-write 0 0xFFFFFFFF MA1 Match Address 1 0 10 read-write MA2 Match Address 2 16 10 read-write MODIR LPUART Modem IrDA Register 0x24 32 read-write 0 0xFFFFFFFF TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 TXCTSC Transmit CTS Configuration 4 1 read-write 0 CTS input is sampled at the start of each character. #0 1 CTS input is sampled when the transmitter is idle. #1 TXCTSSRC Transmit CTS Source 5 1 read-write 0 CTS input is the CTS_B pin. #0 1 CTS input is the inverted Receiver Match result. #1 RTSWATER Receive RTS Configuration 8 2 read-write TNP Transmitter narrow pulse 16 2 read-write 00 1/OSR. #00 01 2/OSR. #01 10 3/OSR. #10 11 4/OSR. #11 IREN Infrared enable 18 1 read-write 0 IR disabled. #0 1 IR enabled. #1 FIFO LPUART FIFO Register 0x28 32 read-write 0xC00011 0xFFFFFFFF RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer depth = 1 dataword. #000 001 Receive FIFO/Buffer depth = 4 datawords. #001 010 Receive FIFO/Buffer depth = 8 datawords. #010 011 Receive FIFO/Buffer depth = 16 datawords. #011 100 Receive FIFO/Buffer depth = 32 datawords. #100 101 Receive FIFO/Buffer depth = 64 datawords. #101 110 Receive FIFO/Buffer depth = 128 datawords. #110 111 Receive FIFO/Buffer depth = 256 datawords. #111 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer depth = 1 dataword. #000 001 Transmit FIFO/Buffer depth = 4 datawords. #001 010 Transmit FIFO/Buffer depth = 8 datawords. #010 011 Transmit FIFO/Buffer depth = 16 datawords. #011 100 Transmit FIFO/Buffer depth = 32 datawords. #100 101 Transmit FIFO/Buffer depth = 64 datawords. #101 110 Transmit FIFO/Buffer depth = 128 datawords. #110 111 Transmit FIFO/Buffer depth = 256 datawords #111 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. #1 RXUFE Receive FIFO Underflow Interrupt Enable 8 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 9 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 RXIDEN Receiver Idle Empty Enable 10 3 read-write 000 Disable RDRF assertion due to partially filled FIFO when receiver is idle. #000 001 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. #001 010 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. #010 011 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. #011 100 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. #100 101 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. #101 110 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. #110 111 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. #111 RXFLUSH Receive FIFO/Buffer Flush 14 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 TXFLUSH Transmit FIFO/Buffer Flush 15 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 RXUF Receiver Buffer Underflow Flag 16 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXOF Transmitter Buffer Overflow Flag 17 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 RXEMPT Receive Buffer/FIFO Empty 22 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 TXEMPT Transmit Buffer/FIFO Empty 23 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 WATER LPUART Watermark Register 0x2C 32 read-write 0 0xFFFFFFFF TXWATER Transmit Watermark 0 2 read-write TXCOUNT Transmit Counter 8 3 read-only RXWATER Receive Watermark 16 2 read-write RXCOUNT Receive Counter 24 3 read-only LPUART1 Universal Asynchronous Receiver/Transmitter LPUART LPUART1_ 0x4006B000 0 0x30 registers LPUART1_RxTx 30 VERID Version ID Register 0 32 read-only 0x4010003 0xFFFFFFFF FEATURE Feature Identification Number 0 16 read-only 0000000000000001 Standard feature set. #1 0000000000000011 Standard feature set with MODEM/IrDA support. #11 MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM Parameter Register 0x4 32 read-only 0x202 0xFFFFFFFF TXFIFO Transmit FIFO Size 0 8 read-only RXFIFO Receive FIFO Size 8 8 read-only GLOBAL LPUART Global Register 0x8 32 read-write 0 0xFFFFFFFF RST Software Reset 1 1 read-write 0 Module is not reset. #0 1 Module is reset. #1 PINCFG LPUART Pin Configuration Register 0xC 32 read-write 0 0xFFFFFFFF TRGSEL Trigger Select 0 2 read-write 00 Input trigger is disabled. #00 01 Input trigger is used instead of RXD pin input. #01 10 Input trigger is used instead of CTS_B pin input. #10 11 Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger. #11 BAUD LPUART Baud Rate Register 0x10 32 read-write 0xF000004 0xFFFFFFFF SBR Baud Rate Modulo Divisor. 0 13 read-write SBNS Stop Bit Number Select 13 1 read-write 0 One stop bit. #0 1 Two stop bits. #1 RXEDGIE RX Input Active Edge Interrupt Enable 14 1 read-write 0 Hardware interrupts from LPUART_STAT[RXEDGIF] disabled. #0 1 Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1. #1 LBKDIE LIN Break Detect Interrupt Enable 15 1 read-write 0 Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling). #0 1 Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1. #1 RESYNCDIS Resynchronization Disable 16 1 read-write 0 Resynchronization during received data word is supported #0 1 Resynchronization during received data word is disabled #1 BOTHEDGE Both Edge Sampling 17 1 read-write 0 Receiver samples input data using the rising edge of the baud rate clock. #0 1 Receiver samples input data using the rising and falling edge of the baud rate clock. #1 MATCFG Match Configuration 18 2 read-write 00 Address Match Wakeup #00 01 Idle Match Wakeup #01 10 Match On and Match Off #10 RIDMAE Receiver Idle DMA Enable 20 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 RDMAE Receiver Full DMA Enable 21 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 TDMAE Transmitter DMA Enable 23 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 OSR Oversampling Ratio 24 5 read-write 00000 Writing 0 to this field will result in an oversampling ratio of 16 #00000 00011 Oversampling ratio of 4, requires BOTHEDGE to be set. #00011 00100 Oversampling ratio of 5, requires BOTHEDGE to be set. #00100 00101 Oversampling ratio of 6, requires BOTHEDGE to be set. #00101 00110 Oversampling ratio of 7, requires BOTHEDGE to be set. #00110 00111 Oversampling ratio of 8. #00111 01000 Oversampling ratio of 9. #01000 01001 Oversampling ratio of 10. #01001 01010 Oversampling ratio of 11. #01010 01011 Oversampling ratio of 12. #01011 01100 Oversampling ratio of 13. #01100 01101 Oversampling ratio of 14. #01101 01110 Oversampling ratio of 15. #01110 01111 Oversampling ratio of 16. #01111 10000 Oversampling ratio of 17. #10000 10001 Oversampling ratio of 18. #10001 10010 Oversampling ratio of 19. #10010 10011 Oversampling ratio of 20. #10011 10100 Oversampling ratio of 21. #10100 10101 Oversampling ratio of 22. #10101 10110 Oversampling ratio of 23. #10110 10111 Oversampling ratio of 24. #10111 11000 Oversampling ratio of 25. #11000 11001 Oversampling ratio of 26. #11001 11010 Oversampling ratio of 27. #11010 11011 Oversampling ratio of 28. #11011 11100 Oversampling ratio of 29. #11100 11101 Oversampling ratio of 30. #11101 11110 Oversampling ratio of 31. #11110 11111 Oversampling ratio of 32. #11111 M10 10-bit Mode select 29 1 read-write 0 Receiver and transmitter use 7-bit to 9-bit data characters. #0 1 Receiver and transmitter use 10-bit data characters. #1 MAEN2 Match Address Mode Enable 2 30 1 read-write 0 Normal operation. #0 1 Enables automatic address matching or data matching mode for MATCH[MA2]. #1 MAEN1 Match Address Mode Enable 1 31 1 read-write 0 Normal operation. #0 1 Enables automatic address matching or data matching mode for MATCH[MA1]. #1 STAT LPUART Status Register 0x14 32 read-write 0xC00000 0xFFFFFFFF MA2F Match 2 Flag 14 1 read-write 0 Received data is not equal to MA2 #0 1 Received data is equal to MA2 #1 MA1F Match 1 Flag 15 1 read-write 0 Received data is not equal to MA1 #0 1 Received data is equal to MA1 #1 PF Parity Error Flag 16 1 read-write 0 No parity error. #0 1 Parity error. #1 FE Framing Error Flag 17 1 read-write 0 No framing error detected. This does not guarantee the framing is correct. #0 1 Framing error. #1 NF Noise Flag 18 1 read-write 0 No noise detected. #0 1 Noise detected in the received character in LPUART_DATA. #1 OR Receiver Overrun Flag 19 1 read-write 0 No overrun. #0 1 Receive overrun (new LPUART data lost). #1 IDLE Idle Line Flag 20 1 read-write 0 No idle line detected. #0 1 Idle line was detected. #1 RDRF Receive Data Register Full Flag 21 1 read-only 0 Receive data buffer empty. #0 1 Receive data buffer full. #1 TC Transmission Complete Flag 22 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 23 1 read-only 0 Transmit data buffer full. #0 1 Transmit data buffer empty. #1 RAF Receiver Active Flag 24 1 read-only 0 LPUART receiver idle waiting for a start bit. #0 1 LPUART receiver active (RXD input not idle). #1 LBKDE LIN Break Detection Enable 25 1 read-write 0 LIN break detect is disabled, normal break character can be detected. #0 1 LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1). #1 BRK13 Break Character Generation Length 26 1 read-write 0 Break character is transmitted with length of 9 to 13 bit times. #0 1 Break character is transmitted with length of 12 to 15 bit times. #1 RWUID Receive Wake Up Idle Detect 27 1 read-write 0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not set when an address does not match. #0 1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does set when an address does not match. #1 RXINV Receive Data Inversion 28 1 read-write 0 Receive data not inverted. #0 1 Receive data inverted. #1 MSBF MSB First 29 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. #1 RXEDGIF RXD Pin Active Edge Interrupt Flag 30 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 LBKDIF LIN Break Detect Interrupt Flag 31 1 read-write 0 No LIN break character has been detected. #0 1 LIN break character has been detected. #1 CTRL LPUART Control Register 0x18 32 read-write 0 0xFFFFFFFF PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 PE Parity Enable 1 1 read-write 0 No hardware parity generation or checking. #0 1 Parity enabled. #1 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Configures RWU for idle-line wakeup. #0 1 Configures RWU with address-mark wakeup. #1 M 9-Bit or 8-Bit Mode Select 4 1 read-write 0 Receiver and transmitter use 8-bit data characters. #0 1 Receiver and transmitter use 9-bit data characters. #1 RSRC Receiver Source Select 5 1 read-write 0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin. #0 1 Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input. #1 DOZEEN Doze Enable 6 1 read-write 0 LPUART is enabled in Doze mode. #0 1 LPUART is disabled in Doze mode. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation - RXD and TXD use separate pins. #0 1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). #1 IDLECFG Idle Configuration 8 3 read-write 000 1 idle character #000 001 2 idle characters #001 010 4 idle characters #010 011 8 idle characters #011 100 16 idle characters #100 101 32 idle characters #101 110 64 idle characters #110 111 128 idle characters #111 M7 7-Bit Mode Select 11 1 read-write 0 Receiver and transmitter use 8-bit to 10-bit data characters. #0 1 Receiver and transmitter use 7-bit data characters. #1 MA2IE Match 2 Interrupt Enable 14 1 read-write 0 MA2F interrupt disabled #0 1 MA2F interrupt enabled #1 MA1IE Match 1 Interrupt Enable 15 1 read-write 0 MA1F interrupt disabled #0 1 MA1F interrupt enabled #1 SBK Send Break 16 1 read-write 0 Normal transmitter operation. #0 1 Queue break character(s) to be sent. #1 RWU Receiver Wakeup Control 17 1 read-write 0 Normal receiver operation. #0 1 LPUART receiver in standby waiting for wakeup condition. #1 RE Receiver Enable 18 1 read-write 0 Receiver disabled. #0 1 Receiver enabled. #1 TE Transmitter Enable 19 1 read-write 0 Transmitter disabled. #0 1 Transmitter enabled. #1 ILIE Idle Line Interrupt Enable 20 1 read-write 0 Hardware interrupts from IDLE disabled; use polling. #0 1 Hardware interrupt requested when IDLE flag is 1. #1 RIE Receiver Interrupt Enable 21 1 read-write 0 Hardware interrupts from RDRF disabled; use polling. #0 1 Hardware interrupt requested when RDRF flag is 1. #1 TCIE Transmission Complete Interrupt Enable for 22 1 read-write 0 Hardware interrupts from TC disabled; use polling. #0 1 Hardware interrupt requested when TC flag is 1. #1 TIE Transmit Interrupt Enable 23 1 read-write 0 Hardware interrupts from TDRE disabled; use polling. #0 1 Hardware interrupt requested when TDRE flag is 1. #1 PEIE Parity Error Interrupt Enable 24 1 read-write 0 PF interrupts disabled; use polling). #0 1 Hardware interrupt requested when PF is set. #1 FEIE Framing Error Interrupt Enable 25 1 read-write 0 FE interrupts disabled; use polling. #0 1 Hardware interrupt requested when FE is set. #1 NEIE Noise Error Interrupt Enable 26 1 read-write 0 NF interrupts disabled; use polling. #0 1 Hardware interrupt requested when NF is set. #1 ORIE Overrun Interrupt Enable 27 1 read-write 0 OR interrupts disabled; use polling. #0 1 Hardware interrupt requested when OR is set. #1 TXINV Transmit Data Inversion 28 1 read-write 0 Transmit data not inverted. #0 1 Transmit data inverted. #1 TXDIR TXD Pin Direction in Single-Wire Mode 29 1 read-write 0 TXD pin is an input in single-wire mode. #0 1 TXD pin is an output in single-wire mode. #1 R9T8 Receive Bit 9 / Transmit Bit 8 30 1 read-write R8T9 Receive Bit 8 / Transmit Bit 9 31 1 read-write DATA LPUART Data Register 0x1C 32 read-write 0x1000 0xFFFFFFFF R0T0 R0T0 0 1 read-write R1T1 R1T1 1 1 read-write R2T2 R2T2 2 1 read-write R3T3 R3T3 3 1 read-write R4T4 R4T4 4 1 read-write R5T5 R5T5 5 1 read-write R6T6 R6T6 6 1 read-write R7T7 R7T7 7 1 read-write R8T8 R8T8 8 1 read-write R9T9 R9T9 9 1 read-write IDLINE Idle Line 11 1 read-only 0 Receiver was not idle before receiving this character. #0 1 Receiver was idle before receiving this character. #1 RXEMPT Receive Buffer Empty 12 1 read-only 0 Receive buffer contains valid data. #0 1 Receive buffer is empty, data returned on read is not valid. #1 FRETSC Frame Error / Transmit Special Character 13 1 read-write 0 The dataword was received without a frame error on read, or transmit a normal character on write. #0 1 The dataword was received with a frame error, or transmit an idle or break character on transmit. #1 PARITYE PARITYE 14 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 NOISY NOISY 15 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 MATCH LPUART Match Address Register 0x20 32 read-write 0 0xFFFFFFFF MA1 Match Address 1 0 10 read-write MA2 Match Address 2 16 10 read-write MODIR LPUART Modem IrDA Register 0x24 32 read-write 0 0xFFFFFFFF TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 TXCTSC Transmit CTS Configuration 4 1 read-write 0 CTS input is sampled at the start of each character. #0 1 CTS input is sampled when the transmitter is idle. #1 TXCTSSRC Transmit CTS Source 5 1 read-write 0 CTS input is the CTS_B pin. #0 1 CTS input is the inverted Receiver Match result. #1 RTSWATER Receive RTS Configuration 8 2 read-write TNP Transmitter narrow pulse 16 2 read-write 00 1/OSR. #00 01 2/OSR. #01 10 3/OSR. #10 11 4/OSR. #11 IREN Infrared enable 18 1 read-write 0 IR disabled. #0 1 IR enabled. #1 FIFO LPUART FIFO Register 0x28 32 read-write 0xC00011 0xFFFFFFFF RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer depth = 1 dataword. #000 001 Receive FIFO/Buffer depth = 4 datawords. #001 010 Receive FIFO/Buffer depth = 8 datawords. #010 011 Receive FIFO/Buffer depth = 16 datawords. #011 100 Receive FIFO/Buffer depth = 32 datawords. #100 101 Receive FIFO/Buffer depth = 64 datawords. #101 110 Receive FIFO/Buffer depth = 128 datawords. #110 111 Receive FIFO/Buffer depth = 256 datawords. #111 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer depth = 1 dataword. #000 001 Transmit FIFO/Buffer depth = 4 datawords. #001 010 Transmit FIFO/Buffer depth = 8 datawords. #010 011 Transmit FIFO/Buffer depth = 16 datawords. #011 100 Transmit FIFO/Buffer depth = 32 datawords. #100 101 Transmit FIFO/Buffer depth = 64 datawords. #101 110 Transmit FIFO/Buffer depth = 128 datawords. #110 111 Transmit FIFO/Buffer depth = 256 datawords #111 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. #1 RXUFE Receive FIFO Underflow Interrupt Enable 8 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 9 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 RXIDEN Receiver Idle Empty Enable 10 3 read-write 000 Disable RDRF assertion due to partially filled FIFO when receiver is idle. #000 001 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. #001 010 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. #010 011 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. #011 100 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. #100 101 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. #101 110 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. #110 111 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. #111 RXFLUSH Receive FIFO/Buffer Flush 14 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 TXFLUSH Transmit FIFO/Buffer Flush 15 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 RXUF Receiver Buffer Underflow Flag 16 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXOF Transmitter Buffer Overflow Flag 17 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 RXEMPT Receive Buffer/FIFO Empty 22 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 TXEMPT Transmit Buffer/FIFO Empty 23 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 WATER LPUART Watermark Register 0x2C 32 read-write 0 0xFFFFFFFF TXWATER Transmit Watermark 0 2 read-write TXCOUNT Transmit Counter 8 3 read-only RXWATER Receive Watermark 16 2 read-write RXCOUNT Receive Counter 24 3 read-only CMP0 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP0_ 0x40073000 0 0xC registers CMP0 29 C0 CMP Control Register 0 0 32 read-write 0 0xFFFFFFFF HYSTCTR Comparator hard block hysteresis control. See chip data sheet to get the actual hysteresis value with each level 0 2 read-write 00 The hard block output has level 0 hysteresis internally. #00 01 The hard block output has level 1 hysteresis internally. #01 10 The hard block output has level 2 hysteresis internally. #10 11 The hard block output has level 3 hysteresis internally. #11 OFFSET Comparator hard block offset control. See chip data sheet to get the actual offset value with each level 2 1 read-write 0 The comparator hard block output has level 0 offset internally. #0 1 The comparator hard block output has level 1 offset internally. #1 FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA. #000 001 1 consecutive sample must agree (comparator output is simply sampled). #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 EN Comparator Module Enable 8 1 read-write 0 Analog Comparator is disabled. #0 1 Analog Comparator is enabled. #1 OPE Comparator Output Pin Enable 9 1 read-write 0 When OPE is 0, the comparator output (after window/filter settings dependent on software configuration) is not available to a packaged pin. #0 1 When OPE is 1, and if the software has configured the comparator to own a packaged pin, the comparator is available in a packaged pin. #1 COS Comparator Output Select 10 1 read-write 0 Set CMPO to equal COUT (filtered comparator output). #0 1 Set CMPO to equal COUTA (unfiltered comparator output). #1 INVT Comparator invert 11 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 PMODE Power Mode Select 12 1 read-write 0 Low Speed (LS) comparison mode is selected. #0 1 High Speed (HS) comparison mode is selected, in VLPx mode, or Stop mode switched to Low Speed (LS) mode. #1 WE Windowing Enable 14 1 read-write 0 Windowing mode is not selected. #0 1 Windowing mode is selected. #1 SE Sample Enable 15 1 read-write 0 Sampling mode is not selected. #0 1 Sampling mode is selected. #1 FPR Filter Sample Period 16 8 read-write COUT Analog Comparator Output 24 1 read-only CFF Analog Comparator Flag Falling 25 1 read-write 0 A falling edge has not been detected on COUT. #0 1 A falling edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 26 1 read-write 0 A rising edge has not been detected on COUT. #0 1 A rising edge on COUT has occurred. #1 IEF Comparator Interrupt Enable Falling 27 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 IER Comparator Interrupt Enable Rising 28 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 DMAEN DMA Enable 30 1 read-write 0 DMA is disabled. #0 1 DMA is enabled. #1 C1 CMP Control Register 1 0x4 32 read-write 0 0xFFFFFFFF VOSEL DAC Output Voltage Select 0 8 read-write MSEL Minus Input MUX Control 8 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PSEL Plus Input MUX Control 11 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 VRSEL Supply Voltage Reference Source Select 14 1 read-write 0 Vin1 is selected as resistor ladder network supply reference Vin. #0 1 Vin2 is selected as resistor ladder network supply reference Vin. #1 DACEN DAC Enable 15 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 CHN0 Channel 0 input enable 16 1 read-write CHN1 Channel 1 input enable 17 1 read-write CHN2 Channel 2 input enable 18 1 read-write CHN3 Channel 3 input enable 19 1 read-write CHN4 Channel 4 input enable 20 1 read-write CHN5 Channel 5 input enable 21 1 read-write CHN6 Channel 6 input enable 22 1 read-write CHN7 Channel 7 input enable 23 1 read-write INNSEL Selection of the input to the negative port of the comparator 24 2 read-write 00 IN0, from the 8-bit DAC output #00 01 IN1, from the analog 8-1 mux #01 INPSEL Selection of the input to the positive port of the comparator 27 2 read-write 00 IN0, from the 8-bit DAC output #00 01 IN1, from the analog 8-1 mux #01 C2 CMP Control Register 2 0x8 32 read-write 0 0xFFFFFFFF ACOn The result of the input comparison for channel n 0 8 read-write INITMOD Comparator and DAC initialization delay modulus. 8 6 read-write 000000 The modulus is set to 64 (same with 111111). #0 NSAM Number of sample clocks 14 2 read-write 00 The comparison result is sampled as soon as the active channel is scanned in one round-robin clock. #00 01 The sampling takes place 1 round-robin clock cycle after the next cycle of the round-robin clock. #01 10 The sampling takes place 2 round-robin clock cycles after the next cycle of the round-robin clock. #10 11 The sampling takes place 3 round-robin clock cycles after the next cycle of the round-robin clock. #11 CH0F Channel 0 input changed flag 16 1 read-write CH1F Channel 1 input changed flag 17 1 read-write CH2F Channel 2 input changed flag 18 1 read-write CH3F Channel 3 input changed flag 19 1 read-write CH4F Channel 4 input changed flag 20 1 read-write CH5F Channel 5 input changed flag 21 1 read-write CH6F Channel 6 input changed flag 22 1 read-write CH7F Channel 7 input changed flag 23 1 read-write FXMXCH Fixed channel selection 25 3 read-write 000 Channel 0 is selected as the fixed reference input for the fixed mux port. #000 001 Channel 1 is selected as the fixed reference input for the fixed mux port. #001 010 Channel 2 is selected as the fixed reference input for the fixed mux port. #010 011 Channel 3 is selected as the fixed reference input for the fixed mux port. #011 100 Channel 4 is selected as the fixed reference input for the fixed mux port. #100 101 Channel 5 is selected as the fixed reference input for the fixed mux port. #101 110 Channel 6 is selected as the fixed reference input for the fixed mux port. #110 111 Channel 7 is selected as the fixed reference input for the fixed mux port. #111 FXMP Fixed MUX Port 29 1 read-write 0 The Plus port is fixed. Only the inputs to the Minus port are swept in each round. #0 1 The Minus port is fixed. Only the inputs to the Plus port are swept in each round. #1 RRIE Round-Robin interrupt enable 30 1 read-write 0 The round-robin interrupt is disabled. #0 1 The round-robin interrupt is enabled when a comparison result changes from the last sample. #1 RRE Round-Robin Enable 31 1 read-write 0 Round-robin operation is disabled. #0 1 Round-robin operation is enabled. #1 PMC PMC PMC_ 0x4007D000 0 0x5 registers SCG_CMU_LVD_LVWSCG 21 LVDSC1 Low Voltage Detect Status and Control 1 Register 0 8 read-write 0 0xEF LVDRE Low Voltage Detect Reset Enable 4 1 read-write 0 No system resets on low voltage detect events. #0 LVDIE Low Voltage Detect Interrupt Enable 5 1 read-write 0 Hardware interrupt disabled (use polling) #0 1 Request a hardware interrupt when LVDF = 1 #1 LVDACK Low Voltage Detect Acknowledge 6 1 write-only LVDF Low Voltage Detect Flag 7 1 read-only 0 Low-voltage event not detected #0 1 Low-voltage event detected #1 LVDSC2 Low Voltage Detect Status and Control 2 Register 0x1 8 read-write 0 0xFF LVWIE Low-Voltage Warning Interrupt Enable 5 1 read-write 0 Hardware interrupt disabled (use polling) #0 1 Request a hardware interrupt when LVWF=1 #1 LVWACK Low-Voltage Warning Acknowledge 6 1 write-only LVWF Low-Voltage Warning Flag 7 1 read-only 0 Low-voltage warning event not detected #0 1 Low-voltage warning event detected #1 REGSC Regulator Status and Control Register 0x2 8 read-write 0x4 0xBF BIASEN Bias Enable Bit 0 1 read-write 0 Biasing disabled, core logic can run in full performance #0 1 Biasing enabled, core logic is slower and there are restrictions in allowed system clock speed (see Data Sheet for details) #1 CLKBIASDIS Clock Bias Disable Bit 1 1 read-write 0 No effect #0 1 In VLPS mode, the bias currents and reference voltages for the following clock modules are disabled: SIRC, FIRC, PLL. (if available on device) #1 REGFPM Regulator in Full Performance Mode Status Bit 2 1 read-only 0 Regulator is in low power mode or transition to/from #0 1 Regulator is in full performance mode #1 LPOSTAT LPO Status Bit 6 1 read-only 0 Low power oscillator in low phase #0 1 Low power oscillator in high phase #1 LPODIS LPO Disable Bit 7 1 read-write 0 Low power oscillator enabled #0 1 Low power oscillator disabled #1 LPOTRIM Low Power Oscillator Trim Register 0x4 8 read-write 0 0xE0 LPOTRIM LPO trimming bits 0 5 read-write SMC System Mode Controller SMC_ 0x4007E000 0 0x18 registers VERID SMC Version ID Register 0 32 read-only 0x1000000 0xFFFFFFFF FEATURE Feature Specification Number 0 16 read-only 0 Standard features implemented #0 MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM SMC Parameter Register 0x4 32 read-only 0 0xFFFFFFFF EHSRUN Existence of HSRUN feature 0 1 read-only 0 The feature is not available. #0 1 The feature is available. #1 ELLS Existence of LLS feature 3 1 read-only 0 The feature is not available. #0 1 The feature is available. #1 ELLS2 Existence of LLS2 feature 5 1 read-only 0 The feature is not available. #0 1 The feature is available. #1 EVLLS0 Existence of VLLS0 feature 6 1 read-only 0 The feature is not available. #0 1 The feature is available. #1 PMPROT Power Mode Protection register 0x8 32 read-write 0 0xFFFFFFFF AVLP Allow Very-Low-Power Modes 5 1 read-write 0 VLPR and VLPS are not allowed. #0 1 VLPR and VLPS are allowed. #1 PMCTRL Power Mode Control register 0xC 32 read-write 0 0xFFFFFFFF STOPM Stop Mode Control 0 3 read-write 000 Normal Stop (STOP) #000 010 Very-Low-Power Stop (VLPS) #010 110 Reseved #110 VLPSA Very Low Power Stop Aborted 3 1 read-only 0 The previous stop mode entry was successful. #0 1 The previous stop mode entry was aborted. #1 RUNM Run Mode Control 5 2 read-write 00 Normal Run mode (RUN) #00 10 Very-Low-Power Run mode (VLPR) #10 STOPCTRL Stop Control Register 0x10 32 read-write 0x3 0xFFFFFFFF STOPO Stop Option 6 2 read-write 01 STOP1 - Stop with both system and bus clocks disabled #01 10 STOP2 - Stop with system clock disabled and bus clock enabled #10 PMSTAT Power Mode Status register 0x14 32 read-only 0x1 0xFFFFFFFF PMSTAT Power Mode Status 0 8 read-only RCM Reset Control Module RCM_ 0x4007F000 0 0x20 registers RCM 23 VERID Version ID Register 0 32 read-only 0x3000003 0xFFFFFFFF FEATURE Feature Specification Number 0 16 read-only 11 Standard feature set. #11 MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM Parameter Register 0x4 32 read-only 0x2FFE 0xFFFFFFFF EWAKEUP Existence of SRS[WAKEUP] status indication feature 0 1 read-only 0 The feature is not available. #0 1 The feature is available. #1 ELVD Existence of SRS[LVD] status indication feature 1 1 read-only 0 The feature is not available. #0 1 The feature is available. #1 ELOC Existence of SRS[LOC] status indication feature 2 1 read-only 0 The feature is not available. #0 1 The feature is available. #1 ELOL Existence of SRS[LOL] status indication feature 3 1 read-only 0 The feature is not available. #0 1 The feature is available. #1 ECMU_LOC Existence of SRS[CMU_LOC] status indication feature 4 1 read-only 0 The feature is not available. #0 1 The feature is available. #1 EWDOG Existence of SRS[WDOG] status indication feature 5 1 read-only 0 The feature is not available. #0 1 The feature is available. #1 EPIN Existence of SRS[PIN] status indication feature 6 1 read-only 0 The feature is not available. #0 1 The feature is available. #1 EPOR Existence of SRS[POR] status indication feature 7 1 read-only 0 The feature is not available. #0 1 The feature is available. #1 EJTAG Existence of SRS[JTAG] status indication feature 8 1 read-only 0 The feature is not available. #0 1 The feature is available. #1 ELOCKUP Existence of SRS[LOCKUP] status indication feature 9 1 read-only 0 The feature is not available. #0 1 The feature is available. #1 ESW Existence of SRS[SW] status indication feature 10 1 read-only 0 The feature is not available. #0 1 The feature is available. #1 EMDM_AP Existence of SRS[MDM_AP] status indication feature 11 1 read-only 0 The feature is not available. #0 1 The feature is available. #1 ESACKERR Existence of SRS[SACKERR] status indication feature 13 1 read-only 0 The feature is not available. #0 1 The feature is available. #1 ETAMPER Existence of SRS[TAMPER] status indication feature 15 1 read-only 0 The feature is not available. #0 1 The feature is available. #1 ECORE1 Existence of SRS[CORE1] status indication feature 16 1 read-only 0 The feature is not available. #0 1 The feature is available. #1 SRS System Reset Status Register 0x8 32 read-only 0x82 0xFFFFFFFF LVD Low-Voltage Detect Reset or High-Voltage Detect Reset 1 1 read-only 0 Reset not caused by LVD trip, HVD trip or POR #0 1 Reset caused by LVD trip, HVD trip or POR #1 LOC Loss-of-Clock Reset 2 1 read-only 0 Reset not caused by a loss of external clock. #0 1 Reset caused by a loss of external clock. #1 LOL Loss-of-Lock Reset 3 1 read-only 0 Reset not caused by a loss of lock in the PLL/FLL #0 1 Reset caused by a loss of lock in the PLL/FLL #1 CMU_LOC CMU Loss-of-Clock Reset 4 1 read-only 0 Reset not caused by the CMU loss-of-clock circuit. #0 1 Reset caused by the CMU loss-of-clock circuit. #1 WDOG Watchdog 5 1 read-only 0 Reset not caused by watchdog timeout #0 1 Reset caused by watchdog timeout #1 PIN External Reset Pin 6 1 read-only 0 Reset not caused by external reset pin #0 1 Reset caused by external reset pin #1 POR Power-On Reset 7 1 read-only 0 Reset not caused by POR #0 1 Reset caused by POR #1 JTAG JTAG generated reset 8 1 read-only 0 Reset not caused by JTAG #0 1 Reset caused by JTAG #1 LOCKUP Core Lockup 9 1 read-only 0 Reset not caused by core LOCKUP event #0 1 Reset caused by core LOCKUP event #1 SW Software 10 1 read-only 0 Reset not caused by software setting of SYSRESETREQ bit #0 1 Reset caused by software setting of SYSRESETREQ bit #1 MDM_AP MDM-AP System Reset Request 11 1 read-only 0 Reset was not caused by host debugger system setting of the System Reset Request bit #0 1 Reset was caused by host debugger system setting of the System Reset Request bit #1 SACKERR Stop Acknowledge Error 13 1 read-only 0 Reset not caused by peripheral failure to acknowledge attempt to enter stop mode #0 1 Reset caused by peripheral failure to acknowledge attempt to enter stop mode #1 RPC Reset Pin Control register 0xC 32 read-write 0 0xFFFFFFFF RSTFLTSRW Reset Pin Filter Select in Run and Wait Modes 0 2 read-write 00 All filtering disabled #00 01 Bus clock filter enabled for normal operation #01 10 LPO clock filter enabled for normal operation #10 RSTFLTSS Reset Pin Filter Select in Stop Mode 2 1 read-write 0 All filtering disabled #0 1 LPO clock filter enabled #1 RSTFLTSEL Reset Pin Filter Bus Clock Select 8 5 read-write SSRS Sticky System Reset Status Register 0x18 32 read-write 0x82 0xFFFFFFFF SLVD Sticky Low-Voltage Detect Reset 1 1 read-write 0 Reset not caused by LVD trip or POR #0 1 Reset caused by LVD trip or POR #1 SLOC Sticky Loss-of-Clock Reset 2 1 read-write 0 Reset not caused by a loss of external clock. #0 1 Reset caused by a loss of external clock. #1 SLOL Sticky Loss-of-Lock Reset 3 1 read-write 0 Reset not caused by a loss of lock in the PLL/FLL #0 1 Reset caused by a loss of lock in the PLL/FLL #1 SCMU_LOC Sticky CMU Loss-of-Clock Reset 4 1 read-write 0 Reset not caused by the CMU loss-of-clock circuit. #0 1 Reset caused by the CMU loss-of-clock circuit. #1 SWDOG Sticky Watchdog 5 1 read-write 0 Reset not caused by watchdog timeout #0 1 Reset caused by watchdog timeout #1 SPIN Sticky External Reset Pin 6 1 read-write 0 Reset not caused by external reset pin #0 1 Reset caused by external reset pin #1 SPOR Sticky Power-On Reset 7 1 read-write 0 Reset not caused by POR #0 1 Reset caused by POR #1 SJTAG Sticky JTAG generated reset 8 1 read-write 0 Reset not caused by JTAG #0 1 Reset caused by JTAG #1 SLOCKUP Sticky Core Lockup 9 1 read-write 0 Reset not caused by core LOCKUP event #0 1 Reset caused by core LOCKUP event #1 SSW Sticky Software 10 1 read-write 0 Reset not caused by software setting of SYSRESETREQ bit #0 1 Reset caused by software setting of SYSRESETREQ bit #1 SMDM_AP Sticky MDM-AP System Reset Request 11 1 read-write 0 Reset was not caused by host debugger system setting of the System Reset Request bit #0 1 Reset was caused by host debugger system setting of the System Reset Request bit #1 SSACKERR Sticky Stop Acknowledge Error 13 1 read-write 0 Reset not caused by peripheral failure to acknowledge attempt to enter stop mode #0 1 Reset caused by peripheral failure to acknowledge attempt to enter stop mode #1 SRIE System Reset Interrupt Enable Register 0x1C 32 read-write 0 0xFFFFFFFF DELAY Reset Delay Time 0 2 read-write 00 10 LPO cycles #00 01 34 LPO cycles #01 10 130 LPO cycles #10 11 514 LPO cycles #11 LOC Loss-of-Clock Interrupt 2 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 LOL Loss-of-Lock Interrupt 3 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 CMU_LOC CMU Loss-of-Clock Interrupt 4 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 WDOG Watchdog Interrupt 5 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 PIN External Reset Pin Interrupt 6 1 read-write 0 Reset not caused by external reset pin #0 1 Reset caused by external reset pin #1 GIE Global Interrupt Enable 7 1 read-write 0 All interrupt sources disabled. #0 1 All interrupt sources enabled. Note that the individual interrupt-enable bits still need to be set to generate interrupts. #1 JTAG JTAG generated reset 8 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 LOCKUP Core Lockup Interrupt 9 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 SW Software Interrupt 10 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 MDM_AP MDM-AP System Reset Request 11 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 SACKERR Stop Acknowledge Error Interrupt 13 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 PTA General Purpose Input/Output GPIO GPIOA_ 0x400FF000 0 0x1C registers PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write PIDR Port Input Disable Register 0x18 32 read-write 0 0xFFFFFFFF PID Port Input Disable 0 32 read-write PTB General Purpose Input/Output GPIO GPIOB_ 0x400FF040 0 0x1C registers PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write PIDR Port Input Disable Register 0x18 32 read-write 0 0xFFFFFFFF PID Port Input Disable 0 32 read-write PTC General Purpose Input/Output GPIO GPIOC_ 0x400FF080 0 0x1C registers PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write PIDR Port Input Disable Register 0x18 32 read-write 0 0xFFFFFFFF PID Port Input Disable 0 32 read-write PTD General Purpose Input/Output GPIO GPIOD_ 0x400FF0C0 0 0x1C registers PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write PIDR Port Input Disable Register 0x18 32 read-write 0 0xFFFFFFFF PID Port Input Disable 0 32 read-write PTE General Purpose Input/Output GPIO GPIOE_ 0x400FF100 0 0x1C registers PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write PIDR Port Input Disable Register 0x18 32 read-write 0 0xFFFFFFFF PID Port Input Disable 0 32 read-write S32_SCB System Control Registers SCB_ 0xE000E000 0x8 0xD2C registers ACTLR Auxiliary Control Register, 0x8 32 read-only 0 0xFFFFFFFF CPUID CPUID Base Register 0xD00 32 read-only 0x410CC600 0xFFFFFFFF REVISION Indicates patch release: 0x0 = Patch 0 0 4 read-only PARTNO Indicates part number 4 12 read-only VARIANT Indicates processor revision: 0x2 = Revision 2 20 4 read-only IMPLEMENTER Implementer code 24 8 read-only ICSR Interrupt Control and State Register 0xD04 32 read-write 0 0xFFFFFFFF VECTACTIVE Active exception number 0 6 read-only VECTPENDING Exception number of the highest priority pending enabled exception 12 6 read-only ISRPENDING Interrupt pending flag, excluding NMI and Faults 22 1 read-only 0 interrupt not pending #0 1 interrupt pending #1 PENDSTCLR SysTick exception clear-pending bit 25 1 write-only 0 no effect #0 1 removes the pending state from the SysTick exception #1 PENDSTSET SysTick exception set-pending bit 26 1 read-write 0 write: no effect; read: SysTick exception is not pending #0 1 write: changes SysTick exception state to pending; read: SysTick exception is pending #1 PENDSVCLR PendSV clear-pending bit 27 1 write-only 0 no effect #0 1 removes the pending state from the PendSV exception #1 PENDSVSET PendSV set-pending bit 28 1 read-write 0 write: no effect; read: PendSV exception is not pending #0 1 write: changes PendSV exception state to pending; read: PendSV exception is pending #1 NMIPENDSET NMI set-pending bit 31 1 read-write 0 write: no effect; read: NMI exception is not pending #0 1 write: changes NMI exception state to pending; read: NMI exception is pending #1 VTOR Vector Table Offset Register 0xD08 32 read-write 0 0xFFFFFFFF TBLOFF Vector table base offset 7 25 read-write AIRCR Application Interrupt and Reset Control Register 0xD0C 32 read-write 0 0xFFFFFFFF VECTCLRACTIVE Reserved for debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable. 1 1 write-only SYSRESETREQ System reset request: 2 1 write-only 0 no system reset request #0 1 asserts a signal to the outer system that requests a reset #1 ENDIANNESS Data endianness implemented 15 1 read-only 0 Little-endian #0 1 Big-endian #1 VECTKEY Register key 16 16 read-write SCR System Control Register 0xD10 32 read-write 0 0xFFFFFFFF SLEEPONEXIT Indicates sleep-on-exit when returning from Handler mode to Thread mode 1 1 read-write 0 o not sleep when returning to Thread mode #0 1 enter sleep, or deep sleep, on return from an ISR #1 SLEEPDEEP Controls whether the processor uses sleep or deep sleep as its low power mode 2 1 read-write 0 sleep #0 1 deep sleep #1 SEVONPEND Send Event on Pending bit 4 1 read-write 0 only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded #0 1 enabled events and all interrupts, including disabled interrupts, can wakeup the processor #1 CCR Configuration and Control Register 0xD14 32 read-only 0x208 0xFFFFFFFF UNALIGN_TRP Always reads as one, indicates that all unaligned accesses generate a HardFault 3 1 read-only STKALIGN Indicates stack alignment on exception entry 9 1 read-only SHPR2 System Handler Priority Register 2 0xD1C 32 read-write 0 0xFFFFFFFF PRI_11 Priority of system handler 11, SVCall 24 8 read-write SHPR3 System Handler Priority Register 3 0xD20 32 read-write 0 0xFFFFFFFF PRI_14 Priority of system handler 14, PendSV 16 8 read-write PRI_15 Priority of system handler 15, SysTick exception 24 8 read-write SHCSR System Handler Control and State Register 0xD24 32 read-write 0 0xFFFFFFFF SVCALLPENDED SVCall pending bit, reads as 1 if exception is pending 15 1 read-write 0 exception is not pending #0 1 exception is pending #1 DFSR Debug Fault Status Register 0xD30 32 read-write 0 0xFFFFFFFF HALTED no description available 0 1 read-write 0 No active halt request debug event #0 1 Halt request debug event active #1 BKPT no description available 1 1 read-write 0 No current breakpoint debug event #0 1 At least one current breakpoint debug event #1 DWTTRAP no description available 2 1 read-write 0 No current debug events generated by the DWT #0 1 At least one current debug event generated by the DWT #1 VCATCH no description available 3 1 read-write 0 No Vector catch triggered #0 1 Vector catch triggered #1 EXTERNAL no description available 4 1 read-write 0 No EDBGRQ debug event #0 1 EDBGRQ debug event #1 S32_SysTick System timer SYST_ 0xE000E010 0 0x10 registers CSR SysTick Control and Status Register 0 32 read-write 0x4 0xFFFFFFFF ENABLE Enables the counter 0 1 read-write 0 counter disabled #0 1 counter enabled #1 TICKINT Enables SysTick exception request 1 1 read-write 0 counting down to 0 does not assert the SysTick exception request #0 1 counting down to 0 asserts the SysTick exception request #1 CLKSOURCE Indicates the clock source 2 1 read-write 0 external clock #0 1 processor clock #1 COUNTFLAG Returns 1 if timer counted to 0 since last time this was read 16 1 read-write RVR SysTick Reload Value Register 0x4 32 read-write 0 0xFFFFFFFF RELOAD Value to load into the SysTick Current Value Register when the counter reaches 0 0 24 read-write CVR SysTick Current Value Register 0x8 32 read-write 0 0xFFFFFFFF CURRENT Current value at the time the register is accessed 0 24 read-write CALIB SysTick Calibration Value Register 0xC 32 read-only 0x80000000 0xFFFFFFFF TENMS Reload value to use for 10ms timing 0 24 read-only SKEW Indicates whether the TENMS value is exact 30 1 read-only 0 TENMS value is exact #0 1 TENMS value is inexact, or not given #1 NOREF Indicates whether the device provides a reference clock to the processor 31 1 read-only 0 The reference clock is provided #0 1 The reference clock is not provided #1 S32_NVIC Nested Vectored Interrupt Controller 0xE000E100 0 0x320 registers DMA0 0 DMA1 1 DMA2 2 DMA3 3 DMA_Error 4 ERM_fault 5 RTC 6 RTC_Seconds 7 LPTMR0 8 PORT 9 CAN0_ORed_Err_Wakeup 10 CAN0_ORed_0_31_MB 11 FTM0_Ch0_7 12 FTM0_Fault 13 FTM0_Ovf_Reload 14 FTM1_Ch0_7 15 FTM1_Fault 16 FTM1_Ovf_Reload 17 FTFC 18 PDB0 19 LPIT0 20 SCG_CMU_LVD_LVWSCG 21 WDOG 22 RCM 23 LPI2C0_Master_Slave 24 FLEXIO 25 LPSPI0 26 LPSPI1 27 ADC0 28 CMP0 29 LPUART1_RxTx 30 LPUART0_RxTx 31 S32_NVIC_ISER Interrupt Set Enable Register 0 32 read-write 0 0xFFFFFFFF SETENA Interrupt set enable bits 0 32 read-write S32_NVIC_ICER Interrupt Clear Enable Register 0x80 32 read-write 0 0xFFFFFFFF CLRENA Interrupt clear-enable bits 0 32 read-write S32_NVIC_ISPR Interrupt Set Pending Register 0x100 32 read-write 0 0xFFFFFFFF SETPEND Interrupt set-pending bits 0 32 read-write S32_NVIC_ICPR Interrupt Clear Pending Register 0x180 32 read-write 0 0xFFFFFFFF CLRPEND Interrupt clear-pending bits 0 32 read-write S32_NVIC_IPR0 Interrupt Priority Register n 0x300 32 read-write 0 0xFFFFFFFF PRI_0 Priority of interrupt 0 0 8 read-write PRI_1 Priority of interrupt 1 8 8 read-write PRI_2 Priority of interrupt 2 16 8 read-write PRI_3 Priority of interrupt 3 24 8 read-write S32_NVIC_IPR1 Interrupt Priority Register n 0x304 32 read-write 0 0xFFFFFFFF PRI_0 Priority of interrupt 0 0 8 read-write PRI_1 Priority of interrupt 1 8 8 read-write PRI_2 Priority of interrupt 2 16 8 read-write PRI_3 Priority of interrupt 3 24 8 read-write S32_NVIC_IPR2 Interrupt Priority Register n 0x308 32 read-write 0 0xFFFFFFFF PRI_0 Priority of interrupt 0 0 8 read-write PRI_1 Priority of interrupt 1 8 8 read-write PRI_2 Priority of interrupt 2 16 8 read-write PRI_3 Priority of interrupt 3 24 8 read-write S32_NVIC_IPR3 Interrupt Priority Register n 0x30C 32 read-write 0 0xFFFFFFFF PRI_0 Priority of interrupt 0 0 8 read-write PRI_1 Priority of interrupt 1 8 8 read-write PRI_2 Priority of interrupt 2 16 8 read-write PRI_3 Priority of interrupt 3 24 8 read-write S32_NVIC_IPR4 Interrupt Priority Register n 0x310 32 read-write 0 0xFFFFFFFF PRI_0 Priority of interrupt 0 0 8 read-write PRI_1 Priority of interrupt 1 8 8 read-write PRI_2 Priority of interrupt 2 16 8 read-write PRI_3 Priority of interrupt 3 24 8 read-write S32_NVIC_IPR5 Interrupt Priority Register n 0x314 32 read-write 0 0xFFFFFFFF PRI_0 Priority of interrupt 0 0 8 read-write PRI_1 Priority of interrupt 1 8 8 read-write PRI_2 Priority of interrupt 2 16 8 read-write PRI_3 Priority of interrupt 3 24 8 read-write S32_NVIC_IPR6 Interrupt Priority Register n 0x318 32 read-write 0 0xFFFFFFFF PRI_0 Priority of interrupt 0 0 8 read-write PRI_1 Priority of interrupt 1 8 8 read-write PRI_2 Priority of interrupt 2 16 8 read-write PRI_3 Priority of interrupt 3 24 8 read-write S32_NVIC_IPR7 Interrupt Priority Register n 0x31C 32 read-write 0 0xFFFFFFFF PRI_0 Priority of interrupt 0 0 8 read-write PRI_1 Priority of interrupt 1 8 8 read-write PRI_2 Priority of interrupt 2 16 8 read-write PRI_3 Priority of interrupt 3 24 8 read-write LMEM Local Memory Controller LMEM_ 0xE0082000 0 0x24 registers LMEM_PCCCR Cache control register 0 32 read-write 0 0xFFFFFFFF ENCACHE Cache enable 0 1 read-write 0 Cache disabled #0 1 Cache enabled #1 PCCR2 Forces all cacheable spaces to write through 2 1 read-write PCCR3 Forces no allocation on cache misses (must also have PCCR2 asserted) 3 1 read-write INVW0 Invalidate Way 0 24 1 read-write 0 No operation #0 1 When setting the GO bit, invalidate all lines in way 0. #1 PUSHW0 Push Way 0 25 1 read-write 0 No operation #0 1 When setting the GO bit, push all modified lines in way 0 #1 INVW1 Invalidate Way 1 26 1 read-write 0 No operation #0 1 When setting the GO bit, invalidate all lines in way 1 #1 PUSHW1 Push Way 1 27 1 read-write 0 No operation #0 1 When setting the GO bit, push all modified lines in way 1 #1 GO Initiate Cache Command 31 1 read-write 0 Write: no effect. Read: no cache command active. #0 1 Write: initiate command indicated by bits 27-24. Read: cache command active. #1 LMEM_PCCLCR Cache line control register 0x4 32 read-write 0 0xFFFFFFFF LGO Initiate Cache Line Command 0 1 read-write 0 Write: no effect. Read: no line command active. #0 1 Write: initiate line command indicated by bits 27-24. Read: line command active. #1 CACHEADDR Cache address 2 12 read-write WSEL Way select 14 1 read-write 0 Way 0 #0 1 Way 1 #1 TDSEL Tag/Data Select 16 1 read-write 0 Data #0 1 Tag #1 LCIVB Line Command Initial Valid Bit 20 1 read-write LCIMB Line Command Initial Modified Bit 21 1 read-write LCWAY Line Command Way 22 1 read-write LCMD Line Command 24 2 read-write 00 Search and read or write #00 01 Invalidate #01 10 Push #10 11 Clear #11 LADSEL Line Address Select 26 1 read-write 0 Cache address #0 1 Physical address #1 LACC Line access type 27 1 read-write 0 Read #0 1 Write #1 LMEM_PCCSAR Cache search address register 0x8 32 read-write 0 0xFFFFFFFF LGO Initiate Cache Line Command 0 1 read-write 0 Write: no effect. Read: no line command active. #0 1 Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active. #1 PHYADDR Physical Address 2 30 read-write LMEM_PCCCVR Cache read/write value register 0xC 32 read-write 0 0xFFFFFFFF DATA Cache read/write Data 0 32 read-write PCCRMR Cache regions mode register 0x20 32 read-write 0xAA0FA000 0xFFFFFFFF R15 Region 15 mode 0 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R14 Region 14 mode 2 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R13 Region 13 mode 4 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R12 Region 12 mode 6 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R11 Region 11 mode 8 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R10 Region 10 mode 10 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R9 Region 9 mode 12 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R8 Region 8 mode 14 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R7 Region 7 mode 16 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R6 Region 6 mode 18 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R5 Region 5 mode 20 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R4 Region 4 mode 22 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R3 Region 3 mode 24 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R2 Region 2 mode 26 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R1 Region 1 mode 28 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R0 Region 0 mode 30 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 MCM Core Platform Miscellaneous Control Module MCM_ 0xF0003000 0x8 0x4A0 registers PLASC Crossbar Switch (AXBS) Slave Configuration 0x8 16 read-only 0x7 0xFFFF ASC Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. 0 8 read-only 0 A bus slave connection to AXBS input port n is absent #0 1 A bus slave connection to AXBS input port n is present #1 PLAMC Crossbar Switch (AXBS) Master Configuration 0xA 16 read-only 0x7 0xFFFF AMC Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 0 8 read-only 0 A bus master connection to AXBS input port n is absent #0 1 A bus master connection to AXBS input port n is present #1 CPCR Core Platform Control Register 0xC 32 read-write 0 0xFFFFFFAF HLT_FSM_ST AXBS Halt State Machine Status 0 2 read-only 00 Waiting for request #00 01 Waiting for platform idle #01 11 Platform stalled #11 10 Unused state #10 AXBS_HLT_REQ AXBS Halt Request 2 1 read-only 0 AXBS is not receiving halt request #0 1 AXBS is receiving halt request #1 AXBS_HLTD AXBS Halted 3 1 read-only 0 AXBS is not currently halted #0 1 AXBS is currently halted #1 FMC_PF_IDLE Flash Memory Controller Program Flash Idle 4 1 read-only 0 FMC program flash is not idle #0 1 FMC program flash is currently idle #1 PBRIDGE_IDLE Peripheral Bridge Idle 6 1 read-only 0 PBRIDGE is not idle #0 1 PBRIDGE is currently idle #1 CBRR Crossbar Round-robin Arbitration Enable 9 1 read-write 0 Fixed-priority arbitration #0 1 Round-robin arbitration #1 PID Process ID Register 0x30 32 read-write 0 0xFFFFFFFF PID M0_PID and M1_PID for MPU 0 8 read-write CPO Compute Operation Control Register 0x40 32 read-write 0 0xFFFFFFFF CPOREQ Compute Operation Request 0 1 read-write 0 Request is cleared. #0 1 Request Compute Operation. #1 CPOACK Compute Operation Acknowledge 1 1 read-only 0 Compute operation entry has not completed or compute operation exit has completed. #0 1 Compute operation entry has completed or compute operation exit has not completed. #1 CPOWOI Compute Operation Wakeup On Interrupt 2 1 read-write 0 No effect. #0 1 When set, the CPOREQ is cleared on any interrupt or exception vector fetch. #1 LMDR0 Local Memory Descriptor Register 0x400 32 read-write 0 0 CF0 Control Field 0 0 4 read-write MT Memory Type 13 3 read-only 000 SRAM_L #000 001 SRAM_U #001 DPW LMEM Data Path Width. This field defines the width of the local memory. 17 3 read-only 010 LMEMn 32-bits wide #010 011 LMEMn 64-bits wide #011 WY Level 1 Cache Ways 20 4 read-only 0000 No Cache #0000 0010 2-Way Set Associative #0010 0100 4-Way Set Associative #0100 LMSZ LMEM Size 24 4 read-only 0000 no LMEMn (0 KB) #0000 0001 1 KB LMEMn #0001 0010 2 KB LMEMn #0010 0011 4 KB LMEMn #0011 0100 8 KB LMEMn #0100 0101 16 KB LMEMn #0101 0110 32 KB LMEMn #0110 0111 64 KB LMEMn #0111 1000 128 KB LMEMn #1000 1001 256 KB LMEMn #1001 1010 512 KB LMEMn #1010 1011 1024 KB LMEMn #1011 1100 2048 KB LMEMn #1100 1101 4096 KB LMEMn #1101 1110 8192 KB LMEMn #1110 1111 16384 KB LMEMn #1111 LMSZH LMEM Size Hole 28 1 read-only 0 LMEMn is a power-of-2 capacity. #0 1 LMEMn is not a power-of-2, with a capacity is 0.75 * LMSZ. #1 V Local Memory Valid 31 1 read-only 0 LMEMn is not present. #0 1 LMEMn is present. #1 LMDR1 Local Memory Descriptor Register 0x404 32 read-write 0 0 CF0 Control Field 0 0 4 read-write MT Memory Type 13 3 read-only 000 SRAM_L #000 001 SRAM_U #001 DPW LMEM Data Path Width. This field defines the width of the local memory. 17 3 read-only 010 LMEMn 32-bits wide #010 011 LMEMn 64-bits wide #011 WY Level 1 Cache Ways 20 4 read-only 0000 No Cache #0000 0010 2-Way Set Associative #0010 0100 4-Way Set Associative #0100 LMSZ LMEM Size 24 4 read-only 0000 no LMEMn (0 KB) #0000 0001 1 KB LMEMn #0001 0010 2 KB LMEMn #0010 0011 4 KB LMEMn #0011 0100 8 KB LMEMn #0100 0101 16 KB LMEMn #0101 0110 32 KB LMEMn #0110 0111 64 KB LMEMn #0111 1000 128 KB LMEMn #1000 1001 256 KB LMEMn #1001 1010 512 KB LMEMn #1010 1011 1024 KB LMEMn #1011 1100 2048 KB LMEMn #1100 1101 4096 KB LMEMn #1101 1110 8192 KB LMEMn #1110 1111 16384 KB LMEMn #1111 LMSZH LMEM Size Hole 28 1 read-only 0 LMEMn is a power-of-2 capacity. #0 1 LMEMn is not a power-of-2, with a capacity is 0.75 * LMSZ. #1 V Local Memory Valid 31 1 read-only 0 LMEMn is not present. #0 1 LMEMn is present. #1 LMDR2 Local Memory Descriptor Register2 0x408 32 read-write 0x842440A0 0xFFFFFFFF CF1 Control Field 1 4 4 read-write MT Memory Type 13 3 read-only 010 PC Cache #010 DPW LMEM Data Path Width. This field defines the width of the local memory. 17 3 read-only 010 LMEMn 32-bits wide #010 011 LMEMn 64-bits wide #011 WY Level 1 Cache Ways 20 4 read-only 0000 No Cache #0000 0010 2-Way Set Associative #0010 0100 4-Way Set Associative #0100 LMSZ LMEM Size 24 4 read-only 0100 4 KB LMEMn #0100 LMSZH LMEM Size Hole 28 1 read-only 0 LMEMn is a power-of-2 capacity. #0 1 LMEMn is not a power-of-2, with a capacity is 0.75 * LMSZ. #1 V Local Memory Valid 31 1 read-only 0 LMEMn is not present. #0 1 LMEMn is present. #1 LMPECR LMEM Parity and ECC Control Register 0x480 32 read-write 0 0xFFFFFFFF ERNCR Enable RAM ECC Noncorrectable Reporting 0 1 read-write 0 Reporting disabled #0 1 Reporting enabled #1 ER1BR Enable RAM ECC 1 Bit Reporting 8 1 read-write 0 Reporting disabled #0 1 Reporting enabled #1 LMPEIR LMEM Parity and ECC Interrupt Register 0x488 32 read-write 0 0xFFFFFFFF ENC ENCn = ECC Noncorrectable Error n 0 8 read-write E1B E1Bn = ECC 1-bit Error n 8 8 read-write PEELOC Parity or ECC Error Location 24 5 read-only 00 Non-correctable ECC event from SRAM_L #00000 01 Non-correctable ECC event from SRAM_U #00001 V Valid Bit 31 1 read-only LMFAR LMEM Fault Address Register 0x490 32 read-only 0 0xFFFFFFFF EFADD ECC Fault Address 0 32 read-only LMFATR LMEM Fault Attribute Register 0x494 32 read-only 0 0xFFFFFFFF PEFPRT Parity/ECC Fault Protection 0 4 read-only PEFSIZE Parity/ECC Fault Master Size 4 3 read-only 000 8-bit access #000 001 16-bit access #001 010 32-bit access #010 011 64-bit access #011 PEFW Parity/ECC Fault Write 7 1 read-only PEFMST Parity/ECC Fault Master Number 8 8 read-only OVR Overrun 31 1 read-only LMFDHR LMEM Fault Data High Register 0x4A0 32 read-only 0 0xFFFFFFFF PEFDH Parity or ECC Fault Data High 0 32 read-only LMFDLR LMEM Fault Data Low Register 0x4A4 32 read-only 0 0xFFFFFFFF PEFDL Parity or ECC Fault Data Low 0 32 read-only