xobs/s32k118.rs
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Re added can interrupt stuff that was erronously removed previously

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This commit is contained in:
Kjetil Kjeka 2017-10-04 22:21:51 +02:00
parent 4e072bc9d4
commit 139fb8ff79
2 changed files with 53 additions and 8 deletions
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27
S32K144.svd
View File

@ -33513,18 +33513,45 @@
</register> </register>
</registers> </registers>
</peripheral> </peripheral>
<peripheral derivedFrom="CAN0"> <name>CAN1</name> <peripheral derivedFrom="CAN0"> <name>CAN1</name>
<description>Flex Controller Area Network module</description> <description>Flex Controller Area Network module</description>
<groupName>CAN</groupName> <groupName>CAN</groupName>
<prependToName>CAN1_</prependToName> <prependToName>CAN1_</prependToName>
<baseAddress>0x40025000</baseAddress> <baseAddress>0x40025000</baseAddress>
<interrupt>
<name>CAN1_ORed</name>
<value>85</value>
</interrupt>
<interrupt>
<name>CAN1_Error</name>
<value>86</value>
</interrupt>
<interrupt>
<name>CAN1_ORed_0_15_MB</name>
<value>88</value>
</interrupt>
</peripheral> </peripheral>
<peripheral derivedFrom="CAN0"> <name>CAN2</name> <peripheral derivedFrom="CAN0"> <name>CAN2</name>
<description>Flex Controller Area Network module</description> <description>Flex Controller Area Network module</description>
<groupName>CAN</groupName> <groupName>CAN</groupName>
<prependToName>CAN2_</prependToName> <prependToName>CAN2_</prependToName>
<baseAddress>0x4002B000</baseAddress> <baseAddress>0x4002B000</baseAddress>
<interrupt>
<name>CAN2_ORed</name>
<value>92</value>
</interrupt>
<interrupt>
<name>CAN2_Error</name>
<value>93</value>
</interrupt>
<interrupt>
<name>CAN2_ORed_0_15_MB</name>
<value>95</value>
</interrupt>
</peripheral> </peripheral>
<peripheral> <name>FTM0</name> <peripheral> <name>FTM0</name>
<description>FlexTimer Module</description> <description>FlexTimer Module</description>
<groupName>FTM</groupName> <groupName>FTM</groupName>

34
src/interrupt/mod.rs
View File

@ -10,7 +10,7 @@ global_asm!(
); );
#[cfg(feature = "rt")] #[cfg(feature = "rt")]
global_asm!( global_asm!(
"\n.weak DMA0\nDMA0 = DH_TRAMPOLINE\n.weak DMA1\nDMA1 = DH_TRAMPOLINE\n.weak DMA2\nDMA2 = DH_TRAMPOLINE\n.weak DMA3\nDMA3 = DH_TRAMPOLINE\n.weak DMA4\nDMA4 = DH_TRAMPOLINE\n.weak DMA5\nDMA5 = DH_TRAMPOLINE\n.weak DMA6\nDMA6 = DH_TRAMPOLINE\n.weak DMA7\nDMA7 = DH_TRAMPOLINE\n.weak DMA8\nDMA8 = DH_TRAMPOLINE\n.weak DMA9\nDMA9 = DH_TRAMPOLINE\n.weak DMA10\nDMA10 = DH_TRAMPOLINE\n.weak DMA11\nDMA11 = DH_TRAMPOLINE\n.weak DMA12\nDMA12 = DH_TRAMPOLINE\n.weak DMA13\nDMA13 = DH_TRAMPOLINE\n.weak DMA14\nDMA14 = DH_TRAMPOLINE\n.weak DMA15\nDMA15 = DH_TRAMPOLINE\n.weak DMA_ERROR\nDMA_ERROR = DH_TRAMPOLINE\n.weak MCM\nMCM = DH_TRAMPOLINE\n.weak FTFC\nFTFC = DH_TRAMPOLINE\n.weak READ_COLLISION\nREAD_COLLISION = DH_TRAMPOLINE\n.weak LVD_LVW\nLVD_LVW = DH_TRAMPOLINE\n.weak FTFC_FAULT\nFTFC_FAULT = DH_TRAMPOLINE\n.weak WDOG_EWM\nWDOG_EWM = DH_TRAMPOLINE\n.weak RCM\nRCM = DH_TRAMPOLINE\n.weak LPI2C0_MASTER\nLPI2C0_MASTER = DH_TRAMPOLINE\n.weak LPI2C0_SLAVE\nLPI2C0_SLAVE = DH_TRAMPOLINE\n.weak LPSPI0\nLPSPI0 = DH_TRAMPOLINE\n.weak LPSPI1\nLPSPI1 = DH_TRAMPOLINE\n.weak LPSPI2\nLPSPI2 = DH_TRAMPOLINE\n.weak LPUART0_RXTX\nLPUART0_RXTX = DH_TRAMPOLINE\n.weak LPUART1_RXTX\nLPUART1_RXTX = DH_TRAMPOLINE\n.weak LPUART2_RXTX\nLPUART2_RXTX = DH_TRAMPOLINE\n.weak ADC0\nADC0 = DH_TRAMPOLINE\n.weak ADC1\nADC1 = DH_TRAMPOLINE\n.weak CMP0\nCMP0 = DH_TRAMPOLINE\n.weak ERM_SINGLE_FAULT\nERM_SINGLE_FAULT = DH_TRAMPOLINE\n.weak ERM_DOUBLE_FAULT\nERM_DOUBLE_FAULT = DH_TRAMPOLINE\n.weak RTC\nRTC = DH_TRAMPOLINE\n.weak RTC_SECONDS\nRTC_SECONDS = DH_TRAMPOLINE\n.weak LPIT0_CH0\nLPIT0_CH0 = DH_TRAMPOLINE\n.weak LPIT0_CH1\nLPIT0_CH1 = DH_TRAMPOLINE\n.weak LPIT0_CH2\nLPIT0_CH2 = DH_TRAMPOLINE\n.weak LPIT0_CH3\nLPIT0_CH3 = DH_TRAMPOLINE\n.weak PDB0\nPDB0 = DH_TRAMPOLINE\n.weak SCG\nSCG = DH_TRAMPOLINE\n.weak LPTMR0\nLPTMR0 = DH_TRAMPOLINE\n.weak PORTA\nPORTA = DH_TRAMPOLINE\n.weak PORTB\nPORTB = DH_TRAMPOLINE\n.weak PORTC\nPORTC = DH_TRAMPOLINE\n.weak PORTD\nPORTD = DH_TRAMPOLINE\n.weak PORTE\nPORTE = DH_TRAMPOLINE\n.weak PDB1\nPDB1 = DH_TRAMPOLINE\n.weak FLEXIO\nFLEXIO = DH_TRAMPOLINE\n.weak CAN0_ORED\nCAN0_ORED = DH_TRAMPOLINE\n.weak CAN0_ERROR\nCAN0_ERROR = DH_TRAMPOLINE\n.weak CAN0_WAKE_UP\nCAN0_WAKE_UP = DH_TRAMPOLINE\n.weak CAN0_ORED_0_15_MB\nCAN0_ORED_0_15_MB = DH_TRAMPOLINE\n.weak CAN0_ORED_16_31_MB\nCAN0_ORED_16_31_MB = DH_TRAMPOLINE\n.weak FTM0_CH0_CH1\nFTM0_CH0_CH1 = DH_TRAMPOLINE\n.weak FTM0_CH2_CH3\nFTM0_CH2_CH3 = DH_TRAMPOLINE\n.weak FTM0_CH4_CH5\nFTM0_CH4_CH5 = DH_TRAMPOLINE\n.weak FTM0_CH6_CH7\nFTM0_CH6_CH7 = DH_TRAMPOLINE\n.weak FTM0_FAULT\nFTM0_FAULT = DH_TRAMPOLINE\n.weak FTM0_OVF_RELOAD\nFTM0_OVF_RELOAD = DH_TRAMPOLINE\n.weak FTM1_CH0_CH1\nFTM1_CH0_CH1 = DH_TRAMPOLINE\n.weak FTM1_CH2_CH3\nFTM1_CH2_CH3 = DH_TRAMPOLINE\n.weak FTM1_CH4_CH5\nFTM1_CH4_CH5 = DH_TRAMPOLINE\n.weak FTM1_CH6_CH7\nFTM1_CH6_CH7 = DH_TRAMPOLINE\n.weak FTM1_FAULT\nFTM1_FAULT = DH_TRAMPOLINE\n.weak FTM1_OVF_RELOAD\nFTM1_OVF_RELOAD = DH_TRAMPOLINE\n.weak FTM2_CH0_CH1\nFTM2_CH0_CH1 = DH_TRAMPOLINE\n.weak FTM2_CH2_CH3\nFTM2_CH2_CH3 = DH_TRAMPOLINE\n.weak FTM2_CH4_CH5\nFTM2_CH4_CH5 = DH_TRAMPOLINE\n.weak FTM2_CH6_CH7\nFTM2_CH6_CH7 = DH_TRAMPOLINE\n.weak FTM2_FAULT\nFTM2_FAULT = DH_TRAMPOLINE\n.weak FTM2_OVF_RELOAD\nFTM2_OVF_RELOAD = DH_TRAMPOLINE\n.weak FTM3_CH0_CH1\nFTM3_CH0_CH1 = DH_TRAMPOLINE\n.weak FTM3_CH2_CH3\nFTM3_CH2_CH3 = DH_TRAMPOLINE\n.weak FTM3_CH4_CH5\nFTM3_CH4_CH5 = DH_TRAMPOLINE\n.weak FTM3_CH6_CH7\nFTM3_CH6_CH7 = DH_TRAMPOLINE\n.weak FTM3_FAULT\nFTM3_FAULT = DH_TRAMPOLINE\n.weak FTM3_OVF_RELOAD\nFTM3_OVF_RELOAD = DH_TRAMPOLINE" "\n.weak DMA0\nDMA0 = DH_TRAMPOLINE\n.weak DMA1\nDMA1 = DH_TRAMPOLINE\n.weak DMA2\nDMA2 = DH_TRAMPOLINE\n.weak DMA3\nDMA3 = DH_TRAMPOLINE\n.weak DMA4\nDMA4 = DH_TRAMPOLINE\n.weak DMA5\nDMA5 = DH_TRAMPOLINE\n.weak DMA6\nDMA6 = DH_TRAMPOLINE\n.weak DMA7\nDMA7 = DH_TRAMPOLINE\n.weak DMA8\nDMA8 = DH_TRAMPOLINE\n.weak DMA9\nDMA9 = DH_TRAMPOLINE\n.weak DMA10\nDMA10 = DH_TRAMPOLINE\n.weak DMA11\nDMA11 = DH_TRAMPOLINE\n.weak DMA12\nDMA12 = DH_TRAMPOLINE\n.weak DMA13\nDMA13 = DH_TRAMPOLINE\n.weak DMA14\nDMA14 = DH_TRAMPOLINE\n.weak DMA15\nDMA15 = DH_TRAMPOLINE\n.weak DMA_ERROR\nDMA_ERROR = DH_TRAMPOLINE\n.weak MCM\nMCM = DH_TRAMPOLINE\n.weak FTFC\nFTFC = DH_TRAMPOLINE\n.weak READ_COLLISION\nREAD_COLLISION = DH_TRAMPOLINE\n.weak LVD_LVW\nLVD_LVW = DH_TRAMPOLINE\n.weak FTFC_FAULT\nFTFC_FAULT = DH_TRAMPOLINE\n.weak WDOG_EWM\nWDOG_EWM = DH_TRAMPOLINE\n.weak RCM\nRCM = DH_TRAMPOLINE\n.weak LPI2C0_MASTER\nLPI2C0_MASTER = DH_TRAMPOLINE\n.weak LPI2C0_SLAVE\nLPI2C0_SLAVE = DH_TRAMPOLINE\n.weak LPSPI0\nLPSPI0 = DH_TRAMPOLINE\n.weak LPSPI1\nLPSPI1 = DH_TRAMPOLINE\n.weak LPSPI2\nLPSPI2 = DH_TRAMPOLINE\n.weak LPUART0_RXTX\nLPUART0_RXTX = DH_TRAMPOLINE\n.weak LPUART1_RXTX\nLPUART1_RXTX = DH_TRAMPOLINE\n.weak LPUART2_RXTX\nLPUART2_RXTX = DH_TRAMPOLINE\n.weak ADC0\nADC0 = DH_TRAMPOLINE\n.weak ADC1\nADC1 = DH_TRAMPOLINE\n.weak CMP0\nCMP0 = DH_TRAMPOLINE\n.weak ERM_SINGLE_FAULT\nERM_SINGLE_FAULT = DH_TRAMPOLINE\n.weak ERM_DOUBLE_FAULT\nERM_DOUBLE_FAULT = DH_TRAMPOLINE\n.weak RTC\nRTC = DH_TRAMPOLINE\n.weak RTC_SECONDS\nRTC_SECONDS = DH_TRAMPOLINE\n.weak LPIT0_CH0\nLPIT0_CH0 = DH_TRAMPOLINE\n.weak LPIT0_CH1\nLPIT0_CH1 = DH_TRAMPOLINE\n.weak LPIT0_CH2\nLPIT0_CH2 = DH_TRAMPOLINE\n.weak LPIT0_CH3\nLPIT0_CH3 = DH_TRAMPOLINE\n.weak PDB0\nPDB0 = DH_TRAMPOLINE\n.weak SCG\nSCG = DH_TRAMPOLINE\n.weak LPTMR0\nLPTMR0 = DH_TRAMPOLINE\n.weak PORTA\nPORTA = DH_TRAMPOLINE\n.weak PORTB\nPORTB = DH_TRAMPOLINE\n.weak PORTC\nPORTC = DH_TRAMPOLINE\n.weak PORTD\nPORTD = DH_TRAMPOLINE\n.weak PORTE\nPORTE = DH_TRAMPOLINE\n.weak PDB1\nPDB1 = DH_TRAMPOLINE\n.weak FLEXIO\nFLEXIO = DH_TRAMPOLINE\n.weak CAN0_ORED\nCAN0_ORED = DH_TRAMPOLINE\n.weak CAN0_ERROR\nCAN0_ERROR = DH_TRAMPOLINE\n.weak CAN0_WAKE_UP\nCAN0_WAKE_UP = DH_TRAMPOLINE\n.weak CAN0_ORED_0_15_MB\nCAN0_ORED_0_15_MB = DH_TRAMPOLINE\n.weak CAN0_ORED_16_31_MB\nCAN0_ORED_16_31_MB = DH_TRAMPOLINE\n.weak CAN1_ORED\nCAN1_ORED = DH_TRAMPOLINE\n.weak CAN1_ERROR\nCAN1_ERROR = DH_TRAMPOLINE\n.weak CAN1_ORED_0_15_MB\nCAN1_ORED_0_15_MB = DH_TRAMPOLINE\n.weak CAN2_ORED\nCAN2_ORED = DH_TRAMPOLINE\n.weak CAN2_ERROR\nCAN2_ERROR = DH_TRAMPOLINE\n.weak CAN2_ORED_0_15_MB\nCAN2_ORED_0_15_MB = DH_TRAMPOLINE\n.weak FTM0_CH0_CH1\nFTM0_CH0_CH1 = DH_TRAMPOLINE\n.weak FTM0_CH2_CH3\nFTM0_CH2_CH3 = DH_TRAMPOLINE\n.weak FTM0_CH4_CH5\nFTM0_CH4_CH5 = DH_TRAMPOLINE\n.weak FTM0_CH6_CH7\nFTM0_CH6_CH7 = DH_TRAMPOLINE\n.weak FTM0_FAULT\nFTM0_FAULT = DH_TRAMPOLINE\n.weak FTM0_OVF_RELOAD\nFTM0_OVF_RELOAD = DH_TRAMPOLINE\n.weak FTM1_CH0_CH1\nFTM1_CH0_CH1 = DH_TRAMPOLINE\n.weak FTM1_CH2_CH3\nFTM1_CH2_CH3 = DH_TRAMPOLINE\n.weak FTM1_CH4_CH5\nFTM1_CH4_CH5 = DH_TRAMPOLINE\n.weak FTM1_CH6_CH7\nFTM1_CH6_CH7 = DH_TRAMPOLINE\n.weak FTM1_FAULT\nFTM1_FAULT = DH_TRAMPOLINE\n.weak FTM1_OVF_RELOAD\nFTM1_OVF_RELOAD = DH_TRAMPOLINE\n.weak FTM2_CH0_CH1\nFTM2_CH0_CH1 = DH_TRAMPOLINE\n.weak FTM2_CH2_CH3\nFTM2_CH2_CH3 = DH_TRAMPOLINE\n.weak FTM2_CH4_CH5\nFTM2_CH4_CH5 = DH_TRAMPOLINE\n.weak FTM2_CH6_CH7\nFTM2_CH6_CH7 = DH_TRAMPOLINE\n.weak FTM2_FAULT\nFTM2_FAULT = DH_TRAMPOLINE\n.weak FTM2_OVF_RELOAD\nFTM2_OVF_RELOAD = DH_TRAMPOLINE\n.weak FTM3_CH0_CH1\nFTM3_CH0_CH1 = DH_TRAMPOLINE\n.weak FTM3_CH2_CH3\nFTM3_CH2_CH3 = DH_TRAMPOLINE\n.weak FTM3_CH4_CH5\nFTM3_CH4_CH5 = DH_TRAMPOLINE\n.weak FTM3_CH6_CH7\nFTM3_CH6_CH7 = DH_TRAMPOLINE\n.weak FTM3_FAULT\nFTM3_FAULT = DH_TRAMPOLINE\n.weak FTM3_OVF_RELOAD\nFTM3_OVF_RELOAD = DH_TRAMPOLINE"
); );
#[cfg(feature = "rt")] #[cfg(feature = "rt")]
extern "C" { extern "C" {
@ -72,6 +72,12 @@ extern "C" {
fn CAN0_WAKE_UP(); fn CAN0_WAKE_UP();
fn CAN0_ORED_0_15_MB(); fn CAN0_ORED_0_15_MB();
fn CAN0_ORED_16_31_MB(); fn CAN0_ORED_16_31_MB();
fn CAN1_ORED();
fn CAN1_ERROR();
fn CAN1_ORED_0_15_MB();
fn CAN2_ORED();
fn CAN2_ERROR();
fn CAN2_ORED_0_15_MB();
fn FTM0_CH0_CH1(); fn FTM0_CH0_CH1();
fn FTM0_CH2_CH3(); fn FTM0_CH2_CH3();
fn FTM0_CH4_CH5(); fn FTM0_CH4_CH5();
@ -189,17 +195,17 @@ pub static INTERRUPTS: [Option<unsafe extern "C" fn()>; 123] = [
Some(CAN0_ORED_16_31_MB), Some(CAN0_ORED_16_31_MB),
None, None,
None, None,
Some(CAN1_ORED),
Some(CAN1_ERROR),
None,
Some(CAN1_ORED_0_15_MB),
None, None,
None, None,
None, None,
Some(CAN2_ORED),
Some(CAN2_ERROR),
None, None,
None, Some(CAN2_ORED_0_15_MB),
None,
None,
None,
None,
None,
None,
None, None,
None, None,
None, None,
@ -288,6 +294,12 @@ pub enum Interrupt {
#[doc = "80 - CAN0_Wake_Up"] CAN0_WAKE_UP, #[doc = "80 - CAN0_Wake_Up"] CAN0_WAKE_UP,
#[doc = "81 - CAN0_ORed_0_15_MB"] CAN0_ORED_0_15_MB, #[doc = "81 - CAN0_ORed_0_15_MB"] CAN0_ORED_0_15_MB,
#[doc = "82 - CAN0_ORed_16_31_MB"] CAN0_ORED_16_31_MB, #[doc = "82 - CAN0_ORed_16_31_MB"] CAN0_ORED_16_31_MB,
#[doc = "85 - CAN1_ORed"] CAN1_ORED,
#[doc = "86 - CAN1_Error"] CAN1_ERROR,
#[doc = "88 - CAN1_ORed_0_15_MB"] CAN1_ORED_0_15_MB,
#[doc = "92 - CAN2_ORed"] CAN2_ORED,
#[doc = "93 - CAN2_Error"] CAN2_ERROR,
#[doc = "95 - CAN2_ORed_0_15_MB"] CAN2_ORED_0_15_MB,
#[doc = "99 - FTM0_Ch0_Ch1"] FTM0_CH0_CH1, #[doc = "99 - FTM0_Ch0_Ch1"] FTM0_CH0_CH1,
#[doc = "100 - FTM0_Ch2_Ch3"] FTM0_CH2_CH3, #[doc = "100 - FTM0_Ch2_Ch3"] FTM0_CH2_CH3,
#[doc = "101 - FTM0_Ch4_Ch5"] FTM0_CH4_CH5, #[doc = "101 - FTM0_Ch4_Ch5"] FTM0_CH4_CH5,
@ -375,6 +387,12 @@ unsafe impl Nr for Interrupt {
Interrupt::CAN0_WAKE_UP => 80, Interrupt::CAN0_WAKE_UP => 80,
Interrupt::CAN0_ORED_0_15_MB => 81, Interrupt::CAN0_ORED_0_15_MB => 81,
Interrupt::CAN0_ORED_16_31_MB => 82, Interrupt::CAN0_ORED_16_31_MB => 82,
Interrupt::CAN1_ORED => 85,
Interrupt::CAN1_ERROR => 86,
Interrupt::CAN1_ORED_0_15_MB => 88,
Interrupt::CAN2_ORED => 92,
Interrupt::CAN2_ERROR => 93,
Interrupt::CAN2_ORED_0_15_MB => 95,
Interrupt::FTM0_CH0_CH1 => 99, Interrupt::FTM0_CH0_CH1 => 99,
Interrupt::FTM0_CH2_CH3 => 100, Interrupt::FTM0_CH2_CH3 => 100,
Interrupt::FTM0_CH4_CH5 => 101, Interrupt::FTM0_CH4_CH5 => 101,