Sean Cross 79f515d63e extmem: invert logic on "Cache enable" ... This seems to be inverted in hardware, at least according to what actually works. Signed-off-by: Sean Cross <sean@xobs.io>		2023-08-05 19:27:37 +08:00
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ESP32_SPIController.cs	initial commit	2023-07-24 12:00:46 +08:00
ESP32_UART.cs	initial commit	2023-07-24 12:00:46 +08:00
ESP32S3_EFUSE.cs	initial commit	2023-07-24 12:00:46 +08:00
ESP32S3_EXTMEM.cs	extmem: invert logic on "Cache enable"	2023-08-05 19:27:37 +08:00
ESP32S3_GPIO.cs	initial commit	2023-07-24 12:00:46 +08:00
ESP32S3_Interrupt_Core0.cs	add interrupt core draft	2023-07-27 15:57:29 +08:00
ESP32S3_RTC_CNTL.cs	initial commit	2023-07-24 12:00:46 +08:00
ESP32S3_SPIController.cs	many hacks to get something booting	2023-08-05 18:46:01 +08:00