From 1283cd2eff7a14c937861ac205bc7c5ab6becfc2 Mon Sep 17 00:00:00 2001 From: Sean Cross Date: Sat, 5 Aug 2023 19:54:44 +0800 Subject: [PATCH] peripherals: add rtc/i2c/pwdet combo block This undocumented block appears to do something important, but we just need to report that i2c is locked. Signed-off-by: Sean Cross --- badge.repl | 5 +- badge.resc | 162 +-------------------------- peripherals/ESP32S3_RTC_I2C_PWDET.cs | 99 ++++++++++++++++ 3 files changed, 103 insertions(+), 163 deletions(-) create mode 100644 peripherals/ESP32S3_RTC_I2C_PWDET.cs diff --git a/badge.repl b/badge.repl index 937b37e..f440f03 100644 --- a/badge.repl +++ b/badge.repl @@ -37,6 +37,8 @@ uart0: UART.ESP32_UART @ sysbus 0x60000000 uart1: UART.ESP32_UART @ sysbus 0x60010000 extmem: Miscellaneous.ESP32S3_EXTMEM @ sysbus 0x600C4000 gpio: GPIOPort.ESP32S3_GPIO @ sysbus 0x60004000 +rtc_i2c_pwdet: Miscellaneous.ESP32S3_RTC_I2C_PWDET @ sysbus 0x6000e000 +rtc_cntl: Miscellaneous.ESP32S3_RTC_CNTL @ sysbus 0x60008000 //spi1: SPI.ESP32_SPIController @ sysbus 0x60002000 @@ -44,9 +46,6 @@ gpio: GPIOPort.ESP32S3_GPIO @ sysbus 0x60004000 efuse: Memory.MappedMemory @ sysbus 0x60007000 size: 0x1000 -// RTC Control -rtc_cntl: Miscellaneous.ESP32S3_RTC_CNTL @ sysbus 0x60008000 - sysbus: init: ApplySVD @esp32s3.svd diff --git a/badge.resc b/badge.resc index 2c21171..22d344e 100644 --- a/badge.resc +++ b/badge.resc @@ -10,6 +10,7 @@ i @peripherals/ESP32_UART.cs i @peripherals/ESP32S3_EXTMEM.cs i @peripherals/ESP32S3_GPIO.cs i @peripherals/ESP32S3_RTC_CNTL.cs +i @peripherals/ESP32S3_RTC_I2C_PWDET.cs using sysbus @@ -37,7 +38,7 @@ sysbus LoadBinary @esp32s3-drom.bin 0x3FF00000 sysbus LoadELF @bootloader.elf #copy_bootrom_data setup_hooks sysbus.cpu -sysbus WriteDoubleWord 0x600c40a0 0x8 +#sysbus WriteDoubleWord 0x600c40a0 0x8 cpu PC 0x40000400 """ @@ -110,72 +111,11 @@ def mc_setup_hooks(cpu): # write address already loaded software bootloader to register self.Machine.SystemBus.WriteDoubleWord(0x3fcedf14, 0x403c9908) - @hook(0x403cf295) - def hook_set_i2c_ctrl(cpu, pc): - log("set i2c ctrl", *args()) - # write address of i2c sysreg control register - self.Machine.SystemBus.WriteDoubleWord(0x403ccb14, 0x600C0018) - - @hook(0x403c99f1) - def hook_cache_hal_init(cpu, pc): - log("cache_hal_init", *args()) - cpu.PC = RegisterValue.Create(0x403c99f4,32) - - @hook (0x403cd59c) - def hook_cache_hal_disable(cpu, pc): - log("cache_hal_disable", *args()) - cpu.PC = RegisterValue.Create(0x403cd59f,32) - - @hook (0x403cd5b7) - def hook_cache_hal_enable(cpu, pc): - log("cache_hal_enable", *args()) - cpu.PC = RegisterValue.Create(0x403cd5ba,32) - - @hook (0x403c9f6f) - def hook_cache_hal_disable2(cpu, pc): - log("cache_hal_disable2", *args()) - cpu.PC = RegisterValue.Create(0x403c9f72,32) - - @hook (0x403c9f94) - def hook_cache_hal_enable2(cpu, pc): - log("cache_hal_enable2", *args()) - cpu.PC = RegisterValue.Create(0x403c9f97,32) - - @hook (0x403cd4c8) - def hook_cache_hal_disable3(cpu, pc): - log("cache_hal_disable3", *args()) - cpu.PC = RegisterValue.Create(0x403cd4cb,32) - - @hook (0x403cd4e3) - def hook_cache_hal_enable3(cpu, pc): - log("cache_hal_enable3", *args()) - cpu.PC = RegisterValue.Create(0x403cd4e6,32) - - @hook (0x403cd50f) - def hook_cache_hal_disable4(cpu, pc): - log("cache_hal_disable4", *args()) - cpu.PC = RegisterValue.Create(0x403cd512,32) - - @hook (0x403cd8f1) - def hook_cache_hal_disable5(cpu, pc): - log("cache_hal_disable5", *args()) - cpu.PC = RegisterValue.Create(0x403cd8f4,32) - - @hook (0x403cd978) - def hook_cache_hal_enable4(cpu, pc): - log("cache_hal_enable4", *args()) - cpu.PC = RegisterValue.Create(0x403cd97b,32) - @hook(0x403c9a1c) def hook_cpu_rev_check(cpu, pc): log("cpu_rev_check", *args()) cpu.PC = RegisterValue.Create(0x403c9a1f,32) - @hook (0x403c9a98) - def hook_skip_rng_init(cpu, pc): - log("skip_rng_init", *args()) - cpu.PC = RegisterValue.Create(0x403c9a9b,32) - @hook (0x403ce971) def hook_skip_part_size_check(cpu, pc): log("skip_part_size_check", *args()) @@ -185,104 +125,6 @@ def mc_setup_hooks(cpu): def hook_skip_flash_check(cpu, pc): log("skip_flash_check", *args()) cpu.PC = RegisterValue.Create(0x403ce1b0,32) - - @hook (0x403cd8c2) - def hook_skip_disable_rng(cpu, pc): - log("skip_disable_rng", *args()) - cpu.PC = RegisterValue.Create(0x403cd8c5,32) - - @hook (0x403cd917) - def hook_skip_hal_map_region(cpu, pc): - log("skip_hal_map_region", *args()) - cpu.PC = RegisterValue.Create(0x403cd91a,32) - - @hook (0x403cd933) - def hook_skip_hal_map_region2(cpu, pc): - log("skip_hal_map_region2", *args()) - cpu.PC = RegisterValue.Create(0x403cd936,32) - -# @hook (0x403cd93c) -# def hook_skip_cache_setup(cpu, pc): -# log("skip_cache_setup", *args()) -# cpu.PC = RegisterValue.Create(0x403cd97b,32) - - @hook (0x403cd8eb) - def hook_image_entry_addr(cpu, pc): - log("image_entry_addr", *args()) - set(A9, 0x42004834) - - @hook (0x4209ec01) - def hook_skip_esp_log_write(cpu, pc): - log("skip_esp_log_write", *args()) - cpu.PC = RegisterValue.Create(0x4209ec04,32) - self.Machine.SystemBus.WriteDoubleWord(0x3fcaa5e8, 0x1) - - @hook (0x4202c611) - def hook_skip_esp_log_write2(cpu, pc): - log("skip_esp_log_write2", *args()) - cpu.PC = RegisterValue.Create(0x4202c614,32) - - @hook (0x4209ec60) - def hook_skip_mem_check(cpu, pc): - log("skip_mem_check", *args()) - cpu.PC = RegisterValue.Create(0x4209ec8c,32) - - @hook (0x420049ba) - def hook_esp_systimer(cpu, pc): - log("esp_systimer", *args()) - cpu.PC = RegisterValue.Create(0x420049bd,32) - - @hook (0x420049c3) - def hook_esp_sysinit(cpu, pc): - log("esp_sysinit", *args()) - cpu.PC = RegisterValue.Create(0x420049c6,32) - - @hook (0x4037dfad) - def hook_spi_flash_chip_init(cpu, pc): - log("spi_flash_chip_init", *args()) - cpu.PC = RegisterValue.Create(0x4037dfb0,32) - - @hook (0x42004a67) - def hook_assert_func(cpu, pc): - log("assert_func", *args()) - cpu.PC = RegisterValue.Create(0x42004a6a,32) - - @hook (0x42008617) - def hook_timer_init(cpu, pc): - log("timer_init", *args()) - set(A10, 0x0) - cpu.PC = RegisterValue.Create(0x4200861a,32) - - @hook (0x40041a7c) - def hook_skip_us_delay(cpu, pc): - log("skip_us_delay", *args()) - set(A2, get(A8)) - cpu.PC = RegisterValue.Create(0x40041a7f,32) - - @hook (0x42004aed) - def hook_delay_skip(cpu, pc): - log("delay_skip", *args()) - cpu.PC = RegisterValue.Create(0x42004af0,32) - - @hook (0x4038a615) - def hook_hal_timer(cpu, pc): - log("hal_timer", *args()) - cpu.PC = RegisterValue.Create(0x42004b11,32) - - @hook (0x4209ecda) - def hook_crosscore_init(cpu, pc): - log("crosscore_init", *args()) - cpu.PC = RegisterValue.Create(0x4209ecdd,32) - - @hook (0x40387f69) - def hook_port_setup_timer(cpu, pc): - log("port_setup_timer", *args()) - cpu.PC = RegisterValue.Create(0x40387f6c,32) - - @hook (0x40386c85) - def hook_timer_get_time(cpu, pc): - log("timer_get_time", *args()) - cpu.PC = RegisterValue.Create(0x40386c88,32) """ runMacro $reset diff --git a/peripherals/ESP32S3_RTC_I2C_PWDET.cs b/peripherals/ESP32S3_RTC_I2C_PWDET.cs new file mode 100644 index 0000000..1e97763 --- /dev/null +++ b/peripherals/ESP32S3_RTC_I2C_PWDET.cs @@ -0,0 +1,99 @@ +// +// Copyright (c) 2010-2023 Antmicro +// Copyright (c) 2011-2015 Realtime Embedded +// +// This file is licensed under the MIT License. +// Full license text is available in 'licenses/MIT.txt'. +// +using System; +using Antmicro.Renode.Peripherals.Bus; +using Antmicro.Renode.Core; +using Antmicro.Renode.Peripherals; +using Antmicro.Renode.Utilities; +using Antmicro.Renode.Logging; +using System.Collections.Generic; +using Antmicro.Renode.Core.Structure.Registers; + +namespace Antmicro.Renode.Peripherals.Miscellaneous +{ + public class ESP32S3_RTC_I2C_PWDET : IBytePeripheral, IDoubleWordPeripheral, IKnownSize + { + public ESP32S3_RTC_I2C_PWDET(Machine machine) + { + var registersMap = new Dictionary + { + {(long)Registers.I2C_MST_ANA_CONF0, new DoubleWordRegister(this) + .WithFlag(2, FieldMode.Read | FieldMode.Write, name: "BBPLL_STOP_FORCE_HIGH") + .WithFlag(3, FieldMode.Read | FieldMode.Write, name: "BBPLL_STOP_FORCE_LOW") + .WithFlag(24, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => true, name: "BBPLL_CAL_DONE") + }, + // {(long)Registers.ANA_CONFIG, new DoubleWordRegister(this) + // .WithValueField(0, 8, FieldMode.Read | FieldMode.Write, name: "CONFIG") + // .WithFlag(17, FieldMode.Read | FieldMode.Write, name: "BBPLL") + // .WithFlag(18, FieldMode.Read | FieldMode.Write, name: "SAR") + // }, + // {(long)Registers.ANA_CONFIG2, new DoubleWordRegister(this) + // .WithFlag(16, FieldMode.Read | FieldMode.Write, name: "SAR_CFG2") + // }, + // {(long)Registers.PWDET_CONF, new DoubleWordRegister(this) + // .WithFlag(6, FieldMode.Read | FieldMode.Write, name: "SAR_POWER_CNTL") + // .WithFlag(7, FieldMode.Read | FieldMode.Write, name: "SAR_POWER_FORCE") + // }, + }; + + registers = new DoubleWordRegisterCollection(this, registersMap); + } + + public uint ReadDoubleWord(long offset) + { + return registers.Read(offset); + } + + public byte ReadByte(long offset) + { + if (offset % 4 != 0) + { + // in the current configuration, only the lowest byte + // contains a meaningful data + return 0; + } + return (byte)ReadDoubleWord(offset); + } + + public void Reset() + { + // base.Reset(); + registers.Reset(); + + // UpdateInterrupts(); + } + + public void WriteDoubleWord(long offset, uint value) + { + registers.Write(offset, value); + } + + public void WriteByte(long offset, byte value) + { + if (offset % 4 != 0) + { + // in the current configuration, only the lowest byte + // contains a meaningful data + return; + } + + WriteDoubleWord(offset, value); + } + + public long Size => 0x17C; + private readonly DoubleWordRegisterCollection registers; + + private enum Registers : long + { + I2C_MST_ANA_CONF0 = 0x40, + ANA_CONFIG = 0x44, + ANA_CONFIG2 = 0x48, + PWDET_CONF = 0x60, + } + } +}