commit 1166c4ce418922ee26013f9fd8d4782c7b258c14 Author: Sean Cross Date: Mon Jul 24 12:00:46 2023 +0800 initial commit Signed-off-by: Sean Cross diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 0000000..f9a88b0 --- /dev/null +++ b/.gitattributes @@ -0,0 +1,41 @@ + +# Various C code +*.h text eol=lf +*.c text eol=lf +*.s text eol=lf +*.S text eol=lf + +# Rust code +*.rs text eol=lf +*.toml text eol=lf +*.lock text eol=lf + +# Misc scripting files +Makefile text eol=lf +*.mk text eol=lf +*.sh text eol=lf +*.ps1 text eol=crlf +*.py text eol=lf + +# Human-readable files +*.md eol=lf +README.* text eol=lf +LICENSE text eol=lf +*.txt text eol=lf + +# Binary files +*.dfu binary +*.png binary +*.jpg binary +*.bin binary +*.elf binary + +# Git configuration files +.gitignore text eol=lf +.gitattributes text eol=lf + +# System description files +*.svd eol=lf + +# JSON +*.json eol=lf diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..f04a95d --- /dev/null +++ b/.gitignore @@ -0,0 +1,48 @@ +**/*.rs.bk +/peripherals.csproj +/emulation/obj + +*.map + +# Emacs +*~ + +# local utility shellscripts +update-precursors.sh +buildpush.ps1 +# local-only routines used to start builds +/*.ps1 +/*.bat +/*.sh +# notes to myself +/*.txt +tools/test-backup-analyze.sh + +# don't record weirdnesses dealing with vscode +.vscode +.vs +settings.json + +# Emacs backup files +*~ + +# Distribution / packaging +.Python +build/ +develop-eggs/ +dist/ +downloads/ +eggs/ +.eggs/ +lib/ +lib64/ +parts/ +sdist/ +var/ +wheels/ +share/python-wheels/ +*.egg-info/ +.installed.cfg +*.egg +*.pyc +MANIFEST diff --git a/README.md b/README.md new file mode 100644 index 0000000..1c2fb76 --- /dev/null +++ b/README.md @@ -0,0 +1,44 @@ +# Platonic RISC-V Device + +Platonic is an ideal system useful for developing an operating system. It does not represent any sort of real hardware, though differences between platforms is minimal. + +## Usage + +For emulation, you will need to install Renode (use the [nightly](https://dl.antmicro.com/projects/renode/builds/) to get `SPI.NORFlash` peripheral support). Then, run `renode` on `xous-release.resc`. For example: + +``` +renode emulation/xous-resc.repl +``` + +## Editing Renode Peripherals + +Renode supports adding peripherals written in C#. For example, many Betrusted peripherals have models created under the `peripherals/` directory. + +Since there is no external compiler, it can be difficult to know if your code is correct. In fact, if you're unfamiliar with C# or the Renode codebase, editing unfamiliar C# code can be a slow exercise in frustration. + +Fortunately, Visual Studio Code is free and has excellent C# tooling. All you need to do is point it at your Renode installation, load the C# plugin, and open a `.cs` file. + +1. Copy `peripherals.csproj.template` to `peripherals.csproj` +2. Open `peripherals.csproj` and point `` to your Renode installation directory. On ubuntu, this may be `/opt/renode/bin/`. +3. Install [C# for VSCode](https://marketplace.visualstudio.com/items?itemName=ms-dotnettools.csharp) +4. You can refer to [core Renode peripherals](https://github.com/renode/renode-infrastructure/tree/master/src/Emulator/Peripherals/Peripherals) as examples of what C# code looks like. + +## Debugging with GDB + +When running Renode, you can attach a GDB instance. It runs on port 3333. Simply run `tar ext :3333` in gdb to attach. + +``` +#!/bin/bash +if [ -z "$1" ] + then + echo "eg: flash.sh application.bin" + exit +fi + +set -x +export FIRMWARE_PATH=$(dirname "$1") +dd if=/dev/zero bs=1M count=4 of=./flash.bin +dd if="$FIRMWARE_PATH/bootloader/bootloader.bin" bs=1 count=$(stat -c%s "$FIRMWARE_PATH/bootloader/bootloader.bin") seek=$((16#1000)) conv=notrunc of=./flash.bin +dd if="$FIRMWARE_PATH/partition_table/partition-table.bin" bs=1 count=$(stat -c%s "$FIRMWARE_PATH/partition_table/partition-table.bin") seek=$((16#8000)) conv=notrunc of=./flash.bin +dd if=$1 bs=1 count=$(stat -c%s "$1") seek=$((16#10000)) conv=notrunc of=./flash.bin +``` diff --git a/badge.repl b/badge.repl new file mode 100644 index 0000000..786566c --- /dev/null +++ b/badge.repl @@ -0,0 +1,57 @@ +cpu: CPU.Xtensa @ sysbus + cpuType: "esp32s3" + +// External data memory +edram: Memory.MappedMemory @ sysbus 0x3C000000 + size: 0x2000000 + +// Internal data memory +dram: Memory.MappedMemory @ sysbus 0x3FC88000 + size: 0x78000 + +// Internal data rom +irom: Memory.MappedMemory @ sysbus 0x3FF00000 + size: 0x20000 + +// Internal instruction rom +drom: Memory.MappedMemory @ sysbus 0x40000000 + size: 0x60000 + +// Internal instruction memory +iram: Memory.MappedMemory @ sysbus 0x40370000 + size: 0x70000 + +// External instruction memory +eiram: Memory.MappedMemory @ sysbus 0x42000000 + size: 0x2000000 + +// Internal RTC SLOW memory +rtcslow: Memory.MappedMemory @ sysbus 0x50000000 + size: 0x2000 + +// Internal RTC FAST memory +rtcfast: Memory.MappedMemory @ sysbus 0x600FE000 + size: 0x2000 + +uart0: UART.ESP32_UART @ sysbus 0x60000000 +uart1: UART.ESP32_UART @ sysbus 0x60010000 +extmem: Miscellaneous.ESP32S3_EXTMEM @ sysbus 0x600C4000 +gpio: GPIOPort.ESP32S3_GPIO @ sysbus 0x60004000 + +// EFUSES +efuse: Memory.MappedMemory @ sysbus 0x60007000 + size: 0x1000 + +// RTC Control +rtc_cntl: Miscellaneous.ESP32S3_RTC_CNTL @ sysbus 0x60008000 + +flash: + size: 0x200000 + +spiflash: SPI.Micron_MT25Q @ usart2 + irq: 20 + underlyingMemory: flash + +sysbus: + init: + ApplySVD @esp32s3.svd diff --git a/badge.resc b/badge.resc new file mode 100644 index 0000000..fa8e129 --- /dev/null +++ b/badge.resc @@ -0,0 +1,42 @@ +# Boot Renode Script (boot.resc) + + +# Add this script's path to the global path, so +# we can include files relative to ourselves. +path add $ORIGIN + +i @peripherals/ESP32_UART.cs +i @peripherals/ESP32S3_EXTMEM.cs +i @peripherals/ESP32S3_GPIO.cs +i @peripherals/ESP32S3_RTC_CNTL.cs + +using sysbus + +mach create "SoC" +machine LoadPlatformDescription @badge.repl + +# Silence regions we don't want to implement yet +sysbus SilenceRange <0x60038000, 0x60038FFF> # USB_DEVICE +sysbus SilenceRange <0x60080000, 0x60080FFF> # USB0 +sysbus SilenceRange <0x60039000, 0x60039FFF> # USB_WRAP + +machine StartGdbServer 3333 true + +showAnalyzer uart0 +showAnalyzer uart1 + +# The macro `reset` gets called implicitly when running `machine Reset` +macro reset +""" +sysbus LoadELF @blackmagic.elf +sysbus LoadBinary @partition-table.bin 0x3C008000 +sysbus LoadBinary @esp32s3-irom.bin 0x40000000 +sysbus LoadBinary @esp32s3-drom.bin 0x3FF00000 +#sysbus LoadBinary @esp32s3-efuses.bin 0x60007000 +sysbus LoadELF @bootloader.elf +cpu PC 0x40000400 +""" + +runMacro $reset + +start diff --git a/esp32s3-drom.bin b/esp32s3-drom.bin new file mode 100644 index 0000000..99951dd Binary files /dev/null and b/esp32s3-drom.bin differ diff --git a/esp32s3-efuses.bin b/esp32s3-efuses.bin new file mode 100644 index 0000000..65531e4 Binary files /dev/null and b/esp32s3-efuses.bin differ diff --git a/esp32s3-irom.bin b/esp32s3-irom.bin new file mode 100644 index 0000000..e93eb01 Binary files /dev/null and b/esp32s3-irom.bin differ diff --git a/esp32s3-rtc-rom.bin b/esp32s3-rtc-rom.bin new file mode 100644 index 0000000..b21b4d6 Binary files /dev/null and b/esp32s3-rtc-rom.bin differ diff --git a/esp32s3-rtccntrl.bin b/esp32s3-rtccntrl.bin new file mode 100644 index 0000000..b6aea10 Binary files /dev/null and b/esp32s3-rtccntrl.bin differ diff --git a/esp32s3.svd b/esp32s3.svd new file mode 100644 index 0000000..c35f8ce --- /dev/null +++ b/esp32s3.svd @@ -0,0 +1,67737 @@ + + + ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. + ESPRESSIF + ESP32-S3 + ESP32 S-Series + 16 + 32-bit MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE) + + Copyright 2023 Espressif Systems (Shanghai) PTE LTD + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + + + Xtensa LX7 + r0p0 + little + false + true + 3 + false + + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + + AES + AES (Advanced Encryption Standard) Accelerator + AES + 0x6003A000 + + 0x0 + 0xB8 + registers + + + + 8 + 0x4 + KEY_%s + AES key register %s + 0x0 + 0x20 + + + KEY_0 + Stores AES keys. + 0 + 32 + read-write + + + + + 4 + 0x4 + TEXT_IN_%s + Source data register %s + 0x20 + 0x20 + + + TEXT_IN_0 + Stores the source data when the AES accelerator operates in the Typical AES working mode. + 0 + 32 + read-write + + + + + 4 + 0x4 + TEXT_OUT_%s + Result data register %s + 0x30 + 0x20 + + + TEXT_OUT_0 + Stores the result data when the AES accelerator operates in the Typical AES working mode. + 0 + 32 + read-write + + + + + MODE + AES Mode register + 0x40 + 0x20 + + + MODE + Defines the key length and the encryption/decryption of the AES accelerator. + 0 + 3 + read-write + + + + + TRIGGER + AES trigger register + 0x48 + 0x20 + + + TRIGGER + Set this bit to 1 to start AES calculation. + 0 + 1 + write-only + + + + + STATE + AES state register + 0x4C + 0x20 + + + STATE + Stores the working status of the AES accelerator. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done. + 0 + 2 + read-only + + + + + 16 + 0x1 + IV_MEM[%s] + The memory that stores initialization vector + 0x50 + 0x8 + + + 16 + 0x1 + H_MEM[%s] + The memory that stores GCM hash subkey + 0x60 + 0x8 + + + 16 + 0x1 + J0_MEM[%s] + The memory that stores J0 + 0x70 + 0x8 + + + 16 + 0x1 + T0_MEM[%s] + The memory that stores T0 + 0x80 + 0x8 + + + DMA_ENABLE + AES accelerator working mode register + 0x90 + 0x20 + + + DMA_ENABLE + Defines the working mode of the AES accelerator. 1'b0: typical AES working mode, 1'b1: DMA-AES working mode. + 0 + 1 + read-write + + + + + BLOCK_MODE + AES cipher block mode register + 0x94 + 0x20 + + + BLOCK_MODE + Defines the block cipher mode of the AES accelerator operating under the DMA-AES working mode. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: reserved, 0x7: reserved. + 0 + 3 + read-write + + + + + BLOCK_NUM + AES block number register + 0x98 + 0x20 + + + BLOCK_NUM + Stores the Block Number of plaintext or ciphertext when the AES accelerator operates under the DMA-AES working mode. + 0 + 32 + read-write + + + + + INC_SEL + Standard incrementing function configure register + 0x9C + 0x20 + + + INC_SEL + Defines the Standard Incrementing Function for CTR block operation. Set this bit to 0 or 1 to choose INC32 or INC128. + 0 + 1 + read-write + + + + + AAD_BLOCK_NUM + Additional Authential Data block number register + 0xA0 + 0x20 + + + AAD_BLOCK_NUM + Those bits stores the number of AAD block. + 0 + 32 + read-write + + + + + REMAINDER_BIT_NUM + AES remainder bit number register + 0xA4 + 0x20 + + + REMAINDER_BIT_NUM + Those bits stores the number of remainder bit. + 0 + 7 + read-write + + + + + CONTINUE + AES continue register + 0xA8 + 0x20 + + + CONTINUE + Set this bit to 1 to continue GCM operation. + 0 + 1 + write-only + + + + + INT_CLR + AES Interrupt clear register + 0xAC + 0x20 + + + INT_CLEAR + Set this bit to 1 to clear AES interrupt. + 0 + 1 + write-only + + + + + INT_ENA + DMA-AES Interrupt enable register + 0xB0 + 0x20 + + + INT_ENA + Set this bit to 1 to enable AES interrupt and 0 to disable interrupt. This field is only effective for DMA-AES operation. + 0 + 1 + read-write + + + + + DATE + AES version control register + 0xB4 + 0x20 + 0x20191210 + + + DATE + This bits stores the version information of AES. + 0 + 30 + read-write + + + + + DMA_EXIT + AES-DMA exit config + 0xB8 + 0x20 + + + DMA_EXIT + Set this bit to 1 to exit AES operation. This field is only effective for DMA-AES operation. + 0 + 1 + write-only + + + + + + + APB_CTRL + APB (Advanced Peripheral Bus) Controller + APB_CTRL + 0x60026000 + + 0x0 + 0xCC + registers + + + + SYSCLK_CONF + ******* Description *********** + 0x0 + 0x20 + 0x00000001 + + + PRE_DIV_CNT + ******* Description *********** + 0 + 10 + read-write + + + CLK_320M_EN + ******* Description *********** + 10 + 1 + read-write + + + CLK_EN + ******* Description *********** + 11 + 1 + read-write + + + RST_TICK_CNT + ******* Description *********** + 12 + 1 + read-write + + + + + TICK_CONF + ******* Description *********** + 0x4 + 0x20 + 0x00010727 + + + XTAL_TICK_NUM + ******* Description *********** + 0 + 8 + read-write + + + CK8M_TICK_NUM + ******* Description *********** + 8 + 8 + read-write + + + TICK_ENABLE + ******* Description *********** + 16 + 1 + read-write + + + + + CLK_OUT_EN + ******* Description *********** + 0x8 + 0x20 + 0x000007FF + + + CLK20_OEN + ******* Description *********** + 0 + 1 + read-write + + + CLK22_OEN + ******* Description *********** + 1 + 1 + read-write + + + CLK44_OEN + ******* Description *********** + 2 + 1 + read-write + + + CLK_BB_OEN + ******* Description *********** + 3 + 1 + read-write + + + CLK80_OEN + ******* Description *********** + 4 + 1 + read-write + + + CLK160_OEN + ******* Description *********** + 5 + 1 + read-write + + + CLK_320M_OEN + ******* Description *********** + 6 + 1 + read-write + + + CLK_ADC_INF_OEN + ******* Description *********** + 7 + 1 + read-write + + + CLK_DAC_CPU_OEN + ******* Description *********** + 8 + 1 + read-write + + + CLK40X_BB_OEN + ******* Description *********** + 9 + 1 + read-write + + + CLK_XTAL_OEN + ******* Description *********** + 10 + 1 + read-write + + + + + WIFI_BB_CFG + ******* Description *********** + 0xC + 0x20 + + + WIFI_BB_CFG + ******* Description *********** + 0 + 32 + read-write + + + + + WIFI_BB_CFG_2 + ******* Description *********** + 0x10 + 0x20 + + + WIFI_BB_CFG_2 + ******* Description *********** + 0 + 32 + read-write + + + + + WIFI_CLK_EN + ******* Description *********** + 0x14 + 0x20 + 0xFFFCE030 + + + WIFI_CLK_EN + ******* Description *********** + 0 + 32 + read-write + + + + + WIFI_RST_EN + ******* Description *********** + 0x18 + 0x20 + + + WIFI_RST + ******* Description *********** + 0 + 32 + read-write + + + + + HOST_INF_SEL + ******* Description *********** + 0x1C + 0x20 + + + PERI_IO_SWAP + ******* Description *********** + 0 + 8 + read-write + + + + + EXT_MEM_PMS_LOCK + ******* Description *********** + 0x20 + 0x20 + + + EXT_MEM_PMS_LOCK + ******* Description *********** + 0 + 1 + read-write + + + + + EXT_MEM_WRITEBACK_BYPASS + ******* Description *********** + 0x24 + 0x20 + + + WRITEBACK_BYPASS + Set 1 to bypass cache writeback request to external memory so that spi will not check its attribute. + 0 + 1 + read-write + + + + + FLASH_ACE0_ATTR + ******* Description *********** + 0x28 + 0x20 + 0x000000FF + + + FLASH_ACE0_ATTR + ******* Description *********** + 0 + 9 + read-write + + + + + FLASH_ACE1_ATTR + ******* Description *********** + 0x2C + 0x20 + 0x000000FF + + + FLASH_ACE1_ATTR + ******* Description *********** + 0 + 9 + read-write + + + + + FLASH_ACE2_ATTR + ******* Description *********** + 0x30 + 0x20 + 0x000000FF + + + FLASH_ACE2_ATTR + ******* Description *********** + 0 + 9 + read-write + + + + + FLASH_ACE3_ATTR + ******* Description *********** + 0x34 + 0x20 + 0x000000FF + + + FLASH_ACE3_ATTR + ******* Description *********** + 0 + 9 + read-write + + + + + FLASH_ACE0_ADDR + ******* Description *********** + 0x38 + 0x20 + + + S + ******* Description *********** + 0 + 32 + read-write + + + + + FLASH_ACE1_ADDR + ******* Description *********** + 0x3C + 0x20 + 0x10000000 + + + S + ******* Description *********** + 0 + 32 + read-write + + + + + FLASH_ACE2_ADDR + ******* Description *********** + 0x40 + 0x20 + 0x20000000 + + + S + ******* Description *********** + 0 + 32 + read-write + + + + + FLASH_ACE3_ADDR + ******* Description *********** + 0x44 + 0x20 + 0x30000000 + + + S + ******* Description *********** + 0 + 32 + read-write + + + + + FLASH_ACE0_SIZE + ******* Description *********** + 0x48 + 0x20 + 0x00001000 + + + FLASH_ACE0_SIZE + ******* Description *********** + 0 + 16 + read-write + + + + + FLASH_ACE1_SIZE + ******* Description *********** + 0x4C + 0x20 + 0x00001000 + + + FLASH_ACE1_SIZE + ******* Description *********** + 0 + 16 + read-write + + + + + FLASH_ACE2_SIZE + ******* Description *********** + 0x50 + 0x20 + 0x00001000 + + + FLASH_ACE2_SIZE + ******* Description *********** + 0 + 16 + read-write + + + + + FLASH_ACE3_SIZE + ******* Description *********** + 0x54 + 0x20 + 0x00001000 + + + FLASH_ACE3_SIZE + ******* Description *********** + 0 + 16 + read-write + + + + + SRAM_ACE0_ATTR + ******* Description *********** + 0x58 + 0x20 + 0x000000FF + + + SRAM_ACE0_ATTR + ******* Description *********** + 0 + 9 + read-write + + + + + SRAM_ACE1_ATTR + ******* Description *********** + 0x5C + 0x20 + 0x000000FF + + + SRAM_ACE1_ATTR + ******* Description *********** + 0 + 9 + read-write + + + + + SRAM_ACE2_ATTR + ******* Description *********** + 0x60 + 0x20 + 0x000000FF + + + SRAM_ACE2_ATTR + ******* Description *********** + 0 + 9 + read-write + + + + + SRAM_ACE3_ATTR + ******* Description *********** + 0x64 + 0x20 + 0x000000FF + + + SRAM_ACE3_ATTR + ******* Description *********** + 0 + 9 + read-write + + + + + SRAM_ACE0_ADDR + ******* Description *********** + 0x68 + 0x20 + + + S + ******* Description *********** + 0 + 32 + read-write + + + + + SRAM_ACE1_ADDR + ******* Description *********** + 0x6C + 0x20 + 0x10000000 + + + S + ******* Description *********** + 0 + 32 + read-write + + + + + SRAM_ACE2_ADDR + ******* Description *********** + 0x70 + 0x20 + 0x20000000 + + + S + ******* Description *********** + 0 + 32 + read-write + + + + + SRAM_ACE3_ADDR + ******* Description *********** + 0x74 + 0x20 + 0x30000000 + + + S + ******* Description *********** + 0 + 32 + read-write + + + + + SRAM_ACE0_SIZE + ******* Description *********** + 0x78 + 0x20 + 0x00001000 + + + SRAM_ACE0_SIZE + ******* Description *********** + 0 + 16 + read-write + + + + + SRAM_ACE1_SIZE + ******* Description *********** + 0x7C + 0x20 + 0x00001000 + + + SRAM_ACE1_SIZE + ******* Description *********** + 0 + 16 + read-write + + + + + SRAM_ACE2_SIZE + ******* Description *********** + 0x80 + 0x20 + 0x00001000 + + + SRAM_ACE2_SIZE + ******* Description *********** + 0 + 16 + read-write + + + + + SRAM_ACE3_SIZE + ******* Description *********** + 0x84 + 0x20 + 0x00001000 + + + SRAM_ACE3_SIZE + ******* Description *********** + 0 + 16 + read-write + + + + + SPI_MEM_PMS_CTRL + ******* Description *********** + 0x88 + 0x20 + + + SPI_MEM_REJECT_INT + ******* Description *********** + 0 + 1 + read-only + + + SPI_MEM_REJECT_CLR + ******* Description *********** + 1 + 1 + write-only + + + SPI_MEM_REJECT_CDE + ******* Description *********** + 2 + 5 + read-only + + + + + SPI_MEM_REJECT_ADDR + ******* Description *********** + 0x8C + 0x20 + + + SPI_MEM_REJECT_ADDR + ******* Description *********** + 0 + 32 + read-only + + + + + SDIO_CTRL + ******* Description *********** + 0x90 + 0x20 + + + SDIO_WIN_ACCESS_EN + ******* Description *********** + 0 + 1 + read-write + + + + + REDCY_SIG0 + ******* Description *********** + 0x94 + 0x20 + + + REDCY_SIG0 + ******* Description *********** + 0 + 31 + read-write + + + REDCY_ANDOR + ******* Description *********** + 31 + 1 + read-only + + + + + REDCY_SIG1 + ******* Description *********** + 0x98 + 0x20 + + + REDCY_SIG1 + ******* Description *********** + 0 + 31 + read-write + + + REDCY_NANDOR + ******* Description *********** + 31 + 1 + read-only + + + + + FRONT_END_MEM_PD + ******* Description *********** + 0x9C + 0x20 + 0x00000055 + + + AGC_MEM_FORCE_PU + ******* Description *********** + 0 + 1 + read-write + + + AGC_MEM_FORCE_PD + ******* Description *********** + 1 + 1 + read-write + + + PBUS_MEM_FORCE_PU + ******* Description *********** + 2 + 1 + read-write + + + PBUS_MEM_FORCE_PD + ******* Description *********** + 3 + 1 + read-write + + + DC_MEM_FORCE_PU + ******* Description *********** + 4 + 1 + read-write + + + DC_MEM_FORCE_PD + ******* Description *********** + 5 + 1 + read-write + + + FREQ_MEM_FORCE_PU + ******* Description *********** + 6 + 1 + read-write + + + FREQ_MEM_FORCE_PD + ******* Description *********** + 7 + 1 + read-write + + + + + SPI_MEM_ECC_CTRL + ******* Description *********** + 0xA0 + 0x20 + 0x00200000 + + + FLASH_PAGE_SIZE + Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes. + 18 + 2 + read-write + + + SRAM_PAGE_SIZE + Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes. + 20 + 2 + read-write + + + + + CLKGATE_FORCE_ON + ******* Description *********** + 0xA8 + 0x20 + 0x00003FFF + + + ROM_CLKGATE_FORCE_ON + ******* Description *********** + 0 + 3 + read-write + + + SRAM_CLKGATE_FORCE_ON + ******* Description *********** + 3 + 11 + read-write + + + + + MEM_POWER_DOWN + ******* Description *********** + 0xAC + 0x20 + + + ROM_POWER_DOWN + ******* Description *********** + 0 + 3 + read-write + + + SRAM_POWER_DOWN + ******* Description *********** + 3 + 11 + read-write + + + + + MEM_POWER_UP + ******* Description *********** + 0xB0 + 0x20 + 0x00003FFF + + + ROM_POWER_UP + ******* Description *********** + 0 + 3 + read-write + + + SRAM_POWER_UP + ******* Description *********** + 3 + 11 + read-write + + + + + RETENTION_CTRL + ******* Description *********** + 0xB4 + 0x20 + + + RETENTION_CPU_LINK_ADDR + ******* Description *********** + 0 + 27 + read-write + + + NOBYPASS_CPU_ISO_RST + ******* Description *********** + 27 + 1 + read-write + + + + + RETENTION_CTRL1 + ******* Description *********** + 0xB8 + 0x20 + + + RETENTION_TAG_LINK_ADDR + ******* Description *********** + 0 + 27 + read-write + + + + + RETENTION_CTRL2 + ******* Description *********** + 0xBC + 0x20 + 0x001FEFF0 + + + RET_ICACHE_SIZE + ******* Description *********** + 4 + 8 + read-write + + + RET_ICACHE_VLD_SIZE + ******* Description *********** + 13 + 8 + read-write + + + RET_ICACHE_START_POINT + ******* Description *********** + 22 + 8 + read-write + + + RET_ICACHE_ENABLE + ******* Description *********** + 31 + 1 + read-write + + + + + RETENTION_CTRL3 + ******* Description *********** + 0xC0 + 0x20 + 0x003FFFF0 + + + RET_DCACHE_SIZE + ******* Description *********** + 4 + 9 + read-write + + + RET_DCACHE_VLD_SIZE + ******* Description *********** + 13 + 9 + read-write + + + RET_DCACHE_START_POINT + ******* Description *********** + 22 + 9 + read-write + + + RET_DCACHE_ENABLE + ******* Description *********** + 31 + 1 + read-write + + + + + RETENTION_CTRL4 + ******* Description *********** + 0xC4 + 0x20 + 0xFFFFFFFF + + + RETENTION_INV_CFG + ******* Description *********** + 0 + 32 + read-write + + + + + RETENTION_CTRL5 + ******* Description *********** + 0xC8 + 0x20 + + + RETENTION_DISABLE + ******* Description *********** + 0 + 1 + read-write + + + + + DATE + ******* Description *********** + 0x3FC + 0x20 + 0x02101150 + + + DATE + Version control + 0 + 32 + read-write + + + + + + + APB_SARADC + SAR (Successive Approximation Register) Analog-to-Digital Converter + APB_SARADC + 0x60040000 + + 0x0 + 0x70 + registers + + + APB_ADC + 65 + + + + CTRL + configure apb saradc controller + 0x0 + 0x20 + 0x407F8240 + + + SARADC_START_FORCE + enable start saradc by sw + 0 + 1 + read-write + + + SARADC_START + start saradc by sw + 1 + 1 + read-write + + + SARADC_WORK_MODE + 0: single mode, 1: double mode, 2: alternate mode + 3 + 2 + read-write + + + SARADC_SAR_SEL + 0: SAR1, 1: SAR2, only work for single SAR mode + 5 + 1 + read-write + + + SARADC_SAR_CLK_GATED + enable SAR CLK gate when saradc idle + 6 + 1 + read-write + + + SARADC_SAR_CLK_DIV + SAR clock divider + 7 + 8 + read-write + + + SARADC_SAR1_PATT_LEN + 0 ~ 15 means length 1 ~ 16 + 15 + 4 + read-write + + + SARADC_SAR2_PATT_LEN + 0 ~ 15 means length 1 ~ 16 + 19 + 4 + read-write + + + SARADC_SAR1_PATT_P_CLEAR + clear the pointer of pattern table for DIG ADC1 CTRL + 23 + 1 + read-write + + + SARADC_SAR2_PATT_P_CLEAR + clear the pointer of pattern table for DIG ADC2 CTRL + 24 + 1 + read-write + + + SARADC_DATA_SAR_SEL + 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits. + 25 + 1 + read-write + + + SARADC_DATA_TO_I2S + 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix + 26 + 1 + read-write + + + SARADC_XPD_SAR_FORCE + force option to xpd sar blocks + 27 + 2 + read-write + + + SARADC_WAIT_ARB_CYCLE + wait arbit signal stable after sar_done + 30 + 2 + read-write + + + + + CTRL2 + configure apb saradc controller + 0x4 + 0x20 + 0x0000A1FE + + + SARADC_MEAS_NUM_LIMIT + enable apb saradc limit the sample num + 0 + 1 + read-write + + + SARADC_MAX_MEAS_NUM + max conversion number + 1 + 8 + read-write + + + SARADC_SAR1_INV + 1: data to DIG ADC1 CTRL is inverted, otherwise not + 9 + 1 + read-write + + + SARADC_SAR2_INV + 1: data to DIG ADC2 CTRL is inverted, otherwise not + 10 + 1 + read-write + + + SARADC_TIMER_SEL + 1: select saradc timer 0: i2s_ws trigger + 11 + 1 + read-write + + + SARADC_TIMER_TARGET + to set saradc timer target + 12 + 12 + read-write + + + SARADC_TIMER_EN + to enable saradc timer trigger + 24 + 1 + read-write + + + + + FILTER_CTRL1 + configure saradc filter + 0x8 + 0x20 + + + FILTER_FACTOR1 + apb saradc factor1 + 26 + 3 + read-write + + + FILTER_FACTOR0 + apb saradc factor0 + 29 + 3 + read-write + + + + + FSM_WAIT + configure apb saradc fsm + 0xC + 0x20 + 0x00FF0808 + + + SARADC_XPD_WAIT + the cycle which saradc controller in xpd state + 0 + 8 + read-write + + + SARADC_RSTB_WAIT + the cycle which saradc controller in rst state + 8 + 8 + read-write + + + SARADC_STANDBY_WAIT + the cycle which saradc controller in standby state + 16 + 8 + read-write + + + + + SAR1_STATUS + saradc1 status for debug + 0x10 + 0x20 + + + SARADC_SAR1_STATUS + saradc1 status + 0 + 32 + read-only + + + + + SAR2_STATUS + saradc2 status for debug + 0x14 + 0x20 + + + SARADC_SAR2_STATUS + saradc2 status + 0 + 32 + read-only + + + + + SAR1_PATT_TAB1 + configure apb saradc pattern table + 0x18 + 0x20 + + + SARADC_SAR1_PATT_TAB1 + item 0 ~ 3 for pattern table 1 (each item 6bit) + 0 + 24 + read-write + + + + + SAR1_PATT_TAB2 + configure apb saradc pattern table + 0x1C + 0x20 + + + SARADC_SAR1_PATT_TAB2 + Item 4 ~ 7 for pattern table 1 (each item 6bit) + 0 + 24 + read-write + + + + + SAR1_PATT_TAB3 + configure apb saradc pattern table + 0x20 + 0x20 + + + SARADC_SAR1_PATT_TAB3 + Item 8 ~ 11 for pattern table 1 (each item 6bit) + 0 + 24 + read-write + + + + + SAR1_PATT_TAB4 + configure apb saradc pattern table + 0x24 + 0x20 + + + SARADC_SAR1_PATT_TAB4 + Item 12 ~ 15 for pattern table 1 (each item 6bit) + 0 + 24 + read-write + + + + + SAR2_PATT_TAB1 + configure apb saradc pattern table + 0x28 + 0x20 + + + SARADC_SAR2_PATT_TAB1 + item 0 ~ 3 for pattern table 2 (each item 6bit) + 0 + 24 + read-write + + + + + SAR2_PATT_TAB2 + configure apb saradc pattern table + 0x2C + 0x20 + + + SARADC_SAR2_PATT_TAB2 + Item 4 ~ 7 for pattern table 2 (each item 6bit) + 0 + 24 + read-write + + + + + SAR2_PATT_TAB3 + configure apb saradc pattern table + 0x30 + 0x20 + + + SARADC_SAR2_PATT_TAB3 + Item 8 ~ 11 for pattern table 2 (each item 6bit) + 0 + 24 + read-write + + + + + SAR2_PATT_TAB4 + configure apb saradc pattern table + 0x34 + 0x20 + + + SARADC_SAR2_PATT_TAB4 + Item 12 ~ 15 for pattern table 2 (each item 6bit) + 0 + 24 + read-write + + + + + ARB_CTRL + configure apb saradc arbit + 0x38 + 0x20 + 0x00000900 + + + ADC_ARB_APB_FORCE + adc2 arbiter force to enableapb controller + 2 + 1 + read-write + + + ADC_ARB_RTC_FORCE + adc2 arbiter force to enable rtc controller + 3 + 1 + read-write + + + ADC_ARB_WIFI_FORCE + adc2 arbiter force to enable wifi controller + 4 + 1 + read-write + + + ADC_ARB_GRANT_FORCE + adc2 arbiter force grant + 5 + 1 + read-write + + + ADC_ARB_APB_PRIORITY + Set adc2 arbiterapb priority + 6 + 2 + read-write + + + ADC_ARB_RTC_PRIORITY + Set adc2 arbiter rtc priority + 8 + 2 + read-write + + + ADC_ARB_WIFI_PRIORITY + Set adc2 arbiter wifi priority + 10 + 2 + read-write + + + ADC_ARB_FIX_PRIORITY + adc2 arbiter uses fixed priority + 12 + 1 + read-write + + + + + FILTER_CTRL0 + configure apb saradc arbit + 0x3C + 0x20 + 0x006B4000 + + + FILTER_CHANNEL1 + configure the filter1 channel + 14 + 5 + read-write + + + FILTER_CHANNEL0 + configure the filter0 channel + 19 + 5 + read-write + + + FILTER_RESET + enable apb_adc1_filter + 31 + 1 + read-write + + + + + APB_SARADC1_DATA_STATUS + get apb saradc sample data + 0x40 + 0x20 + + + APB_SARADC1_DATA + apbsaradc sample data + 0 + 17 + read-only + + + + + THRES0_CTRL + configure apb saradc thres monitor + 0x44 + 0x20 + 0x0003FFED + + + THRES0_CHANNEL + configure which channel thres0 monitor + 0 + 5 + read-write + + + THRES0_HIGH + thres0 monitor high thres + 5 + 13 + read-write + + + THRES0_LOW + thres0 monitor low thres + 18 + 13 + read-write + + + + + THRES1_CTRL + configure apb saradc thres monitor + 0x48 + 0x20 + 0x0003FFED + + + THRES1_CHANNEL + configure which channel thres0 monitor + 0 + 5 + read-write + + + THRES1_HIGH + thres1 monitor high thres + 5 + 13 + read-write + + + THRES1_LOW + thres1 monitor low thres + 18 + 13 + read-write + + + + + THRES_CTRL + configure thres monitor enable + 0x58 + 0x20 + + + THRES_ALL_EN + enable thres0 to monitor all channel + 27 + 1 + read-write + + + THRES3_EN + no public + 28 + 1 + read-write + + + THRES2_EN + no public + 29 + 1 + read-write + + + THRES1_EN + enable thres1 + 30 + 1 + read-write + + + THRES0_EN + enable thres0 + 31 + 1 + read-write + + + + + INT_ENA + enable interrupt + 0x5C + 0x20 + + + THRES1_LOW_INT_ENA + interrupt of thres1 low + 26 + 1 + read-write + + + THRES0_LOW_INT_ENA + interrupt of thres0 low + 27 + 1 + read-write + + + THRES1_HIGH_INT_ENA + interrupt of thres1 high + 28 + 1 + read-write + + + THRES0_HIGH_INT_ENA + interrupt of thres0 high + 29 + 1 + read-write + + + APB_SARADC2_DONE_INT_ENA + interrupt of sar2 done + 30 + 1 + read-write + + + APB_SARADC1_DONE_INT_ENA + interrupt of sar1 done + 31 + 1 + read-write + + + + + INT_RAW + raw of interrupt + 0x60 + 0x20 + + + THRES1_LOW_INT_RAW + interrupt of thres1 low + 26 + 1 + read-only + + + THRES0_LOW_INT_RAW + interrupt of thres0 low + 27 + 1 + read-only + + + THRES1_HIGH_INT_RAW + interrupt of thres1 high + 28 + 1 + read-only + + + THRES0_HIGH_INT_RAW + interrupt of thres0 high + 29 + 1 + read-only + + + APB_SARADC2_DONE_INT_RAW + interrupt of sar2 done + 30 + 1 + read-only + + + APB_SARADC1_DONE_INT_RAW + interrupt of sar1 done + 31 + 1 + read-only + + + + + INT_ST + state of interrupt + 0x64 + 0x20 + + + THRES1_LOW_INT_ST + interrupt of thres1 low + 26 + 1 + read-only + + + THRES0_LOW_INT_ST + interrupt of thres0 low + 27 + 1 + read-only + + + THRES1_HIGH_INT_ST + interrupt of thres1 high + 28 + 1 + read-only + + + THRES0_HIGH_INT_ST + interrupt of thres0 high + 29 + 1 + read-only + + + APB_SARADC2_DONE_INT_ST + interrupt of sar2 done + 30 + 1 + read-only + + + APB_SARADC1_DONE_INT_ST + interrupt of sar1 done + 31 + 1 + read-only + + + + + INT_CLR + clear interrupt + 0x68 + 0x20 + + + THRES1_LOW_INT_CLR + interrupt of thres1 low + 26 + 1 + write-only + + + THRES0_LOW_INT_CLR + interrupt of thres0 low + 27 + 1 + write-only + + + THRES1_HIGH_INT_CLR + interrupt of thres1 high + 28 + 1 + write-only + + + THRES0_HIGH_INT_CLR + interrupt of thres0 high + 29 + 1 + write-only + + + APB_SARADC2_DONE_INT_CLR + interrupt of sar2 done + 30 + 1 + write-only + + + APB_SARADC1_DONE_INT_CLR + interrupt of sar1 done + 31 + 1 + write-only + + + + + DMA_CONF + configure apb saradc dma + 0x6C + 0x20 + 0x000000FF + + + APB_ADC_EOF_NUM + the dma_in_suc_eof gen when sample cnt = spi_eof_num + 0 + 16 + read-write + + + APB_ADC_RESET_FSM + reset_apb_adc_state + 30 + 1 + read-write + + + APB_ADC_TRANS + enable apb_adc use spi_dma + 31 + 1 + read-write + + + + + CLKM_CONF + configure apb saradc clock + 0x70 + 0x20 + 0x00000004 + + + CLKM_DIV_NUM + Integral clock divider value + 0 + 8 + read-write + + + CLKM_DIV_B + Fractional clock divider numerator value + 8 + 6 + read-write + + + CLKM_DIV_A + Fractional clock divider denominator value + 14 + 6 + read-write + + + CLK_EN + no public + 20 + 1 + read-write + + + CLK_SEL + Set this bit to enable clk_apll + 21 + 2 + read-write + + + + + APB_SARADC2_DATA_STATUS + get apb saradc2 sample data + 0x78 + 0x20 + + + APB_SARADC2_DATA + apb saradc2 sample data + 0 + 17 + read-only + + + + + APB_CTRL_DATE + version + 0x3FC + 0x20 + 0x02101180 + + + APB_CTRL_DATE + version + 0 + 32 + read-write + + + + + + + BB + BB Peripheral + BB + 0x6001D000 + + 0x0 + 0x4 + registers + + + + BBPD_CTRL + Baseband control register + 0x54 + 0x20 + + + DC_EST_FORCE_PD + 0 + 1 + read-write + + + DC_EST_FORCE_PU + 1 + 1 + read-write + + + FFT_FORCE_PD + 2 + 1 + read-write + + + FFT_FORCE_PU + 3 + 1 + read-write + + + + + + + ASSIST_DEBUG + Debug Assist + DEBUG_ASSIST + 0x600CE000 + + 0x0 + 0x15C + registers + + + ASSIST_DEBUG + 83 + + + + CORE_0_INTERRUPT_ENA + core0 monitor enable configuration register + 0x0 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_ENA + Core0 dram0 area0 read monitor enable + 0 + 1 + read-write + + + CORE_0_AREA_DRAM0_0_WR_ENA + Core0 dram0 area0 write monitor enable + 1 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_RD_ENA + Core0 dram0 area1 read monitor enable + 2 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_WR_ENA + Core0 dram0 area1 write monitor enable + 3 + 1 + read-write + + + CORE_0_AREA_PIF_0_RD_ENA + Core0 PIF area0 read monitor enable + 4 + 1 + read-write + + + CORE_0_AREA_PIF_0_WR_ENA + Core0 PIF area0 write monitor enable + 5 + 1 + read-write + + + CORE_0_AREA_PIF_1_RD_ENA + Core0 PIF area1 read monitor enable + 6 + 1 + read-write + + + CORE_0_AREA_PIF_1_WR_ENA + Core0 PIF area1 write monitor enable + 7 + 1 + read-write + + + CORE_0_SP_SPILL_MIN_ENA + Core0 stackpoint overflow monitor enable + 8 + 1 + read-write + + + CORE_0_SP_SPILL_MAX_ENA + Core0 stackpoint underflow monitor enable + 9 + 1 + read-write + + + CORE_0_IRAM0_EXCEPTION_MONITOR_ENA + IBUS busy monitor enable + 10 + 1 + read-write + + + CORE_0_DRAM0_EXCEPTION_MONITOR_ENA + DBUS busy monitor enbale + 11 + 1 + read-write + + + + + CORE_0_INTERRUPT_RAW + core0 monitor interrupt status register + 0x4 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_RAW + Core0 dram0 area0 read monitor interrupt status + 0 + 1 + read-only + + + CORE_0_AREA_DRAM0_0_WR_RAW + Core0 dram0 area0 write monitor interrupt status + 1 + 1 + read-only + + + CORE_0_AREA_DRAM0_1_RD_RAW + Core0 dram0 area1 read monitor interrupt status + 2 + 1 + read-only + + + CORE_0_AREA_DRAM0_1_WR_RAW + Core0 dram0 area1 write monitor interrupt status + 3 + 1 + read-only + + + CORE_0_AREA_PIF_0_RD_RAW + Core0 PIF area0 read monitor interrupt status + 4 + 1 + read-only + + + CORE_0_AREA_PIF_0_WR_RAW + Core0 PIF area0 write monitor interrupt status + 5 + 1 + read-only + + + CORE_0_AREA_PIF_1_RD_RAW + Core0 PIF area1 read monitor interrupt status + 6 + 1 + read-only + + + CORE_0_AREA_PIF_1_WR_RAW + Core0 PIF area1 write monitor interrupt status + 7 + 1 + read-only + + + CORE_0_SP_SPILL_MIN_RAW + Core0 stackpoint overflow monitor interrupt status + 8 + 1 + read-only + + + CORE_0_SP_SPILL_MAX_RAW + Core0 stackpoint underflow monitor interrupt status + 9 + 1 + read-only + + + CORE_0_IRAM0_EXCEPTION_MONITOR_RAW + IBUS busy monitor interrupt status + 10 + 1 + read-only + + + CORE_0_DRAM0_EXCEPTION_MONITOR_RAW + DBUS busy monitor initerrupt status + 11 + 1 + read-only + + + + + CORE_0_INTERRUPT_RLS + core0 monitor interrupt enable register + 0x8 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_RLS + Core0 dram0 area0 read monitor interrupt enable + 0 + 1 + read-write + + + CORE_0_AREA_DRAM0_0_WR_RLS + Core0 dram0 area0 write monitor interrupt enable + 1 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_RD_RLS + Core0 dram0 area1 read monitor interrupt enable + 2 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_WR_RLS + Core0 dram0 area1 write monitor interrupt enable + 3 + 1 + read-write + + + CORE_0_AREA_PIF_0_RD_RLS + Core0 PIF area0 read monitor interrupt enable + 4 + 1 + read-write + + + CORE_0_AREA_PIF_0_WR_RLS + Core0 PIF area0 write monitor interrupt enable + 5 + 1 + read-write + + + CORE_0_AREA_PIF_1_RD_RLS + Core0 PIF area1 read monitor interrupt enable + 6 + 1 + read-write + + + CORE_0_AREA_PIF_1_WR_RLS + Core0 PIF area1 write monitor interrupt enable + 7 + 1 + read-write + + + CORE_0_SP_SPILL_MIN_RLS + Core0 stackpoint overflow monitor interrupt enable + 8 + 1 + read-write + + + CORE_0_SP_SPILL_MAX_RLS + Core0 stackpoint underflow monitor interrupt enable + 9 + 1 + read-write + + + CORE_0_IRAM0_EXCEPTION_MONITOR_RLS + IBUS busy monitor interrupt enable + 10 + 1 + read-write + + + CORE_0_DRAM0_EXCEPTION_MONITOR_RLS + DBUS busy monitor interrupt enbale + 11 + 1 + read-write + + + + + CORE_0_INTERRUPT_CLR + core0 monitor interrupt clr register + 0xC + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_CLR + Core0 dram0 area0 read monitor interrupt clr + 0 + 1 + read-write + + + CORE_0_AREA_DRAM0_0_WR_CLR + Core0 dram0 area0 write monitor interrupt clr + 1 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_RD_CLR + Core0 dram0 area1 read monitor interrupt clr + 2 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_WR_CLR + Core0 dram0 area1 write monitor interrupt clr + 3 + 1 + read-write + + + CORE_0_AREA_PIF_0_RD_CLR + Core0 PIF area0 read monitor interrupt clr + 4 + 1 + read-write + + + CORE_0_AREA_PIF_0_WR_CLR + Core0 PIF area0 write monitor interrupt clr + 5 + 1 + read-write + + + CORE_0_AREA_PIF_1_RD_CLR + Core0 PIF area1 read monitor interrupt clr + 6 + 1 + read-write + + + CORE_0_AREA_PIF_1_WR_CLR + Core0 PIF area1 write monitor interrupt clr + 7 + 1 + read-write + + + CORE_0_SP_SPILL_MIN_CLR + Core0 stackpoint overflow monitor interrupt clr + 8 + 1 + read-write + + + CORE_0_SP_SPILL_MAX_CLR + Core0 stackpoint underflow monitor interrupt clr + 9 + 1 + read-write + + + CORE_0_IRAM0_EXCEPTION_MONITOR_CLR + IBUS busy monitor interrupt clr + 10 + 1 + read-write + + + CORE_0_DRAM0_EXCEPTION_MONITOR_CLR + DBUS busy monitor interrupt clr + 11 + 1 + read-write + + + + + CORE_0_AREA_DRAM0_0_MIN + core0 dram0 region0 addr configuration register + 0x10 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_DRAM0_0_MIN + Core0 dram0 region0 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_0_MAX + core0 dram0 region0 addr configuration register + 0x14 + 0x20 + + + CORE_0_AREA_DRAM0_0_MAX + Core0 dram0 region0 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_1_MIN + core0 dram0 region1 addr configuration register + 0x18 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_DRAM0_1_MIN + Core0 dram0 region1 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_1_MAX + core0 dram0 region1 addr configuration register + 0x1C + 0x20 + + + CORE_0_AREA_DRAM0_1_MAX + Core0 dram0 region1 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_0_MIN + core0 PIF region0 addr configuration register + 0x20 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_PIF_0_MIN + Core0 PIF region0 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_0_MAX + core0 PIF region0 addr configuration register + 0x24 + 0x20 + + + CORE_0_AREA_PIF_0_MAX + Core0 PIF region0 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_1_MIN + core0 PIF region1 addr configuration register + 0x28 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_PIF_1_MIN + Core0 PIF region1 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_1_MAX + core0 PIF region1 addr configuration register + 0x2C + 0x20 + + + CORE_0_AREA_PIF_1_MAX + Core0 PIF region1 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_SP + core0 area sp status register + 0x30 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_SP + the stackpointer when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_0_AREA_PC + core0 area pc status register + 0x34 + 0x20 + + + CORE_0_AREA_PC + the PC when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_0_SP_UNSTABLE + core0 sp unstable configuration register + 0x38 + 0x20 + 0x0000000B + + + CORE_0_SP_UNSTABLE + unstable period when window change,during this period no check stackpointer + 0 + 8 + read-write + + + + + CORE_0_SP_MIN + core0 sp region configuration regsiter + 0x3C + 0x20 + + + CORE_0_SP_MIN + stack min value + 0 + 32 + read-write + + + + + CORE_0_SP_MAX + core0 sp region configuration regsiter + 0x40 + 0x20 + 0xFFFFFFFF + + + CORE_0_SP_MAX + stack max value + 0 + 32 + read-write + + + + + CORE_0_SP_PC + core0 sp pc status register + 0x44 + 0x20 + + + CORE_0_SP_PC + the PC when first touch stack monitor interrupt + 0 + 32 + read-only + + + + + CORE_0_RCD_PDEBUGENABLE + core0 pdebug configuration register + 0x48 + 0x20 + + + CORE_0_RCD_PDEBUGENABLE + Core0 Pdebugenable,set 1 to open core0 Pdebug interface,then can get core0 PC + 0 + 1 + read-write + + + + + CORE_0_RCD_RECORDING + core0 pdebug status register + 0x4C + 0x20 + + + CORE_0_RCD_RECORDING + Pdebug record enable,set 1 to record core0 pdebug interface signal + 0 + 1 + read-write + + + + + CORE_0_RCD_PDEBUGINST + core0 pdebug status register + 0x50 + 0x20 + + + CORE_0_RCD_PDEBUGINST + core0 pdebuginst + 0 + 32 + read-only + + + + + CORE_0_RCD_PDEBUGSTATUS + core0 pdebug status register + 0x54 + 0x20 + + + CORE_0_RCD_PDEBUGSTATUS + core0 pdebugstatus + 0 + 8 + read-only + + + + + CORE_0_RCD_PDEBUGDATA + core0 pdebug status register + 0x58 + 0x20 + + + CORE_0_RCD_PDEBUGDATA + core0_pdebugdata + 0 + 32 + read-only + + + + + CORE_0_RCD_PDEBUGPC + core0 pdebug status register + 0x5C + 0x20 + + + CORE_0_RCD_PDEBUGPC + core0_pdebugPC + 0 + 32 + read-only + + + + + CORE_0_RCD_PDEBUGLS0STAT + core0 pdebug status register + 0x60 + 0x20 + + + CORE_0_RCD_PDEBUGLS0STAT + core0_pdebug_s0stat + 0 + 32 + read-only + + + + + CORE_0_RCD_PDEBUGLS0ADDR + core0 pdebug status register + 0x64 + 0x20 + + + CORE_0_RCD_PDEBUGLS0ADDR + core0_pdebug_s0addr + 0 + 32 + read-only + + + + + CORE_0_RCD_PDEBUGLS0DATA + core0 pdebug status register + 0x68 + 0x20 + + + CORE_0_RCD_PDEBUGLS0DATA + core0_pdebug_s0data + 0 + 32 + read-only + + + + + CORE_0_RCD_SP + core0 pdebug status register + 0x6C + 0x20 + + + CORE_0_RCD_SP + core0_stack pointer + 0 + 32 + read-only + + + + + CORE_0_IRAM0_EXCEPTION_MONITOR_0 + core0 bus busy status regsiter + 0x70 + 0x20 + + + CORE_0_IRAM0_RECORDING_ADDR_0 + The first iram0's addr[25:2] status when trigger IRAM busy interrupt + 0 + 24 + read-only + + + CORE_0_IRAM0_RECORDING_WR_0 + The first iram0's wr status when trigger IRAM busy interrupt + 24 + 1 + read-only + + + CORE_0_IRAM0_RECORDING_LOADSTORE_0 + The first iram0's loadstore status when trigger IRAM busy interrupt + 25 + 1 + read-only + + + + + CORE_0_IRAM0_EXCEPTION_MONITOR_1 + core0 bus busy status regsiter + 0x74 + 0x20 + + + CORE_0_IRAM0_RECORDING_ADDR_1 + The second iram0's addr[25:2] status when trigger IRAM busy interrupt + 0 + 24 + read-only + + + CORE_0_IRAM0_RECORDING_WR_1 + The second iram0's wr status when trigger IRAM busy interrupt + 24 + 1 + read-only + + + CORE_0_IRAM0_RECORDING_LOADSTORE_1 + The second iram0's loadstore status when trigger IRAM busy interrupt + 25 + 1 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_0 + core0 bus busy status regsiter + 0x78 + 0x20 + + + CORE_0_DRAM0_RECORDING_ADDR_0 + The first dram0's addr[25:4] status when trigger DRAM busy interrupt + 0 + 22 + read-only + + + CORE_0_DRAM0_RECORDING_WR_0 + The first dram0's wr status when trigger DRAM busy interrupt + 22 + 1 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_1 + core0 bus busy status regsiter + 0x7C + 0x20 + + + CORE_0_DRAM0_RECORDING_BYTEEN_0 + The first dram0's byteen status when trigger DRAM busy interrupt + 0 + 16 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_2 + core0 bus busy status regsiter + 0x80 + 0x20 + 0xFFFFFFFF + + + CORE_0_DRAM0_RECORDING_PC_0 + The first dram0's PC status when trigger DRAM busy interrupt + 0 + 32 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_3 + core0 bus busy status regsiter + 0x84 + 0x20 + + + CORE_0_DRAM0_RECORDING_ADDR_1 + The second dram0's addr[25:4] status when trigger DRAM busy interrupt + 0 + 22 + read-only + + + CORE_0_DRAM0_RECORDING_WR_1 + The second dram0's wr status when trigger DRAM busy interrupt + 22 + 1 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_4 + core0 bus busy configuration regsiter + 0x88 + 0x20 + + + CORE_0_DRAM0_RECORDING_BYTEEN_1 + The second dram0's byteen status when trigger DRAM busy interrupt + 0 + 16 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_5 + core0 bus busy configuration regsiter + 0x8C + 0x20 + 0xFFFFFFFF + + + CORE_0_DRAM0_RECORDING_PC_1 + The second dram0's PC status when trigger DRAM busy interrupt + 0 + 32 + read-only + + + + + CORE_1_INTERRUPT_ENA + Core1 monitor enable configuration register + 0x90 + 0x20 + + + CORE_1_AREA_DRAM0_0_RD_ENA + Core1 dram0 area0 read monitor enable + 0 + 1 + read-write + + + CORE_1_AREA_DRAM0_0_WR_ENA + Core1 dram0 area0 write monitor enable + 1 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_RD_ENA + Core1 dram0 area1 read monitor enable + 2 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_WR_ENA + Core1 dram0 area1 write monitor enable + 3 + 1 + read-write + + + CORE_1_AREA_PIF_0_RD_ENA + Core1 PIF area0 read monitor enable + 4 + 1 + read-write + + + CORE_1_AREA_PIF_0_WR_ENA + Core1 PIF area0 write monitor enable + 5 + 1 + read-write + + + CORE_1_AREA_PIF_1_RD_ENA + Core1 PIF area1 read monitor enable + 6 + 1 + read-write + + + CORE_1_AREA_PIF_1_WR_ENA + Core1 PIF area1 write monitor enable + 7 + 1 + read-write + + + CORE_1_SP_SPILL_MIN_ENA + Core1 stackpoint overflow monitor enable + 8 + 1 + read-write + + + CORE_1_SP_SPILL_MAX_ENA + Core1 stackpoint underflow monitor enable + 9 + 1 + read-write + + + CORE_1_IRAM0_EXCEPTION_MONITOR_ENA + IBUS busy monitor enable + 10 + 1 + read-write + + + CORE_1_DRAM0_EXCEPTION_MONITOR_ENA + DBUS busy monitor enbale + 11 + 1 + read-write + + + + + CORE_1_INTERRUPT_RAW + Core1 monitor interrupt status register + 0x94 + 0x20 + + + CORE_1_AREA_DRAM0_0_RD_RAW + Core1 dram0 area0 read monitor interrupt status + 0 + 1 + read-only + + + CORE_1_AREA_DRAM0_0_WR_RAW + Core1 dram0 area0 write monitor interrupt status + 1 + 1 + read-only + + + CORE_1_AREA_DRAM0_1_RD_RAW + Core1 dram0 area1 read monitor interrupt status + 2 + 1 + read-only + + + CORE_1_AREA_DRAM0_1_WR_RAW + Core1 dram0 area1 write monitor interrupt status + 3 + 1 + read-only + + + CORE_1_AREA_PIF_0_RD_RAW + Core1 PIF area0 read monitor interrupt status + 4 + 1 + read-only + + + CORE_1_AREA_PIF_0_WR_RAW + Core1 PIF area0 write monitor interrupt status + 5 + 1 + read-only + + + CORE_1_AREA_PIF_1_RD_RAW + Core1 PIF area1 read monitor interrupt status + 6 + 1 + read-only + + + CORE_1_AREA_PIF_1_WR_RAW + Core1 PIF area1 write monitor interrupt status + 7 + 1 + read-only + + + CORE_1_SP_SPILL_MIN_RAW + Core1 stackpoint overflow monitor interrupt status + 8 + 1 + read-only + + + CORE_1_SP_SPILL_MAX_RAW + Core1 stackpoint underflow monitor interrupt status + 9 + 1 + read-only + + + CORE_1_IRAM0_EXCEPTION_MONITOR_RAW + IBUS busy monitor interrupt status + 10 + 1 + read-only + + + CORE_1_DRAM0_EXCEPTION_MONITOR_RAW + DBUS busy monitor initerrupt status + 11 + 1 + read-only + + + + + CORE_1_INTERRUPT_RLS + Core1 monitor interrupt enable register + 0x98 + 0x20 + + + CORE_1_AREA_DRAM0_0_RD_RLS + Core1 dram0 area0 read monitor interrupt enable + 0 + 1 + read-write + + + CORE_1_AREA_DRAM0_0_WR_RLS + Core1 dram0 area0 write monitor interrupt enable + 1 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_RD_RLS + Core1 dram0 area1 read monitor interrupt enable + 2 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_WR_RLS + Core1 dram0 area1 write monitor interrupt enable + 3 + 1 + read-write + + + CORE_1_AREA_PIF_0_RD_RLS + Core1 PIF area0 read monitor interrupt enable + 4 + 1 + read-write + + + CORE_1_AREA_PIF_0_WR_RLS + Core1 PIF area0 write monitor interrupt enable + 5 + 1 + read-write + + + CORE_1_AREA_PIF_1_RD_RLS + Core1 PIF area1 read monitor interrupt enable + 6 + 1 + read-write + + + CORE_1_AREA_PIF_1_WR_RLS + Core1 PIF area1 write monitor interrupt enable + 7 + 1 + read-write + + + CORE_1_SP_SPILL_MIN_RLS + Core1 stackpoint overflow monitor interrupt enable + 8 + 1 + read-write + + + CORE_1_SP_SPILL_MAX_RLS + Core1 stackpoint underflow monitor interrupt enable + 9 + 1 + read-write + + + CORE_1_IRAM0_EXCEPTION_MONITOR_RLS + IBUS busy monitor interrupt enable + 10 + 1 + read-write + + + CORE_1_DRAM0_EXCEPTION_MONITOR_RLS + DBUS busy monitor interrupt enbale + 11 + 1 + read-write + + + + + CORE_1_INTERRUPT_CLR + Core1 monitor interrupt clr register + 0x9C + 0x20 + + + CORE_1_AREA_DRAM0_0_RD_CLR + Core1 dram0 area0 read monitor interrupt clr + 0 + 1 + read-write + + + CORE_1_AREA_DRAM0_0_WR_CLR + Core1 dram0 area0 write monitor interrupt clr + 1 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_RD_CLR + Core1 dram0 area1 read monitor interrupt clr + 2 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_WR_CLR + Core1 dram0 area1 write monitor interrupt clr + 3 + 1 + read-write + + + CORE_1_AREA_PIF_0_RD_CLR + Core1 PIF area0 read monitor interrupt clr + 4 + 1 + read-write + + + CORE_1_AREA_PIF_0_WR_CLR + Core1 PIF area0 write monitor interrupt clr + 5 + 1 + read-write + + + CORE_1_AREA_PIF_1_RD_CLR + Core1 PIF area1 read monitor interrupt clr + 6 + 1 + read-write + + + CORE_1_AREA_PIF_1_WR_CLR + Core1 PIF area1 write monitor interrupt clr + 7 + 1 + read-write + + + CORE_1_SP_SPILL_MIN_CLR + Core1 stackpoint overflow monitor interrupt clr + 8 + 1 + read-write + + + CORE_1_SP_SPILL_MAX_CLR + Core1 stackpoint underflow monitor interrupt clr + 9 + 1 + read-write + + + CORE_1_IRAM0_EXCEPTION_MONITOR_CLR + IBUS busy monitor interrupt clr + 10 + 1 + read-write + + + CORE_1_DRAM0_EXCEPTION_MONITOR_CLR + DBUS busy monitor interrupt clr + 11 + 1 + read-write + + + + + CORE_1_AREA_DRAM0_0_MIN + Core1 dram0 region0 addr configuration register + 0xA0 + 0x20 + 0xFFFFFFFF + + + CORE_1_AREA_DRAM0_0_MIN + Core1 dram0 region0 start addr + 0 + 32 + read-write + + + + + CORE_1_AREA_DRAM0_0_MAX + Core1 dram0 region0 addr configuration register + 0xA4 + 0x20 + + + CORE_1_AREA_DRAM0_0_MAX + Core1 dram0 region0 end addr + 0 + 32 + read-write + + + + + CORE_1_AREA_DRAM0_1_MIN + Core1 dram0 region1 addr configuration register + 0xA8 + 0x20 + 0xFFFFFFFF + + + CORE_1_AREA_DRAM0_1_MIN + Core1 dram0 region1 start addr + 0 + 32 + read-write + + + + + CORE_1_AREA_DRAM0_1_MAX + Core1 dram0 region1 addr configuration register + 0xAC + 0x20 + + + CORE_1_AREA_DRAM0_1_MAX + Core1 dram0 region1 end addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PIF_0_MIN + Core1 PIF region0 addr configuration register + 0xB0 + 0x20 + 0xFFFFFFFF + + + CORE_1_AREA_PIF_0_MIN + Core1 PIF region0 start addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PIF_0_MAX + Core1 PIF region0 addr configuration register + 0xB4 + 0x20 + + + CORE_1_AREA_PIF_0_MAX + Core1 PIF region0 end addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PIF_1_MIN + Core1 PIF region1 addr configuration register + 0xB8 + 0x20 + 0xFFFFFFFF + + + CORE_1_AREA_PIF_1_MIN + Core1 PIF region1 start addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PIF_1_MAX + Core1 PIF region1 addr configuration register + 0xBC + 0x20 + + + CORE_1_AREA_PIF_1_MAX + Core1 PIF region1 end addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PC + Core1 area sp status register + 0xC0 + 0x20 + + + CORE_1_AREA_PC + the stackpointer when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_1_AREA_SP + Core1 area pc status register + 0xC4 + 0x20 + + + CORE_1_AREA_SP + the PC when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_1_SP_UNSTABLE + Core1 sp unstable configuration register + 0xC8 + 0x20 + 0x0000000B + + + CORE_1_SP_UNSTABLE + unstable period when window change,during this period no check stackpointer + 0 + 8 + read-write + + + + + CORE_1_SP_MIN + Core1 sp region configuration regsiter + 0xCC + 0x20 + + + CORE_1_SP_MIN + stack min value + 0 + 32 + read-write + + + + + CORE_1_SP_MAX + Core1 sp region configuration regsiter + 0xD0 + 0x20 + 0xFFFFFFFF + + + CORE_1_SP_MAX + stack max value + 0 + 32 + read-write + + + + + CORE_1_SP_PC + Core1 sp pc status register + 0xD4 + 0x20 + + + CORE_1_SP_PC + the PC when first touch stack monitor interrupt + 0 + 32 + read-only + + + + + CORE_1_RCD_PDEBUGENABLE + Core1 pdebug configuration register + 0xD8 + 0x20 + + + CORE_1_RCD_PDEBUGENABLE + Core1 Pdebugenable,set 1 to open Core1 Pdebug interface, then can get Core1 PC + 0 + 1 + read-write + + + + + CORE_1_RCD_RECORDING + Core1 pdebug status register + 0xDC + 0x20 + + + CORE_1_RCD_RECORDING + Pdebug record enable,set 1 to record Core1 pdebug interface signal + 0 + 1 + read-write + + + + + CORE_1_RCD_PDEBUGINST + Core1 pdebug status register + 0xE0 + 0x20 + + + CORE_1_RCD_PDEBUGINST + Core1 pdebuginst + 0 + 32 + read-only + + + + + CORE_1_RCD_PDEBUGSTATUS + Core1 pdebug status register + 0xE4 + 0x20 + + + CORE_1_RCD_PDEBUGSTATUS + Core1 pdebugstatus + 0 + 8 + read-only + + + + + CORE_1_RCD_PDEBUGDATA + Core1 pdebug status register + 0xE8 + 0x20 + + + CORE_1_RCD_PDEBUGDATA + Core1_pdebugdata + 0 + 32 + read-only + + + + + CORE_1_RCD_PDEBUGPC + Core1 pdebug status register + 0xEC + 0x20 + + + CORE_1_RCD_PDEBUGPC + Core1_pdebugPC + 0 + 32 + read-only + + + + + CORE_1_RCD_PDEBUGLS0STAT + Core1 pdebug status register + 0xF0 + 0x20 + + + CORE_1_RCD_PDEBUGLS0STAT + Core1_pdebug_s0stat + 0 + 32 + read-only + + + + + CORE_1_RCD_PDEBUGLS0ADDR + Core1 pdebug status register + 0xF4 + 0x20 + + + CORE_1_RCD_PDEBUGLS0ADDR + Core1_pdebug_s0addr + 0 + 32 + read-only + + + + + CORE_1_RCD_PDEBUGLS0DATA + Core1 pdebug status register + 0xF8 + 0x20 + + + CORE_1_RCD_PDEBUGLS0DATA + Core1_pdebug_s0data + 0 + 32 + read-only + + + + + CORE_1_RCD_SP + Core1 pdebug status register + 0xFC + 0x20 + + + CORE_1_RCD_SP + Core1_stack pointer + 0 + 32 + read-only + + + + + CORE_1_IRAM0_EXCEPTION_MONITOR_0 + Core1 bus busy status regsiter + 0x100 + 0x20 + + + CORE_1_IRAM0_RECORDING_ADDR_0 + The first iram0's addr[25:2] status when trigger IRAM busy interrupt + 0 + 24 + read-only + + + CORE_1_IRAM0_RECORDING_WR_0 + The first iram0's wr status when trigger IRAM busy interrupt + 24 + 1 + read-only + + + CORE_1_IRAM0_RECORDING_LOADSTORE_0 + The first iram0's loadstore status when trigger IRAM busy interrupt + 25 + 1 + read-only + + + + + CORE_1_IRAM0_EXCEPTION_MONITOR_1 + Core1 bus busy status regsiter + 0x104 + 0x20 + + + CORE_1_IRAM0_RECORDING_ADDR_1 + The second iram0's addr[25:2] status when trigger IRAM busy interrupt + 0 + 24 + read-only + + + CORE_1_IRAM0_RECORDING_WR_1 + The second iram0's wr status when trigger IRAM busy interrupt + 24 + 1 + read-only + + + CORE_1_IRAM0_RECORDING_LOADSTORE_1 + The second iram0's loadstore status when trigger IRAM busy interrupt + 25 + 1 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_0 + Core1 bus busy status regsiter + 0x108 + 0x20 + + + CORE_1_DRAM0_RECORDING_ADDR_0 + The first dram0's addr[25:4] status when trigger DRAM busy interrupt + 0 + 22 + read-only + + + CORE_1_DRAM0_RECORDING_WR_0 + The first dram0's wr status when trigger DRAM busy interrupt + 22 + 1 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_1 + Core1 bus busy status regsiter + 0x10C + 0x20 + + + CORE_1_DRAM0_RECORDING_BYTEEN_0 + The first dram0's byteen status when trigger DRAM busy interrupt + 0 + 16 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_2 + Core1 bus busy status regsiter + 0x110 + 0x20 + 0xFFFFFFFF + + + CORE_1_DRAM0_RECORDING_PC_0 + The first dram0's PC status when trigger DRAM busy interrupt + 0 + 32 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_3 + Core1 bus busy status regsiter + 0x114 + 0x20 + + + CORE_1_DRAM0_RECORDING_ADDR_1 + The second dram0's addr[25:4] status when trigger DRAM busy interrupt + 0 + 22 + read-only + + + CORE_1_DRAM0_RECORDING_WR_1 + The second dram0's wr status when trigger DRAM busy interrupt + 22 + 1 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_4 + Core1 bus busy status regsiter + 0x118 + 0x20 + + + CORE_1_DRAM0_RECORDING_BYTEEN_1 + The second dram0's byteen status when trigger DRAM busy interrupt + 0 + 16 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_5 + Core1 bus busy status regsiter + 0x11C + 0x20 + 0xFFFFFFFF + + + CORE_1_DRAM0_RECORDING_PC_1 + The second dram0's PC status when trigger DRAM busy interrupt + 0 + 32 + read-only + + + + + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 + bus busy configuration register + 0x120 + 0x20 + 0x000FFFFF + + + CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 + busy monitor window cycle + 0 + 20 + read-write + + + + + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 + bus busy configuration register + 0x124 + 0x20 + 0x000FFFFF + + + CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 + non busy cycle,for example: when cycle=100 and cycle=10,it means that in 100 cycle, if busy access success time less than 10, it will trigger interrutpt + 0 + 20 + read-write + + + + + LOG_SETTING + log set register + 0x128 + 0x20 + 0x00000040 + + + LOG_ENA + bus moniter enable: [0]Core1,[1]core1,[2]dma + 0 + 3 + read-write + + + LOG_MODE + check_mode:0:write,1:word,2:halword,3:byte,4:doubleword,5:4word + 3 + 3 + read-write + + + LOG_MEM_LOOP_ENABLE + mem_loop enable,1 means that loop write + 6 + 1 + read-write + + + + + LOG_DATA_0 + log check data register + 0x12C + 0x20 + + + LOG_DATA_0 + check data0 + 0 + 32 + read-write + + + + + LOG_DATA_1 + log check data register + 0x130 + 0x20 + + + LOG_DATA_1 + check data1 + 0 + 32 + read-write + + + + + LOG_DATA_2 + log check data register + 0x134 + 0x20 + + + LOG_DATA_2 + check data2 + 0 + 32 + read-write + + + + + LOG_DATA_3 + log check data register + 0x138 + 0x20 + + + LOG_DATA_3 + check data3 + 0 + 32 + read-write + + + + + LOG_DATA_MASK + log check data mask register + 0x13C + 0x20 + + + LOG_DATA_SIZE + data mask + 0 + 16 + read-write + + + + + LOG_MIN + log check region configuration register + 0x140 + 0x20 + + + LOG_MIN + check region min addr + 0 + 32 + read-write + + + + + LOG_MAX + log check region configuration register + 0x144 + 0x20 + + + LOG_MAX + check region max addr + 0 + 32 + read-write + + + + + LOG_MEM_START + log mem region configuration register + 0x148 + 0x20 + + + LOG_MEM_START + mem start addr + 0 + 32 + read-write + + + + + LOG_MEM_END + log mem region configuration register + 0x14C + 0x20 + + + LOG_MEM_END + mem end addr + 0 + 32 + read-write + + + + + LOG_MEM_WRITING_ADDR + log mem addr status register + 0x150 + 0x20 + + + LOG_MEM_WRITING_ADDR + mem current addr, it means next writing addr + 0 + 32 + read-only + + + + + LOG_MEM_FULL_FLAG + log mem status register + 0x154 + 0x20 + + + LOG_MEM_FULL_FLAG + when it's 1,show that mem write loop morte than one time. + 0 + 1 + read-write + + + + + DATE + version register + 0x1FC + 0x20 + 0x02003040 + + + DATE + version register + 0 + 28 + read-write + + + + + + + DMA + DMA (Direct Memory Access) Controller + DMA + 0x6003F000 + + 0x0 + 0x320 + registers + + + DMA_IN_CH0 + 66 + + + DMA_IN_CH1 + 67 + + + DMA_IN_CH2 + 68 + + + DMA_IN_CH3 + 69 + + + DMA_IN_CH4 + 70 + + + DMA_OUT_CH0 + 71 + + + DMA_OUT_CH1 + 72 + + + DMA_OUT_CH2 + 73 + + + DMA_OUT_CH3 + 74 + + + DMA_OUT_CH4 + 75 + + + DMA_APBPERI_PMS + 84 + + + BACKUP_PMS_VIOLATE + 93 + + + DMA_EXTMEM_REJECT + 98 + + + + 5 + 0xC0 + IN_CONF0_CH%s + Configure 0 register of Rx channel 0 + 0x0 + 0x20 + + + IN_RST + This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. + 0 + 1 + read-write + + + IN_LOOP_TEST + reserved + 1 + 1 + read-write + + + INDSCR_BURST_EN + Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. + 2 + 1 + read-write + + + IN_DATA_BURST_EN + Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. + 3 + 1 + read-write + + + MEM_TRANS_EN + Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + 4 + 1 + read-write + + + + + 5 + 0xC0 + IN_CONF1_CH%s + Configure 1 register of Rx channel 0 + 0x4 + 0x20 + 0x0000000C + + + DMA_INFIFO_FULL_THRS + This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register. + 0 + 12 + read-write + + + IN_CHECK_OWNER + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + IN_EXT_MEM_BK_SIZE + Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved + 13 + 2 + read-write + + + + + 5 + 0xC0 + IN_INT_RAW_CH%s + Raw status interrupt of Rx channel 0 + 0x8 + 0x20 + + + IN_DONE + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. + 0 + 1 + read-write + + + IN_SUC_EOF + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. + 1 + 1 + read-write + + + IN_ERR_EOF + The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved. + 2 + 1 + read-write + + + IN_DSCR_ERR + The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0. + 3 + 1 + read-write + + + IN_DSCR_EMPTY + The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0. + 4 + 1 + read-write + + + INFIFO_FULL_WM + The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0. + 5 + 1 + read-write + + + INFIFO_OVF_L1 + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + 6 + 1 + read-write + + + INFIFO_UDF_L1 + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + 7 + 1 + read-write + + + INFIFO_OVF_L3 + This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is overflow. + 8 + 1 + read-write + + + INFIFO_UDF_L3 + This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is underflow. + 9 + 1 + read-write + + + + + 5 + 0xC0 + IN_INT_ST_CH%s + Masked interrupt of Rx channel 0 + 0xC + 0x20 + + + IN_DONE + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + IN_DSCR_ERR + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-only + + + IN_DSCR_EMPTY + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + read-only + + + INFIFO_FULL_WM + The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt. + 5 + 1 + read-only + + + INFIFO_OVF_L1 + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 6 + 1 + read-only + + + INFIFO_UDF_L1 + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 7 + 1 + read-only + + + INFIFO_OVF_L3 + The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. + 8 + 1 + read-only + + + INFIFO_UDF_L3 + The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. + 9 + 1 + read-only + + + + + 5 + 0xC0 + IN_INT_ENA_CH%s + Interrupt enable bits of Rx channel 0 + 0x10 + 0x20 + + + IN_DONE + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + IN_DSCR_ERR + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-write + + + IN_DSCR_EMPTY + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + read-write + + + INFIFO_FULL_WM + The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt. + 5 + 1 + read-write + + + INFIFO_OVF_L1 + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 6 + 1 + read-write + + + INFIFO_UDF_L1 + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 7 + 1 + read-write + + + INFIFO_OVF_L3 + The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. + 8 + 1 + read-write + + + INFIFO_UDF_L3 + The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. + 9 + 1 + read-write + + + + + 5 + 0xC0 + IN_INT_CLR_CH%s + Interrupt clear bits of Rx channel 0 + 0x14 + 0x20 + + + IN_DONE + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + IN_DSCR_ERR + Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + write-only + + + IN_DSCR_EMPTY + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + write-only + + + DMA_INFIFO_FULL_WM + Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt. + 5 + 1 + write-only + + + INFIFO_OVF_L1 + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 6 + 1 + write-only + + + INFIFO_UDF_L1 + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 7 + 1 + write-only + + + INFIFO_OVF_L3 + Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. + 8 + 1 + write-only + + + INFIFO_UDF_L3 + Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. + 9 + 1 + write-only + + + + + 5 + 0xC0 + INFIFO_STATUS_CH%s + Receive FIFO status of Rx channel 0 + 0x18 + 0x20 + 0x0F00003A + + + INFIFO_FULL_L1 + L1 Rx FIFO full signal for Rx channel 0. + 0 + 1 + read-only + + + INFIFO_EMPTY_L1 + L1 Rx FIFO empty signal for Rx channel 0. + 1 + 1 + read-only + + + INFIFO_FULL_L2 + L2 Rx FIFO full signal for Rx channel 0. + 2 + 1 + read-only + + + INFIFO_EMPTY_L2 + L2 Rx FIFO empty signal for Rx channel 0. + 3 + 1 + read-only + + + INFIFO_FULL_L3 + L3 Rx FIFO full signal for Rx channel 0. + 4 + 1 + read-only + + + INFIFO_EMPTY_L3 + L3 Rx FIFO empty signal for Rx channel 0. + 5 + 1 + read-only + + + INFIFO_CNT_L1 + The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + 6 + 6 + read-only + + + INFIFO_CNT_L2 + The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0. + 12 + 7 + read-only + + + INFIFO_CNT_L3 + The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0. + 19 + 5 + read-only + + + IN_REMAIN_UNDER_1B_L3 + reserved + 24 + 1 + read-only + + + IN_REMAIN_UNDER_2B_L3 + reserved + 25 + 1 + read-only + + + IN_REMAIN_UNDER_3B_L3 + reserved + 26 + 1 + read-only + + + IN_REMAIN_UNDER_4B_L3 + reserved + 27 + 1 + read-only + + + IN_BUF_HUNGRY + reserved + 28 + 1 + read-only + + + + + 5 + 0xC0 + IN_POP_CH%s + Pop control register of Rx channel 0 + 0x1C + 0x20 + 0x00000800 + + + INFIFO_RDATA + This register stores the data popping from DMA FIFO. + 0 + 12 + read-only + + + INFIFO_POP + Set this bit to pop data from DMA FIFO. + 12 + 1 + read-write + + + + + 5 + 0xC0 + IN_LINK_CH%s + Link descriptor configure and control register of Rx channel 0 + 0x20 + 0x20 + 0x01100000 + + + INLINK_ADDR + This register stores the 20 least significant bits of the first inlink descriptor's address. + 0 + 20 + read-write + + + INLINK_AUTO_RET + Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. + 20 + 1 + read-write + + + INLINK_STOP + Set this bit to stop dealing with the inlink descriptors. + 21 + 1 + read-write + + + INLINK_START + Set this bit to start dealing with the inlink descriptors. + 22 + 1 + read-write + + + INLINK_RESTART + Set this bit to mount a new inlink descriptor. + 23 + 1 + read-write + + + INLINK_PARK + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 24 + 1 + read-only + + + + + 5 + 0xC0 + IN_STATE_CH%s + Receive status of Rx channel 0 + 0x24 + 0x20 + + + INLINK_DSCR_ADDR + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE + reserved + 18 + 2 + read-only + + + IN_STATE + reserved + 20 + 3 + read-only + + + + + 5 + 0xC0 + IN_SUC_EOF_DES_ADDR_CH%s + Inlink descriptor address when EOF occurs of Rx channel 0 + 0x28 + 0x20 + + + IN_SUC_EOF_DES_ADDR + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + 5 + 0xC0 + IN_ERR_EOF_DES_ADDR_CH%s + Inlink descriptor address when errors occur of Rx channel 0 + 0x2C + 0x20 + + + IN_ERR_EOF_DES_ADDR + This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. + 0 + 32 + read-only + + + + + 5 + 0xC0 + IN_DSCR_CH%s + Current inlink descriptor address of Rx channel 0 + 0x30 + 0x20 + + + INLINK_DSCR + The address of the current inlink descriptor x. + 0 + 32 + read-only + + + + + 5 + 0xC0 + IN_DSCR_BF0_CH%s + The last inlink descriptor address of Rx channel 0 + 0x34 + 0x20 + + + INLINK_DSCR_BF0 + The address of the last inlink descriptor x-1. + 0 + 32 + read-only + + + + + 5 + 0xC0 + IN_DSCR_BF1_CH%s + The second-to-last inlink descriptor address of Rx channel 0 + 0x38 + 0x20 + + + INLINK_DSCR_BF1 + The address of the second-to-last inlink descriptor x-2. + 0 + 32 + read-only + + + + + 5 + 0xC0 + IN_WIGHT_CH%s + Weight register of Rx channel 0 + 0x3C + 0x20 + 0x00000F00 + + + RX_WEIGHT + The weight of Rx channel 0. + 8 + 4 + read-write + + + + + 5 + 0xC0 + IN_PRI_CH%s + Priority register of Rx channel 0 + 0x44 + 0x20 + + + RX_PRI + The priority of Rx channel 0. The larger of the value, the higher of the priority. + 0 + 4 + read-write + + + + + 5 + 0xC0 + IN_PERI_SEL_CH%s + Peripheral selection of Rx channel 0 + 0x48 + 0x20 + 0x0000003F + + + PERI_IN_SEL + This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT. + 0 + 6 + read-write + + + + + 5 + 0xC0 + OUT_CONF0_CH%s + Configure 0 register of Tx channel 0 + 0x60 + 0x20 + 0x00000008 + + + OUT_RST + This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. + 0 + 1 + read-write + + + OUT_LOOP_TEST + reserved + 1 + 1 + read-write + + + OUT_AUTO_WRBACK + Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + 2 + 1 + read-write + + + OUT_EOF_MODE + EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA + 3 + 1 + read-write + + + OUTDSCR_BURST_EN + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + 4 + 1 + read-write + + + OUT_DATA_BURST_EN + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. + 5 + 1 + read-write + + + + + 5 + 0xC0 + OUT_CONF1_CH%s + Configure 1 register of Tx channel 0 + 0x64 + 0x20 + + + OUT_CHECK_OWNER + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + OUT_EXT_MEM_BK_SIZE + Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved + 13 + 2 + read-write + + + + + 5 + 0xC0 + OUT_INT_RAW_CH%s + Raw status interrupt of Tx channel 0 + 0x68 + 0x20 + + + OUT_DONE + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + 0 + 1 + read-write + + + OUT_EOF + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + 1 + 1 + read-write + + + OUT_DSCR_ERR + The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. + 2 + 1 + read-write + + + OUT_TOTAL_EOF + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1 + This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1 + This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. + 5 + 1 + read-write + + + OUTFIFO_OVF_L3 + This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is overflow. + 6 + 1 + read-write + + + OUTFIFO_UDF_L3 + This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is underflow. + 7 + 1 + read-write + + + + + 5 + 0xC0 + OUT_INT_ST_CH%s + Masked interrupt of Tx channel 0 + 0x6C + 0x20 + + + OUT_DONE + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + OUT_EOF + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + OUT_DSCR_ERR + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_TOTAL_EOF + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-only + + + OUTFIFO_OVF_L1 + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + OUTFIFO_UDF_L1 + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + OUTFIFO_OVF_L3 + The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. + 6 + 1 + read-only + + + OUTFIFO_UDF_L3 + The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. + 7 + 1 + read-only + + + + + 5 + 0xC0 + OUT_INT_ENA_CH%s + Interrupt enable bits of Tx channel 0 + 0x70 + 0x20 + + + OUT_DONE + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + OUT_EOF + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + OUT_DSCR_ERR + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_TOTAL_EOF + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1 + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1 + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + OUTFIFO_OVF_L3 + The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. + 6 + 1 + read-write + + + OUTFIFO_UDF_L3 + The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. + 7 + 1 + read-write + + + + + 5 + 0xC0 + OUT_INT_CLR_CH%s + Interrupt clear bits of Tx channel 0 + 0x74 + 0x20 + + + OUT_DONE + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + OUT_EOF + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + OUT_DSCR_ERR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_TOTAL_EOF + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + write-only + + + OUTFIFO_OVF_L1 + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + OUTFIFO_UDF_L1 + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + OUTFIFO_OVF_L3 + Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. + 6 + 1 + write-only + + + OUTFIFO_UDF_L3 + Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. + 7 + 1 + write-only + + + + + 5 + 0xC0 + OUTFIFO_STATUS_CH%s + Transmit FIFO status of Tx channel 0 + 0x78 + 0x20 + 0x0780002A + + + OUTFIFO_FULL_L1 + L1 Tx FIFO full signal for Tx channel 0. + 0 + 1 + read-only + + + OUTFIFO_EMPTY_L1 + L1 Tx FIFO empty signal for Tx channel 0. + 1 + 1 + read-only + + + OUTFIFO_FULL_L2 + L2 Tx FIFO full signal for Tx channel 0. + 2 + 1 + read-only + + + OUTFIFO_EMPTY_L2 + L2 Tx FIFO empty signal for Tx channel 0. + 3 + 1 + read-only + + + OUTFIFO_FULL_L3 + L3 Tx FIFO full signal for Tx channel 0. + 4 + 1 + read-only + + + OUTFIFO_EMPTY_L3 + L3 Tx FIFO empty signal for Tx channel 0. + 5 + 1 + read-only + + + OUTFIFO_CNT_L1 + The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + 6 + 5 + read-only + + + OUTFIFO_CNT_L2 + The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0. + 11 + 7 + read-only + + + OUTFIFO_CNT_L3 + The register stores the byte number of the data in L3 Tx FIFO for Tx channel 0. + 18 + 5 + read-only + + + OUT_REMAIN_UNDER_1B_L3 + reserved + 23 + 1 + read-only + + + OUT_REMAIN_UNDER_2B_L3 + reserved + 24 + 1 + read-only + + + OUT_REMAIN_UNDER_3B_L3 + reserved + 25 + 1 + read-only + + + OUT_REMAIN_UNDER_4B_L3 + reserved + 26 + 1 + read-only + + + + + 5 + 0xC0 + OUT_PUSH_CH%s + Push control register of Rx channel 0 + 0x7C + 0x20 + + + OUTFIFO_WDATA + This register stores the data that need to be pushed into DMA FIFO. + 0 + 9 + read-write + + + OUTFIFO_PUSH + Set this bit to push data into DMA FIFO. + 9 + 1 + read-write + + + + + 5 + 0xC0 + OUT_LINK_CH%s + Link descriptor configure and control register of Tx channel 0 + 0x80 + 0x20 + 0x00800000 + + + OUTLINK_ADDR + This register stores the 20 least significant bits of the first outlink descriptor's address. + 0 + 20 + read-write + + + OUTLINK_STOP + Set this bit to stop dealing with the outlink descriptors. + 20 + 1 + read-write + + + OUTLINK_START + Set this bit to start dealing with the outlink descriptors. + 21 + 1 + read-write + + + OUTLINK_RESTART + Set this bit to restart a new outlink from the last address. + 22 + 1 + read-write + + + OUTLINK_PARK + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 23 + 1 + read-only + + + + + 5 + 0xC0 + OUT_STATE_CH%s + Transmit status of Tx channel 0 + 0x84 + 0x20 + + + OUTLINK_DSCR_ADDR + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE + reserved + 18 + 2 + read-only + + + OUT_STATE + reserved + 20 + 3 + read-only + + + + + 5 + 0xC0 + OUT_EOF_DES_ADDR_CH%s + Outlink descriptor address when EOF occurs of Tx channel 0 + 0x88 + 0x20 + + + OUT_EOF_DES_ADDR + This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + 5 + 0xC0 + OUT_EOF_BFR_DES_ADDR_CH%s + The last outlink descriptor address when EOF occurs of Tx channel 0 + 0x8C + 0x20 + + + OUT_EOF_BFR_DES_ADDR + This register stores the address of the outlink descriptor before the last outlink descriptor. + 0 + 32 + read-only + + + + + 5 + 0xC0 + OUT_DSCR_CH%s + Current inlink descriptor address of Tx channel 0 + 0x90 + 0x20 + + + OUTLINK_DSCR + The address of the current outlink descriptor y. + 0 + 32 + read-only + + + + + 5 + 0xC0 + OUT_DSCR_BF0_CH%s + The last inlink descriptor address of Tx channel 0 + 0x94 + 0x20 + + + OUTLINK_DSCR_BF0 + The address of the last outlink descriptor y-1. + 0 + 32 + read-only + + + + + 5 + 0xC0 + OUT_DSCR_BF1_CH%s + The second-to-last inlink descriptor address of Tx channel 0 + 0x98 + 0x20 + + + OUTLINK_DSCR_BF1 + The address of the second-to-last inlink descriptor x-2. + 0 + 32 + read-only + + + + + 5 + 0xC0 + OUT_WIGHT_CH%s + Weight register of Rx channel 0 + 0x9C + 0x20 + 0x00000F00 + + + TX_WEIGHT + The weight of Tx channel 0. + 8 + 4 + read-write + + + + + 5 + 0xC0 + OUT_PRI_CH%s + Priority register of Tx channel 0. + 0xA4 + 0x20 + + + TX_PRI + The priority of Tx channel 0. The larger of the value, the higher of the priority. + 0 + 4 + read-write + + + + + 5 + 0xC0 + OUT_PERI_SEL_CH%s + Peripheral selection of Tx channel 0 + 0xA8 + 0x20 + 0x0000003F + + + PERI_OUT_SEL + This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT. + 0 + 6 + read-write + + + + + AHB_TEST + reserved + 0x3C0 + 0x20 + + + AHB_TESTMODE + reserved + 0 + 3 + read-write + + + AHB_TESTADDR + reserved + 4 + 2 + read-write + + + + + PD_CONF + reserved + 0x3C4 + 0x20 + 0x00000020 + + + DMA_RAM_FORCE_PD + Set this bit to force power down DMA internal memory. + 4 + 1 + read-write + + + DMA_RAM_FORCE_PU + Set this bit to force power up DMA internal memory + 5 + 1 + read-write + + + DMA_RAM_CLK_FO + 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA. + 6 + 1 + read-write + + + + + MISC_CONF + MISC register + 0x3C8 + 0x20 + + + AHBM_RST_INTER + Set this bit, then clear this bit to reset the internal ahb FSM. + 0 + 1 + read-write + + + AHBM_RST_EXTER + Set this bit, then clear this bit to reset the external ahb FSM. + 1 + 1 + read-write + + + ARB_PRI_DIS + Set this bit to disable priority arbitration function. + 2 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 4 + 1 + read-write + + + + + 5 + 0x8 + IN_SRAM_SIZE_CH%s + Receive L2 FIFO depth of Rx channel 0 + 0x3CC + 0x20 + 0x0000000E + + + IN_SIZE + This register is used to configure the size of L2 Tx FIFO for Rx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes. + 0 + 7 + read-write + + + + + 5 + 0x8 + OUT_SRAM_SIZE_CH%s + Transmit L2 FIFO depth of Tx channel 0 + 0x3D0 + 0x20 + 0x0000000E + + + OUT_SIZE + This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes. + 0 + 7 + read-write + + + + + EXTMEM_REJECT_ADDR + Reject address accessing external RAM + 0x3F4 + 0x20 + + + EXTMEM_REJECT_ADDR + This register store the first address rejected by permission control when accessing external RAM. + 0 + 32 + read-only + + + + + EXTMEM_REJECT_ST + Reject status accessing external RAM + 0x3F8 + 0x20 + + + EXTMEM_REJECT_ATRR + The reject accessing. Bit 0: if this bit is 1, the rejected accessing is READ. Bit 1: if this bit is 1, the rejected accessing is WRITE. + 0 + 2 + read-only + + + EXTMEM_REJECT_CHANNEL_NUM + The register indicate the reject accessing from which channel. + 2 + 4 + read-only + + + EXTMEM_REJECT_PERI_NUM + This register indicate reject accessing from which peripheral. + 6 + 6 + read-only + + + + + EXTMEM_REJECT_INT_RAW + Raw interrupt status of external RAM permission + 0x3FC + 0x20 + + + EXTMEM_REJECT_INT_RAW + The raw interrupt bit turns to high level when accessing external RAM is rejected by permission control. + 0 + 1 + read-write + + + + + EXTMEM_REJECT_INT_ST + Masked interrupt status of external RAM permission + 0x400 + 0x20 + + + EXTMEM_REJECT_INT_ST + The raw interrupt status bit for the EXTMEM_REJECT_INT interrupt. + 0 + 1 + read-only + + + + + EXTMEM_REJECT_INT_ENA + Interrupt enable bits of external RAM permission + 0x404 + 0x20 + + + EXTMEM_REJECT_INT_ENA + The interrupt enable bit for the EXTMEM_REJECT_INT interrupt. + 0 + 1 + read-write + + + + + EXTMEM_REJECT_INT_CLR + Interrupt clear bits of external RAM permission + 0x408 + 0x20 + + + EXTMEM_REJECT_INT_CLR + Set this bit to clear the EXTMEM_REJECT_INT interrupt. + 0 + 1 + write-only + + + + + DATE + Version control register + 0x40C + 0x20 + 0x02101180 + + + DATE + register version. + 0 + 32 + read-write + + + + + + + DS + Digital Signature + DS + 0x6003D000 + + 0x0 + 0xA5C + registers + + + + 1584 + 0x1 + C_MEM[%s] + Memory C + 0x0 + 0x8 + + + 4 + 0x4 + IV_%s + IV block data + 0x630 + 0x20 + + + IV_0 + Stores IV block data + 0 + 32 + read-write + + + + + 512 + 0x1 + X_MEM[%s] + Memory X + 0x800 + 0x8 + + + 512 + 0x1 + Z_MEM[%s] + Memory Z + 0xA00 + 0x8 + + + SET_START + Activates the DS peripheral + 0xE00 + 0x20 + + + SET_START + Write 1 to this register to active the DS peripheral + 0 + 1 + write-only + + + + + SET_ME + Starts DS operation + 0xE04 + 0x20 + + + SET_ME + Write 1 to this register to start DS operation. + 0 + 1 + write-only + + + + + SET_FINISH + Ends DS operation + 0xE08 + 0x20 + + + SET_FINISH + Write 1 to this register to end DS operation. + 0 + 1 + write-only + + + + + QUERY_BUSY + Status of the DS perihperal + 0xE0C + 0x20 + + + QUERY_BUSY + Stores the status of the DS peripheral. 1: The DS peripheral is busy. 0: The DS peripheral is idle. + 0 + 1 + read-only + + + + + QUERY_KEY_WRONG + Checks the reason why DS_KEY is not ready + 0xE10 + 0x20 + + + QUERY_KEY_WRONG + 1-15: HMAC was activated, but the DS peripheral did not successfully receive the DS_KEY from the HMAC peripheral. (The biggest value is 15). 0: HMAC is not activated. + 0 + 4 + read-only + + + + + QUERY_CHECK + Queries DS check result + 0xE14 + 0x20 + + + MD_ERROR + MD checkout result. 1: The MD check fails. 0: The MD check passes. + 0 + 1 + read-only + + + PADDING_BAD + padding checkout result. 1: The padding check fails. 0: The padding check passes. + 1 + 1 + read-only + + + + + DATE + DS version control register + 0xE20 + 0x20 + 0x20191217 + + + DATE + ds version information + 0 + 30 + read-write + + + + + + + EFUSE + eFuse Controller + EFUSE + 0x60007000 + + 0x0 + 0x1CC + registers + + + EFUSE + 36 + + + + PGM_DATA0 + Register 0 that stores data to be programmed. + 0x0 + 0x20 + + + PGM_DATA_0 + The content of the 0th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA1 + Register 1 that stores data to be programmed. + 0x4 + 0x20 + + + PGM_DATA_1 + The content of the 1st 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA2 + Register 2 that stores data to be programmed. + 0x8 + 0x20 + + + PGM_DATA_2 + The content of the 2nd 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA3 + Register 3 that stores data to be programmed. + 0xC + 0x20 + + + PGM_DATA_3 + The content of the 3rd 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA4 + Register 4 that stores data to be programmed. + 0x10 + 0x20 + + + PGM_DATA_4 + The content of the 4th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA5 + Register 5 that stores data to be programmed. + 0x14 + 0x20 + + + PGM_DATA_5 + The content of the 5th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA6 + Register 6 that stores data to be programmed. + 0x18 + 0x20 + + + PGM_DATA_6 + The content of the 6th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA7 + Register 7 that stores data to be programmed. + 0x1C + 0x20 + + + PGM_DATA_7 + The content of the 7th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE0 + Register 0 that stores the RS code to be programmed. + 0x20 + 0x20 + + + PGM_RS_DATA_0 + The content of the 0th 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE1 + Register 1 that stores the RS code to be programmed. + 0x24 + 0x20 + + + PGM_RS_DATA_1 + The content of the 1st 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE2 + Register 2 that stores the RS code to be programmed. + 0x28 + 0x20 + + + PGM_RS_DATA_2 + The content of the 2nd 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + RD_WR_DIS + BLOCK0 data register 0. + 0x2C + 0x20 + + + WR_DIS + Disable programming of individual eFuses. + 0 + 32 + read-only + + + + + RD_REPEAT_DATA0 + BLOCK0 data register 1. + 0x30 + 0x20 + + + RD_DIS + Set this bit to disable reading from BlOCK4-10. + 0 + 7 + read-only + + + DIS_RTC_RAM_BOOT + Set this bit to disable boot from RTC RAM. + 7 + 1 + read-only + + + DIS_ICACHE + Set this bit to disable Icache. + 8 + 1 + read-only + + + DIS_DCACHE + Set this bit to disable Dcache. + 9 + 1 + read-only + + + DIS_DOWNLOAD_ICACHE + Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 7). + 10 + 1 + read-only + + + DIS_DOWNLOAD_DCACHE + Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0, 1, 2, 3, 6, 7). + 11 + 1 + read-only + + + DIS_FORCE_DOWNLOAD + Set this bit to disable the function that forces chip into download mode. + 12 + 1 + read-only + + + DIS_USB + Set this bit to disable USB function. + 13 + 1 + read-only + + + DIS_CAN + Set this bit to disable CAN function. + 14 + 1 + read-only + + + DIS_APP_CPU + Disable app cpu. + 15 + 1 + read-only + + + SOFT_DIS_JTAG + Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module. + 16 + 3 + read-only + + + DIS_PAD_JTAG + Set this bit to disable JTAG in the hard way. JTAG is disabled permanently. + 19 + 1 + read-only + + + DIS_DOWNLOAD_MANUAL_ENCRYPT + Set this bit to disable flash encryption when in download boot modes. + 20 + 1 + read-only + + + USB_DREFH + Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse. + 21 + 2 + read-only + + + USB_DREFL + Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse. + 23 + 2 + read-only + + + USB_EXCHG_PINS + Set this bit to exchange USB D+ and D- pins. + 25 + 1 + read-only + + + EXT_PHY_ENABLE + Set this bit to enable external PHY. + 26 + 1 + read-only + + + BTLC_GPIO_ENABLE + Bluetooth GPIO signal output security level control. + 27 + 2 + read-only + + + VDD_SPI_MODECURLIM + SPI regulator switches current limit mode. + 29 + 1 + read-only + + + VDD_SPI_DREFH + SPI regulator high voltage reference. + 30 + 2 + read-only + + + + + RD_REPEAT_DATA1 + BLOCK0 data register 2. + 0x34 + 0x20 + + + VDD_SPI_DREFM + SPI regulator medium voltage reference. + 0 + 2 + read-only + + + VDD_SPI_DREFL + SPI regulator low voltage reference. + 2 + 2 + read-only + + + VDD_SPI_XPD + SPI regulator power up signal. + 4 + 1 + read-only + + + VDD_SPI_TIEH + SPI regulator output is short connected to VDD3P3_RTC_IO. + 5 + 1 + read-only + + + VDD_SPI_FORCE + Set this bit and force to use the configuration of eFuse to configure VDD_SPI. + 6 + 1 + read-only + + + VDD_SPI_EN_INIT + Set SPI regulator to 0 to configure init[1:0]=0. + 7 + 1 + read-only + + + VDD_SPI_ENCURLIM + Set SPI regulator to 1 to enable output current limit. + 8 + 1 + read-only + + + VDD_SPI_DCURLIM + Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d). + 9 + 3 + read-only + + + VDD_SPI_INIT + Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K 3: 2 K. + 12 + 2 + read-only + + + VDD_SPI_DCAP + Prevents SPI regulator from overshoot. + 14 + 2 + read-only + + + WDT_DELAY_SEL + Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000. + 16 + 2 + read-only + + + SPI_BOOT_CRYPT_CNT + Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable. + 18 + 3 + read-only + + + SECURE_BOOT_KEY_REVOKE0 + Set this bit to enable revoking first secure boot key. + 21 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE1 + Set this bit to enable revoking second secure boot key. + 22 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE2 + Set this bit to enable revoking third secure boot key. + 23 + 1 + read-only + + + KEY_PURPOSE_0 + Purpose of Key0. + 24 + 4 + read-only + + + KEY_PURPOSE_1 + Purpose of Key1. + 28 + 4 + read-only + + + + + RD_REPEAT_DATA2 + BLOCK0 data register 3. + 0x38 + 0x20 + + + KEY_PURPOSE_2 + Purpose of Key2. + 0 + 4 + read-only + + + KEY_PURPOSE_3 + Purpose of Key3. + 4 + 4 + read-only + + + KEY_PURPOSE_4 + Purpose of Key4. + 8 + 4 + read-only + + + KEY_PURPOSE_5 + Purpose of Key5. + 12 + 4 + read-only + + + RPT4_RESERVED0 + Reserved (used for four backups method). + 16 + 4 + read-only + + + SECURE_BOOT_EN + Set this bit to enable secure boot. + 20 + 1 + read-only + + + SECURE_BOOT_AGGRESSIVE_REVOKE + Set this bit to enable revoking aggressive secure boot. + 21 + 1 + read-only + + + DIS_USB_JTAG + Set this bit to disable function of usb switch to jtag in module of usb device. + 22 + 1 + read-only + + + DIS_USB_DEVICE + Set this bit to disable usb device. + 23 + 1 + read-only + + + STRAP_JTAG_SEL + Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. + 24 + 1 + read-only + + + USB_PHY_SEL + This bit is used to switch internal PHY and external PHY for USB OTG and USB Device. 0: internal PHY is assigned to USB Device while external PHY is assigned to USB OTG. 1: internal PHY is assigned to USB OTG while external PHY is assigned to USB Device. + 25 + 1 + read-only + + + POWER_GLITCH_DSENSE + Sample delay configuration of power glitch. + 26 + 2 + read-only + + + FLASH_TPUW + Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value. Otherwise, the waiting time is twice the configurable value. + 28 + 4 + read-only + + + + + RD_REPEAT_DATA3 + BLOCK0 data register 4. + 0x3C + 0x20 + + + DIS_DOWNLOAD_MODE + Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7). + 0 + 1 + read-only + + + DIS_LEGACY_SPI_BOOT + Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4). + 1 + 1 + read-only + + + UART_PRINT_CHANNEL + Selectes the default UART print channel. 0: UART0. 1: UART1. + 2 + 1 + read-only + + + FLASH_ECC_MODE + Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode. + 3 + 1 + read-only + + + DIS_USB_DOWNLOAD_MODE + Set this bit to disable UART download mode through USB. + 4 + 1 + read-only + + + ENABLE_SECURITY_DOWNLOAD + Set this bit to enable secure UART download mode. + 5 + 1 + read-only + + + UART_PRINT_CONTROL + Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled. + 6 + 2 + read-only + + + PIN_POWER_SELECTION + GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI. + 8 + 1 + read-only + + + FLASH_TYPE + Set the maximum lines of SPI flash. 0: four lines. 1: eight lines. + 9 + 1 + read-only + + + FLASH_PAGE_SIZE + Set Flash page size. + 10 + 2 + read-only + + + FLASH_ECC_EN + Set 1 to enable ECC for flash boot. + 12 + 1 + read-only + + + FORCE_SEND_RESUME + Set this bit to force ROM code to send a resume command during SPI boot. + 13 + 1 + read-only + + + SECURE_VERSION + Secure version (used by ESP-IDF anti-rollback feature). + 14 + 16 + read-only + + + POWERGLITCH_EN + Set this bit to enable power glitch function. + 30 + 1 + read-only + + + RPT4_RESERVED1 + Reserved (used for four backups method). + 31 + 1 + read-only + + + + + RD_REPEAT_DATA4 + BLOCK0 data register 5. + 0x40 + 0x20 + + + RPT4_RESERVED2 + Reserved (used for four backups method). + 0 + 24 + read-only + + + + + RD_MAC_SPI_SYS_0 + BLOCK1 data register 0. + 0x44 + 0x20 + + + MAC_0 + Stores the low 32 bits of MAC address. + 0 + 32 + read-only + + + + + RD_MAC_SPI_SYS_1 + BLOCK1 data register 1. + 0x48 + 0x20 + + + MAC_1 + Stores the high 16 bits of MAC address. + 0 + 16 + read-only + + + SPI_PAD_CONF_0 + Stores the zeroth part of SPI_PAD_CONF. + 16 + 16 + read-only + + + + + RD_MAC_SPI_SYS_2 + BLOCK1 data register 2. + 0x4C + 0x20 + + + SPI_PAD_CONF_1 + Stores the first part of SPI_PAD_CONF. + 0 + 32 + read-only + + + + + RD_MAC_SPI_SYS_3 + BLOCK1 data register 3. + 0x50 + 0x20 + + + SPI_PAD_CONF_2 + Stores the second part of SPI_PAD_CONF. + 0 + 18 + read-only + + + SYS_DATA_PART0_0 + Stores the fist 14 bits of the zeroth part of system data. + 18 + 14 + read-only + + + + + RD_MAC_SPI_SYS_4 + BLOCK1 data register 4. + 0x54 + 0x20 + + + SYS_DATA_PART0_1 + Stores the fist 32 bits of the zeroth part of system data. + 0 + 32 + read-only + + + + + RD_MAC_SPI_SYS_5 + BLOCK1 data register 5. + 0x58 + 0x20 + + + SYS_DATA_PART0_2 + Stores the second 32 bits of the zeroth part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA0 + Register 0 of BLOCK2 (system). + 0x5C + 0x20 + + + SYS_DATA_PART1_0 + Stores the zeroth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA1 + Register 1 of BLOCK2 (system). + 0x60 + 0x20 + + + SYS_DATA_PART1_1 + Stores the first 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA2 + Register 2 of BLOCK2 (system). + 0x64 + 0x20 + + + SYS_DATA_PART1_2 + Stores the second 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA3 + Register 3 of BLOCK2 (system). + 0x68 + 0x20 + + + SYS_DATA_PART1_3 + Stores the third 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA4 + Register 4 of BLOCK2 (system). + 0x6C + 0x20 + + + SYS_DATA_PART1_4 + Stores the fourth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA5 + Register 5 of BLOCK2 (system). + 0x70 + 0x20 + + + SYS_DATA_PART1_5 + Stores the fifth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA6 + Register 6 of BLOCK2 (system). + 0x74 + 0x20 + + + SYS_DATA_PART1_6 + Stores the sixth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA7 + Register 7 of BLOCK2 (system). + 0x78 + 0x20 + + + SYS_DATA_PART1_7 + Stores the seventh 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_USR_DATA0 + Register 0 of BLOCK3 (user). + 0x7C + 0x20 + + + USR_DATA0 + Stores the zeroth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA1 + Register 1 of BLOCK3 (user). + 0x80 + 0x20 + + + USR_DATA1 + Stores the first 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA2 + Register 2 of BLOCK3 (user). + 0x84 + 0x20 + + + USR_DATA2 + Stores the second 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA3 + Register 3 of BLOCK3 (user). + 0x88 + 0x20 + + + USR_DATA3 + Stores the third 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA4 + Register 4 of BLOCK3 (user). + 0x8C + 0x20 + + + USR_DATA4 + Stores the fourth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA5 + Register 5 of BLOCK3 (user). + 0x90 + 0x20 + + + USR_DATA5 + Stores the fifth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA6 + Register 6 of BLOCK3 (user). + 0x94 + 0x20 + + + USR_DATA6 + Stores the sixth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA7 + Register 7 of BLOCK3 (user). + 0x98 + 0x20 + + + USR_DATA7 + Stores the seventh 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_KEY0_DATA0 + Register 0 of BLOCK4 (KEY0). + 0x9C + 0x20 + + + KEY0_DATA0 + Stores the zeroth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA1 + Register 1 of BLOCK4 (KEY0). + 0xA0 + 0x20 + + + KEY0_DATA1 + Stores the first 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA2 + Register 2 of BLOCK4 (KEY0). + 0xA4 + 0x20 + + + KEY0_DATA2 + Stores the second 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA3 + Register 3 of BLOCK4 (KEY0). + 0xA8 + 0x20 + + + KEY0_DATA3 + Stores the third 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA4 + Register 4 of BLOCK4 (KEY0). + 0xAC + 0x20 + + + KEY0_DATA4 + Stores the fourth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA5 + Register 5 of BLOCK4 (KEY0). + 0xB0 + 0x20 + + + KEY0_DATA5 + Stores the fifth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA6 + Register 6 of BLOCK4 (KEY0). + 0xB4 + 0x20 + + + KEY0_DATA6 + Stores the sixth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA7 + Register 7 of BLOCK4 (KEY0). + 0xB8 + 0x20 + + + KEY0_DATA7 + Stores the seventh 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY1_DATA0 + Register 0 of BLOCK5 (KEY1). + 0xBC + 0x20 + + + KEY1_DATA0 + Stores the zeroth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA1 + Register 1 of BLOCK5 (KEY1). + 0xC0 + 0x20 + + + KEY1_DATA1 + Stores the first 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA2 + Register 2 of BLOCK5 (KEY1). + 0xC4 + 0x20 + + + KEY1_DATA2 + Stores the second 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA3 + Register 3 of BLOCK5 (KEY1). + 0xC8 + 0x20 + + + KEY1_DATA3 + Stores the third 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA4 + Register 4 of BLOCK5 (KEY1). + 0xCC + 0x20 + + + KEY1_DATA4 + Stores the fourth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA5 + Register 5 of BLOCK5 (KEY1). + 0xD0 + 0x20 + + + KEY1_DATA5 + Stores the fifth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA6 + Register 6 of BLOCK5 (KEY1). + 0xD4 + 0x20 + + + KEY1_DATA6 + Stores the sixth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA7 + Register 7 of BLOCK5 (KEY1). + 0xD8 + 0x20 + + + KEY1_DATA7 + Stores the seventh 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY2_DATA0 + Register 0 of BLOCK6 (KEY2). + 0xDC + 0x20 + + + KEY2_DATA0 + Stores the zeroth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA1 + Register 1 of BLOCK6 (KEY2). + 0xE0 + 0x20 + + + KEY2_DATA1 + Stores the first 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA2 + Register 2 of BLOCK6 (KEY2). + 0xE4 + 0x20 + + + KEY2_DATA2 + Stores the second 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA3 + Register 3 of BLOCK6 (KEY2). + 0xE8 + 0x20 + + + KEY2_DATA3 + Stores the third 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA4 + Register 4 of BLOCK6 (KEY2). + 0xEC + 0x20 + + + KEY2_DATA4 + Stores the fourth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA5 + Register 5 of BLOCK6 (KEY2). + 0xF0 + 0x20 + + + KEY2_DATA5 + Stores the fifth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA6 + Register 6 of BLOCK6 (KEY2). + 0xF4 + 0x20 + + + KEY2_DATA6 + Stores the sixth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA7 + Register 7 of BLOCK6 (KEY2). + 0xF8 + 0x20 + + + KEY2_DATA7 + Stores the seventh 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY3_DATA0 + Register 0 of BLOCK7 (KEY3). + 0xFC + 0x20 + + + KEY3_DATA0 + Stores the zeroth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA1 + Register 1 of BLOCK7 (KEY3). + 0x100 + 0x20 + + + KEY3_DATA1 + Stores the first 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA2 + Register 2 of BLOCK7 (KEY3). + 0x104 + 0x20 + + + KEY3_DATA2 + Stores the second 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA3 + Register 3 of BLOCK7 (KEY3). + 0x108 + 0x20 + + + KEY3_DATA3 + Stores the third 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA4 + Register 4 of BLOCK7 (KEY3). + 0x10C + 0x20 + + + KEY3_DATA4 + Stores the fourth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA5 + Register 5 of BLOCK7 (KEY3). + 0x110 + 0x20 + + + KEY3_DATA5 + Stores the fifth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA6 + Register 6 of BLOCK7 (KEY3). + 0x114 + 0x20 + + + KEY3_DATA6 + Stores the sixth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA7 + Register 7 of BLOCK7 (KEY3). + 0x118 + 0x20 + + + KEY3_DATA7 + Stores the seventh 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY4_DATA0 + Register 0 of BLOCK8 (KEY4). + 0x11C + 0x20 + + + KEY4_DATA0 + Stores the zeroth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA1 + Register 1 of BLOCK8 (KEY4). + 0x120 + 0x20 + + + KEY4_DATA1 + Stores the first 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA2 + Register 2 of BLOCK8 (KEY4). + 0x124 + 0x20 + + + KEY4_DATA2 + Stores the second 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA3 + Register 3 of BLOCK8 (KEY4). + 0x128 + 0x20 + + + KEY4_DATA3 + Stores the third 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA4 + Register 4 of BLOCK8 (KEY4). + 0x12C + 0x20 + + + KEY4_DATA4 + Stores the fourth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA5 + Register 5 of BLOCK8 (KEY4). + 0x130 + 0x20 + + + KEY4_DATA5 + Stores the fifth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA6 + Register 6 of BLOCK8 (KEY4). + 0x134 + 0x20 + + + KEY4_DATA6 + Stores the sixth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA7 + Register 7 of BLOCK8 (KEY4). + 0x138 + 0x20 + + + KEY4_DATA7 + Stores the seventh 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY5_DATA0 + Register 0 of BLOCK9 (KEY5). + 0x13C + 0x20 + + + KEY5_DATA0 + Stores the zeroth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA1 + Register 1 of BLOCK9 (KEY5). + 0x140 + 0x20 + + + KEY5_DATA1 + Stores the first 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA2 + Register 2 of BLOCK9 (KEY5). + 0x144 + 0x20 + + + KEY5_DATA2 + Stores the second 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA3 + Register 3 of BLOCK9 (KEY5). + 0x148 + 0x20 + + + KEY5_DATA3 + Stores the third 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA4 + Register 4 of BLOCK9 (KEY5). + 0x14C + 0x20 + + + KEY5_DATA4 + Stores the fourth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA5 + Register 5 of BLOCK9 (KEY5). + 0x150 + 0x20 + + + KEY5_DATA5 + Stores the fifth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA6 + Register 6 of BLOCK9 (KEY5). + 0x154 + 0x20 + + + KEY5_DATA6 + Stores the sixth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA7 + Register 7 of BLOCK9 (KEY5). + 0x158 + 0x20 + + + KEY5_DATA7 + Stores the seventh 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA0 + Register 0 of BLOCK10 (system). + 0x15C + 0x20 + + + SYS_DATA_PART2_0 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA1 + Register 1 of BLOCK9 (KEY5). + 0x160 + 0x20 + + + SYS_DATA_PART2_1 + Stores the 1st 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA2 + Register 2 of BLOCK10 (system). + 0x164 + 0x20 + + + SYS_DATA_PART2_2 + Stores the 2nd 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA3 + Register 3 of BLOCK10 (system). + 0x168 + 0x20 + + + SYS_DATA_PART2_3 + Stores the 3rd 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA4 + Register 4 of BLOCK10 (system). + 0x16C + 0x20 + + + SYS_DATA_PART2_4 + Stores the 4th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA5 + Register 5 of BLOCK10 (system). + 0x170 + 0x20 + + + SYS_DATA_PART2_5 + Stores the 5th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA6 + Register 6 of BLOCK10 (system). + 0x174 + 0x20 + + + SYS_DATA_PART2_6 + Stores the 6th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA7 + Register 7 of BLOCK10 (system). + 0x178 + 0x20 + + + SYS_DATA_PART2_7 + Stores the 7th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_REPEAT_ERR0 + Programming error record register 0 of BLOCK0. + 0x17C + 0x20 + + + RD_DIS_ERR + If any bits in this filed are 1, then it indicates a programming error. + 0 + 7 + read-only + + + DIS_RTC_RAM_BOOT_ERR + If any bits in this filed are 1, then it indicates a programming error. + 7 + 1 + read-only + + + DIS_ICACHE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 8 + 1 + read-only + + + DIS_DCACHE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 9 + 1 + read-only + + + DIS_DOWNLOAD_ICACHE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 10 + 1 + read-only + + + DIS_DOWNLOAD_DCACHE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 11 + 1 + read-only + + + DIS_FORCE_DOWNLOAD_ERR + If any bits in this filed are 1, then it indicates a programming error. + 12 + 1 + read-only + + + DIS_USB_ERR + If any bits in this filed are 1, then it indicates a programming error. + 13 + 1 + read-only + + + DIS_CAN_ERR + If any bits in this filed are 1, then it indicates a programming error. + 14 + 1 + read-only + + + DIS_APP_CPU_ERR + If any bits in this filed are 1, then it indicates a programming error. + 15 + 1 + read-only + + + SOFT_DIS_JTAG_ERR + If any bits in this filed are 1, then it indicates a programming error. + 16 + 3 + read-only + + + DIS_PAD_JTAG_ERR + If any bits in this filed are 1, then it indicates a programming error. + 19 + 1 + read-only + + + DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR + If any bits in this filed are 1, then it indicates a programming error. + 20 + 1 + read-only + + + USB_DREFH_ERR + If any bits in this filed are 1, then it indicates a programming error. + 21 + 2 + read-only + + + USB_DREFL_ERR + If any bits in this filed are 1, then it indicates a programming error. + 23 + 2 + read-only + + + USB_EXCHG_PINS_ERR + If any bits in this filed are 1, then it indicates a programming error. + 25 + 1 + read-only + + + EXT_PHY_ENABLE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 26 + 1 + read-only + + + BTLC_GPIO_ENABLE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 27 + 2 + read-only + + + VDD_SPI_MODECURLIM_ERR + If any bits in this filed are 1, then it indicates a programming error. + 29 + 1 + read-only + + + VDD_SPI_DREFH_ERR + If any bits in this filed are 1, then it indicates a programming error. + 30 + 2 + read-only + + + + + RD_REPEAT_ERR1 + Programming error record register 1 of BLOCK0. + 0x180 + 0x20 + + + VDD_SPI_DREFM_ERR + If any bits in this filed are 1, then it indicates a programming error. + 0 + 2 + read-only + + + VDD_SPI_DREFL_ERR + If any bits in this filed are 1, then it indicates a programming error. + 2 + 2 + read-only + + + VDD_SPI_XPD_ERR + If any bits in this filed are 1, then it indicates a programming error. + 4 + 1 + read-only + + + VDD_SPI_TIEH_ERR + If any bits in this filed are 1, then it indicates a programming error. + 5 + 1 + read-only + + + VDD_SPI_FORCE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 6 + 1 + read-only + + + VDD_SPI_EN_INIT_ERR + If any bits in this filed are 1, then it indicates a programming error. + 7 + 1 + read-only + + + VDD_SPI_ENCURLIM_ERR + If any bits in this filed are 1, then it indicates a programming error. + 8 + 1 + read-only + + + VDD_SPI_DCURLIM_ERR + If any bits in this filed are 1, then it indicates a programming error. + 9 + 3 + read-only + + + VDD_SPI_INIT_ERR + If any bits in this filed are 1, then it indicates a programming error. + 12 + 2 + read-only + + + VDD_SPI_DCAP_ERR + If any bits in this filed are 1, then it indicates a programming error. + 14 + 2 + read-only + + + WDT_DELAY_SEL_ERR + If any bits in this filed are 1, then it indicates a programming error. + 16 + 2 + read-only + + + SPI_BOOT_CRYPT_CNT_ERR + If any bits in this filed are 1, then it indicates a programming error. + 18 + 3 + read-only + + + SECURE_BOOT_KEY_REVOKE0_ERR + If any bits in this filed are 1, then it indicates a programming error. + 21 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE1_ERR + If any bits in this filed are 1, then it indicates a programming error. + 22 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE2_ERR + If any bits in this filed are 1, then it indicates a programming error. + 23 + 1 + read-only + + + KEY_PURPOSE_0_ERR + If any bits in this filed are 1, then it indicates a programming error. + 24 + 4 + read-only + + + KEY_PURPOSE_1_ERR + If any bits in this filed are 1, then it indicates a programming error. + 28 + 4 + read-only + + + + + RD_REPEAT_ERR2 + Programming error record register 2 of BLOCK0. + 0x184 + 0x20 + + + KEY_PURPOSE_2_ERR + If any bits in this filed are 1, then it indicates a programming error. + 0 + 4 + read-only + + + KEY_PURPOSE_3_ERR + If any bits in this filed are 1, then it indicates a programming error. + 4 + 4 + read-only + + + KEY_PURPOSE_4_ERR + If any bits in this filed are 1, then it indicates a programming error. + 8 + 4 + read-only + + + KEY_PURPOSE_5_ERR + If any bits in this filed are 1, then it indicates a programming error. + 12 + 4 + read-only + + + RPT4_RESERVED0_ERR + If any bits in this filed are 1, then it indicates a programming error. + 16 + 4 + read-only + + + SECURE_BOOT_EN_ERR + If any bits in this filed are 1, then it indicates a programming error. + 20 + 1 + read-only + + + SECURE_BOOT_AGGRESSIVE_REVOKE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 21 + 1 + read-only + + + DIS_USB_JTAG_ERR + If any bits in this filed are 1, then it indicates a programming error. + 22 + 1 + read-only + + + DIS_USB_DEVICE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 23 + 1 + read-only + + + STRAP_JTAG_SEL_ERR + If any bits in this filed are 1, then it indicates a programming error. + 24 + 1 + read-only + + + USB_PHY_SEL_ERR + If any bits in this filed are 1, then it indicates a programming error. + 25 + 1 + read-only + + + POWER_GLITCH_DSENSE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 26 + 2 + read-only + + + FLASH_TPUW_ERR + If any bits in this filed are 1, then it indicates a programming error. + 28 + 4 + read-only + + + + + RD_REPEAT_ERR3 + Programming error record register 3 of BLOCK0. + 0x188 + 0x20 + + + DIS_DOWNLOAD_MODE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 0 + 1 + read-only + + + DIS_LEGACY_SPI_BOOT_ERR + If any bits in this filed are 1, then it indicates a programming error. + 1 + 1 + read-only + + + UART_PRINT_CHANNEL_ERR + If any bits in this filed are 1, then it indicates a programming error. + 2 + 1 + read-only + + + FLASH_ECC_MODE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 3 + 1 + read-only + + + DIS_USB_DOWNLOAD_MODE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 4 + 1 + read-only + + + ENABLE_SECURITY_DOWNLOAD_ERR + If any bits in this filed are 1, then it indicates a programming error. + 5 + 1 + read-only + + + UART_PRINT_CONTROL_ERR + If any bits in this filed are 1, then it indicates a programming error. + 6 + 2 + read-only + + + PIN_POWER_SELECTION_ERR + If any bits in this filed are 1, then it indicates a programming error. + 8 + 1 + read-only + + + FLASH_TYPE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 9 + 1 + read-only + + + FLASH_PAGE_SIZE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 10 + 2 + read-only + + + FLASH_ECC_EN_ERR + If any bits in this filed are 1, then it indicates a programming error. + 12 + 1 + read-only + + + FORCE_SEND_RESUME_ERR + If any bits in this filed are 1, then it indicates a programming error. + 13 + 1 + read-only + + + SECURE_VERSION_ERR + If any bits in this filed are 1, then it indicates a programming error. + 14 + 16 + read-only + + + POWERGLITCH_EN_ERR + If any bits in this filed are 1, then it indicates a programming error. + 30 + 1 + read-only + + + RPT4_RESERVED1_ERR + Reserved. + 31 + 1 + read-only + + + + + RD_REPEAT_ERR4 + Programming error record register 4 of BLOCK0. + 0x190 + 0x20 + + + RPT4_RESERVED2_ERR + If any bits in this filed are 1, then it indicates a programming error. + 0 + 24 + read-only + + + + + RD_RS_ERR0 + Programming error record register 0 of BLOCK1-10. + 0x1C0 + 0x20 + + + MAC_SPI_8M_ERR_NUM + The value of this signal means the number of error bytes. + 0 + 3 + read-only + + + MAC_SPI_8M_FAIL + 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 3 + 1 + read-only + + + SYS_PART1_NUM + The value of this signal means the number of error bytes. + 4 + 3 + read-only + + + SYS_PART1_FAIL + 0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 7 + 1 + read-only + + + USR_DATA_ERR_NUM + The value of this signal means the number of error bytes. + 8 + 3 + read-only + + + USR_DATA_FAIL + 0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 11 + 1 + read-only + + + KEY0_ERR_NUM + The value of this signal means the number of error bytes. + 12 + 3 + read-only + + + KEY0_FAIL + 0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6. + 15 + 1 + read-only + + + KEY1_ERR_NUM + The value of this signal means the number of error bytes. + 16 + 3 + read-only + + + KEY1_FAIL + 0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6. + 19 + 1 + read-only + + + KEY2_ERR_NUM + The value of this signal means the number of error bytes. + 20 + 3 + read-only + + + KEY2_FAIL + 0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6. + 23 + 1 + read-only + + + KEY3_ERR_NUM + The value of this signal means the number of error bytes. + 24 + 3 + read-only + + + KEY3_FAIL + 0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6. + 27 + 1 + read-only + + + KEY4_ERR_NUM + The value of this signal means the number of error bytes. + 28 + 3 + read-only + + + KEY4_FAIL + 0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6. + 31 + 1 + read-only + + + + + RD_RS_ERR1 + Programming error record register 1 of BLOCK1-10. + 0x1C4 + 0x20 + + + KEY5_ERR_NUM + The value of this signal means the number of error bytes. + 0 + 3 + read-only + + + KEY5_FAIL + 0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 3 + 1 + read-only + + + SYS_PART2_ERR_NUM + The value of this signal means the number of error bytes. + 4 + 3 + read-only + + + SYS_PART2_FAIL + 0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 7 + 1 + read-only + + + + + CLK + eFuse clcok configuration register. + 0x1C8 + 0x20 + 0x00000002 + + + EFUSE_MEM_FORCE_PD + Set this bit to force eFuse SRAM into power-saving mode. + 0 + 1 + read-write + + + MEM_CLK_FORCE_ON + Set this bit and force to activate clock signal of eFuse SRAM. + 1 + 1 + read-write + + + EFUSE_MEM_FORCE_PU + Set this bit to force eFuse SRAM into working mode. + 2 + 1 + read-write + + + EN + Set this bit and force to enable clock signal of eFuse memory. + 16 + 1 + read-write + + + + + CONF + eFuse operation mode configuraiton register + 0x1CC + 0x20 + + + OP_CODE + 0x5A5A: Operate programming command 0x5AA5: Operate read command. + 0 + 16 + read-write + + + + + STATUS + eFuse status register. + 0x1D0 + 0x20 + + + STATE + Indicates the state of the eFuse state machine. + 0 + 4 + read-only + + + OTP_LOAD_SW + The value of OTP_LOAD_SW. + 4 + 1 + read-only + + + OTP_VDDQ_C_SYNC2 + The value of OTP_VDDQ_C_SYNC2. + 5 + 1 + read-only + + + OTP_STROBE_SW + The value of OTP_STROBE_SW. + 6 + 1 + read-only + + + OTP_CSB_SW + The value of OTP_CSB_SW. + 7 + 1 + read-only + + + OTP_PGENB_SW + The value of OTP_PGENB_SW. + 8 + 1 + read-only + + + OTP_VDDQ_IS_SW + The value of OTP_VDDQ_IS_SW. + 9 + 1 + read-only + + + REPEAT_ERR_CNT + Indicates the number of error bits during programming BLOCK0. + 10 + 8 + read-only + + + + + CMD + eFuse command register. + 0x1D4 + 0x20 + + + READ_CMD + Set this bit to send read command. + 0 + 1 + read-write + + + PGM_CMD + Set this bit to send programming command. + 1 + 1 + read-write + + + BLK_NUM + The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively. + 2 + 4 + read-write + + + + + INT_RAW + eFuse raw interrupt register. + 0x1D8 + 0x20 + + + READ_DONE_INT_RAW + The raw bit signal for read_done interrupt. + 0 + 1 + read-write + + + PGM_DONE_INT_RAW + The raw bit signal for pgm_done interrupt. + 1 + 1 + read-write + + + + + INT_ST + eFuse interrupt status register. + 0x1DC + 0x20 + + + READ_DONE_INT_ST + The status signal for read_done interrupt. + 0 + 1 + read-only + + + PGM_DONE_INT_ST + The status signal for pgm_done interrupt. + 1 + 1 + read-only + + + + + INT_ENA + eFuse interrupt enable register. + 0x1E0 + 0x20 + + + READ_DONE_INT_ENA + The enable signal for read_done interrupt. + 0 + 1 + read-write + + + PGM_DONE_INT_ENA + The enable signal for pgm_done interrupt. + 1 + 1 + read-write + + + + + INT_CLR + eFuse interrupt clear register. + 0x1E4 + 0x20 + + + READ_DONE_INT_CLR + The clear signal for read_done interrupt. + 0 + 1 + write-only + + + PGM_DONE_INT_CLR + The clear signal for pgm_done interrupt. + 1 + 1 + write-only + + + + + DAC_CONF + Controls the eFuse programming voltage. + 0x1E8 + 0x20 + 0x0001FE1C + + + DAC_CLK_DIV + Controls the division factor of the rising clock of the programming voltage. + 0 + 8 + read-write + + + DAC_CLK_PAD_SEL + Don't care. + 8 + 1 + read-write + + + DAC_NUM + Controls the rising period of the programming voltage. + 9 + 8 + read-write + + + OE_CLR + Reduces the power supply of the programming voltage. + 17 + 1 + read-write + + + + + RD_TIM_CONF + Configures read timing parameters. + 0x1EC + 0x20 + 0x12000000 + + + READ_INIT_NUM + Configures the initial read time of eFuse. + 24 + 8 + read-write + + + + + WR_TIM_CONF1 + Configurarion register 1 of eFuse programming timing parameters. + 0x1F4 + 0x20 + 0x00288000 + + + PWR_ON_NUM + Configures the power up time for VDDQ. + 8 + 16 + read-write + + + + + WR_TIM_CONF2 + Configurarion register 2 of eFuse programming timing parameters. + 0x1F8 + 0x20 + 0x00000190 + + + PWR_OFF_NUM + Configures the power outage time for VDDQ. + 0 + 16 + read-write + + + + + DATE + eFuse version register. + 0x1FC + 0x20 + 0x02101290 + + + DATE + Stores eFuse version. + 0 + 28 + read-write + + + + + + + EXTMEM + External Memory + EXTMEM + 0x600C4000 + + 0x0 + 0x17C + registers + + + + DCACHE_CTRL + ******* Description *********** + 0x0 + 0x20 + + + DCACHE_ENABLE + The bit is used to activate the data cache. 0: disable, 1: enable + 0 + 1 + read-write + + + DCACHE_SIZE_MODE + The bit is used to configure cache memory size.0: 32KB, 1: 64KB + 2 + 1 + read-write + + + DCACHE_BLOCKSIZE_MODE + The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2: 64 bytes + 3 + 2 + read-write + + + + + DCACHE_CTRL1 + ******* Description *********** + 0x4 + 0x20 + 0x00000003 + + + DCACHE_SHUT_CORE0_BUS + The bit is used to disable core0 dbus, 0: enable, 1: disable + 0 + 1 + read-write + + + DCACHE_SHUT_CORE1_BUS + The bit is used to disable core1 dbus, 0: enable, 1: disable + 1 + 1 + read-write + + + + + DCACHE_TAG_POWER_CTRL + ******* Description *********** + 0x8 + 0x20 + 0x00000005 + + + DCACHE_TAG_MEM_FORCE_ON + The bit is used to close clock gating of dcache tag memory. 1: close gating, 0: open clock gating. + 0 + 1 + read-write + + + DCACHE_TAG_MEM_FORCE_PD + The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd, 1: power down + 1 + 1 + read-write + + + DCACHE_TAG_MEM_FORCE_PU + The bit is used to power dcache tag memory up, 0: follow rtc_lslp_pd, 1: power up + 2 + 1 + read-write + + + + + DCACHE_PRELOCK_CTRL + ******* Description *********** + 0xC + 0x20 + + + DCACHE_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function. + 0 + 1 + read-write + + + DCACHE_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function. + 1 + 1 + read-write + + + + + DCACHE_PRELOCK_SCT0_ADDR + ******* Description *********** + 0x10 + 0x20 + + + DCACHE_PRELOCK_SCT0_ADDR + The bits are used to configure the first start virtual address of data prelock, which is combined with DCACHE_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-write + + + + + DCACHE_PRELOCK_SCT1_ADDR + ******* Description *********** + 0x14 + 0x20 + + + DCACHE_PRELOCK_SCT1_ADDR + The bits are used to configure the second start virtual address of data prelock, which is combined with DCACHE_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-write + + + + + DCACHE_PRELOCK_SCT_SIZE + ******* Description *********** + 0x18 + 0x20 + + + DCACHE_PRELOCK_SCT1_SIZE + The bits are used to configure the second length of data locking, which is combined with DCACHE_PRELOCK_SCT1_ADDR_REG + 0 + 16 + read-write + + + DCACHE_PRELOCK_SCT0_SIZE + The bits are used to configure the first length of data locking, which is combined with DCACHE_PRELOCK_SCT0_ADDR_REG + 16 + 16 + read-write + + + + + DCACHE_LOCK_CTRL + ******* Description *********** + 0x1C + 0x20 + 0x00000004 + + + DCACHE_LOCK_ENA + The bit is used to enable lock operation. It will be cleared by hardware after lock operation done. + 0 + 1 + read-write + + + DCACHE_UNLOCK_ENA + The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done. + 1 + 1 + read-write + + + DCACHE_LOCK_DONE + The bit is used to indicate unlock/lock operation is finished. + 2 + 1 + read-only + + + + + DCACHE_LOCK_ADDR + ******* Description *********** + 0x20 + 0x20 + + + DCACHE_LOCK_ADDR + The bits are used to configure the start virtual address for lock operations. It should be combined with DCACHE_LOCK_SIZE_REG. + 0 + 32 + read-write + + + + + DCACHE_LOCK_SIZE + ******* Description *********** + 0x24 + 0x20 + + + DCACHE_LOCK_SIZE + The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG. + 0 + 16 + read-write + + + + + DCACHE_SYNC_CTRL + ******* Description *********** + 0x28 + 0x20 + 0x00000001 + + + DCACHE_INVALIDATE_ENA + The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. + 0 + 1 + read-write + + + DCACHE_WRITEBACK_ENA + The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done. + 1 + 1 + read-write + + + DCACHE_CLEAN_ENA + The bit is used to enable clean operation. It will be cleared by hardware after clean operation done. + 2 + 1 + read-write + + + DCACHE_SYNC_DONE + The bit is used to indicate clean/writeback/invalidate operation is finished. + 3 + 1 + read-only + + + + + DCACHE_SYNC_ADDR + ******* Description *********** + 0x2C + 0x20 + + + DCACHE_SYNC_ADDR + The bits are used to configure the start virtual address for clean operations. It should be combined with DCACHE_SYNC_SIZE_REG. + 0 + 32 + read-write + + + + + DCACHE_SYNC_SIZE + ******* Description *********** + 0x30 + 0x20 + + + DCACHE_SYNC_SIZE + The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG. + 0 + 23 + read-write + + + + + DCACHE_OCCUPY_CTRL + ******* Description *********** + 0x34 + 0x20 + 0x00000002 + + + DCACHE_OCCUPY_ENA + The bit is used to enable occupy operation. It will be cleared by hardware after issuing Auot-Invalidate Operation. + 0 + 1 + read-write + + + DCACHE_OCCUPY_DONE + The bit is used to indicate occupy operation is finished. + 1 + 1 + read-only + + + + + DCACHE_OCCUPY_ADDR + ******* Description *********** + 0x38 + 0x20 + + + DCACHE_OCCUPY_ADDR + The bits are used to configure the start virtual address for occupy operation. It should be combined with DCACHE_OCCUPY_SIZE_REG. + 0 + 32 + read-write + + + + + DCACHE_OCCUPY_SIZE + ******* Description *********** + 0x3C + 0x20 + + + DCACHE_OCCUPY_SIZE + The bits are used to configure the length for occupy operation. The bits are the counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG. + 0 + 16 + read-write + + + + + DCACHE_PRELOAD_CTRL + ******* Description *********** + 0x40 + 0x20 + 0x00000002 + + + DCACHE_PRELOAD_ENA + The bit is used to enable preload operation. It will be cleared by hardware after preload operation done. + 0 + 1 + read-write + + + DCACHE_PRELOAD_DONE + The bit is used to indicate preload operation is finished. + 1 + 1 + read-only + + + DCACHE_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 1: descending, 0: ascending. + 2 + 1 + read-write + + + + + DCACHE_PRELOAD_ADDR + ******* Description *********** + 0x44 + 0x20 + + + DCACHE_PRELOAD_ADDR + The bits are used to configure the start virtual address for preload operation. It should be combined with DCACHE_PRELOAD_SIZE_REG. + 0 + 32 + read-write + + + + + DCACHE_PRELOAD_SIZE + ******* Description *********** + 0x48 + 0x20 + + + DCACHE_PRELOAD_SIZE + The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG.. + 0 + 16 + read-write + + + + + DCACHE_AUTOLOAD_CTRL + ******* Description *********** + 0x4C + 0x20 + 0x00000008 + + + DCACHE_AUTOLOAD_SCT0_ENA + The bits are used to enable the first section for autoload operation. + 0 + 1 + read-write + + + DCACHE_AUTOLOAD_SCT1_ENA + The bits are used to enable the second section for autoload operation. + 1 + 1 + read-write + + + DCACHE_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable, 0: disable. + 2 + 1 + read-write + + + DCACHE_AUTOLOAD_DONE + The bit is used to indicate autoload operation is finished. + 3 + 1 + read-only + + + DCACHE_AUTOLOAD_ORDER + The bits are used to configure the direction of autoload. 1: descending, 0: ascending. + 4 + 1 + read-write + + + DCACHE_AUTOLOAD_RQST + The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit. + 5 + 2 + read-write + + + DCACHE_AUTOLOAD_SIZE + The bits are used to configure the numbers of the cache block for the issuing autoload operation. + 7 + 2 + read-write + + + DCACHE_AUTOLOAD_BUFFER_CLEAR + The bit is used to clear autoload buffer in dcache. + 9 + 1 + read-write + + + + + DCACHE_AUTOLOAD_SCT0_ADDR + ******* Description *********** + 0x50 + 0x20 + + + DCACHE_AUTOLOAD_SCT0_ADDR + The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena. + 0 + 32 + read-write + + + + + DCACHE_AUTOLOAD_SCT0_SIZE + ******* Description *********** + 0x54 + 0x20 + + + DCACHE_AUTOLOAD_SCT0_SIZE + The bits are used to configure the length of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena. + 0 + 27 + read-write + + + + + DCACHE_AUTOLOAD_SCT1_ADDR + ******* Description *********** + 0x58 + 0x20 + + + DCACHE_AUTOLOAD_SCT1_ADDR + The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena. + 0 + 32 + read-write + + + + + DCACHE_AUTOLOAD_SCT1_SIZE + ******* Description *********** + 0x5C + 0x20 + + + DCACHE_AUTOLOAD_SCT1_SIZE + The bits are used to configure the length of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena. + 0 + 27 + read-write + + + + + ICACHE_CTRL + ******* Description *********** + 0x60 + 0x20 + + + ICACHE_ENABLE + The bit is used to activate the data cache. 0: disable, 1: enable + 0 + 1 + read-write + + + ICACHE_WAY_MODE + The bit is used to configure cache way mode.0: 4-way, 1: 8-way + 1 + 1 + read-write + + + ICACHE_SIZE_MODE + The bit is used to configure cache memory size.0: 16KB, 1: 32KB + 2 + 1 + read-write + + + ICACHE_BLOCKSIZE_MODE + The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes + 3 + 1 + read-write + + + + + ICACHE_CTRL1 + ******* Description *********** + 0x64 + 0x20 + 0x00000003 + + + ICACHE_SHUT_CORE0_BUS + The bit is used to disable core0 ibus, 0: enable, 1: disable + 0 + 1 + read-write + + + ICACHE_SHUT_CORE1_BUS + The bit is used to disable core1 ibus, 0: enable, 1: disable + 1 + 1 + read-write + + + + + ICACHE_TAG_POWER_CTRL + ******* Description *********** + 0x68 + 0x20 + 0x00000005 + + + ICACHE_TAG_MEM_FORCE_ON + The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating. + 0 + 1 + read-write + + + ICACHE_TAG_MEM_FORCE_PD + The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power down + 1 + 1 + read-write + + + ICACHE_TAG_MEM_FORCE_PU + The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up + 2 + 1 + read-write + + + + + ICACHE_PRELOCK_CTRL + ******* Description *********** + 0x6C + 0x20 + + + ICACHE_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function. + 0 + 1 + read-write + + + ICACHE_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function. + 1 + 1 + read-write + + + + + ICACHE_PRELOCK_SCT0_ADDR + ******* Description *********** + 0x70 + 0x20 + + + ICACHE_PRELOCK_SCT0_ADDR + The bits are used to configure the first start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-write + + + + + ICACHE_PRELOCK_SCT1_ADDR + ******* Description *********** + 0x74 + 0x20 + + + ICACHE_PRELOCK_SCT1_ADDR + The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-write + + + + + ICACHE_PRELOCK_SCT_SIZE + ******* Description *********** + 0x78 + 0x20 + + + ICACHE_PRELOCK_SCT1_SIZE + The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG + 0 + 16 + read-write + + + ICACHE_PRELOCK_SCT0_SIZE + The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG + 16 + 16 + read-write + + + + + ICACHE_LOCK_CTRL + ******* Description *********** + 0x7C + 0x20 + 0x00000004 + + + ICACHE_LOCK_ENA + The bit is used to enable lock operation. It will be cleared by hardware after lock operation done. + 0 + 1 + read-write + + + ICACHE_UNLOCK_ENA + The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done. + 1 + 1 + read-write + + + ICACHE_LOCK_DONE + The bit is used to indicate unlock/lock operation is finished. + 2 + 1 + read-only + + + + + ICACHE_LOCK_ADDR + ******* Description *********** + 0x80 + 0x20 + + + ICACHE_LOCK_ADDR + The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG. + 0 + 32 + read-write + + + + + ICACHE_LOCK_SIZE + ******* Description *********** + 0x84 + 0x20 + + + ICACHE_LOCK_SIZE + The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG. + 0 + 16 + read-write + + + + + ICACHE_SYNC_CTRL + ******* Description *********** + 0x88 + 0x20 + 0x00000001 + + + ICACHE_INVALIDATE_ENA + The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. + 0 + 1 + read-write + + + ICACHE_SYNC_DONE + The bit is used to indicate invalidate operation is finished. + 1 + 1 + read-only + + + + + ICACHE_SYNC_ADDR + ******* Description *********** + 0x8C + 0x20 + + + ICACHE_SYNC_ADDR + The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG. + 0 + 32 + read-write + + + + + ICACHE_SYNC_SIZE + ******* Description *********** + 0x90 + 0x20 + + + ICACHE_SYNC_SIZE + The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG. + 0 + 23 + read-write + + + + + ICACHE_PRELOAD_CTRL + ******* Description *********** + 0x94 + 0x20 + 0x00000002 + + + ICACHE_PRELOAD_ENA + The bit is used to enable preload operation. It will be cleared by hardware after preload operation done. + 0 + 1 + read-write + + + ICACHE_PRELOAD_DONE + The bit is used to indicate preload operation is finished. + 1 + 1 + read-only + + + ICACHE_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 1: descending, 0: ascending. + 2 + 1 + read-write + + + + + ICACHE_PRELOAD_ADDR + ******* Description *********** + 0x98 + 0x20 + + + ICACHE_PRELOAD_ADDR + The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG. + 0 + 32 + read-write + + + + + ICACHE_PRELOAD_SIZE + ******* Description *********** + 0x9C + 0x20 + + + ICACHE_PRELOAD_SIZE + The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG.. + 0 + 16 + read-write + + + + + ICACHE_AUTOLOAD_CTRL + ******* Description *********** + 0xA0 + 0x20 + 0x00000008 + + + ICACHE_AUTOLOAD_SCT0_ENA + The bits are used to enable the first section for autoload operation. + 0 + 1 + read-write + + + ICACHE_AUTOLOAD_SCT1_ENA + The bits are used to enable the second section for autoload operation. + 1 + 1 + read-write + + + ICACHE_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable. + 2 + 1 + read-write + + + ICACHE_AUTOLOAD_DONE + The bit is used to indicate autoload operation is finished. + 3 + 1 + read-only + + + ICACHE_AUTOLOAD_ORDER + The bits are used to configure the direction of autoload. 1: descending, 0: ascending. + 4 + 1 + read-write + + + ICACHE_AUTOLOAD_RQST + The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit. + 5 + 2 + read-write + + + ICACHE_AUTOLOAD_SIZE + The bits are used to configure the numbers of the cache block for the issuing autoload operation. + 7 + 2 + read-write + + + ICACHE_AUTOLOAD_BUFFER_CLEAR + The bit is used to clear autoload buffer in icache. + 9 + 1 + read-write + + + + + ICACHE_AUTOLOAD_SCT0_ADDR + ******* Description *********** + 0xA4 + 0x20 + + + ICACHE_AUTOLOAD_SCT0_ADDR + The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena. + 0 + 32 + read-write + + + + + ICACHE_AUTOLOAD_SCT0_SIZE + ******* Description *********** + 0xA8 + 0x20 + + + ICACHE_AUTOLOAD_SCT0_SIZE + The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena. + 0 + 27 + read-write + + + + + ICACHE_AUTOLOAD_SCT1_ADDR + ******* Description *********** + 0xAC + 0x20 + + + ICACHE_AUTOLOAD_SCT1_ADDR + The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena. + 0 + 32 + read-write + + + + + ICACHE_AUTOLOAD_SCT1_SIZE + ******* Description *********** + 0xB0 + 0x20 + + + ICACHE_AUTOLOAD_SCT1_SIZE + The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena. + 0 + 27 + read-write + + + + + IBUS_TO_FLASH_START_VADDR + ******* Description *********** + 0xB4 + 0x20 + 0x44000000 + + + IBUS_TO_FLASH_START_VADDR + The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter. + 0 + 32 + read-write + + + + + IBUS_TO_FLASH_END_VADDR + ******* Description *********** + 0xB8 + 0x20 + 0x47FFFFFF + + + IBUS_TO_FLASH_END_VADDR + The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter. + 0 + 32 + read-write + + + + + DBUS_TO_FLASH_START_VADDR + ******* Description *********** + 0xBC + 0x20 + + + DBUS_TO_FLASH_START_VADDR + The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter. + 0 + 32 + read-write + + + + + DBUS_TO_FLASH_END_VADDR + ******* Description *********** + 0xC0 + 0x20 + + + DBUS_TO_FLASH_END_VADDR + The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter. + 0 + 32 + read-write + + + + + CACHE_ACS_CNT_CLR + ******* Description *********** + 0xC4 + 0x20 + + + DCACHE_ACS_CNT_CLR + The bit is used to clear dcache counter. + 0 + 1 + write-only + + + ICACHE_ACS_CNT_CLR + The bit is used to clear icache counter. + 1 + 1 + write-only + + + + + IBUS_ACS_MISS_CNT + ******* Description *********** + 0xC8 + 0x20 + + + IBUS_ACS_MISS_CNT + The bits are used to count the number of the cache miss caused by ibus access flash/spiram. + 0 + 32 + read-only + + + + + IBUS_ACS_CNT + ******* Description *********** + 0xCC + 0x20 + + + IBUS_ACS_CNT + The bits are used to count the number of ibus access flash/spiram through icache. + 0 + 32 + read-only + + + + + DBUS_ACS_FLASH_MISS_CNT + ******* Description *********** + 0xD0 + 0x20 + + + DBUS_ACS_FLASH_MISS_CNT + The bits are used to count the number of the cache miss caused by dbus access flash. + 0 + 32 + read-only + + + + + DBUS_ACS_SPIRAM_MISS_CNT + ******* Description *********** + 0xD4 + 0x20 + + + DBUS_ACS_SPIRAM_MISS_CNT + The bits are used to count the number of the cache miss caused by dbus access spiram. + 0 + 32 + read-only + + + + + DBUS_ACS_CNT + ******* Description *********** + 0xD8 + 0x20 + + + DBUS_ACS_CNT + The bits are used to count the number of dbus access flash/spiram through dcache. + 0 + 32 + read-only + + + + + CACHE_ILG_INT_ENA + ******* Description *********** + 0xDC + 0x20 + + + ICACHE_SYNC_OP_FAULT_INT_ENA + The bit is used to enable interrupt by sync configurations fault. + 0 + 1 + read-write + + + ICACHE_PRELOAD_OP_FAULT_INT_ENA + The bit is used to enable interrupt by preload configurations fault. + 1 + 1 + read-write + + + DCACHE_SYNC_OP_FAULT_INT_ENA + The bit is used to enable interrupt by sync configurations fault. + 2 + 1 + read-write + + + DCACHE_PRELOAD_OP_FAULT_INT_ENA + The bit is used to enable interrupt by preload configurations fault. + 3 + 1 + read-write + + + DCACHE_WRITE_FLASH_INT_ENA + The bit is used to enable interrupt by dcache trying to write flash. + 4 + 1 + read-write + + + MMU_ENTRY_FAULT_INT_ENA + The bit is used to enable interrupt by mmu entry fault. + 5 + 1 + read-write + + + DCACHE_OCCUPY_EXC_INT_ENA + The bit is used to enable interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode. + 6 + 1 + read-write + + + IBUS_CNT_OVF_INT_ENA + The bit is used to enable interrupt by ibus counter overflow. + 7 + 1 + read-write + + + DBUS_CNT_OVF_INT_ENA + The bit is used to enable interrupt by dbus counter overflow. + 8 + 1 + read-write + + + + + CACHE_ILG_INT_CLR + ******* Description *********** + 0xE0 + 0x20 + + + ICACHE_SYNC_OP_FAULT_INT_CLR + The bit is used to clear interrupt by sync configurations fault. + 0 + 1 + write-only + + + ICACHE_PRELOAD_OP_FAULT_INT_CLR + The bit is used to clear interrupt by preload configurations fault. + 1 + 1 + write-only + + + DCACHE_SYNC_OP_FAULT_INT_CLR + The bit is used to clear interrupt by sync configurations fault. + 2 + 1 + write-only + + + DCACHE_PRELOAD_OP_FAULT_INT_CLR + The bit is used to clear interrupt by preload configurations fault. + 3 + 1 + write-only + + + DCACHE_WRITE_FLASH_INT_CLR + The bit is used to clear interrupt by dcache trying to write flash. + 4 + 1 + write-only + + + MMU_ENTRY_FAULT_INT_CLR + The bit is used to clear interrupt by mmu entry fault. + 5 + 1 + write-only + + + DCACHE_OCCUPY_EXC_INT_CLR + The bit is used to clear interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode. + 6 + 1 + write-only + + + IBUS_CNT_OVF_INT_CLR + The bit is used to clear interrupt by ibus counter overflow. + 7 + 1 + write-only + + + DBUS_CNT_OVF_INT_CLR + The bit is used to clear interrupt by dbus counter overflow. + 8 + 1 + write-only + + + + + CACHE_ILG_INT_ST + ******* Description *********** + 0xE4 + 0x20 + + + ICACHE_SYNC_OP_FAULT_ST + The bit is used to indicate interrupt by sync configurations fault. + 0 + 1 + read-only + + + ICACHE_PRELOAD_OP_FAULT_ST + The bit is used to indicate interrupt by preload configurations fault. + 1 + 1 + read-only + + + DCACHE_SYNC_OP_FAULT_ST + The bit is used to indicate interrupt by sync configurations fault. + 2 + 1 + read-only + + + DCACHE_PRELOAD_OP_FAULT_ST + The bit is used to indicate interrupt by preload configurations fault. + 3 + 1 + read-only + + + DCACHE_WRITE_FLASH_ST + The bit is used to indicate interrupt by dcache trying to write flash. + 4 + 1 + read-only + + + MMU_ENTRY_FAULT_ST + The bit is used to indicate interrupt by mmu entry fault. + 5 + 1 + read-only + + + DCACHE_OCCUPY_EXC_ST + The bit is used to indicate interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode. + 6 + 1 + read-only + + + IBUS_ACS_CNT_OVF_ST + The bit is used to indicate interrupt by ibus access flash/spiram counter overflow. + 7 + 1 + read-only + + + IBUS_ACS_MISS_CNT_OVF_ST + The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow. + 8 + 1 + read-only + + + DBUS_ACS_CNT_OVF_ST + The bit is used to indicate interrupt by dbus access flash/spiram counter overflow. + 9 + 1 + read-only + + + DBUS_ACS_FLASH_MISS_CNT_OVF_ST + The bit is used to indicate interrupt by dbus access flash miss counter overflow. + 10 + 1 + read-only + + + DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST + The bit is used to indicate interrupt by dbus access spiram miss counter overflow. + 11 + 1 + read-only + + + + + CORE0_ACS_CACHE_INT_ENA + ******* Description *********** + 0xE8 + 0x20 + + + CORE0_IBUS_ACS_MSK_IC_INT_ENA + The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access. + 0 + 1 + read-write + + + CORE0_IBUS_WR_IC_INT_ENA + The bit is used to enable interrupt by ibus trying to write icache + 1 + 1 + read-write + + + CORE0_IBUS_REJECT_INT_ENA + The bit is used to enable interrupt by authentication fail. + 2 + 1 + read-write + + + CORE0_DBUS_ACS_MSK_DC_INT_ENA + The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access. + 3 + 1 + read-write + + + CORE0_DBUS_REJECT_INT_ENA + The bit is used to enable interrupt by authentication fail. + 4 + 1 + read-write + + + + + CORE0_ACS_CACHE_INT_CLR + ******* Description *********** + 0xEC + 0x20 + + + CORE0_IBUS_ACS_MSK_IC_INT_CLR + The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access. + 0 + 1 + write-only + + + CORE0_IBUS_WR_IC_INT_CLR + The bit is used to clear interrupt by ibus trying to write icache + 1 + 1 + write-only + + + CORE0_IBUS_REJECT_INT_CLR + The bit is used to clear interrupt by authentication fail. + 2 + 1 + write-only + + + CORE0_DBUS_ACS_MSK_DC_INT_CLR + The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access. + 3 + 1 + write-only + + + CORE0_DBUS_REJECT_INT_CLR + The bit is used to clear interrupt by authentication fail. + 4 + 1 + write-only + + + + + CORE0_ACS_CACHE_INT_ST + ******* Description *********** + 0xF0 + 0x20 + + + CORE0_IBUS_ACS_MSK_ICACHE_ST + The bit is used to indicate interrupt by cpu access icache while the core0_ibus is disabled or icache is disabled which include speculative access. + 0 + 1 + read-only + + + CORE0_IBUS_WR_ICACHE_ST + The bit is used to indicate interrupt by ibus trying to write icache + 1 + 1 + read-only + + + CORE0_IBUS_REJECT_ST + The bit is used to indicate interrupt by authentication fail. + 2 + 1 + read-only + + + CORE0_DBUS_ACS_MSK_DCACHE_ST + The bit is used to indicate interrupt by cpu access dcache while the core0_dbus is disabled or dcache is disabled which include speculative access. + 3 + 1 + read-only + + + CORE0_DBUS_REJECT_ST + The bit is used to indicate interrupt by authentication fail. + 4 + 1 + read-only + + + + + CORE1_ACS_CACHE_INT_ENA + ******* Description *********** + 0xF4 + 0x20 + + + CORE1_IBUS_ACS_MSK_IC_INT_ENA + The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access. + 0 + 1 + read-write + + + CORE1_IBUS_WR_IC_INT_ENA + The bit is used to enable interrupt by ibus trying to write icache + 1 + 1 + read-write + + + CORE1_IBUS_REJECT_INT_ENA + The bit is used to enable interrupt by authentication fail. + 2 + 1 + read-write + + + CORE1_DBUS_ACS_MSK_DC_INT_ENA + The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access. + 3 + 1 + read-write + + + CORE1_DBUS_REJECT_INT_ENA + The bit is used to enable interrupt by authentication fail. + 4 + 1 + read-write + + + + + CORE1_ACS_CACHE_INT_CLR + ******* Description *********** + 0xF8 + 0x20 + + + CORE1_IBUS_ACS_MSK_IC_INT_CLR + The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access. + 0 + 1 + write-only + + + CORE1_IBUS_WR_IC_INT_CLR + The bit is used to clear interrupt by ibus trying to write icache + 1 + 1 + write-only + + + CORE1_IBUS_REJECT_INT_CLR + The bit is used to clear interrupt by authentication fail. + 2 + 1 + write-only + + + CORE1_DBUS_ACS_MSK_DC_INT_CLR + The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access. + 3 + 1 + write-only + + + CORE1_DBUS_REJECT_INT_CLR + The bit is used to clear interrupt by authentication fail. + 4 + 1 + write-only + + + + + CORE1_ACS_CACHE_INT_ST + ******* Description *********** + 0xFC + 0x20 + + + CORE1_IBUS_ACS_MSK_ICACHE_ST + The bit is used to indicate interrupt by cpu access icache while the core1_ibus is disabled or icache is disabled which include speculative access. + 0 + 1 + read-only + + + CORE1_IBUS_WR_ICACHE_ST + The bit is used to indicate interrupt by ibus trying to write icache + 1 + 1 + read-only + + + CORE1_IBUS_REJECT_ST + The bit is used to indicate interrupt by authentication fail. + 2 + 1 + read-only + + + CORE1_DBUS_ACS_MSK_DCACHE_ST + The bit is used to indicate interrupt by cpu access dcache while the core1_dbus is disabled or dcache is disabled which include speculative access. + 3 + 1 + read-only + + + CORE1_DBUS_REJECT_ST + The bit is used to indicate interrupt by authentication fail. + 4 + 1 + read-only + + + + + CORE0_DBUS_REJECT_ST + ******* Description *********** + 0x100 + 0x20 + + + CORE0_DBUS_TAG_ATTR + The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. + 0 + 3 + read-only + + + CORE0_DBUS_ATTR + The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. + 3 + 3 + read-only + + + CORE0_DBUS_WORLD + The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1 + 6 + 1 + read-only + + + + + CORE0_DBUS_REJECT_VADDR + ******* Description *********** + 0x104 + 0x20 + 0xFFFFFFFF + + + CORE0_DBUS_VADDR + The bits are used to indicate the virtual address of CPU access dbus when authentication fail. + 0 + 32 + read-only + + + + + CORE0_IBUS_REJECT_ST + ******* Description *********** + 0x108 + 0x20 + + + CORE0_IBUS_TAG_ATTR + The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. + 0 + 3 + read-only + + + CORE0_IBUS_ATTR + The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able + 3 + 3 + read-only + + + CORE0_IBUS_WORLD + The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1 + 6 + 1 + read-only + + + + + CORE0_IBUS_REJECT_VADDR + ******* Description *********** + 0x10C + 0x20 + 0xFFFFFFFF + + + CORE0_IBUS_VADDR + The bits are used to indicate the virtual address of CPU access ibus when authentication fail. + 0 + 32 + read-only + + + + + CORE1_DBUS_REJECT_ST + ******* Description *********** + 0x110 + 0x20 + + + CORE1_DBUS_TAG_ATTR + The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. + 0 + 3 + read-only + + + CORE1_DBUS_ATTR + The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. + 3 + 3 + read-only + + + CORE1_DBUS_WORLD + The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1 + 6 + 1 + read-only + + + + + CORE1_DBUS_REJECT_VADDR + ******* Description *********** + 0x114 + 0x20 + 0xFFFFFFFF + + + CORE1_DBUS_VADDR + The bits are used to indicate the virtual address of CPU access dbus when authentication fail. + 0 + 32 + read-only + + + + + CORE1_IBUS_REJECT_ST + ******* Description *********** + 0x118 + 0x20 + + + CORE1_IBUS_TAG_ATTR + The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. + 0 + 3 + read-only + + + CORE1_IBUS_ATTR + The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able + 3 + 3 + read-only + + + CORE1_IBUS_WORLD + The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1 + 6 + 1 + read-only + + + + + CORE1_IBUS_REJECT_VADDR + ******* Description *********** + 0x11C + 0x20 + 0xFFFFFFFF + + + CORE1_IBUS_VADDR + The bits are used to indicate the virtual address of CPU access ibus when authentication fail. + 0 + 32 + read-only + + + + + CACHE_MMU_FAULT_CONTENT + ******* Description *********** + 0x120 + 0x20 + + + CACHE_MMU_FAULT_CONTENT + The bits are used to indicate the content of mmu entry which cause mmu fault.. + 0 + 16 + read-only + + + CACHE_MMU_FAULT_CODE + The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache. + 16 + 4 + read-only + + + + + CACHE_MMU_FAULT_VADDR + ******* Description *********** + 0x124 + 0x20 + + + CACHE_MMU_FAULT_VADDR + The bits are used to indicate the virtual address which cause mmu fault.. + 0 + 32 + read-only + + + + + CACHE_WRAP_AROUND_CTRL + ******* Description *********** + 0x128 + 0x20 + + + CACHE_FLASH_WRAP_AROUND + The bit is used to enable wrap around mode when read data from flash. + 0 + 1 + read-write + + + CACHE_SRAM_RD_WRAP_AROUND + The bit is used to enable wrap around mode when read data from spiram. + 1 + 1 + read-write + + + + + CACHE_MMU_POWER_CTRL + ******* Description *********** + 0x12C + 0x20 + 0x00000005 + + + CACHE_MMU_MEM_FORCE_ON + The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable + 0 + 1 + read-write + + + CACHE_MMU_MEM_FORCE_PD + The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down + 1 + 1 + read-write + + + CACHE_MMU_MEM_FORCE_PU + The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up + 2 + 1 + read-write + + + + + CACHE_STATE + ******* Description *********** + 0x130 + 0x20 + + + ICACHE_STATE + The bit is used to indicate whether icache main fsm is in idle state or not. 1: in idle state, 0: not in idle state + 0 + 12 + read-only + + + DCACHE_STATE + The bit is used to indicate whether dcache main fsm is in idle state or not. 1: in idle state, 0: not in idle state + 12 + 12 + read-only + + + + + CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE + ******* Description *********** + 0x134 + 0x20 + + + RECORD_DISABLE_DB_ENCRYPT + Reserved + 0 + 1 + read-write + + + RECORD_DISABLE_G0CB_DECRYPT + Reserved + 1 + 1 + read-write + + + + + CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON + ******* Description *********** + 0x138 + 0x20 + 0x00000007 + + + CLK_FORCE_ON_MANUAL_CRYPT + The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating. + 0 + 1 + read-write + + + CLK_FORCE_ON_AUTO_CRYPT + The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating. + 1 + 1 + read-write + + + CLK_FORCE_ON_CRYPT + The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating. + 2 + 1 + read-write + + + + + CACHE_BRIDGE_ARBITER_CTRL + ******* Description *********** + 0x13C + 0x20 + + + ALLOC_WB_HOLD_ARBITER + Reserved + 0 + 1 + read-write + + + + + CACHE_PRELOAD_INT_CTRL + ******* Description *********** + 0x140 + 0x20 + + + ICACHE_PRELOAD_INT_ST + The bit is used to indicate the interrupt by icache pre-load done. + 0 + 1 + read-only + + + ICACHE_PRELOAD_INT_ENA + The bit is used to enable the interrupt by icache pre-load done. + 1 + 1 + read-write + + + ICACHE_PRELOAD_INT_CLR + The bit is used to clear the interrupt by icache pre-load done. + 2 + 1 + write-only + + + DCACHE_PRELOAD_INT_ST + The bit is used to indicate the interrupt by dcache pre-load done. + 3 + 1 + read-only + + + DCACHE_PRELOAD_INT_ENA + The bit is used to enable the interrupt by dcache pre-load done. + 4 + 1 + read-write + + + DCACHE_PRELOAD_INT_CLR + The bit is used to clear the interrupt by dcache pre-load done. + 5 + 1 + write-only + + + + + CACHE_SYNC_INT_CTRL + ******* Description *********** + 0x144 + 0x20 + + + ICACHE_SYNC_INT_ST + The bit is used to indicate the interrupt by icache sync done. + 0 + 1 + read-only + + + ICACHE_SYNC_INT_ENA + The bit is used to enable the interrupt by icache sync done. + 1 + 1 + read-write + + + ICACHE_SYNC_INT_CLR + The bit is used to clear the interrupt by icache sync done. + 2 + 1 + write-only + + + DCACHE_SYNC_INT_ST + The bit is used to indicate the interrupt by dcache sync done. + 3 + 1 + read-only + + + DCACHE_SYNC_INT_ENA + The bit is used to enable the interrupt by dcache sync done. + 4 + 1 + read-write + + + DCACHE_SYNC_INT_CLR + The bit is used to clear the interrupt by dcache sync done. + 5 + 1 + write-only + + + + + CACHE_MMU_OWNER + ******* Description *********** + 0x148 + 0x20 + + + CACHE_MMU_OWNER + The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, bit2: dma, bit3: reserved. + 0 + 24 + read-write + + + + + CACHE_CONF_MISC + ******* Description *********** + 0x14C + 0x20 + 0x00000007 + + + CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT + The bit is used to disable checking mmu entry fault by preload operation. + 0 + 1 + read-write + + + CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT + The bit is used to disable checking mmu entry fault by sync operation. + 1 + 1 + read-write + + + CACHE_TRACE_ENA + The bit is used to enable cache trace function. + 2 + 1 + read-write + + + + + DCACHE_FREEZE + ******* Description *********** + 0x150 + 0x20 + 0x00000004 + + + ENA + The bit is used to enable dcache freeze mode + 0 + 1 + read-write + + + MODE + The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss + 1 + 1 + read-write + + + DONE + The bit is used to indicate dcache freeze success + 2 + 1 + read-only + + + + + ICACHE_FREEZE + ******* Description *********** + 0x154 + 0x20 + 0x00000004 + + + ENA + The bit is used to enable icache freeze mode + 0 + 1 + read-write + + + MODE + The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss + 1 + 1 + read-write + + + DONE + The bit is used to indicate icache freeze success + 2 + 1 + read-only + + + + + ICACHE_ATOMIC_OPERATE_ENA + ******* Description *********** + 0x158 + 0x20 + 0x00000001 + + + ICACHE_ATOMIC_OPERATE_ENA + The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation. + 0 + 1 + read-write + + + + + DCACHE_ATOMIC_OPERATE_ENA + ******* Description *********** + 0x15C + 0x20 + 0x00000001 + + + DCACHE_ATOMIC_OPERATE_ENA + The bit is used to activate dcache atomic operation protection. In this case, sync/lock/occupy operation can not interrupt miss-work. This feature does not work during invalidateAll operation. + 0 + 1 + read-write + + + + + CACHE_REQUEST + ******* Description *********** + 0x160 + 0x20 + + + BYPASS + The bit is used to disable request recording which could cause performance issue + 0 + 1 + read-write + + + + + CLOCK_GATE + ******* Description *********** + 0x164 + 0x20 + 0x00000001 + + + CLK_EN + Reserved + 0 + 1 + read-write + + + + + CACHE_TAG_OBJECT_CTRL + ******* Description *********** + 0x180 + 0x20 + + + ICACHE_TAG_OBJECT + Set this bit to set icache tag memory as object. This bit should be onehot with the others fields inside this register. + 0 + 1 + read-write + + + DCACHE_TAG_OBJECT + Set this bit to set dcache tag memory as object. This bit should be onehot with the others fields inside this register. + 1 + 1 + read-write + + + + + CACHE_TAG_WAY_OBJECT + ******* Description *********** + 0x184 + 0x20 + + + CACHE_TAG_WAY_OBJECT + Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, .., 7: way7. + 0 + 3 + read-write + + + + + CACHE_VADDR + ******* Description *********** + 0x188 + 0x20 + + + CACHE_VADDR + Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed. + 0 + 32 + read-write + + + + + CACHE_TAG_CONTENT + ******* Description *********** + 0x18C + 0x20 + + + CACHE_TAG_CONTENT + This is a constant place where we can write data to or read data from the tag memory on the specified cache. + 0 + 32 + read-write + + + + + DATE + ******* Description *********** + 0x3FC + 0x20 + 0x02012310 + + + DATE + version information. + 0 + 28 + read-write + + + + + + + GPIO + General Purpose Input/Output + GPIO + 0x60004000 + + 0x0 + 0x634 + registers + + + GPIO + 16 + + + GPIO_NMI + 17 + + + GPIO_INTR_2 + 18 + + + GPIO_NMI_2 + 19 + + + + BT_SELECT + GPIO bit select register + 0x0 + 0x20 + + + BT_SEL + GPIO bit select register + 0 + 32 + read-write + + + + + OUT + GPIO output register for GPIO0-31 + 0x4 + 0x20 + + + DATA_ORIG + GPIO output register for GPIO0-31 + 0 + 32 + read-write + + + + + OUT_W1TS + GPIO output set register for GPIO0-31 + 0x8 + 0x20 + + + OUT_W1TS + GPIO output set register for GPIO0-31 + 0 + 32 + write-only + + + + + OUT_W1TC + GPIO output clear register for GPIO0-31 + 0xC + 0x20 + + + OUT_W1TC + GPIO output clear register for GPIO0-31 + 0 + 32 + write-only + + + + + OUT1 + GPIO output register for GPIO32-53 + 0x10 + 0x20 + + + DATA_ORIG + GPIO output register for GPIO32-53 + 0 + 22 + read-write + + + + + OUT1_W1TS + GPIO output set register for GPIO32-53 + 0x14 + 0x20 + + + OUT1_W1TS + GPIO output set register for GPIO32-53 + 0 + 22 + write-only + + + + + OUT1_W1TC + GPIO output clear register for GPIO32-53 + 0x18 + 0x20 + + + OUT1_W1TC + GPIO output clear register for GPIO32-53 + 0 + 22 + write-only + + + + + SDIO_SELECT + GPIO sdio select register + 0x1C + 0x20 + + + SDIO_SEL + GPIO sdio select register + 0 + 8 + read-write + + + + + ENABLE + GPIO output enable register for GPIO0-31 + 0x20 + 0x20 + + + DATA + GPIO output enable register for GPIO0-31 + 0 + 32 + read-write + + + + + ENABLE_W1TS + GPIO output enable set register for GPIO0-31 + 0x24 + 0x20 + + + ENABLE_W1TS + GPIO output enable set register for GPIO0-31 + 0 + 32 + write-only + + + + + ENABLE_W1TC + GPIO output enable clear register for GPIO0-31 + 0x28 + 0x20 + + + ENABLE_W1TC + GPIO output enable clear register for GPIO0-31 + 0 + 32 + write-only + + + + + ENABLE1 + GPIO output enable register for GPIO32-53 + 0x2C + 0x20 + + + DATA + GPIO output enable register for GPIO32-53 + 0 + 22 + read-write + + + + + ENABLE1_W1TS + GPIO output enable set register for GPIO32-53 + 0x30 + 0x20 + + + ENABLE1_W1TS + GPIO output enable set register for GPIO32-53 + 0 + 22 + write-only + + + + + ENABLE1_W1TC + GPIO output enable clear register for GPIO32-53 + 0x34 + 0x20 + + + ENABLE1_W1TC + GPIO output enable clear register for GPIO32-53 + 0 + 22 + write-only + + + + + STRAP + pad strapping register + 0x38 + 0x20 + + + STRAPPING + pad strapping register + 0 + 16 + read-only + + + + + IN + GPIO input register for GPIO0-31 + 0x3C + 0x20 + + + DATA_NEXT + GPIO input register for GPIO0-31 + 0 + 32 + read-write + + + + + IN1 + GPIO input register for GPIO32-53 + 0x40 + 0x20 + + + DATA_NEXT + GPIO input register for GPIO32-53 + 0 + 22 + read-write + + + + + STATUS + GPIO interrupt status register for GPIO0-31 + 0x44 + 0x20 + + + INTERRUPT + GPIO interrupt status register for GPIO0-31 + 0 + 32 + read-write + + + + + STATUS_W1TS + GPIO interrupt status set register for GPIO0-31 + 0x48 + 0x20 + + + STATUS_W1TS + GPIO interrupt status set register for GPIO0-31 + 0 + 32 + write-only + + + + + STATUS_W1TC + GPIO interrupt status clear register for GPIO0-31 + 0x4C + 0x20 + + + STATUS_W1TC + GPIO interrupt status clear register for GPIO0-31 + 0 + 32 + write-only + + + + + STATUS1 + GPIO interrupt status register for GPIO32-53 + 0x50 + 0x20 + + + INTERRUPT + GPIO interrupt status register for GPIO32-53 + 0 + 22 + read-write + + + + + STATUS1_W1TS + GPIO interrupt status set register for GPIO32-53 + 0x54 + 0x20 + + + STATUS1_W1TS + GPIO interrupt status set register for GPIO32-53 + 0 + 22 + write-only + + + + + STATUS1_W1TC + GPIO interrupt status clear register for GPIO32-53 + 0x58 + 0x20 + + + STATUS1_W1TC + GPIO interrupt status clear register for GPIO32-53 + 0 + 22 + write-only + + + + + PCPU_INT + GPIO PRO_CPU interrupt status register for GPIO0-31 + 0x5C + 0x20 + + + PROCPU_INT + GPIO PRO_CPU interrupt status register for GPIO0-31 + 0 + 32 + read-only + + + + + PCPU_NMI_INT + GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + 0x60 + 0x20 + + + PROCPU_NMI_INT + GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + 0 + 32 + read-only + + + + + CPUSDIO_INT + GPIO CPUSDIO interrupt status register for GPIO0-31 + 0x64 + 0x20 + + + SDIO_INT + GPIO CPUSDIO interrupt status register for GPIO0-31 + 0 + 32 + read-only + + + + + PCPU_INT1 + GPIO PRO_CPU interrupt status register for GPIO32-53 + 0x68 + 0x20 + + + PROCPU_INT1 + GPIO PRO_CPU interrupt status register for GPIO32-53 + 0 + 22 + read-only + + + + + PCPU_NMI_INT1 + GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-53 + 0x6C + 0x20 + + + PROCPU_NMI_INT1 + GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-53 + 0 + 22 + read-only + + + + + CPUSDIO_INT1 + GPIO CPUSDIO interrupt status register for GPIO32-53 + 0x70 + 0x20 + + + SDIO_INT1 + GPIO CPUSDIO interrupt status register for GPIO32-53 + 0 + 22 + read-only + + + + + 54 + 0x4 + 0-53 + PIN%s + GPIO pin configuration register + 0x74 + 0x20 + + + SYNC2_BYPASS + set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. + 0 + 2 + read-write + + + PAD_DRIVER + set this bit to select pad driver. 1:open-drain. 0:normal. + 2 + 1 + read-write + + + SYNC1_BYPASS + set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. + 3 + 2 + read-write + + + INT_TYPE + set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level + 7 + 3 + read-write + + + WAKEUP_ENABLE + set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + 10 + 1 + read-write + + + CONFIG + reserved + 11 + 2 + read-write + + + INT_ENA + set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt. + 13 + 5 + read-write + + + + + STATUS_NEXT + GPIO interrupt source register for GPIO0-31 + 0x14C + 0x20 + + + STATUS_INTERRUPT_NEXT + GPIO interrupt source register for GPIO0-31 + 0 + 32 + read-only + + + + + STATUS_NEXT1 + GPIO interrupt source register for GPIO32-53 + 0x150 + 0x20 + + + STATUS_INTERRUPT_NEXT1 + GPIO interrupt source register for GPIO32-53 + 0 + 22 + read-only + + + + + 256 + 0x4 + 0-255 + FUNC%s_IN_SEL_CFG + GPIO input function configuration register + 0x154 + 0x20 + + + IN_SEL + set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + 54 + 0x4 + 0-53 + FUNC%s_OUT_SEL_CFG + GPIO output function select register + 0x554 + 0x20 + 0x00000100 + + + OUT_SEL + The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. + 0 + 9 + read-write + + + INV_SEL + set this bit to invert output signal.1:invert.0:not invert. + 9 + 1 + read-write + + + OEN_SEL + set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal. + 10 + 1 + read-write + + + OEN_INV_SEL + set this bit to invert output enable signal.1:invert.0:not invert. + 11 + 1 + read-write + + + + + CLOCK_GATE + GPIO clock gate register + 0x62C + 0x20 + 0x00000001 + + + CLK_EN + set this bit to enable GPIO clock gate + 0 + 1 + read-write + + + + + REG_DATE + GPIO version register + 0x6FC + 0x20 + 0x01907040 + + + REG_DATE + version register + 0 + 28 + read-write + + + + + + + GPIO_SD + Sigma-Delta Modulation + GPIOSD + 0x60004F00 + + 0x0 + 0x2C + registers + + + + 8 + 0x4 + SIGMADELTA%s + Duty Cycle Configure Register of SDM%s + 0x0 + 0x20 + 0x0000FF00 + + + SD_IN + This field is used to configure the duty cycle of sigma delta modulation output. + 0 + 8 + read-write + + + SD_PRESCALE + This field is used to set a divider value to divide APB clock. + 8 + 8 + read-write + + + + + SIGMADELTA_CG + Clock Gating Configure Register + 0x20 + 0x20 + + + CLK_EN + Clock enable bit of configuration registers for sigma delta modulation. + 31 + 1 + read-write + + + + + SIGMADELTA_MISC + MISC Register + 0x24 + 0x20 + + + FUNCTION_CLK_EN + Clock enable bit of sigma delta modulation. + 30 + 1 + read-write + + + SPI_SWAP + Reserved. + 31 + 1 + read-write + + + + + SIGMADELTA_VERSION + Version Control Register + 0x28 + 0x20 + 0x01802260 + + + GPIO_SD_DATE + Version control register. + 0 + 28 + read-write + + + + + + + HMAC + HMAC (Hash-based Message Authentication Code) Accelerator + HMAC + 0x6003E000 + + 0x0 + 0xA4 + registers + + + + SET_START + Process control register 0. + 0x40 + 0x20 + + + SET_START + Start hmac operation. + 0 + 1 + write-only + + + + + SET_PARA_PURPOSE + Configure purpose. + 0x44 + 0x20 + + + PURPOSE_SET + Set hmac parameter purpose. + 0 + 4 + write-only + + + + + SET_PARA_KEY + Configure key. + 0x48 + 0x20 + + + KEY_SET + Set hmac parameter key. + 0 + 3 + write-only + + + + + SET_PARA_FINISH + Finish initial configuration. + 0x4C + 0x20 + + + SET_PARA_END + Finish hmac configuration. + 0 + 1 + write-only + + + + + SET_MESSAGE_ONE + Process control register 1. + 0x50 + 0x20 + + + SET_TEXT_ONE + Call SHA to calculate one message block. + 0 + 1 + write-only + + + + + SET_MESSAGE_ING + Process control register 2. + 0x54 + 0x20 + + + SET_TEXT_ING + Continue typical hmac. + 0 + 1 + write-only + + + + + SET_MESSAGE_END + Process control register 3. + 0x58 + 0x20 + + + SET_TEXT_END + Start hardware padding. + 0 + 1 + write-only + + + + + SET_RESULT_FINISH + Process control register 4. + 0x5C + 0x20 + + + SET_RESULT_END + After read result from upstream, then let hmac back to idle. + 0 + 1 + write-only + + + + + SET_INVALIDATE_JTAG + Invalidate register 0. + 0x60 + 0x20 + + + SET_INVALIDATE_JTAG + Clear result from hmac downstream JTAG. + 0 + 1 + write-only + + + + + SET_INVALIDATE_DS + Invalidate register 1. + 0x64 + 0x20 + + + SET_INVALIDATE_DS + Clear result from hmac downstream DS. + 0 + 1 + write-only + + + + + QUERY_ERROR + Error register. + 0x68 + 0x20 + + + QUREY_CHECK + Hmac configuration state. 0: key are agree with purpose. 1: error + 0 + 1 + read-only + + + + + QUERY_BUSY + Busy register. + 0x6C + 0x20 + + + BUSY_STATE + Hmac state. 1'b0: idle. 1'b1: busy + 0 + 1 + read-only + + + + + 64 + 0x1 + WR_MESSAGE_MEM[%s] + Message block memory. + 0x80 + 0x8 + + + 32 + 0x1 + RD_RESULT_MEM[%s] + Result from upstream. + 0xC0 + 0x8 + + + SET_MESSAGE_PAD + Process control register 5. + 0xF0 + 0x20 + + + SET_TEXT_PAD + Start software padding. + 0 + 1 + write-only + + + + + ONE_BLOCK + Process control register 6. + 0xF4 + 0x20 + + + SET_ONE_BLOCK + Don't have to do padding. + 0 + 1 + write-only + + + + + SOFT_JTAG_CTRL + Jtag register 0. + 0xF8 + 0x20 + + + SOFT_JTAG_CTRL + Turn on JTAG verification. + 0 + 1 + write-only + + + + + WR_JTAG + Jtag register 1. + 0xFC + 0x20 + + + WR_JTAG + 32-bit of key to be compared. + 0 + 32 + write-only + + + + + DATE + Date register. + 0x1FC + 0x20 + 0x02101070 + + + DATE + Hmac date information/ hmac version information. + 0 + 28 + read-write + + + + + + + I2C0 + I2C (Inter-Integrated Circuit) Controller 0 + I2C + 0x60013000 + + 0x0 + 0x90 + registers + + + I2C_MASTER + 11 + + + I2C_EXT0 + 42 + + + + SCL_LOW_PERIOD + Configures the low level width of the SCL +Clock + 0x0 + 0x20 + + + SCL_LOW_PERIOD + This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles. + 0 + 9 + read-write + + + + + CTR + Transmission setting + 0x4 + 0x20 + 0x0000020B + + + SDA_FORCE_OUT + 0: direct output; 1: open drain output. + 0 + 1 + read-write + + + SCL_FORCE_OUT + 0: direct output; 1: open drain output. + 1 + 1 + read-write + + + SAMPLE_SCL_LEVEL + This register is used to select the sample mode. +1: sample SDA data on the SCL low level. +0: sample SDA data on the SCL high level. + 2 + 1 + read-write + + + RX_FULL_ACK_LEVEL + This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold. + 3 + 1 + read-write + + + MS_MODE + Set this bit to configure the module as an I2C Master. Clear this bit to configure the +module as an I2C Slave. + 4 + 1 + read-write + + + TRANS_START + Set this bit to start sending the data in txfifo. + 5 + 1 + write-only + + + TX_LSB_FIRST + This bit is used to control the sending mode for data needing to be sent. +1: send data from the least significant bit; +0: send data from the most significant bit. + 6 + 1 + read-write + + + RX_LSB_FIRST + This bit is used to control the storage mode for received data. +1: receive data from the least significant bit; +0: receive data from the most significant bit. + 7 + 1 + read-write + + + CLK_EN + Reserved + 8 + 1 + read-write + + + ARBITRATION_EN + This is the enable bit for arbitration_lost. + 9 + 1 + read-write + + + FSM_RST + This register is used to reset the scl FMS. + 10 + 1 + write-only + + + CONF_UPGATE + synchronization bit + 11 + 1 + write-only + + + SLV_TX_AUTO_START_EN + This is the enable bit for slave to send data automatically + 12 + 1 + read-write + + + ADDR_10BIT_RW_CHECK_EN + This is the enable bit to check if the r/w bit of 10bit addressing consists with I2C protocol + 13 + 1 + read-write + + + ADDR_BROADCASTING_EN + This is the enable bit to support the 7bit general call function. + 14 + 1 + read-write + + + + + SR + Describe I2C work status. + 0x8 + 0x20 + 0x0000C000 + + + RESP_REC + The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. + 0 + 1 + read-only + + + SLAVE_RW + When in slave mode, 1: master reads from slave; 0: master writes to slave. + 1 + 1 + read-only + + + ARB_LOST + When the I2C controller loses control of SCL line, this register changes to 1. + 3 + 1 + read-only + + + BUS_BUSY + 1: the I2C bus is busy transferring data; 0: the I2C bus is in idle state. + 4 + 1 + read-only + + + SLAVE_ADDRESSED + When configured as an I2C Slave, and the address sent by the master is +equal to the address of the slave, then this bit will be of high level. + 5 + 1 + read-only + + + RXFIFO_CNT + This field represents the amount of data needed to be sent. + 8 + 6 + read-only + + + STRETCH_CAUSE + The cause of stretching SCL low in slave mode. 0: stretching SCL low at the beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode. + 14 + 2 + read-only + + + TXFIFO_CNT + This field stores the amount of received data in RAM. + 18 + 6 + read-only + + + SCL_MAIN_STATE_LAST + This field indicates the states of the I2C module state machine. +0: Idle; 1: Address shift; 2: ACK address; 3: Rx data; 4: Tx data; 5: Send ACK; 6: Wait ACK + 24 + 3 + read-only + + + SCL_STATE_LAST + This field indicates the states of the state machine used to produce SCL. +0: Idle; 1: Start; 2: Negative edge; 3: Low; 4: Positive edge; 5: High; 6: Stop + 28 + 3 + read-only + + + + + TO + Setting time out control for receiving data. + 0xC + 0x20 + 0x00000010 + + + TIME_OUT_VALUE + This register is used to configure the timeout for receiving a data bit in APB +clock cycles. + 0 + 5 + read-write + + + TIME_OUT_EN + This is the enable bit for time out control. + 5 + 1 + read-write + + + + + SLAVE_ADDR + Local slave address setting + 0x10 + 0x20 + + + SLAVE_ADDR + When configured as an I2C Slave, this field is used to configure the slave address. + 0 + 15 + read-write + + + ADDR_10BIT_EN + This field is used to enable the slave 10-bit addressing mode in master mode. + 31 + 1 + read-write + + + + + FIFO_ST + FIFO status register. + 0x14 + 0x20 + + + RXFIFO_RADDR + This is the offset address of the APB reading from rxfifo + 0 + 5 + read-only + + + RXFIFO_WADDR + This is the offset address of i2c module receiving data and writing to rxfifo. + 5 + 5 + read-only + + + TXFIFO_RADDR + This is the offset address of i2c module reading from txfifo. + 10 + 5 + read-only + + + TXFIFO_WADDR + This is the offset address of APB bus writing to txfifo. + 15 + 5 + read-only + + + SLAVE_RW_POINT + The received data in I2C slave mode. + 22 + 8 + read-only + + + + + FIFO_CONF + FIFO configuration register. + 0x18 + 0x20 + 0x0000408B + + + RXFIFO_WM_THRHD + The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. + 0 + 5 + read-write + + + TXFIFO_WM_THRHD + The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. + 5 + 5 + read-write + + + NONFIFO_EN + Set this bit to enable APB nonfifo access. + 10 + 1 + read-write + + + FIFO_ADDR_CFG_EN + When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM. + 11 + 1 + read-write + + + RX_FIFO_RST + Set this bit to reset rx-fifo. + 12 + 1 + read-write + + + TX_FIFO_RST + Set this bit to reset tx-fifo. + 13 + 1 + read-write + + + FIFO_PRT_EN + The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. + 14 + 1 + read-write + + + + + DATA + Rx FIFO read data. + 0x1C + 0x20 + + + FIFO_RDATA + The value of rx FIFO read data. + 0 + 8 + read-write + + + + + INT_RAW + Raw interrupt status + 0x20 + 0x20 + 0x00000002 + + + RXFIFO_WM_INT_RAW + The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_RAW + The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_RAW + The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_RAW + The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_RAW + The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_RAW + The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_RAW + The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_RAW + The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_RAW + The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_RAW + The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_RAW + The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_RAW + The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_RAW + The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_RAW + The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_RAW + The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_RAW + The raw interrupt bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + SLAVE_STRETCH_INT_RAW + The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-only + + + GENERAL_CALL_INT_RAW + The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-only + + + + + INT_CLR + Interrupt clear bits + 0x24 + 0x20 + + + RXFIFO_WM_INT_CLR + Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + write-only + + + TXFIFO_WM_INT_CLR + Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + write-only + + + END_DETECT_INT_CLR + Set this bit to clear the I2C_END_DETECT_INT interrupt. + 3 + 1 + write-only + + + BYTE_TRANS_DONE_INT_CLR + Set this bit to clear the I2C_END_DETECT_INT interrupt. + 4 + 1 + write-only + + + ARBITRATION_LOST_INT_CLR + Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + write-only + + + MST_TXFIFO_UDF_INT_CLR + Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + write-only + + + TRANS_COMPLETE_INT_CLR + Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + write-only + + + TIME_OUT_INT_CLR + Set this bit to clear the I2C_TIME_OUT_INT interrupt. + 8 + 1 + write-only + + + TRANS_START_INT_CLR + Set this bit to clear the I2C_TRANS_START_INT interrupt. + 9 + 1 + write-only + + + NACK_INT_CLR + Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + write-only + + + TXFIFO_OVF_INT_CLR + Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + write-only + + + RXFIFO_UDF_INT_CLR + Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + write-only + + + SCL_ST_TO_INT_CLR + Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + write-only + + + SCL_MAIN_ST_TO_INT_CLR + Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + write-only + + + DET_START_INT_CLR + Set this bit to clear I2C_DET_START_INT interrupt. + 15 + 1 + write-only + + + SLAVE_STRETCH_INT_CLR + Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + write-only + + + GENERAL_CALL_INT_CLR + Set this bit for I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + write-only + + + + + INT_ENA + Interrupt enable bits + 0x28 + 0x20 + + + RXFIFO_WM_INT_ENA + The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-write + + + TXFIFO_WM_INT_ENA + The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-write + + + END_DETECT_INT_ENA + The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-write + + + BYTE_TRANS_DONE_INT_ENA + The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-write + + + MST_TXFIFO_UDF_INT_ENA + The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-write + + + TRANS_COMPLETE_INT_ENA + The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-write + + + TIME_OUT_INT_ENA + The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-write + + + TRANS_START_INT_ENA + The interrupt enable bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-write + + + NACK_INT_ENA + The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-write + + + TXFIFO_OVF_INT_ENA + The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-write + + + RXFIFO_UDF_INT_ENA + The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-write + + + SCL_ST_TO_INT_ENA + The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-write + + + SCL_MAIN_ST_TO_INT_ENA + The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-write + + + DET_START_INT_ENA + The interrupt enable bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-write + + + SLAVE_STRETCH_INT_ENA + The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-write + + + GENERAL_CALL_INT_ENA + The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-write + + + + + INT_STATUS + Status of captured I2C communication events + 0x2C + 0x20 + + + RXFIFO_WM_INT_ST + The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_ST + The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_ST + The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_ST + The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_ST + The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_ST + The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_ST + The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_ST + The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_ST + The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_ST + The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_ST + The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_ST + The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_ST + The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_ST + The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_ST + The masked interrupt status bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + SLAVE_STRETCH_INT_ST + The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-only + + + GENERAL_CALL_INT_ST + The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-only + + + + + SDA_HOLD + Configures the hold time after a negative SCL edge. + 0x30 + 0x20 + + + TIME + This register is used to configure the time to hold the data after the negative +edge of SCL, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SDA_SAMPLE + Configures the sample time after a positive SCL edge. + 0x34 + 0x20 + + + TIME + This register is used to configure for how long SDA is sampled, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_HIGH_PERIOD + Configures the high level width of SCL + 0x38 + 0x20 + + + SCL_HIGH_PERIOD + This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles. + 0 + 9 + read-write + + + SCL_WAIT_HIGH_PERIOD + This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles. + 9 + 7 + read-write + + + + + SCL_START_HOLD + Configures the delay between the SDA and SCL negative edge for a start condition + 0x40 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the negative edge +of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_RSTART_SETUP + Configures the delay between the positive +edge of SCL and the negative edge of SDA + 0x44 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the positive +edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_STOP_HOLD + Configures the delay after the SCL clock +edge for a stop condition + 0x48 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the delay after the STOP condition, +in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_STOP_SETUP + Configures the delay between the SDA and +SCL positive edge for a stop condition + 0x4C + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the positive edge +of SCL and the positive edge of SDA, in I2C module clock cycles. + 0 + 9 + read-write + + + + + FILTER_CFG + SCL and SDA filter configuration register + 0x50 + 0x20 + 0x00000300 + + + SCL_FILTER_THRES + When a pulse on the SCL input has smaller width than this register value +in I2C module clock cycles, the I2C controller will ignore that pulse. + 0 + 4 + read-write + + + SDA_FILTER_THRES + When a pulse on the SDA input has smaller width than this register value +in I2C module clock cycles, the I2C controller will ignore that pulse. + 4 + 4 + read-write + + + SCL_FILTER_EN + This is the filter enable bit for SCL. + 8 + 1 + read-write + + + SDA_FILTER_EN + This is the filter enable bit for SDA. + 9 + 1 + read-write + + + + + CLK_CONF + I2C CLK configuration register + 0x54 + 0x20 + 0x00200000 + + + SCLK_DIV_NUM + the integral part of the fractional divisor for i2c module + 0 + 8 + read-write + + + SCLK_DIV_A + the numerator of the fractional part of the fractional divisor for i2c module + 8 + 6 + read-write + + + SCLK_DIV_B + the denominator of the fractional part of the fractional divisor for i2c module + 14 + 6 + read-write + + + SCLK_SEL + The clock selection for i2c module:0-XTAL;1-CLK_8MHz. + 20 + 1 + read-write + + + SCLK_ACTIVE + The clock switch for i2c module + 21 + 1 + read-write + + + + + 8 + 0x4 + 0-7 + COMD%s + I2C command register %s + 0x58 + 0x20 + + + COMMAND + This is the content of command 0. It consists of three parts: +op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + COMMAND_DONE + When command 0 is done in I2C Master mode, this bit changes to high +level. + 31 + 1 + read-write + + + + + SCL_ST_TIME_OUT + SCL status time out register + 0x78 + 0x20 + 0x00000010 + + + SCL_ST_TO_I2C + The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + 0 + 5 + read-write + + + + + SCL_MAIN_ST_TIME_OUT + SCL main status time out register + 0x7C + 0x20 + 0x00000010 + + + SCL_MAIN_ST_TO_I2C + The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23 + 0 + 5 + read-write + + + + + SCL_SP_CONF + Power configuration register + 0x80 + 0x20 + + + SCL_RST_SLV_EN + When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0]. + 0 + 1 + read-write + + + SCL_RST_SLV_NUM + Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1. + 1 + 5 + read-write + + + SCL_PD_EN + The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. + 6 + 1 + read-write + + + SDA_PD_EN + The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. + 7 + 1 + read-write + + + + + SCL_STRETCH_CONF + Set SCL stretch of I2C slave + 0x84 + 0x20 + + + STRETCH_PROTECT_NUM + Configure the period of I2C slave stretching SCL line. + 0 + 10 + read-write + + + SLAVE_SCL_STRETCH_EN + The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch event happens. The stretch cause can be seen in reg_stretch_cause. + 10 + 1 + read-write + + + SLAVE_SCL_STRETCH_CLR + Set this bit to clear the I2C slave SCL stretch function. + 11 + 1 + write-only + + + SLAVE_BYTE_ACK_CTL_EN + The enable bit for slave to control ACK level function. + 12 + 1 + read-write + + + SLAVE_BYTE_ACK_LVL + Set the ACK level when slave controlling ACK level function enables. + 13 + 1 + read-write + + + + + DATE + Version register + 0xF8 + 0x20 + 0x20070201 + + + DATE + This is the the version register. + 0 + 32 + read-write + + + + + TXFIFO_START_ADDR + I2C TXFIFO base address register + 0x100 + 0x20 + + + TXFIFO_START_ADDR + This is the I2C txfifo first address. + 0 + 32 + read-only + + + + + RXFIFO_START_ADDR + I2C RXFIFO base address register + 0x180 + 0x20 + + + RXFIFO_START_ADDR + This is the I2C rxfifo first address. + 0 + 32 + read-only + + + + + + + I2C1 + I2C (Inter-Integrated Circuit) Controller 1 + 0x60027000 + + I2C_EXT1 + 43 + + + + I2S0 + I2S (Inter-IC Sound) Controller 0 + I2S + 0x6000F000 + + 0x0 + 0x5C + registers + + + I2S0 + 25 + + + + INT_RAW + I2S interrupt raw register, valid in level. + 0xC + 0x20 + + + RX_DONE_INT_RAW + The raw interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + TX_DONE_INT_RAW + The raw interrupt status bit for the i2s_tx_done_int interrupt + 1 + 1 + read-only + + + RX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-only + + + TX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-only + + + + + INT_ST + I2S interrupt status register. + 0x10 + 0x20 + + + RX_DONE_INT_ST + The masked interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + TX_DONE_INT_ST + The masked interrupt status bit for the i2s_tx_done_int interrupt + 1 + 1 + read-only + + + RX_HUNG_INT_ST + The masked interrupt status bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-only + + + TX_HUNG_INT_ST + The masked interrupt status bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-only + + + + + INT_ENA + I2S interrupt enable register. + 0x14 + 0x20 + + + RX_DONE_INT_ENA + The interrupt enable bit for the i2s_rx_done_int interrupt + 0 + 1 + read-write + + + TX_DONE_INT_ENA + The interrupt enable bit for the i2s_tx_done_int interrupt + 1 + 1 + read-write + + + RX_HUNG_INT_ENA + The interrupt enable bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-write + + + TX_HUNG_INT_ENA + The interrupt enable bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-write + + + + + INT_CLR + I2S interrupt clear register. + 0x18 + 0x20 + + + RX_DONE_INT_CLR + Set this bit to clear the i2s_rx_done_int interrupt + 0 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the i2s_tx_done_int interrupt + 1 + 1 + write-only + + + RX_HUNG_INT_CLR + Set this bit to clear the i2s_rx_hung_int interrupt + 2 + 1 + write-only + + + TX_HUNG_INT_CLR + Set this bit to clear the i2s_tx_hung_int interrupt + 3 + 1 + write-only + + + + + RX_CONF + I2S RX configure register + 0x20 + 0x20 + 0x00009600 + + + RX_RESET + Set this bit to reset receiver + 0 + 1 + write-only + + + RX_FIFO_RESET + Set this bit to reset Rx AFIFO + 1 + 1 + write-only + + + RX_START + Set this bit to start receiving data + 2 + 1 + read-write + + + RX_SLAVE_MOD + Set this bit to enable slave receiver mode + 3 + 1 + read-write + + + RX_MONO + Set this bit to enable receiver in mono mode + 5 + 1 + read-write + + + RX_BIG_ENDIAN + I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + RX_UPDATE + Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. + 8 + 1 + read-write + + + RX_MONO_FST_VLD + 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode. + 9 + 1 + read-write + + + RX_PCM_CONF + I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 + 2 + read-write + + + RX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for received data. + 12 + 1 + read-write + + + RX_STOP_MODE + 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. + 13 + 2 + read-write + + + RX_LEFT_ALIGN + 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + 15 + 1 + read-write + + + RX_24_FILL_EN + 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + 16 + 1 + read-write + + + RX_WS_IDLE_POL + 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + RX_BIT_ORDER + I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first. + 18 + 1 + read-write + + + RX_TDM_EN + 1: Enable I2S TDM Rx mode . 0: Disable. + 19 + 1 + read-write + + + RX_PDM_EN + 1: Enable I2S PDM Rx mode . 0: Disable. + 20 + 1 + read-write + + + RX_PDM2PCM_EN + 1: Enable PDM2PCM RX mode. 0: DIsable. + 21 + 1 + read-write + + + RX_PDM_SINC_DSR_16_EN + Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64. + 22 + 1 + read-write + + + + + TX_CONF + I2S TX configure register + 0x24 + 0x20 + 0x0000B200 + + + TX_RESET + Set this bit to reset transmitter + 0 + 1 + write-only + + + TX_FIFO_RESET + Set this bit to reset Tx AFIFO + 1 + 1 + write-only + + + TX_START + Set this bit to start transmitting data + 2 + 1 + read-write + + + TX_SLAVE_MOD + Set this bit to enable slave transmitter mode + 3 + 1 + read-write + + + TX_MONO + Set this bit to enable transmitter in mono mode + 5 + 1 + read-write + + + TX_CHAN_EQUAL + 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. + 6 + 1 + read-write + + + TX_BIG_ENDIAN + I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + TX_UPDATE + Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. + 8 + 1 + read-write + + + TX_MONO_FST_VLD + 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode. + 9 + 1 + read-write + + + TX_PCM_CONF + I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 + 2 + read-write + + + TX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for transmitted data. + 12 + 1 + read-write + + + TX_STOP_EN + Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + 13 + 1 + read-write + + + TX_LEFT_ALIGN + 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. + 15 + 1 + read-write + + + TX_24_FILL_EN + 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode + 16 + 1 + read-write + + + TX_WS_IDLE_POL + 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + TX_BIT_ORDER + I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first. + 18 + 1 + read-write + + + TX_TDM_EN + 1: Enable I2S TDM Tx mode . 0: Disable. + 19 + 1 + read-write + + + TX_PDM_EN + 1: Enable I2S PDM Tx mode . 0: Disable. + 20 + 1 + read-write + + + TX_CHAN_MOD + I2S transmitter channel mode configuration bits. + 24 + 3 + read-write + + + SIG_LOOPBACK + Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. + 27 + 1 + read-write + + + + + RX_CONF1 + I2S RX configure register 1 + 0x28 + 0x20 + 0x2F3DE300 + + + RX_TDM_WS_WIDTH + The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck + 0 + 7 + read-write + + + RX_BCK_DIV_NUM + Bit clock configuration bits in receiver mode. + 7 + 6 + read-write + + + RX_BITS_MOD + Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 13 + 5 + read-write + + + RX_HALF_SAMPLE_BITS + I2S Rx half sample bits -1. + 18 + 6 + read-write + + + RX_TDM_CHAN_BITS + The Rx bit number for each channel minus 1in TDM mode. + 24 + 5 + read-write + + + RX_MSB_SHIFT + Set this bit to enable receiver in Phillips standard mode + 29 + 1 + read-write + + + + + TX_CONF1 + I2S TX configure register 1 + 0x2C + 0x20 + 0x6F3DE300 + + + TX_TDM_WS_WIDTH + The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck + 0 + 7 + read-write + + + TX_BCK_DIV_NUM + Bit clock configuration bits in transmitter mode. + 7 + 6 + read-write + + + TX_BITS_MOD + Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 13 + 5 + read-write + + + TX_HALF_SAMPLE_BITS + I2S Tx half sample bits -1. + 18 + 6 + read-write + + + TX_TDM_CHAN_BITS + The Tx bit number for each channel minus 1in TDM mode. + 24 + 5 + read-write + + + TX_MSB_SHIFT + Set this bit to enable transmitter in Phillips standard mode + 29 + 1 + read-write + + + TX_BCK_NO_DLY + 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode. + 30 + 1 + read-write + + + + + RX_CLKM_CONF + I2S RX clock configure register + 0x30 + 0x20 + 0x00000002 + + + RX_CLKM_DIV_NUM + Integral I2S clock divider value + 0 + 8 + read-write + + + RX_CLK_ACTIVE + I2S Rx module clock enable signal. + 26 + 1 + read-write + + + RX_CLK_SEL + Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + 27 + 2 + read-write + + + MCLK_SEL + 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT. + 29 + 1 + read-write + + + + + TX_CLKM_CONF + I2S TX clock configure register + 0x34 + 0x20 + 0x00000002 + + + TX_CLKM_DIV_NUM + Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. + 0 + 8 + read-write + + + TX_CLK_ACTIVE + I2S Tx module clock enable signal. + 26 + 1 + read-write + + + TX_CLK_SEL + Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + 27 + 2 + read-write + + + CLK_EN + Set this bit to enable clk gate + 29 + 1 + read-write + + + + + RX_CLKM_DIV_CONF + I2S RX module clock divider configure register + 0x38 + 0x20 + 0x00000200 + + + RX_CLKM_DIV_Z + For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b). + 0 + 9 + read-write + + + RX_CLKM_DIV_Y + For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)). + 9 + 9 + read-write + + + RX_CLKM_DIV_X + For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + 18 + 9 + read-write + + + RX_CLKM_DIV_YN1 + For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1. + 27 + 1 + read-write + + + + + TX_CLKM_DIV_CONF + I2S TX module clock divider configure register + 0x3C + 0x20 + 0x00000200 + + + TX_CLKM_DIV_Z + For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b). + 0 + 9 + read-write + + + TX_CLKM_DIV_Y + For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)). + 9 + 9 + read-write + + + TX_CLKM_DIV_X + For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + 18 + 9 + read-write + + + TX_CLKM_DIV_YN1 + For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1. + 27 + 1 + read-write + + + + + TX_PCM2PDM_CONF + I2S TX PCM2PDM configuration register + 0x40 + 0x20 + 0x004AA004 + + + TX_PDM_HP_BYPASS + I2S TX PDM bypass hp filter or not. The option has been removed. + 0 + 1 + read-write + + + TX_PDM_SINC_OSR2 + I2S TX PDM OSR2 value + 1 + 4 + read-write + + + TX_PDM_PRESCALE + I2S TX PDM prescale for sigmadelta + 5 + 8 + read-write + + + TX_PDM_HP_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 13 + 2 + read-write + + + TX_PDM_LP_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 15 + 2 + read-write + + + TX_PDM_SINC_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 17 + 2 + read-write + + + TX_PDM_SIGMADELTA_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 19 + 2 + read-write + + + TX_PDM_SIGMADELTA_DITHER2 + I2S TX PDM sigmadelta dither2 value + 21 + 1 + read-write + + + TX_PDM_SIGMADELTA_DITHER + I2S TX PDM sigmadelta dither value + 22 + 1 + read-write + + + TX_PDM_DAC_2OUT_EN + I2S TX PDM dac mode enable + 23 + 1 + read-write + + + TX_PDM_DAC_MODE_EN + I2S TX PDM dac 2channel enable + 24 + 1 + read-write + + + PCM2PDM_CONV_EN + I2S TX PDM Converter enable + 25 + 1 + read-write + + + + + TX_PCM2PDM_CONF1 + I2S TX PCM2PDM configuration register + 0x44 + 0x20 + 0x03F783C0 + + + TX_PDM_FP + I2S TX PDM Fp + 0 + 10 + read-write + + + TX_PDM_FS + I2S TX PDM Fs + 10 + 10 + read-write + + + TX_IIR_HP_MULT12_5 + The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0]) + 20 + 3 + read-write + + + TX_IIR_HP_MULT12_0 + The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0]) + 23 + 3 + read-write + + + + + RX_TDM_CTRL + I2S TX TDM mode control register + 0x50 + 0x20 + 0x0000FFFF + + + RX_TDM_PDM_CHAN0_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel. + 0 + 1 + read-write + + + RX_TDM_PDM_CHAN1_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel. + 1 + 1 + read-write + + + RX_TDM_PDM_CHAN2_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel. + 2 + 1 + read-write + + + RX_TDM_PDM_CHAN3_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel. + 3 + 1 + read-write + + + RX_TDM_PDM_CHAN4_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel. + 4 + 1 + read-write + + + RX_TDM_PDM_CHAN5_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel. + 5 + 1 + read-write + + + RX_TDM_PDM_CHAN6_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel. + 6 + 1 + read-write + + + RX_TDM_PDM_CHAN7_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel. + 7 + 1 + read-write + + + RX_TDM_CHAN8_EN + 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel. + 8 + 1 + read-write + + + RX_TDM_CHAN9_EN + 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel. + 9 + 1 + read-write + + + RX_TDM_CHAN10_EN + 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel. + 10 + 1 + read-write + + + RX_TDM_CHAN11_EN + 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel. + 11 + 1 + read-write + + + RX_TDM_CHAN12_EN + 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel. + 12 + 1 + read-write + + + RX_TDM_CHAN13_EN + 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel. + 13 + 1 + read-write + + + RX_TDM_CHAN14_EN + 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel. + 14 + 1 + read-write + + + RX_TDM_CHAN15_EN + 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel. + 15 + 1 + read-write + + + RX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + + + + + TX_TDM_CTRL + I2S TX TDM mode control register + 0x54 + 0x20 + 0x0000FFFF + + + TX_TDM_CHAN0_EN + 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel. + 0 + 1 + read-write + + + TX_TDM_CHAN1_EN + 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel. + 1 + 1 + read-write + + + TX_TDM_CHAN2_EN + 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel. + 2 + 1 + read-write + + + TX_TDM_CHAN3_EN + 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel. + 3 + 1 + read-write + + + TX_TDM_CHAN4_EN + 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel. + 4 + 1 + read-write + + + TX_TDM_CHAN5_EN + 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel. + 5 + 1 + read-write + + + TX_TDM_CHAN6_EN + 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel. + 6 + 1 + read-write + + + TX_TDM_CHAN7_EN + 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel. + 7 + 1 + read-write + + + TX_TDM_CHAN8_EN + 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel. + 8 + 1 + read-write + + + TX_TDM_CHAN9_EN + 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel. + 9 + 1 + read-write + + + TX_TDM_CHAN10_EN + 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel. + 10 + 1 + read-write + + + TX_TDM_CHAN11_EN + 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel. + 11 + 1 + read-write + + + TX_TDM_CHAN12_EN + 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel. + 12 + 1 + read-write + + + TX_TDM_CHAN13_EN + 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel. + 13 + 1 + read-write + + + TX_TDM_CHAN14_EN + 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel. + 14 + 1 + read-write + + + TX_TDM_CHAN15_EN + 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel. + 15 + 1 + read-write + + + TX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + + + TX_TDM_SKIP_MSK_EN + When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels. + 20 + 1 + read-write + + + + + RX_TIMING + I2S RX timing control register + 0x58 + 0x20 + + + RX_SD_IN_DM + The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + RX_SD1_IN_DM + The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 4 + 2 + read-write + + + RX_SD2_IN_DM + The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 8 + 2 + read-write + + + RX_SD3_IN_DM + The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 12 + 2 + read-write + + + RX_WS_OUT_DM + The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 + read-write + + + RX_BCK_OUT_DM + The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 + read-write + + + RX_WS_IN_DM + The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + RX_BCK_IN_DM + The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + TX_TIMING + I2S TX timing control register + 0x5C + 0x20 + + + TX_SD_OUT_DM + The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + TX_SD1_OUT_DM + The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 4 + 2 + read-write + + + TX_WS_OUT_DM + The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 + read-write + + + TX_BCK_OUT_DM + The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 + read-write + + + TX_WS_IN_DM + The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + TX_BCK_IN_DM + The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + LC_HUNG_CONF + I2S HUNG configure register. + 0x60 + 0x20 + 0x00000810 + + + LC_FIFO_TIMEOUT + the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value + 0 + 8 + read-write + + + LC_FIFO_TIMEOUT_SHIFT + The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift + 8 + 3 + read-write + + + LC_FIFO_TIMEOUT_ENA + The enable bit for FIFO timeout + 11 + 1 + read-write + + + + + RXEOF_NUM + I2S RX data number control register. + 0x64 + 0x20 + 0x00000040 + + + RX_EOF_NUM + The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. + 0 + 12 + read-write + + + + + CONF_SIGLE_DATA + I2S signal data register + 0x68 + 0x20 + + + SINGLE_DATA + The configured constant channel data to be sent out. + 0 + 32 + read-write + + + + + STATE + I2S TX status register + 0x6C + 0x20 + 0x00000001 + + + TX_IDLE + 1: i2s_tx is idle state. 0: i2s_tx is working. + 0 + 1 + read-only + + + + + DATE + Version control register + 0x80 + 0x20 + 0x02009070 + + + DATE + I2S version control register + 0 + 28 + read-write + + + + + + + I2S1 + I2S (Inter-IC Sound) Controller 1 + I2S1 + 0x6002D000 + + 0x0 + 0x54 + registers + + + I2S1 + 26 + + + + INT_RAW + I2S interrupt raw register, valid in level. + 0xC + 0x20 + + + RX_DONE_INT_RAW + The raw interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + TX_DONE_INT_RAW + The raw interrupt status bit for the i2s_tx_done_int interrupt + 1 + 1 + read-only + + + RX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-only + + + TX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-only + + + + + INT_ST + I2S interrupt status register. + 0x10 + 0x20 + + + RX_DONE_INT_ST + The masked interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + TX_DONE_INT_ST + The masked interrupt status bit for the i2s_tx_done_int interrupt + 1 + 1 + read-only + + + RX_HUNG_INT_ST + The masked interrupt status bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-only + + + TX_HUNG_INT_ST + The masked interrupt status bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-only + + + + + INT_ENA + I2S interrupt enable register. + 0x14 + 0x20 + + + RX_DONE_INT_ENA + The interrupt enable bit for the i2s_rx_done_int interrupt + 0 + 1 + read-write + + + TX_DONE_INT_ENA + The interrupt enable bit for the i2s_tx_done_int interrupt + 1 + 1 + read-write + + + RX_HUNG_INT_ENA + The interrupt enable bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-write + + + TX_HUNG_INT_ENA + The interrupt enable bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-write + + + + + INT_CLR + I2S interrupt clear register. + 0x18 + 0x20 + + + RX_DONE_INT_CLR + Set this bit to clear the i2s_rx_done_int interrupt + 0 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the i2s_tx_done_int interrupt + 1 + 1 + write-only + + + RX_HUNG_INT_CLR + Set this bit to clear the i2s_rx_hung_int interrupt + 2 + 1 + write-only + + + TX_HUNG_INT_CLR + Set this bit to clear the i2s_tx_hung_int interrupt + 3 + 1 + write-only + + + + + RX_CONF + I2S RX configure register + 0x20 + 0x20 + 0x00009600 + + + RX_RESET + Set this bit to reset receiver + 0 + 1 + write-only + + + RX_FIFO_RESET + Set this bit to reset Rx AFIFO + 1 + 1 + write-only + + + RX_START + Set this bit to start receiving data + 2 + 1 + read-write + + + RX_SLAVE_MOD + Set this bit to enable slave receiver mode + 3 + 1 + read-write + + + RX_MONO + Set this bit to enable receiver in mono mode + 5 + 1 + read-write + + + RX_BIG_ENDIAN + I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + RX_UPDATE + Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. + 8 + 1 + read-write + + + RX_MONO_FST_VLD + 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode. + 9 + 1 + read-write + + + RX_PCM_CONF + I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 + 2 + read-write + + + RX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for received data. + 12 + 1 + read-write + + + RX_STOP_MODE + 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. + 13 + 2 + read-write + + + RX_LEFT_ALIGN + 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + 15 + 1 + read-write + + + RX_24_FILL_EN + 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + 16 + 1 + read-write + + + RX_WS_IDLE_POL + 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + RX_BIT_ORDER + I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first. + 18 + 1 + read-write + + + RX_TDM_EN + 1: Enable I2S TDM Rx mode . 0: Disable. + 19 + 1 + read-write + + + RX_PDM_EN + 1: Enable I2S PDM Rx mode . 0: Disable. + 20 + 1 + read-write + + + + + TX_CONF + I2S TX configure register + 0x24 + 0x20 + 0x0000B200 + + + TX_RESET + Set this bit to reset transmitter + 0 + 1 + write-only + + + TX_FIFO_RESET + Set this bit to reset Tx AFIFO + 1 + 1 + write-only + + + TX_START + Set this bit to start transmitting data + 2 + 1 + read-write + + + TX_SLAVE_MOD + Set this bit to enable slave transmitter mode + 3 + 1 + read-write + + + TX_MONO + Set this bit to enable transmitter in mono mode + 5 + 1 + read-write + + + TX_CHAN_EQUAL + 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. + 6 + 1 + read-write + + + TX_BIG_ENDIAN + I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + TX_UPDATE + Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. + 8 + 1 + read-write + + + TX_MONO_FST_VLD + 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode. + 9 + 1 + read-write + + + TX_PCM_CONF + I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 + 2 + read-write + + + TX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for transmitted data. + 12 + 1 + read-write + + + TX_STOP_EN + Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + 13 + 1 + read-write + + + TX_LEFT_ALIGN + 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. + 15 + 1 + read-write + + + TX_24_FILL_EN + 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode + 16 + 1 + read-write + + + TX_WS_IDLE_POL + 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + TX_BIT_ORDER + I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first. + 18 + 1 + read-write + + + TX_TDM_EN + 1: Enable I2S TDM Tx mode . 0: Disable. + 19 + 1 + read-write + + + TX_PDM_EN + 1: Enable I2S PDM Tx mode . 0: Disable. + 20 + 1 + read-write + + + TX_CHAN_MOD + I2S transmitter channel mode configuration bits. + 24 + 3 + read-write + + + SIG_LOOPBACK + Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. + 27 + 1 + read-write + + + + + RX_CONF1 + I2S RX configure register 1 + 0x28 + 0x20 + 0x2F3DE300 + + + RX_TDM_WS_WIDTH + The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck + 0 + 7 + read-write + + + RX_BCK_DIV_NUM + Bit clock configuration bits in receiver mode. + 7 + 6 + read-write + + + RX_BITS_MOD + Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 13 + 5 + read-write + + + RX_HALF_SAMPLE_BITS + I2S Rx half sample bits -1. + 18 + 6 + read-write + + + RX_TDM_CHAN_BITS + The Rx bit number for each channel minus 1in TDM mode. + 24 + 5 + read-write + + + RX_MSB_SHIFT + Set this bit to enable receiver in Phillips standard mode + 29 + 1 + read-write + + + + + TX_CONF1 + I2S TX configure register 1 + 0x2C + 0x20 + 0x6F3DE300 + + + TX_TDM_WS_WIDTH + The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck + 0 + 7 + read-write + + + TX_BCK_DIV_NUM + Bit clock configuration bits in transmitter mode. + 7 + 6 + read-write + + + TX_BITS_MOD + Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 13 + 5 + read-write + + + TX_HALF_SAMPLE_BITS + I2S Tx half sample bits -1. + 18 + 6 + read-write + + + TX_TDM_CHAN_BITS + The Tx bit number for each channel minus 1in TDM mode. + 24 + 5 + read-write + + + TX_MSB_SHIFT + Set this bit to enable transmitter in Phillips standard mode + 29 + 1 + read-write + + + TX_BCK_NO_DLY + 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode. + 30 + 1 + read-write + + + + + RX_CLKM_CONF + I2S RX clock configure register + 0x30 + 0x20 + 0x00000002 + + + RX_CLKM_DIV_NUM + Integral I2S clock divider value + 0 + 8 + read-write + + + RX_CLK_ACTIVE + I2S Rx module clock enable signal. + 26 + 1 + read-write + + + RX_CLK_SEL + Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + 27 + 2 + read-write + + + MCLK_SEL + 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT. + 29 + 1 + read-write + + + + + TX_CLKM_CONF + I2S TX clock configure register + 0x34 + 0x20 + 0x00000002 + + + TX_CLKM_DIV_NUM + Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. + 0 + 8 + read-write + + + TX_CLK_ACTIVE + I2S Tx module clock enable signal. + 26 + 1 + read-write + + + TX_CLK_SEL + Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + 27 + 2 + read-write + + + CLK_EN + Set this bit to enable clk gate + 29 + 1 + read-write + + + + + RX_CLKM_DIV_CONF + I2S RX module clock divider configure register + 0x38 + 0x20 + 0x00000200 + + + RX_CLKM_DIV_Z + For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b). + 0 + 9 + read-write + + + RX_CLKM_DIV_Y + For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)). + 9 + 9 + read-write + + + RX_CLKM_DIV_X + For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + 18 + 9 + read-write + + + RX_CLKM_DIV_YN1 + For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1. + 27 + 1 + read-write + + + + + TX_CLKM_DIV_CONF + I2S TX module clock divider configure register + 0x3C + 0x20 + 0x00000200 + + + TX_CLKM_DIV_Z + For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b). + 0 + 9 + read-write + + + TX_CLKM_DIV_Y + For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)). + 9 + 9 + read-write + + + TX_CLKM_DIV_X + For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + 18 + 9 + read-write + + + TX_CLKM_DIV_YN1 + For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1. + 27 + 1 + read-write + + + + + RX_TDM_CTRL + I2S TX TDM mode control register + 0x50 + 0x20 + 0x0000FFFF + + + RX_TDM_PDM_CHAN0_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel. + 0 + 1 + read-write + + + RX_TDM_PDM_CHAN1_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel. + 1 + 1 + read-write + + + RX_TDM_PDM_CHAN2_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel. + 2 + 1 + read-write + + + RX_TDM_PDM_CHAN3_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel. + 3 + 1 + read-write + + + RX_TDM_PDM_CHAN4_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel. + 4 + 1 + read-write + + + RX_TDM_PDM_CHAN5_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel. + 5 + 1 + read-write + + + RX_TDM_PDM_CHAN6_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel. + 6 + 1 + read-write + + + RX_TDM_PDM_CHAN7_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel. + 7 + 1 + read-write + + + RX_TDM_CHAN8_EN + 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel. + 8 + 1 + read-write + + + RX_TDM_CHAN9_EN + 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel. + 9 + 1 + read-write + + + RX_TDM_CHAN10_EN + 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel. + 10 + 1 + read-write + + + RX_TDM_CHAN11_EN + 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel. + 11 + 1 + read-write + + + RX_TDM_CHAN12_EN + 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel. + 12 + 1 + read-write + + + RX_TDM_CHAN13_EN + 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel. + 13 + 1 + read-write + + + RX_TDM_CHAN14_EN + 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel. + 14 + 1 + read-write + + + RX_TDM_CHAN15_EN + 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel. + 15 + 1 + read-write + + + RX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + + + + + TX_TDM_CTRL + I2S TX TDM mode control register + 0x54 + 0x20 + 0x0000FFFF + + + TX_TDM_CHAN0_EN + 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel. + 0 + 1 + read-write + + + TX_TDM_CHAN1_EN + 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel. + 1 + 1 + read-write + + + TX_TDM_CHAN2_EN + 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel. + 2 + 1 + read-write + + + TX_TDM_CHAN3_EN + 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel. + 3 + 1 + read-write + + + TX_TDM_CHAN4_EN + 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel. + 4 + 1 + read-write + + + TX_TDM_CHAN5_EN + 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel. + 5 + 1 + read-write + + + TX_TDM_CHAN6_EN + 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel. + 6 + 1 + read-write + + + TX_TDM_CHAN7_EN + 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel. + 7 + 1 + read-write + + + TX_TDM_CHAN8_EN + 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel. + 8 + 1 + read-write + + + TX_TDM_CHAN9_EN + 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel. + 9 + 1 + read-write + + + TX_TDM_CHAN10_EN + 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel. + 10 + 1 + read-write + + + TX_TDM_CHAN11_EN + 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel. + 11 + 1 + read-write + + + TX_TDM_CHAN12_EN + 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel. + 12 + 1 + read-write + + + TX_TDM_CHAN13_EN + 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel. + 13 + 1 + read-write + + + TX_TDM_CHAN14_EN + 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel. + 14 + 1 + read-write + + + TX_TDM_CHAN15_EN + 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel. + 15 + 1 + read-write + + + TX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + + + TX_TDM_SKIP_MSK_EN + When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels. + 20 + 1 + read-write + + + + + RX_TIMING + I2S RX timing control register + 0x58 + 0x20 + + + RX_SD_IN_DM + The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + RX_WS_OUT_DM + The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 + read-write + + + RX_BCK_OUT_DM + The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 + read-write + + + RX_WS_IN_DM + The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + RX_BCK_IN_DM + The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + TX_TIMING + I2S TX timing control register + 0x5C + 0x20 + + + TX_SD_OUT_DM + The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + TX_SD1_OUT_DM + The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 4 + 2 + read-write + + + TX_WS_OUT_DM + The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 + read-write + + + TX_BCK_OUT_DM + The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 + read-write + + + TX_WS_IN_DM + The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + TX_BCK_IN_DM + The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + LC_HUNG_CONF + I2S HUNG configure register. + 0x60 + 0x20 + 0x00000810 + + + LC_FIFO_TIMEOUT + the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value + 0 + 8 + read-write + + + LC_FIFO_TIMEOUT_SHIFT + The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift + 8 + 3 + read-write + + + LC_FIFO_TIMEOUT_ENA + The enable bit for FIFO timeout + 11 + 1 + read-write + + + + + RXEOF_NUM + I2S RX data number control register. + 0x64 + 0x20 + 0x00000040 + + + RX_EOF_NUM + The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. + 0 + 12 + read-write + + + + + CONF_SIGLE_DATA + I2S signal data register + 0x68 + 0x20 + + + SINGLE_DATA + The configured constant channel data to be sent out. + 0 + 32 + read-write + + + + + STATE + I2S TX status register + 0x6C + 0x20 + 0x00000001 + + + TX_IDLE + 1: i2s_tx is idle state. 0: i2s_tx is working. + 0 + 1 + read-only + + + + + DATE + Version control register + 0x80 + 0x20 + 0x02009070 + + + DATE + I2S version control register + 0 + 28 + read-write + + + + + + + INTERRUPT_CORE0 + Interrupt Controller (Core 0) + INTERRUPT_CORE0 + 0x600C2000 + + 0x0 + 0x1A4 + registers + + + WIFI_MAC + 0 + + + WIFI_NMI + 1 + + + WIFI_PWR + 2 + + + WIFI_BB + 3 + + + BT_MAC + 4 + + + BT_BB + 5 + + + BT_BB_NMI + 6 + + + RWBT + 7 + + + RWBLE + 8 + + + RWBT_NMI + 9 + + + RWBLE_NMI + 10 + + + SLC0 + 12 + + + SLC1 + 13 + + + SDIO_HOST + 30 + + + WDT + 47 + + + CACHE_IA + 56 + + + DCACHE_PRELOAD0 + 61 + + + ICACHE_PRELOAD0 + 62 + + + DCACHE_SYNC0 + 63 + + + ICACHE_SYNC0 + 64 + + + FROM_CPU_INTR0 + 79 + + + FROM_CPU_INTR1 + 80 + + + FROM_CPU_INTR2 + 81 + + + FROM_CPU_INTR3 + 82 + + + CORE0_IRAM0_PMS + 85 + + + CORE0_DRAM0_PMS + 86 + + + CORE0_PIF_PMS + 87 + + + CORE0_PIF_PMS_SIZE + 88 + + + CACHE_CORE0_ACS + 94 + + + + PRO_MAC_INTR_MAP + mac interrupt configuration register + 0x0 + 0x20 + 0x00000010 + + + MAC_INTR_MAP + this register used to map mac interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + MAC_NMI_MAP + mac_nmi interrupt configuration register + 0x4 + 0x20 + 0x00000010 + + + MAC_NMI_MAP + this register used to map_nmi interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + PWR_INTR_MAP + pwr interrupt configuration register + 0x8 + 0x20 + 0x00000010 + + + PWR_INTR_MAP + this register used to map pwr interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + BB_INT_MAP + bb interrupt configuration register + 0xC + 0x20 + 0x00000010 + + + BB_INT_MAP + this register used to map bb interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + BT_MAC_INT_MAP + bb_mac interrupt configuration register + 0x10 + 0x20 + 0x00000010 + + + BT_MAC_INT_MAP + this register used to map bb_mac interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + BT_BB_INT_MAP + bt_bb interrupt configuration register + 0x14 + 0x20 + 0x00000010 + + + BT_BB_INT_MAP + this register used to map bt_bb interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + BT_BB_NMI_MAP + bt_bb_nmi interrupt configuration register + 0x18 + 0x20 + 0x00000010 + + + BT_BB_NMI_MAP + this register used to map bb_bt_nmi interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + RWBT_IRQ_MAP + rwbt_irq interrupt configuration register + 0x1C + 0x20 + 0x00000010 + + + RWBT_IRQ_MAP + this register used to map rwbt_irq interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + RWBLE_IRQ_MAP + rwble_irq interrupt configuration register + 0x20 + 0x20 + 0x00000010 + + + RWBLE_IRQ_MAP + this register used to map rwble_irq interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + RWBT_NMI_MAP + rwbt_nmi interrupt configuration register + 0x24 + 0x20 + 0x00000010 + + + RWBT_NMI_MAP + this register used to map mac rwbt_nmi to one of core0's external interrupt + 0 + 5 + read-write + + + + + RWBLE_NMI_MAP + rwble_nmi interrupt configuration register + 0x28 + 0x20 + 0x00000010 + + + RWBLE_NMI_MAP + this register used to map rwble_nmi interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + I2C_MST_INT_MAP + i2c_mst interrupt configuration register + 0x2C + 0x20 + 0x00000010 + + + I2C_MST_INT_MAP + this register used to map i2c_mst interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SLC0_INTR_MAP + slc0 interrupt configuration register + 0x30 + 0x20 + 0x00000010 + + + SLC0_INTR_MAP + this register used to map slc0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SLC1_INTR_MAP + slc1 interrupt configuration register + 0x34 + 0x20 + 0x00000010 + + + SLC1_INTR_MAP + this register used to map slc1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + UHCI0_INTR_MAP + uhci0 interrupt configuration register + 0x38 + 0x20 + 0x00000010 + + + UHCI0_INTR_MAP + this register used to map uhci0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + UHCI1_INTR_MAP + uhci1 interrupt configuration register + 0x3C + 0x20 + 0x00000010 + + + UHCI1_INTR_MAP + this register used to map uhci1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_PRO_MAP + gpio_interrupt_pro interrupt configuration register + 0x40 + 0x20 + 0x00000010 + + + GPIO_INTERRUPT_PRO_MAP + this register used to map gpio_interrupt_pro interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_PRO_NMI_MAP + gpio_interrupt_pro_nmi interrupt configuration register + 0x44 + 0x20 + 0x00000010 + + + GPIO_INTERRUPT_PRO_NMI_MAP + this register used to map gpio_interrupt_pro_nmi interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_APP_MAP + gpio_interrupt_app interrupt configuration register + 0x48 + 0x20 + 0x00000010 + + + GPIO_INTERRUPT_APP_MAP + this register used to map gpio_interrupt_app interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_APP_NMI_MAP + gpio_interrupt_app_nmi interrupt configuration register + 0x4C + 0x20 + 0x00000010 + + + GPIO_INTERRUPT_APP_NMI_MAP + this register used to map gpio_interrupt_app_nmi interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SPI_INTR_1_MAP + spi_intr_1 interrupt configuration register + 0x50 + 0x20 + 0x00000010 + + + SPI_INTR_1_MAP + this register used to map spi_intr_1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SPI_INTR_2_MAP + spi_intr_2 interrupt configuration register + 0x54 + 0x20 + 0x00000010 + + + SPI_INTR_2_MAP + this register used to map spi_intr_2 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SPI_INTR_3_MAP + spi_intr_3 interrupt configuration register + 0x58 + 0x20 + 0x00000010 + + + SPI_INTR_3_MAP + this register used to map spi_intr_3 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SPI_INTR_4_MAP + spi_intr_4 interrupt configuration register + 0x5C + 0x20 + 0x00000010 + + + SPI_INTR_4_MAP + this register used to map spi_intr_4 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + LCD_CAM_INT_MAP + lcd_cam interrupt configuration register + 0x60 + 0x20 + 0x00000010 + + + LCD_CAM_INT_MAP + this register used to map lcd_cam interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + I2S0_INT_MAP + i2s0 interrupt configuration register + 0x64 + 0x20 + 0x00000010 + + + I2S0_INT_MAP + this register used to map i2s0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + I2S1_INT_MAP + i2s1 interrupt configuration register + 0x68 + 0x20 + 0x00000010 + + + I2S1_INT_MAP + this register used to map i2s1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + UART_INTR_MAP + uart interrupt configuration register + 0x6C + 0x20 + 0x00000010 + + + UART_INTR_MAP + this register used to map uart interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + UART1_INTR_MAP + uart1 interrupt configuration register + 0x70 + 0x20 + 0x00000010 + + + UART1_INTR_MAP + this register used to map uart1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + UART2_INTR_MAP + uart2 interrupt configuration register + 0x74 + 0x20 + 0x00000010 + + + UART2_INTR_MAP + this register used to map uart2 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SDIO_HOST_INTERRUPT_MAP + sdio_host interrupt configuration register + 0x78 + 0x20 + 0x00000010 + + + SDIO_HOST_INTERRUPT_MAP + this register used to map sdio_host interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + PWM0_INTR_MAP + pwm0 interrupt configuration register + 0x7C + 0x20 + 0x00000010 + + + PWM0_INTR_MAP + this register used to map pwm0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + PWM1_INTR_MAP + pwm1 interrupt configuration register + 0x80 + 0x20 + 0x00000010 + + + PWM1_INTR_MAP + this register used to map pwm1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + PWM2_INTR_MAP + pwm2 interrupt configuration register + 0x84 + 0x20 + 0x00000010 + + + PWM2_INTR_MAP + this register used to map pwm2 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + PWM3_INTR_MAP + pwm3 interrupt configuration register + 0x88 + 0x20 + 0x00000010 + + + PWM3_INTR_MAP + this register used to map pwm3 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + LEDC_INT_MAP + ledc interrupt configuration register + 0x8C + 0x20 + 0x00000010 + + + LEDC_INT_MAP + this register used to map ledc interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + EFUSE_INT_MAP + efuse interrupt configuration register + 0x90 + 0x20 + 0x00000010 + + + EFUSE_INT_MAP + this register used to map efuse interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CAN_INT_MAP + can interrupt configuration register + 0x94 + 0x20 + 0x00000010 + + + CAN_INT_MAP + this register used to map can interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + USB_INTR_MAP + usb interrupt configuration register + 0x98 + 0x20 + 0x00000010 + + + USB_INTR_MAP + this register used to map usb interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + RTC_CORE_INTR_MAP + rtc_core interrupt configuration register + 0x9C + 0x20 + 0x00000010 + + + RTC_CORE_INTR_MAP + this register used to map rtc_core interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + RMT_INTR_MAP + rmt interrupt configuration register + 0xA0 + 0x20 + 0x00000010 + + + RMT_INTR_MAP + this register used to map rmt interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + PCNT_INTR_MAP + pcnt interrupt configuration register + 0xA4 + 0x20 + 0x00000010 + + + PCNT_INTR_MAP + this register used to map pcnt interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + I2C_EXT0_INTR_MAP + i2c_ext0 interrupt configuration register + 0xA8 + 0x20 + 0x00000010 + + + I2C_EXT0_INTR_MAP + this register used to map i2c_ext0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + I2C_EXT1_INTR_MAP + i2c_ext1 interrupt configuration register + 0xAC + 0x20 + 0x00000010 + + + I2C_EXT1_INTR_MAP + this register used to map i2c_ext1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SPI2_DMA_INT_MAP + spi2_dma interrupt configuration register + 0xB0 + 0x20 + 0x00000010 + + + SPI2_DMA_INT_MAP + this register used to map spi2_dma interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SPI3_DMA_INT_MAP + spi3_dma interrupt configuration register + 0xB4 + 0x20 + 0x00000010 + + + SPI3_DMA_INT_MAP + this register used to map spi3_dma interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SPI4_DMA_INT_MAP + spi4_dma interrupt configuration register + 0xB8 + 0x20 + 0x00000010 + + + SPI4_DMA_INT_MAP + this register used to map spi4_dma interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + WDG_INT_MAP + wdg interrupt configuration register + 0xBC + 0x20 + 0x00000010 + + + WDG_INT_MAP + this register used to map wdg interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + TIMER_INT1_MAP + timer_int1 interrupt configuration register + 0xC0 + 0x20 + 0x00000010 + + + TIMER_INT1_MAP + this register used to map timer_int1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + TIMER_INT2_MAP + timer_int2 interrupt configuration register + 0xC4 + 0x20 + 0x00000010 + + + TIMER_INT2_MAP + this register used to map timer_int2 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + TG_T0_INT_MAP + tg_t0 interrupt configuration register + 0xC8 + 0x20 + 0x00000010 + + + TG_T0_INT_MAP + this register used to map tg_t0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + TG_T1_INT_MAP + tg_t1 interrupt configuration register + 0xCC + 0x20 + 0x00000010 + + + TG_T1_INT_MAP + this register used to map tg_t1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + TG_WDT_INT_MAP + tg_wdt interrupt configuration register + 0xD0 + 0x20 + 0x00000010 + + + TG_WDT_INT_MAP + this register used to map rg_wdt interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + TG1_T0_INT_MAP + tg1_t0 interrupt configuration register + 0xD4 + 0x20 + 0x00000010 + + + TG1_T0_INT_MAP + this register used to map tg1_t0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + TG1_T1_INT_MAP + tg1_t1 interrupt configuration register + 0xD8 + 0x20 + 0x00000010 + + + TG1_T1_INT_MAP + this register used to map tg1_t1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + TG1_WDT_INT_MAP + tg1_wdt interrupt configuration register + 0xDC + 0x20 + 0x00000010 + + + TG1_WDT_INT_MAP + this register used to map tg1_wdt interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CACHE_IA_INT_MAP + cache_ia interrupt configuration register + 0xE0 + 0x20 + 0x00000010 + + + CACHE_IA_INT_MAP + this register used to map cache_ia interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SYSTIMER_TARGET0_INT_MAP + systimer_target0 interrupt configuration register + 0xE4 + 0x20 + 0x00000010 + + + SYSTIMER_TARGET0_INT_MAP + this register used to map systimer_target0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SYSTIMER_TARGET1_INT_MAP + systimer_target1 interrupt configuration register + 0xE8 + 0x20 + 0x00000010 + + + SYSTIMER_TARGET1_INT_MAP + this register used to map systimer_target1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SYSTIMER_TARGET2_INT_MAP + systimer_target2 interrupt configuration register + 0xEC + 0x20 + 0x00000010 + + + SYSTIMER_TARGET2_INT_MAP + this register used to map systimer_target2 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SPI_MEM_REJECT_INTR_MAP + spi_mem_reject interrupt configuration register + 0xF0 + 0x20 + 0x00000010 + + + SPI_MEM_REJECT_INTR_MAP + this register used to map spi_mem_reject interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DCACHE_PRELOAD_INT_MAP + dcache_prelaod interrupt configuration register + 0xF4 + 0x20 + 0x00000010 + + + DCACHE_PRELOAD_INT_MAP + this register used to map dcache_prelaod interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + ICACHE_PRELOAD_INT_MAP + icache_preload interrupt configuration register + 0xF8 + 0x20 + 0x00000010 + + + ICACHE_PRELOAD_INT_MAP + this register used to map icache_preload interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DCACHE_SYNC_INT_MAP + dcache_sync interrupt configuration register + 0xFC + 0x20 + 0x00000010 + + + DCACHE_SYNC_INT_MAP + this register used to map dcache_sync interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + ICACHE_SYNC_INT_MAP + icache_sync interrupt configuration register + 0x100 + 0x20 + 0x00000010 + + + ICACHE_SYNC_INT_MAP + this register used to map icache_sync interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + APB_ADC_INT_MAP + apb_adc interrupt configuration register + 0x104 + 0x20 + 0x00000010 + + + APB_ADC_INT_MAP + this register used to map apb_adc interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH0_INT_MAP + dma_in_ch0 interrupt configuration register + 0x108 + 0x20 + 0x00000010 + + + DMA_IN_CH0_INT_MAP + this register used to map dma_in_ch0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH1_INT_MAP + dma_in_ch1 interrupt configuration register + 0x10C + 0x20 + 0x00000010 + + + DMA_IN_CH1_INT_MAP + this register used to map dma_in_ch1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH2_INT_MAP + dma_in_ch2 interrupt configuration register + 0x110 + 0x20 + 0x00000010 + + + DMA_IN_CH2_INT_MAP + this register used to map dma_in_ch2 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH3_INT_MAP + dma_in_ch3 interrupt configuration register + 0x114 + 0x20 + 0x00000010 + + + DMA_IN_CH3_INT_MAP + this register used to map dma_in_ch3 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH4_INT_MAP + dma_in_ch4 interrupt configuration register + 0x118 + 0x20 + 0x00000010 + + + DMA_IN_CH4_INT_MAP + this register used to map dma_in_ch4 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH0_INT_MAP + dma_out_ch0 interrupt configuration register + 0x11C + 0x20 + 0x00000010 + + + DMA_OUT_CH0_INT_MAP + this register used to map dma_out_ch0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH1_INT_MAP + dma_out_ch1 interrupt configuration register + 0x120 + 0x20 + 0x00000010 + + + DMA_OUT_CH1_INT_MAP + this register used to map dma_out_ch1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH2_INT_MAP + dma_out_ch2 interrupt configuration register + 0x124 + 0x20 + 0x00000010 + + + DMA_OUT_CH2_INT_MAP + this register used to map dma_out_ch2 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH3_INT_MAP + dma_out_ch3 interrupt configuration register + 0x128 + 0x20 + 0x00000010 + + + DMA_OUT_CH3_INT_MAP + this register used to map dma_out_ch3 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH4_INT_MAP + dma_out_ch4 interrupt configuration register + 0x12C + 0x20 + 0x00000010 + + + DMA_OUT_CH4_INT_MAP + this register used to map dma_out_ch4 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + RSA_INT_MAP + rsa interrupt configuration register + 0x130 + 0x20 + 0x00000010 + + + RSA_INT_MAP + this register used to map rsa interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + AES_INT_MAP + aes interrupt configuration register + 0x134 + 0x20 + 0x00000010 + + + AES_INT_MAP + this register used to map aes interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SHA_INT_MAP + sha interrupt configuration register + 0x138 + 0x20 + 0x00000010 + + + SHA_INT_MAP + this register used to map sha interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_0_MAP + cpu_intr_from_cpu_0 interrupt configuration register + 0x13C + 0x20 + 0x00000010 + + + CPU_INTR_FROM_CPU_0_MAP + this register used to map cpu_intr_from_cpu_0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_1_MAP + cpu_intr_from_cpu_1 interrupt configuration register + 0x140 + 0x20 + 0x00000010 + + + CPU_INTR_FROM_CPU_1_MAP + this register used to map cpu_intr_from_cpu_1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_2_MAP + cpu_intr_from_cpu_2 interrupt configuration register + 0x144 + 0x20 + 0x00000010 + + + CPU_INTR_FROM_CPU_2_MAP + this register used to map cpu_intr_from_cpu_2 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_3_MAP + cpu_intr_from_cpu_3 interrupt configuration register + 0x148 + 0x20 + 0x00000010 + + + CPU_INTR_FROM_CPU_3_MAP + this register used to map cpu_intr_from_cpu_3 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + ASSIST_DEBUG_INTR_MAP + assist_debug interrupt configuration register + 0x14C + 0x20 + 0x00000010 + + + ASSIST_DEBUG_INTR_MAP + this register used to map assist_debug interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP + dma_pms_monitor_violatile interrupt configuration register + 0x150 + 0x20 + 0x00000010 + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map dma_pms_monitor_violatile interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + core0_IRam0_pms_monitor_violatile interrupt configuration register + 0x154 + 0x20 + 0x00000010 + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core0_IRam0_pms_monitor_violatile interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + core0_DRam0_pms_monitor_violatile interrupt configuration register + 0x158 + 0x20 + 0x00000010 + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core0_DRam0_pms_monitor_violatile interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + core0_PIF_pms_monitor_violatile interrupt configuration register + 0x15C + 0x20 + 0x00000010 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core0_PIF_pms_monitor_violatile interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + core0_PIF_pms_monitor_violatile_size interrupt configuration register + 0x160 + 0x20 + 0x00000010 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + this register used to map core0_PIF_pms_monitor_violatile_size interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + core1_IRam0_pms_monitor_violatile interrupt configuration register + 0x164 + 0x20 + 0x00000010 + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core1_IRam0_pms_monitor_violatile interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + core1_DRam0_pms_monitor_violatile interrupt configuration register + 0x168 + 0x20 + 0x00000010 + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core1_DRam0_pms_monitor_violatile interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + core1_PIF_pms_monitor_violatile interrupt configuration register + 0x16C + 0x20 + 0x00000010 + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core1_PIF_pms_monitor_violatile interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + core1_PIF_pms_monitor_violatile_size interrupt configuration register + 0x170 + 0x20 + 0x00000010 + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + this register used to map core1_PIF_pms_monitor_violatile_size interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + BACKUP_PMS_VIOLATE_INTR_MAP + backup_pms_monitor_violatile interrupt configuration register + 0x174 + 0x20 + 0x00000010 + + + BACKUP_PMS_VIOLATE_INTR_MAP + this register used to map backup_pms_monitor_violatile interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CACHE_CORE0_ACS_INT_MAP + cache_core0_acs interrupt configuration register + 0x178 + 0x20 + 0x00000010 + + + CACHE_CORE0_ACS_INT_MAP + this register used to map cache_core0_acs interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CACHE_CORE1_ACS_INT_MAP + cache_core1_acs interrupt configuration register + 0x17C + 0x20 + 0x00000010 + + + CACHE_CORE1_ACS_INT_MAP + this register used to map cache_core1_acs interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + USB_DEVICE_INT_MAP + usb_device interrupt configuration register + 0x180 + 0x20 + 0x00000010 + + + USB_DEVICE_INT_MAP + this register used to map usb_device interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + PERI_BACKUP_INT_MAP + peri_backup interrupt configuration register + 0x184 + 0x20 + 0x00000010 + + + PERI_BACKUP_INT_MAP + this register used to map peri_backup interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_EXTMEM_REJECT_INT_MAP + dma_extmem_reject interrupt configuration register + 0x188 + 0x20 + 0x00000010 + + + DMA_EXTMEM_REJECT_INT_MAP + this register used to map dma_extmem_reject interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + PRO_INTR_STATUS_0 + interrupt status register + 0x18C + 0x20 + + + INTR_STATUS_0 + this register store the status of the first 32 interrupt source + 0 + 32 + read-only + + + + + PRO_INTR_STATUS_1 + interrupt status register + 0x190 + 0x20 + + + INTR_STATUS_1 + this register store the status of the first 32 interrupt source + 0 + 32 + read-only + + + + + PRO_INTR_STATUS_2 + interrupt status register + 0x194 + 0x20 + + + INTR_STATUS_2 + this register store the status of the first 32 interrupt source + 0 + 32 + read-only + + + + + PRO_INTR_STATUS_3 + interrupt status register + 0x198 + 0x20 + + + INTR_STATUS_3 + this register store the status of the first 32 interrupt source + 0 + 32 + read-only + + + + + CLOCK_GATE + clock gate register + 0x19C + 0x20 + 0x00000001 + + + REG_CLK_EN + this register uesd to control clock-gating interupt martrix + 0 + 1 + read-write + + + + + DATE + version register + 0x7FC + 0x20 + 0x02012300 + + + INTERRUPT_REG_DATE + version register + 0 + 28 + read-write + + + + + + + INTERRUPT_CORE1 + Interrupt Controller (Core 1) + INTERRUPT_CORE1 + 0x600C2800 + + 0x0 + 0x1A4 + registers + + + CORE1_IRAM0_PMS + 89 + + + CORE1_DRAM0_PMS + 90 + + + CORE1_PIF_PMS + 91 + + + CORE1_PIF_PMS_SIZE + 92 + + + CACHE_CORE1_ACS + 95 + + + + APP_MAC_INTR_MAP + mac interrupt configuration register + 0x800 + 0x20 + 0x00000010 + + + MAC_INTR_MAP + this register used to map mac interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + MAC_NMI_MAP + mac_nmi interrupt configuration register + 0x804 + 0x20 + 0x00000010 + + + MAC_NMI_MAP + this register used to map_nmi interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + PWR_INTR_MAP + pwr interrupt configuration register + 0x808 + 0x20 + 0x00000010 + + + PWR_INTR_MAP + this register used to map pwr interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + BB_INT_MAP + bb interrupt configuration register + 0x80C + 0x20 + 0x00000010 + + + BB_INT_MAP + this register used to map bb interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + BT_MAC_INT_MAP + bb_mac interrupt configuration register + 0x810 + 0x20 + 0x00000010 + + + BT_MAC_INT_MAP + this register used to map bb_mac interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + BT_BB_INT_MAP + bt_bb interrupt configuration register + 0x814 + 0x20 + 0x00000010 + + + BT_BB_INT_MAP + this register used to map bt_bb interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + BT_BB_NMI_MAP + bt_bb_nmi interrupt configuration register + 0x818 + 0x20 + 0x00000010 + + + BT_BB_NMI_MAP + this register used to map bb_bt_nmi interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + RWBT_IRQ_MAP + rwbt_irq interrupt configuration register + 0x81C + 0x20 + 0x00000010 + + + RWBT_IRQ_MAP + this register used to map rwbt_irq interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + RWBLE_IRQ_MAP + rwble_irq interrupt configuration register + 0x820 + 0x20 + 0x00000010 + + + RWBLE_IRQ_MAP + this register used to map rwble_irq interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + RWBT_NMI_MAP + rwbt_nmi interrupt configuration register + 0x824 + 0x20 + 0x00000010 + + + RWBT_NMI_MAP + this register used to map rwbt_nmi interupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + RWBLE_NMI_MAP + rwble_nmi interrupt configuration register + 0x828 + 0x20 + 0x00000010 + + + RWBLE_NMI_MAP + this register used to map rwble_nmi interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + I2C_MST_INT_MAP + i2c_mst interrupt configuration register + 0x82C + 0x20 + 0x00000010 + + + I2C_MST_INT_MAP + this register used to map i2c_mst interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SLC0_INTR_MAP + slc0 interrupt configuration register + 0x830 + 0x20 + 0x00000010 + + + SLC0_INTR_MAP + this register used to map slc0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SLC1_INTR_MAP + slc1 interrupt configuration register + 0x834 + 0x20 + 0x00000010 + + + SLC1_INTR_MAP + this register used to map slc1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + UHCI0_INTR_MAP + uhci0 interrupt configuration register + 0x838 + 0x20 + 0x00000010 + + + UHCI0_INTR_MAP + this register used to map uhci0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + UHCI1_INTR_MAP + uhci1 interrupt configuration register + 0x83C + 0x20 + 0x00000010 + + + UHCI1_INTR_MAP + this register used to map uhci1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_PRO_MAP + gpio_interrupt_pro interrupt configuration register + 0x840 + 0x20 + 0x00000010 + + + GPIO_INTERRUPT_PRO_MAP + this register used to map gpio_interrupt_pro interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_PRO_NMI_MAP + gpio_interrupt_pro_nmi interrupt configuration register + 0x844 + 0x20 + 0x00000010 + + + GPIO_INTERRUPT_PRO_NMI_MAP + this register used to map gpio_interrupt_pro_nmi interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_APP_MAP + gpio_interrupt_app interrupt configuration register + 0x848 + 0x20 + 0x00000010 + + + GPIO_INTERRUPT_APP_MAP + this register used to map gpio_interrupt_app interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_APP_NMI_MAP + gpio_interrupt_app_nmi interrupt configuration register + 0x84C + 0x20 + 0x00000010 + + + GPIO_INTERRUPT_APP_NMI_MAP + this register used to map gpio_interrupt_app_nmi interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SPI_INTR_1_MAP + spi_intr_1 interrupt configuration register + 0x850 + 0x20 + 0x00000010 + + + SPI_INTR_1_MAP + this register used to map spi_intr_1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SPI_INTR_2_MAP + spi_intr_2 interrupt configuration register + 0x854 + 0x20 + 0x00000010 + + + SPI_INTR_2_MAP + this register used to map spi_intr_2 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SPI_INTR_3_MAP + spi_intr_3 interrupt configuration register + 0x858 + 0x20 + 0x00000010 + + + SPI_INTR_3_MAP + this register used to map spi_intr_3 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SPI_INTR_4_MAP + spi_intr_4 interrupt configuration register + 0x85C + 0x20 + 0x00000010 + + + SPI_INTR_4_MAP + this register used to map spi_intr_4 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + LCD_CAM_INT_MAP + lcd_cam interrupt configuration register + 0x860 + 0x20 + 0x00000010 + + + LCD_CAM_INT_MAP + this register used to map lcd_cam interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + I2S0_INT_MAP + i2s0 interrupt configuration register + 0x864 + 0x20 + 0x00000010 + + + I2S0_INT_MAP + this register used to map i2s0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + I2S1_INT_MAP + i2s1 interrupt configuration register + 0x868 + 0x20 + 0x00000010 + + + I2S1_INT_MAP + this register used to map i2s1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + UART_INTR_MAP + uart interrupt configuration register + 0x86C + 0x20 + 0x00000010 + + + UART_INTR_MAP + this register used to map uart interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + UART1_INTR_MAP + uart1 interrupt configuration register + 0x870 + 0x20 + 0x00000010 + + + UART1_INTR_MAP + this register used to map uart1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + UART2_INTR_MAP + uart2 interrupt configuration register + 0x874 + 0x20 + 0x00000010 + + + UART2_INTR_MAP + this register used to map uart2 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SDIO_HOST_INTERRUPT_MAP + sdio_host interrupt configuration register + 0x878 + 0x20 + 0x00000010 + + + SDIO_HOST_INTERRUPT_MAP + this register used to map sdio_host interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + PWM0_INTR_MAP + pwm0 interrupt configuration register + 0x87C + 0x20 + 0x00000010 + + + PWM0_INTR_MAP + this register used to map pwm0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + PWM1_INTR_MAP + pwm1 interrupt configuration register + 0x880 + 0x20 + 0x00000010 + + + PWM1_INTR_MAP + this register used to map pwm1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + PWM2_INTR_MAP + pwm2 interrupt configuration register + 0x884 + 0x20 + 0x00000010 + + + PWM2_INTR_MAP + this register used to map pwm2 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + PWM3_INTR_MAP + pwm3 interrupt configuration register + 0x888 + 0x20 + 0x00000010 + + + PWM3_INTR_MAP + this register used to map pwm3 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + LEDC_INT_MAP + ledc interrupt configuration register + 0x88C + 0x20 + 0x00000010 + + + LEDC_INT_MAP + this register used to map ledc interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + EFUSE_INT_MAP + efuse interrupt configuration register + 0x890 + 0x20 + 0x00000010 + + + EFUSE_INT_MAP + this register used to map efuse interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CAN_INT_MAP + can interrupt configuration register + 0x894 + 0x20 + 0x00000010 + + + CAN_INT_MAP + this register used to map can interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + USB_INTR_MAP + usb interrupt configuration register + 0x898 + 0x20 + 0x00000010 + + + USB_INTR_MAP + this register used to map usb interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + RTC_CORE_INTR_MAP + rtc_core interrupt configuration register + 0x89C + 0x20 + 0x00000010 + + + RTC_CORE_INTR_MAP + this register used to map rtc_core interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + RMT_INTR_MAP + rmt interrupt configuration register + 0x8A0 + 0x20 + 0x00000010 + + + RMT_INTR_MAP + this register used to map rmt interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + PCNT_INTR_MAP + pcnt interrupt configuration register + 0x8A4 + 0x20 + 0x00000010 + + + PCNT_INTR_MAP + this register used to map pcnt interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + I2C_EXT0_INTR_MAP + i2c_ext0 interrupt configuration register + 0x8A8 + 0x20 + 0x00000010 + + + I2C_EXT0_INTR_MAP + this register used to map i2c_ext0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + I2C_EXT1_INTR_MAP + i2c_ext1 interrupt configuration register + 0x8AC + 0x20 + 0x00000010 + + + I2C_EXT1_INTR_MAP + this register used to map i2c_ext1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SPI2_DMA_INT_MAP + spi2_dma interrupt configuration register + 0x8B0 + 0x20 + 0x00000010 + + + SPI2_DMA_INT_MAP + this register used to map spi2_dma interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SPI3_DMA_INT_MAP + spi3_dma interrupt configuration register + 0x8B4 + 0x20 + 0x00000010 + + + SPI3_DMA_INT_MAP + this register used to map spi3_dma interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SPI4_DMA_INT_MAP + spi4_dma interrupt configuration register + 0x8B8 + 0x20 + 0x00000010 + + + SPI4_DMA_INT_MAP + this register used to map spi4_dma interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + WDG_INT_MAP + wdg interrupt configuration register + 0x8BC + 0x20 + 0x00000010 + + + WDG_INT_MAP + this register used to map wdg interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + TIMER_INT1_MAP + timer_int1 interrupt configuration register + 0x8C0 + 0x20 + 0x00000010 + + + TIMER_INT1_MAP + this register used to map timer_int1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + TIMER_INT2_MAP + timer_int2 interrupt configuration register + 0x8C4 + 0x20 + 0x00000010 + + + TIMER_INT2_MAP + this register used to map timer_int2 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + TG_T0_INT_MAP + tg_t0 interrupt configuration register + 0x8C8 + 0x20 + 0x00000010 + + + TG_T0_INT_MAP + this register used to map tg_t0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + TG_T1_INT_MAP + tg_t1 interrupt configuration register + 0x8CC + 0x20 + 0x00000010 + + + TG_T1_INT_MAP + this register used to map tg_t1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + TG_WDT_INT_MAP + tg_wdt interrupt configuration register + 0x8D0 + 0x20 + 0x00000010 + + + TG_WDT_INT_MAP + this register used to map rg_wdt interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + TG1_T0_INT_MAP + tg1_t0 interrupt configuration register + 0x8D4 + 0x20 + 0x00000010 + + + TG1_T0_INT_MAP + this register used to map tg1_t0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + TG1_T1_INT_MAP + tg1_t1 interrupt configuration register + 0x8D8 + 0x20 + 0x00000010 + + + TG1_T1_INT_MAP + this register used to map tg1_t1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + TG1_WDT_INT_MAP + tg1_wdt interrupt configuration register + 0x8DC + 0x20 + 0x00000010 + + + TG1_WDT_INT_MAP + this register used to map tg1_wdt interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CACHE_IA_INT_MAP + cache_ia interrupt configuration register + 0x8E0 + 0x20 + 0x00000010 + + + CACHE_IA_INT_MAP + this register used to map cache_ia interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SYSTIMER_TARGET0_INT_MAP + systimer_target0 interrupt configuration register + 0x8E4 + 0x20 + 0x00000010 + + + SYSTIMER_TARGET0_INT_MAP + this register used to map systimer_target0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SYSTIMER_TARGET1_INT_MAP + systimer_target1 interrupt configuration register + 0x8E8 + 0x20 + 0x00000010 + + + SYSTIMER_TARGET1_INT_MAP + this register used to map systimer_target1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SYSTIMER_TARGET2_INT_MAP + systimer_target2 interrupt configuration register + 0x8EC + 0x20 + 0x00000010 + + + SYSTIMER_TARGET2_INT_MAP + this register used to map systimer_target2 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SPI_MEM_REJECT_INTR_MAP + spi_mem_reject interrupt configuration register + 0x8F0 + 0x20 + 0x00000010 + + + SPI_MEM_REJECT_INTR_MAP + this register used to map spi_mem_reject interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DCACHE_PRELOAD_INT_MAP + dcache_prelaod interrupt configuration register + 0x8F4 + 0x20 + 0x00000010 + + + DCACHE_PRELOAD_INT_MAP + this register used to map dcache_prelaod interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + ICACHE_PRELOAD_INT_MAP + icache_preload interrupt configuration register + 0x8F8 + 0x20 + 0x00000010 + + + ICACHE_PRELOAD_INT_MAP + this register used to map icache_preload interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DCACHE_SYNC_INT_MAP + dcache_sync interrupt configuration register + 0x8FC + 0x20 + 0x00000010 + + + DCACHE_SYNC_INT_MAP + this register used to map dcache_sync interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + ICACHE_SYNC_INT_MAP + icache_sync interrupt configuration register + 0x900 + 0x20 + 0x00000010 + + + ICACHE_SYNC_INT_MAP + this register used to map icache_sync interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + APB_ADC_INT_MAP + apb_adc interrupt configuration register + 0x904 + 0x20 + 0x00000010 + + + APB_ADC_INT_MAP + this register used to map apb_adc interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH0_INT_MAP + dma_in_ch0 interrupt configuration register + 0x908 + 0x20 + 0x00000010 + + + DMA_IN_CH0_INT_MAP + this register used to map dma_in_ch0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH1_INT_MAP + dma_in_ch1 interrupt configuration register + 0x90C + 0x20 + 0x00000010 + + + DMA_IN_CH1_INT_MAP + this register used to map dma_in_ch1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH2_INT_MAP + dma_in_ch2 interrupt configuration register + 0x910 + 0x20 + 0x00000010 + + + DMA_IN_CH2_INT_MAP + this register used to map dma_in_ch2 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH3_INT_MAP + dma_in_ch3 interrupt configuration register + 0x914 + 0x20 + 0x00000010 + + + DMA_IN_CH3_INT_MAP + this register used to map dma_in_ch3 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH4_INT_MAP + dma_in_ch4 interrupt configuration register + 0x918 + 0x20 + 0x00000010 + + + DMA_IN_CH4_INT_MAP + this register used to map dma_in_ch4 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH0_INT_MAP + dma_out_ch0 interrupt configuration register + 0x91C + 0x20 + 0x00000010 + + + DMA_OUT_CH0_INT_MAP + this register used to map dma_out_ch0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH1_INT_MAP + dma_out_ch1 interrupt configuration register + 0x920 + 0x20 + 0x00000010 + + + DMA_OUT_CH1_INT_MAP + this register used to map dma_out_ch1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH2_INT_MAP + dma_out_ch2 interrupt configuration register + 0x924 + 0x20 + 0x00000010 + + + DMA_OUT_CH2_INT_MAP + this register used to map dma_out_ch2 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH3_INT_MAP + dma_out_ch3 interrupt configuration register + 0x928 + 0x20 + 0x00000010 + + + DMA_OUT_CH3_INT_MAP + this register used to map dma_out_ch3 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH4_INT_MAP + dma_out_ch4 interrupt configuration register + 0x92C + 0x20 + 0x00000010 + + + DMA_OUT_CH4_INT_MAP + this register used to map dma_out_ch4 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + RSA_INT_MAP + rsa interrupt configuration register + 0x930 + 0x20 + 0x00000010 + + + RSA_INT_MAP + this register used to map rsa interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + AES_INT_MAP + aes interrupt configuration register + 0x934 + 0x20 + 0x00000010 + + + AES_INT_MAP + this register used to map aes interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SHA_INT_MAP + sha interrupt configuration register + 0x938 + 0x20 + 0x00000010 + + + SHA_INT_MAP + this register used to map sha interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_0_MAP + cpu_intr_from_cpu_0 interrupt configuration register + 0x93C + 0x20 + 0x00000010 + + + CPU_INTR_FROM_CPU_0_MAP + this register used to map cpu_intr_from_cpu_0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_1_MAP + cpu_intr_from_cpu_1 interrupt configuration register + 0x940 + 0x20 + 0x00000010 + + + CPU_INTR_FROM_CPU_1_MAP + this register used to map cpu_intr_from_cpu_1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_2_MAP + cpu_intr_from_cpu_2 interrupt configuration register + 0x944 + 0x20 + 0x00000010 + + + CPU_INTR_FROM_CPU_2_MAP + this register used to map cpu_intr_from_cpu_2 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_3_MAP + cpu_intr_from_cpu_3 interrupt configuration register + 0x948 + 0x20 + 0x00000010 + + + CPU_INTR_FROM_CPU_3_MAP + this register used to map cpu_intr_from_cpu_3 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + ASSIST_DEBUG_INTR_MAP + assist_debug interrupt configuration register + 0x94C + 0x20 + 0x00000010 + + + ASSIST_DEBUG_INTR_MAP + this register used to map assist_debug interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP + dma_pms_monitor_violatile interrupt configuration register + 0x950 + 0x20 + 0x00000010 + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map dma_pms_monitor_violatile interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + core0_IRam0_pms_monitor_violatile interrupt configuration register + 0x954 + 0x20 + 0x00000010 + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core0_IRam0_pms_monitor_violatile interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + core0_DRam0_pms_monitor_violatile interrupt configuration register + 0x958 + 0x20 + 0x00000010 + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core0_DRam0_pms_monitor_violatile interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + core0_PIF_pms_monitor_violatile interrupt configuration register + 0x95C + 0x20 + 0x00000010 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core0_PIF_pms_monitor_violatile interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + core0_PIF_pms_monitor_violatile_size interrupt configuration register + 0x960 + 0x20 + 0x00000010 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + this register used to map core0_PIF_pms_monitor_violatile_size interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + core1_IRam0_pms_monitor_violatile interrupt configuration register + 0x964 + 0x20 + 0x00000010 + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core1_IRam0_pms_monitor_violatile interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + core1_DRam0_pms_monitor_violatile interrupt configuration register + 0x968 + 0x20 + 0x00000010 + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core1_DRam0_pms_monitor_violatile interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + core1_PIF_pms_monitor_violatile interrupt configuration register + 0x96C + 0x20 + 0x00000010 + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core1_PIF_pms_monitor_violatile interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + core1_PIF_pms_monitor_violatile_size interrupt configuration register + 0x970 + 0x20 + 0x00000010 + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + this register used to map core1_PIF_pms_monitor_violatile_size interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + BACKUP_PMS_VIOLATE_INTR_MAP + backup_pms_monitor_violatile interrupt configuration register + 0x974 + 0x20 + 0x00000010 + + + BACKUP_PMS_VIOLATE_INTR_MAP + this register used to map backup_pms_monitor_violatile interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CACHE_CORE0_ACS_INT_MAP + cache_core0_acs interrupt configuration register + 0x978 + 0x20 + 0x00000010 + + + CACHE_CORE0_ACS_INT_MAP + this register used to map cache_core0_acs interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CACHE_CORE1_ACS_INT_MAP + cache_core1_acs interrupt configuration register + 0x97C + 0x20 + 0x00000010 + + + CACHE_CORE1_ACS_INT_MAP + this register used to map cache_core1_acs interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + USB_DEVICE_INT_MAP + usb_device interrupt configuration register + 0x980 + 0x20 + 0x00000010 + + + USB_DEVICE_INT_MAP + this register used to map usb_device interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + PERI_BACKUP_INT_MAP + peri_backup interrupt configuration register + 0x984 + 0x20 + 0x00000010 + + + PERI_BACKUP_INT_MAP + this register used to map peri_backup interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_EXTMEM_REJECT_INT_MAP + dma_extmem_reject interrupt configuration register + 0x988 + 0x20 + 0x00000010 + + + DMA_EXTMEM_REJECT_INT_MAP + this register used to map dma_extmem_reject interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + APP_INTR_STATUS_0 + interrupt status register + 0x98C + 0x20 + + + INTR_STATUS_0 + this register store the status of the first 32 interrupt source + 0 + 32 + read-only + + + + + APP_INTR_STATUS_1 + interrupt status register + 0x990 + 0x20 + + + INTR_STATUS_1 + this register store the status of the first 32 interrupt source + 0 + 32 + read-only + + + + + APP_INTR_STATUS_2 + interrupt status register + 0x994 + 0x20 + + + INTR_STATUS_2 + this register store the status of the first 32 interrupt source + 0 + 32 + read-only + + + + + APP_INTR_STATUS_3 + interrupt status register + 0x998 + 0x20 + + + INTR_STATUS_3 + this register store the status of the first 32 interrupt source + 0 + 32 + read-only + + + + + CLOCK_GATE + clock gate register + 0x99C + 0x20 + 0x00000001 + + + REG_CLK_EN + this register uesd to control clock-gating interupt martrix + 0 + 1 + read-write + + + + + DATE + version register + 0xFFC + 0x20 + 0x02012300 + + + INTERRUPT_DATE + version register + 0 + 28 + read-write + + + + + + + IO_MUX + Input/Output Multiplexer + IO_MUX + 0x60009000 + + 0x0 + 0xCC + registers + + + + PIN_CTRL + Clock Output Configuration Register + 0x0 + 0x20 + 0x000007FF + + + CLK_OUT1 + If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals. + 0 + 4 + read-write + + + CLK_OUT2 + If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals. + 4 + 4 + read-write + + + CLK_OUT3 + If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals. + 8 + 4 + read-write + + + + + 49 + 0x4 + GPIO%s + IO MUX Configure Register for pad GPIO0 + 0x4 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function 2; etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled. + 15 + 1 + read-write + + + + + DATE + IO MUX Version Control Register + 0xFC + 0x20 + 0x01907160 + + + REG_DATE + Version control register + 0 + 28 + read-write + + + + + + + LCD_CAM + LCD_CAM Peripheral + LCD_CAM + 0x60041000 + + 0x0 + 0x48 + registers + + + LCD_CAM + 24 + + + + LCD_CLOCK + LCD clock register + 0x0 + 0x20 + 0x00000843 + + + LCD_CLKCNT_N + f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0. + 0 + 6 + read-write + + + LCD_CLK_EQU_SYSCLK + 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1). + 6 + 1 + read-write + + + LCD_CK_IDLE_EDGE + 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle. + 7 + 1 + read-write + + + LCD_CK_OUT_EDGE + 1: LCD_PCLK high in first half clock cycle. 0: LCD_PCLK low in first half clock cycle. + 8 + 1 + read-write + + + LCD_CLKM_DIV_NUM + Integral LCD clock divider value + 9 + 8 + read-write + + + LCD_CLKM_DIV_B + Fractional clock divider numerator value + 17 + 6 + read-write + + + LCD_CLKM_DIV_A + Fractional clock divider denominator value + 23 + 6 + read-write + + + LCD_CLK_SEL + Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. + 29 + 2 + read-write + + + CLK_EN + Set this bit to enable clk gate + 31 + 1 + read-write + + + + + CAM_CTRL + Camera configuration register + 0x4 + 0x20 + 0x00000800 + + + CAM_STOP_EN + Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop. + 0 + 1 + read-write + + + CAM_VSYNC_FILTER_THRES + Filter threshold value for CAM_VSYNC signal. + 1 + 3 + read-write + + + CAM_UPDATE + 1: Update Camera registers, will be cleared by hardware. 0 : Not care. + 4 + 1 + read-write + + + CAM_BYTE_ORDER + 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. + 5 + 1 + read-write + + + CAM_BIT_ORDER + 1: invert data byte order, only valid in 2 byte mode. 0: Not change. + 6 + 1 + read-write + + + CAM_LINE_INT_EN + 1: Enable to generate CAM_HS_INT. 0: Disable. + 7 + 1 + read-write + + + CAM_VS_EOF_EN + 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_data_cyclelen. + 8 + 1 + read-write + + + CAM_CLKM_DIV_NUM + Integral Camera clock divider value + 9 + 8 + read-write + + + CAM_CLKM_DIV_B + Fractional clock divider numerator value + 17 + 6 + read-write + + + CAM_CLKM_DIV_A + Fractional clock divider denominator value + 23 + 6 + read-write + + + CAM_CLK_SEL + Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. + 29 + 2 + read-write + + + + + CAM_CTRL1 + Camera configuration register + 0x8 + 0x20 + + + CAM_REC_DATA_BYTELEN + Camera receive data byte length minus 1 to set DMA in_suc_eof_int. + 0 + 16 + read-write + + + CAM_LINE_INT_NUM + The line number minus 1 to generate cam_hs_int. + 16 + 6 + read-write + + + CAM_CLK_INV + 1: Invert the input signal CAM_PCLK. 0: Not invert. + 22 + 1 + read-write + + + CAM_VSYNC_FILTER_EN + 1: Enable CAM_VSYNC filter function. 0: bypass. + 23 + 1 + read-write + + + CAM_2BYTE_EN + 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8. + 24 + 1 + read-write + + + CAM_DE_INV + CAM_DE invert enable signal, valid in high level. + 25 + 1 + read-write + + + CAM_HSYNC_INV + CAM_HSYNC invert enable signal, valid in high level. + 26 + 1 + read-write + + + CAM_VSYNC_INV + CAM_VSYNC invert enable signal, valid in high level. + 27 + 1 + read-write + + + CAM_VH_DE_MODE_EN + 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC is 1. 0: Input control signals are CAM_DE and CAM_VSYNC. CAM_HSYNC and CAM_DE are all 1 the the same time. + 28 + 1 + read-write + + + CAM_START + Camera module start signal. + 29 + 1 + read-write + + + CAM_RESET + Camera module reset signal. + 30 + 1 + write-only + + + CAM_AFIFO_RESET + Camera AFIFO reset signal. + 31 + 1 + write-only + + + + + CAM_RGB_YUV + Camera configuration register + 0xC + 0x20 + 0x00C00000 + + + CAM_CONV_8BITS_DATA_INV + 1:invert every two 8bits input data. 2. disabled. + 21 + 1 + read-write + + + CAM_CONV_YUV2YUV_MODE + 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1. + 22 + 2 + read-write + + + CAM_CONV_YUV_MODE + 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in + 24 + 2 + read-write + + + CAM_CONV_PROTOCOL_MODE + 0:BT601. 1:BT709. + 26 + 1 + read-write + + + CAM_CONV_DATA_OUT_MODE + LIMIT or FULL mode of Data out. 0: limit. 1: full + 27 + 1 + read-write + + + CAM_CONV_DATA_IN_MODE + LIMIT or FULL mode of Data in. 0: limit. 1: full + 28 + 1 + read-write + + + CAM_CONV_MODE_8BITS_ON + 0: 16bits mode. 1: 8bits mode. + 29 + 1 + read-write + + + CAM_CONV_TRANS_MODE + 0: YUV to RGB. 1: RGB to YUV. + 30 + 1 + read-write + + + CAM_CONV_BYPASS + 0: Bypass converter. 1: Enable converter. + 31 + 1 + read-write + + + + + LCD_RGB_YUV + LCD configuration register + 0x10 + 0x20 + 0x00C00000 + + + LCD_CONV_8BITS_DATA_INV + 1:invert every two 8bits input data. 2. disabled. + 20 + 1 + read-write + + + LCD_CONV_TXTORX + 0: txtorx mode off. 1: txtorx mode on. + 21 + 1 + read-write + + + LCD_CONV_YUV2YUV_MODE + 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1. + 22 + 2 + read-write + + + LCD_CONV_YUV_MODE + 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in + 24 + 2 + read-write + + + LCD_CONV_PROTOCOL_MODE + 0:BT601. 1:BT709. + 26 + 1 + read-write + + + LCD_CONV_DATA_OUT_MODE + LIMIT or FULL mode of Data out. 0: limit. 1: full + 27 + 1 + read-write + + + LCD_CONV_DATA_IN_MODE + LIMIT or FULL mode of Data in. 0: limit. 1: full + 28 + 1 + read-write + + + LCD_CONV_MODE_8BITS_ON + 0: 16bits mode. 1: 8bits mode. + 29 + 1 + read-write + + + LCD_CONV_TRANS_MODE + 0: YUV to RGB. 1: RGB to YUV. + 30 + 1 + read-write + + + LCD_CONV_BYPASS + 0: Bypass converter. 1: Enable converter. + 31 + 1 + read-write + + + + + LCD_USER + LCD configuration register + 0x14 + 0x20 + 0x00000001 + + + LCD_DOUT_CYCLELEN + The output data cycles minus 1 of LCD module. + 0 + 13 + read-write + + + LCD_ALWAYS_OUT_EN + LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or reg_lcd_reset is set. + 13 + 1 + read-write + + + LCD_8BITS_ORDER + 1: invert every two data byte, valid in 1 byte mode. 0: Not change. + 19 + 1 + read-write + + + LCD_UPDATE + 1: Update LCD registers, will be cleared by hardware. 0 : Not care. + 20 + 1 + read-write + + + LCD_BIT_ORDER + 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. + 21 + 1 + read-write + + + LCD_BYTE_ORDER + 1: invert data byte order, only valid in 2 byte mode. 0: Not change. + 22 + 1 + read-write + + + LCD_2BYTE_EN + 1: The bit number of output LCD data is 9~16. 0: The bit number of output LCD data is 0~8. + 23 + 1 + read-write + + + LCD_DOUT + 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable. + 24 + 1 + read-write + + + LCD_DUMMY + 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable. + 25 + 1 + read-write + + + LCD_CMD + 1: Be able to send command in LCD sequence when LCD starts. 0: Disable. + 26 + 1 + read-write + + + LCD_START + LCD start sending data enable signal, valid in high level. + 27 + 1 + read-write + + + LCD_RESET + The value of command. + 28 + 1 + write-only + + + LCD_DUMMY_CYCLELEN + The dummy cycle length minus 1. + 29 + 2 + read-write + + + LCD_CMD_2_CYCLE_EN + The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. + 31 + 1 + read-write + + + + + LCD_MISC + LCD configuration register + 0x18 + 0x20 + 0x000000D6 + + + LCD_AFIFO_THRESHOLD_NUM + The awfull threshold number of lcd_afifo. + 1 + 5 + read-write + + + LCD_VFK_CYCLELEN + The setup cycle length minus 1 in LCD non-RGB mode. + 6 + 6 + read-write + + + LCD_VBK_CYCLELEN + The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold time cycle length in LCD non-RGB mode. + 12 + 13 + read-write + + + LCD_NEXT_FRAME_EN + 1: Send the next frame data when the current frame is sent out. 0: LCD stops when the current frame is sent out. + 25 + 1 + read-write + + + LCD_BK_EN + 1: Enable blank region when LCD sends data out. 0: No blank region. + 26 + 1 + read-write + + + LCD_AFIFO_RESET + LCD AFIFO reset signal. + 27 + 1 + write-only + + + LCD_CD_DATA_SET + 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state. 0: LCD_CD = reg_cd_idle_edge. + 28 + 1 + read-write + + + LCD_CD_DUMMY_SET + 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state. 0: LCD_CD = reg_cd_idle_edge. + 29 + 1 + read-write + + + LCD_CD_CMD_SET + 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state. 0: LCD_CD = reg_cd_idle_edge. + 30 + 1 + read-write + + + LCD_CD_IDLE_EDGE + The default value of LCD_CD. + 31 + 1 + read-write + + + + + LCD_CTRL + LCD configuration register + 0x1C + 0x20 + + + LCD_HB_FRONT + It is the horizontal blank front porch of a frame. + 0 + 11 + read-write + + + LCD_VA_HEIGHT + It is the vertical active height of a frame. + 11 + 10 + read-write + + + LCD_VT_HEIGHT + It is the vertical total height of a frame. + 21 + 10 + read-write + + + LCD_RGB_MODE_EN + 1: Enable reg mode input vsync, hsync, de. 0: Disable. + 31 + 1 + read-write + + + + + LCD_CTRL1 + LCD configuration register + 0x20 + 0x20 + + + LCD_VB_FRONT + It is the vertical blank front porch of a frame. + 0 + 8 + read-write + + + LCD_HA_WIDTH + It is the horizontal active width of a frame. + 8 + 12 + read-write + + + LCD_HT_WIDTH + It is the horizontal total width of a frame. + 20 + 12 + read-write + + + + + LCD_CTRL2 + LCD configuration register + 0x24 + 0x20 + 0x00010001 + + + LCD_VSYNC_WIDTH + It is the position of LCD_VSYNC active pulse in a line. + 0 + 7 + read-write + + + LCD_VSYNC_IDLE_POL + It is the idle value of LCD_VSYNC. + 7 + 1 + read-write + + + LCD_DE_IDLE_POL + It is the idle value of LCD_DE. + 8 + 1 + read-write + + + LCD_HS_BLANK_EN + 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode. + 9 + 1 + read-write + + + LCD_HSYNC_WIDTH + It is the position of LCD_HSYNC active pulse in a line. + 16 + 7 + read-write + + + LCD_HSYNC_IDLE_POL + It is the idle value of LCD_HSYNC. + 23 + 1 + read-write + + + LCD_HSYNC_POSITION + It is the position of LCD_HSYNC active pulse in a line. + 24 + 8 + read-write + + + + + LCD_CMD_VAL + LCD configuration register + 0x28 + 0x20 + + + LCD_CMD_VALUE + The LCD write command value. + 0 + 32 + read-write + + + + + LCD_DLY_MODE + LCD configuration register + 0x30 + 0x20 + + + LCD_CD_MODE + The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 0 + 2 + read-write + + + LCD_DE_MODE + The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 2 + 2 + read-write + + + LCD_HSYNC_MODE + The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 4 + 2 + read-write + + + LCD_VSYNC_MODE + The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 6 + 2 + read-write + + + + + LCD_DATA_DOUT_MODE + LCD configuration register + 0x38 + 0x20 + + + DOUT0_MODE + The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 0 + 2 + read-write + + + DOUT1_MODE + The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 2 + 2 + read-write + + + DOUT2_MODE + The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 4 + 2 + read-write + + + DOUT3_MODE + The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 6 + 2 + read-write + + + DOUT4_MODE + The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 8 + 2 + read-write + + + DOUT5_MODE + The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 10 + 2 + read-write + + + DOUT6_MODE + The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 12 + 2 + read-write + + + DOUT7_MODE + The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 14 + 2 + read-write + + + DOUT8_MODE + The output data bit 16 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 16 + 2 + read-write + + + DOUT9_MODE + The output data bit 18 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 18 + 2 + read-write + + + DOUT10_MODE + The output data bit 20 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 20 + 2 + read-write + + + DOUT11_MODE + The output data bit 22 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 22 + 2 + read-write + + + DOUT12_MODE + The output data bit 24 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 24 + 2 + read-write + + + DOUT13_MODE + The output data bit 26 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 26 + 2 + read-write + + + DOUT14_MODE + The output data bit 28 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 28 + 2 + read-write + + + DOUT15_MODE + The output data bit 30 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 30 + 2 + read-write + + + + + LC_DMA_INT_ENA + LCD_camera DMA inturrupt enable register + 0x64 + 0x20 + + + LCD_VSYNC_INT_ENA + The enable bit for LCD frame end interrupt. + 0 + 1 + read-write + + + LCD_TRANS_DONE_INT_ENA + The enable bit for lcd transfer end interrupt. + 1 + 1 + read-write + + + CAM_VSYNC_INT_ENA + The enable bit for Camera frame end interrupt. + 2 + 1 + read-write + + + CAM_HS_INT_ENA + The enable bit for Camera line interrupt. + 3 + 1 + read-write + + + + + LC_DMA_INT_RAW + LCD_camera DMA raw inturrupt status register + 0x68 + 0x20 + + + LCD_VSYNC_INT_RAW + The raw bit for LCD frame end interrupt. + 0 + 1 + read-only + + + LCD_TRANS_DONE_INT_RAW + The raw bit for lcd transfer end interrupt. + 1 + 1 + read-only + + + CAM_VSYNC_INT_RAW + The raw bit for Camera frame end interrupt. + 2 + 1 + read-only + + + CAM_HS_INT_RAW + The raw bit for Camera line interrupt. + 3 + 1 + read-only + + + + + LC_DMA_INT_ST + LCD_camera DMA masked inturrupt status register + 0x6C + 0x20 + + + LCD_VSYNC_INT_ST + The status bit for LCD frame end interrupt. + 0 + 1 + read-only + + + LCD_TRANS_DONE_INT_ST + The status bit for lcd transfer end interrupt. + 1 + 1 + read-only + + + CAM_VSYNC_INT_ST + The status bit for Camera frame end interrupt. + 2 + 1 + read-only + + + CAM_HS_INT_ST + The status bit for Camera transfer end interrupt. + 3 + 1 + read-only + + + + + LC_DMA_INT_CLR + LCD_camera DMA inturrupt clear register + 0x70 + 0x20 + + + LCD_VSYNC_INT_CLR + The clear bit for LCD frame end interrupt. + 0 + 1 + write-only + + + LCD_TRANS_DONE_INT_CLR + The clear bit for lcd transfer end interrupt. + 1 + 1 + write-only + + + CAM_VSYNC_INT_CLR + The clear bit for Camera frame end interrupt. + 2 + 1 + write-only + + + CAM_HS_INT_CLR + The clear bit for Camera line interrupt. + 3 + 1 + write-only + + + + + LC_REG_DATE + Version register + 0xFC + 0x20 + 0x02003020 + + + LC_DATE + LCD_CAM version control register + 0 + 28 + read-write + + + + + + + LEDC + LED Control PWM (Pulse Width Modulation) + LEDC + 0x60019000 + + 0x0 + 0xD8 + registers + + + LEDC + 35 + + + TIMER1 + 48 + + + TIMER2 + 49 + + + + 8 + 0x14 + CH%s_CONF0 + Configuration register 0 for channel %s + 0x0 + 0x20 + + + TIMER_SEL + This field is used to select one of timers for channel %s. + +0: select timer0 + +1: select timer1 + +2: select timer2 + +3: select timer3 + 0 + 2 + read-write + + + SIG_OUT_EN + Set this bit to enable signal output on channel %s. + 2 + 1 + read-write + + + IDLE_LV + This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0). + 3 + 1 + read-write + + + PARA_UP + This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware. + 4 + 1 + write-only + + + OVF_NUM + This register is used to configure the maximum times of overflow minus 1. + +The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times. + 5 + 10 + read-write + + + OVF_CNT_EN + This bit is used to enable the ovf_cnt of channel %s. + 15 + 1 + read-write + + + OVF_CNT_RESET + Set this bit to reset the ovf_cnt of channel %s. + 16 + 1 + write-only + + + OVF_CNT_RESET_ST + This is the status bit of LEDC_OVF_CNT_RESET_CH%s. + 17 + 1 + read-write + + + + + 8 + 0x14 + CH%s_HPOINT + High point register for channel %s + 0x4 + 0x20 + + + HPOINT + The output value changes to high when the selected timers has reached the value specified by this register. + 0 + 14 + read-write + + + + + 8 + 0x14 + CH%s_DUTY + Initial duty cycle for channel %s + 0x8 + 0x20 + + + DUTY + This register is used to change the output duty by controlling the Lpoint. + +The output value turns to low when the selected timers has reached the Lpoint. + 0 + 19 + read-write + + + + + 8 + 0x14 + CH%s_CONF1 + Configuration register 1 for channel %s + 0xC + 0x20 + 0x40000000 + + + DUTY_SCALE + This register is used to configure the changing step scale of duty on channel %s. + 0 + 10 + read-write + + + DUTY_CYCLE + The duty will change every LEDC_DUTY_CYCLE_CH%s on channel %s. + 10 + 10 + read-write + + + DUTY_NUM + This register is used to control the number of times the duty cycle will be changed. + 20 + 10 + read-write + + + DUTY_INC + This register is used to increase or decrease the duty of output signal on channel %s. 1: Increase; 0: Decrease. + 30 + 1 + read-write + + + DUTY_START + Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1. + 31 + 1 + read-write + + + + + 8 + 0x14 + CH%s_DUTY_R + Current duty cycle for channel %s + 0x10 + 0x20 + + + DUTY_R + This register stores the current duty of output signal on channel %s. + 0 + 19 + read-only + + + + + 4 + 0x8 + TIMER%s_CONF + Timer %s configuration + 0xA0 + 0x20 + 0x00800000 + + + DUTY_RES + This register is used to control the range of the counter in timer %s. + 0 + 4 + read-write + + + CLK_DIV + This register is used to configure the divisor for the divider in timer %s. + +The least significant eight bits represent the fractional part. + 4 + 18 + read-write + + + PAUSE + This bit is used to suspend the counter in timer %s. + 22 + 1 + read-write + + + RST + This bit is used to reset timer %s. The counter will show 0 after reset. + 23 + 1 + read-write + + + TICK_SEL + This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. + +1'h0: SLOW_CLK 1'h1: REF_TICK + 24 + 1 + read-write + + + PARA_UP + Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES. + 25 + 1 + write-only + + + + + 4 + 0x8 + TIMER%s_VALUE + Timer %s current counter value + 0xA4 + 0x20 + + + CNT + This register stores the current counter value of timer %s. + 0 + 14 + read-only + + + + + INT_RAW + Raw interrupt status + 0xC0 + 0x20 + + + TIMER0_OVF_INT_RAW + Triggered when the timer0 has reached its maximum counter value. + 0 + 1 + read-write + + + TIMER1_OVF_INT_RAW + Triggered when the timer1 has reached its maximum counter value. + 1 + 1 + read-write + + + TIMER2_OVF_INT_RAW + Triggered when the timer2 has reached its maximum counter value. + 2 + 1 + read-write + + + TIMER3_OVF_INT_RAW + Triggered when the timer3 has reached its maximum counter value. + 3 + 1 + read-write + + + DUTY_CHNG_END_CH0_INT_RAW + Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished. + 4 + 1 + read-write + + + DUTY_CHNG_END_CH1_INT_RAW + Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished. + 5 + 1 + read-write + + + DUTY_CHNG_END_CH2_INT_RAW + Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished. + 6 + 1 + read-write + + + DUTY_CHNG_END_CH3_INT_RAW + Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished. + 7 + 1 + read-write + + + DUTY_CHNG_END_CH4_INT_RAW + Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished. + 8 + 1 + read-write + + + DUTY_CHNG_END_CH5_INT_RAW + Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished. + 9 + 1 + read-write + + + DUTY_CHNG_END_CH6_INT_RAW + Interrupt raw bit for channel 6. Triggered when the gradual change of duty has finished. + 10 + 1 + read-write + + + DUTY_CHNG_END_CH7_INT_RAW + Interrupt raw bit for channel 7. Triggered when the gradual change of duty has finished. + 11 + 1 + read-write + + + OVF_CNT_CH0_INT_RAW + Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. + 12 + 1 + read-write + + + OVF_CNT_CH1_INT_RAW + Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. + 13 + 1 + read-write + + + OVF_CNT_CH2_INT_RAW + Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. + 14 + 1 + read-write + + + OVF_CNT_CH3_INT_RAW + Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. + 15 + 1 + read-write + + + OVF_CNT_CH4_INT_RAW + Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. + 16 + 1 + read-write + + + OVF_CNT_CH5_INT_RAW + Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. + 17 + 1 + read-write + + + OVF_CNT_CH6_INT_RAW + Interrupt raw bit for channel 6. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6. + 18 + 1 + read-write + + + OVF_CNT_CH7_INT_RAW + Interrupt raw bit for channel 7. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7. + 19 + 1 + read-write + + + + + INT_ST + Masked interrupt status + 0xC4 + 0x20 + + + TIMER0_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1. + 0 + 1 + read-only + + + TIMER1_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1. + 1 + 1 + read-only + + + TIMER2_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1. + 2 + 1 + read-only + + + TIMER3_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1. + 3 + 1 + read-only + + + DUTY_CHNG_END_CH0_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENAIS set to 1. + 4 + 1 + read-only + + + DUTY_CHNG_END_CH1_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENAIS set to 1. + 5 + 1 + read-only + + + DUTY_CHNG_END_CH2_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENAIS set to 1. + 6 + 1 + read-only + + + DUTY_CHNG_END_CH3_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENAIS set to 1. + 7 + 1 + read-only + + + DUTY_CHNG_END_CH4_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENAIS set to 1. + 8 + 1 + read-only + + + DUTY_CHNG_END_CH5_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENAIS set to 1. + 9 + 1 + read-only + + + DUTY_CHNG_END_CH6_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH6_INT interrupt when LEDC_DUTY_CHNG_END_CH6_INT_ENAIS set to 1. + 10 + 1 + read-only + + + DUTY_CHNG_END_CH7_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH7_INT interrupt when LEDC_DUTY_CHNG_END_CH7_INT_ENAIS set to 1. + 11 + 1 + read-only + + + OVF_CNT_CH0_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + 12 + 1 + read-only + + + OVF_CNT_CH1_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + 13 + 1 + read-only + + + OVF_CNT_CH2_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + 14 + 1 + read-only + + + OVF_CNT_CH3_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + 15 + 1 + read-only + + + OVF_CNT_CH4_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + 16 + 1 + read-only + + + OVF_CNT_CH5_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + 17 + 1 + read-only + + + OVF_CNT_CH6_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH6_INT interrupt when LEDC_OVF_CNT_CH6_INT_ENA is set to 1. + 18 + 1 + read-only + + + OVF_CNT_CH7_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH7_INT interrupt when LEDC_OVF_CNT_CH7_INT_ENA is set to 1. + 19 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC8 + 0x20 + + + TIMER0_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt. + 0 + 1 + read-write + + + TIMER1_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt. + 1 + 1 + read-write + + + TIMER2_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt. + 2 + 1 + read-write + + + TIMER3_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt. + 3 + 1 + read-write + + + DUTY_CHNG_END_CH0_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + 4 + 1 + read-write + + + DUTY_CHNG_END_CH1_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + 5 + 1 + read-write + + + DUTY_CHNG_END_CH2_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + 6 + 1 + read-write + + + DUTY_CHNG_END_CH3_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + 7 + 1 + read-write + + + DUTY_CHNG_END_CH4_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + 8 + 1 + read-write + + + DUTY_CHNG_END_CH5_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + 9 + 1 + read-write + + + DUTY_CHNG_END_CH6_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH6_INT interrupt. + 10 + 1 + read-write + + + DUTY_CHNG_END_CH7_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH7_INT interrupt. + 11 + 1 + read-write + + + OVF_CNT_CH0_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt. + 12 + 1 + read-write + + + OVF_CNT_CH1_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt. + 13 + 1 + read-write + + + OVF_CNT_CH2_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt. + 14 + 1 + read-write + + + OVF_CNT_CH3_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt. + 15 + 1 + read-write + + + OVF_CNT_CH4_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt. + 16 + 1 + read-write + + + OVF_CNT_CH5_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt. + 17 + 1 + read-write + + + OVF_CNT_CH6_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH6_INT interrupt. + 18 + 1 + read-write + + + OVF_CNT_CH7_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH7_INT interrupt. + 19 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0xCC + 0x20 + + + TIMER0_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt. + 0 + 1 + write-only + + + TIMER1_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt. + 1 + 1 + write-only + + + TIMER2_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt. + 2 + 1 + write-only + + + TIMER3_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt. + 3 + 1 + write-only + + + DUTY_CHNG_END_CH0_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + 4 + 1 + write-only + + + DUTY_CHNG_END_CH1_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + 5 + 1 + write-only + + + DUTY_CHNG_END_CH2_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + 6 + 1 + write-only + + + DUTY_CHNG_END_CH3_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + 7 + 1 + write-only + + + DUTY_CHNG_END_CH4_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + 8 + 1 + write-only + + + DUTY_CHNG_END_CH5_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + 9 + 1 + write-only + + + DUTY_CHNG_END_CH6_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH6_INT interrupt. + 10 + 1 + write-only + + + DUTY_CHNG_END_CH7_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH7_INT interrupt. + 11 + 1 + write-only + + + OVF_CNT_CH0_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt. + 12 + 1 + write-only + + + OVF_CNT_CH1_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt. + 13 + 1 + write-only + + + OVF_CNT_CH2_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt. + 14 + 1 + write-only + + + OVF_CNT_CH3_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt. + 15 + 1 + write-only + + + OVF_CNT_CH4_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt. + 16 + 1 + write-only + + + OVF_CNT_CH5_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt. + 17 + 1 + write-only + + + OVF_CNT_CH6_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH6_INT interrupt. + 18 + 1 + write-only + + + OVF_CNT_CH7_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH7_INT interrupt. + 19 + 1 + write-only + + + + + CONF + Global ledc configuration register + 0xD0 + 0x20 + + + APB_CLK_SEL + This bit is used to select clock source for the 4 timers . + +2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK + 0 + 2 + read-write + + + CLK_EN + This bit is used to control clock. + +1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 31 + 1 + read-write + + + + + DATE + Version control register + 0xFC + 0x20 + 0x19040200 + + + DATE + This is the version control register. + 0 + 32 + read-write + + + + + + + PCNT + Pulse Count Controller + PCNT + 0x60017000 + + 0x0 + 0x68 + registers + + + PCNT + 41 + + + + 4 + 0xC + U%s_CONF0 + Configuration register 0 for unit %s + 0x0 + 0x20 + 0x00003C10 + + + FILTER_THRES + This sets the maximum threshold, in APB_CLK cycles, for the filter. + +Any pulses with width less than this will be ignored when the filter is enabled. + 0 + 10 + read-write + + + FILTER_EN + This is the enable bit for unit %s's input filter. + 10 + 1 + read-write + + + THR_ZERO_EN + This is the enable bit for unit %s's zero comparator. + 11 + 1 + read-write + + + THR_H_LIM_EN + This is the enable bit for unit %s's thr_h_lim comparator. + 12 + 1 + read-write + + + THR_L_LIM_EN + This is the enable bit for unit %s's thr_l_lim comparator. + 13 + 1 + read-write + + + THR_THRES0_EN + This is the enable bit for unit %s's thres0 comparator. + 14 + 1 + read-write + + + THR_THRES1_EN + This is the enable bit for unit %s's thres1 comparator. + 15 + 1 + read-write + + + CH0_NEG_MODE + This register sets the behavior when the signal input of channel 0 detects a negative edge. + +1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter + 16 + 2 + read-write + + + CH0_POS_MODE + This register sets the behavior when the signal input of channel 0 detects a positive edge. + +1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter + 18 + 2 + read-write + + + CH0_HCTRL_MODE + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. + +0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification + 20 + 2 + read-write + + + CH0_LCTRL_MODE + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. + +0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification + 22 + 2 + read-write + + + CH1_NEG_MODE + This register sets the behavior when the signal input of channel 1 detects a negative edge. + +1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter + 24 + 2 + read-write + + + CH1_POS_MODE + This register sets the behavior when the signal input of channel 1 detects a positive edge. + +1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter + 26 + 2 + read-write + + + CH1_HCTRL_MODE + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. + +0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification + 28 + 2 + read-write + + + CH1_LCTRL_MODE + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. + +0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification + 30 + 2 + read-write + + + + + 4 + 0xC + U%s_CONF1 + Configuration register 1 for unit %s + 0x4 + 0x20 + + + CNT_THRES0 + This register is used to configure the thres0 value for unit %s. + 0 + 16 + read-write + + + CNT_THRES1 + This register is used to configure the thres1 value for unit %s. + 16 + 16 + read-write + + + + + 4 + 0xC + U%s_CONF2 + Configuration register 2 for unit %s + 0x8 + 0x20 + + + CNT_H_LIM + This register is used to configure the thr_h_lim value for unit %s. + 0 + 16 + read-write + + + CNT_L_LIM + This register is used to configure the thr_l_lim value for unit %s. + 16 + 16 + read-write + + + + + 4 + 0x4 + U%s_CNT + Counter value for unit %s + 0x30 + 0x20 + + + CNT + This register stores the current pulse count value for unit %s. + 0 + 16 + read-only + + + + + INT_RAW + Interrupt raw status register + 0x40 + 0x20 + + + CNT_THR_EVENT_U0 + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-only + + + CNT_THR_EVENT_U1 + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-only + + + CNT_THR_EVENT_U2 + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-only + + + CNT_THR_EVENT_U3 + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-only + + + + + INT_ST + Interrupt status register + 0x44 + 0x20 + + + CNT_THR_EVENT_U0 + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-only + + + CNT_THR_EVENT_U1 + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-only + + + CNT_THR_EVENT_U2 + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-only + + + CNT_THR_EVENT_U3 + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-only + + + + + INT_ENA + Interrupt enable register + 0x48 + 0x20 + + + CNT_THR_EVENT_U0 + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-write + + + CNT_THR_EVENT_U1 + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-write + + + CNT_THR_EVENT_U2 + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-write + + + CNT_THR_EVENT_U3 + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-write + + + + + INT_CLR + Interrupt clear register + 0x4C + 0x20 + + + CNT_THR_EVENT_U0 + Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + write-only + + + CNT_THR_EVENT_U1 + Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + write-only + + + CNT_THR_EVENT_U2 + Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + write-only + + + CNT_THR_EVENT_U3 + Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + write-only + + + + + 4 + 0x4 + U%s_STATUS + PNCT UNIT%s status register + 0x50 + 0x20 + + + ZERO_MODE + The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive. + 0 + 2 + read-only + + + THRES1 + The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others + 2 + 1 + read-only + + + THRES0 + The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others + 3 + 1 + read-only + + + L_LIM + The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others + 4 + 1 + read-only + + + H_LIM + The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others + 5 + 1 + read-only + + + ZERO + The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others + 6 + 1 + read-only + + + + + CTRL + Control register for all counters + 0x60 + 0x20 + 0x00000001 + + + CNT_RST_U0 + Set this bit to clear unit 0's counter. + 0 + 1 + read-write + + + CNT_PAUSE_U0 + Set this bit to freeze unit 0's counter. + 1 + 1 + read-write + + + CNT_RST_U1 + Set this bit to clear unit 1's counter. + 2 + 1 + read-write + + + CNT_PAUSE_U1 + Set this bit to freeze unit 1's counter. + 3 + 1 + read-write + + + CNT_RST_U2 + Set this bit to clear unit 2's counter. + 4 + 1 + read-write + + + CNT_PAUSE_U2 + Set this bit to freeze unit 2's counter. + 5 + 1 + read-write + + + CNT_RST_U3 + Set this bit to clear unit 3's counter. + 6 + 1 + read-write + + + CNT_PAUSE_U3 + Set this bit to freeze unit 3's counter. + 7 + 1 + read-write + + + CLK_EN + The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application + 16 + 1 + read-write + + + + + DATE + PCNT version control register + 0xFC + 0x20 + 0x19072601 + + + DATE + This is the PCNT version control register. + 0 + 32 + read-write + + + + + + + PERI_BACKUP + PERI_BACKUP Peripheral + PERI_BACKUP + 0x6002A000 + + 0x0 + 0x30 + registers + + + PERI_BACKUP + 97 + + + + CONFIG + x + 0x0 + 0x20 + 0x00006480 + + + FLOW_ERR + x + 0 + 3 + read-only + + + ADDR_MAP_MODE + x + 3 + 1 + read-write + + + BURST_LIMIT + x + 4 + 5 + read-write + + + TOUT_THRES + x + 9 + 10 + read-write + + + SIZE + x + 19 + 10 + read-write + + + START + x + 29 + 1 + write-only + + + TO_MEM + x + 30 + 1 + read-write + + + ENA + x + 31 + 1 + read-write + + + + + APB_ADDR + x + 0x4 + 0x20 + + + APB_START_ADDR + x + 0 + 32 + read-write + + + + + MEM_ADDR + x + 0x8 + 0x20 + + + MEM_START_ADDR + x + 0 + 32 + read-write + + + + + REG_MAP0 + x + 0xC + 0x20 + + + MAP0 + x + 0 + 32 + read-write + + + + + REG_MAP1 + x + 0x10 + 0x20 + + + MAP1 + x + 0 + 32 + read-write + + + + + REG_MAP2 + x + 0x14 + 0x20 + + + MAP2 + x + 0 + 32 + read-write + + + + + REG_MAP3 + x + 0x18 + 0x20 + + + MAP3 + x + 0 + 32 + read-write + + + + + INT_RAW + x + 0x1C + 0x20 + + + DONE_INT_RAW + x + 0 + 1 + read-only + + + ERR_INT_RAW + x + 1 + 1 + read-only + + + + + INT_ST + x + 0x20 + 0x20 + + + DONE_INT_ST + x + 0 + 1 + read-only + + + ERR_INT_ST + x + 1 + 1 + read-only + + + + + INT_ENA + x + 0x24 + 0x20 + + + DONE_INT_ENA + x + 0 + 1 + read-write + + + ERR_INT_ENA + x + 1 + 1 + read-write + + + + + INT_CLR + x + 0x28 + 0x20 + + + DONE_INT_CLR + x + 0 + 1 + write-only + + + ERR_INT_CLR + x + 1 + 1 + write-only + + + + + DATE + x + 0xFC + 0x20 + 0x02012300 + + + DATE + x + 0 + 28 + read-write + + + CLK_EN + register file clk gating + 31 + 1 + read-write + + + + + + + MCPWM0 + Motor Control Pulse-Width Modulation 0 + PWM + 0x6001E000 + + 0x0 + 0x128 + registers + + + MCPWM0 + 31 + + + + CLK_CFG + PWM clock prescaler register. + 0x0 + 0x20 + + + CLK_PRESCALE + Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1) + 0 + 8 + read-write + + + + + TIMER0_CFG0 + PWM timer0 period and update method configuration register. + 0x4 + 0x20 + 0x0000FF00 + + + TIMER0_PRESCALE + period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1) + 0 + 8 + read-write + + + TIMER0_PERIOD + period shadow register of PWM timer0 + 8 + 16 + read-write + + + TIMER0_PERIOD_UPMETHOD + Update method for active register of PWM timer0 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + 24 + 2 + read-write + + + + + TIMER0_CFG1 + PWM timer0 working mode and start/stop control configuration register. + 0x8 + 0x20 + + + TIMER0_START + PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1: if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0 starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period + 0 + 3 + read-write + + + TIMER0_MOD + PWM timer0 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode + 3 + 2 + read-write + + + + + TIMER0_SYNC + PWM timer0 sync function configuration register. + 0xC + 0x20 + + + TIMER0_SYNCI_EN + When set, timer reloading with phase on sync input event is enabled. + 0 + 1 + read-write + + + SW + Toggling this bit will trigger a software sync. + 1 + 1 + read-write + + + TIMER0_SYNCO_SEL + PWM timer0 sync_out selection, 0: synci, 1: TEZ, 2: TEP, otherwise:sync out is software sync + 2 + 2 + read-write + + + TIMER0_PHASE + phase for timer reload on sync event + 4 + 16 + read-write + + + TIMER0_PHASE_DIRECTION + Configure the PWM timer0's direction when timer0 mode is up-down mode. 0: increase; 1: decrease. + 20 + 1 + read-write + + + + + TIMER0_STATUS + PWM timer0 status register. + 0x10 + 0x20 + + + TIMER0_VALUE + current PWM timer0 counter value + 0 + 16 + read-only + + + TIMER0_DIRECTION + current PWM timer0 counter direction, 0: increment 1: decrement + 16 + 1 + read-only + + + + + TIMER1_CFG0 + PWM timer1 period and update method configuration register. + 0x14 + 0x20 + 0x0000FF00 + + + TIMER1_PRESCALE + period of PT0_clk = Period of PWM_clk * (PWM_timer1_PRESCALE + 1) + 0 + 8 + read-write + + + TIMER1_PERIOD + period shadow register of PWM timer1 + 8 + 16 + read-write + + + TIMER1_PERIOD_UPMETHOD + Update method for active register of PWM timer1 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + 24 + 2 + read-write + + + + + TIMER1_CFG1 + PWM timer1 working mode and start/stop control configuration register. + 0x18 + 0x20 + + + TIMER1_START + PWM timer1 start and stop control. 0: if PWM timer1 starts, then stops at TEZ, 1: if timer1 starts, then stops at TEP, 2: PWM timer1 starts and runs on, 3: timer1 starts and stops at the next TEZ, 4: timer1 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period + 0 + 3 + read-write + + + TIMER1_MOD + PWM timer1 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode + 3 + 2 + read-write + + + + + TIMER1_SYNC + PWM timer1 sync function configuration register. + 0x1C + 0x20 + + + TIMER1_SYNCI_EN + When set, timer reloading with phase on sync input event is enabled. + 0 + 1 + read-write + + + SW + Toggling this bit will trigger a software sync. + 1 + 1 + read-write + + + TIMER1_SYNCO_SEL + PWM timer1 sync_out selection, 0: synci, 1: TEZ, 2: TEP, otherwise:sync out is software sync + 2 + 2 + read-write + + + TIMER1_PHASE + phase for timer reload on sync event + 4 + 16 + read-write + + + TIMER1_PHASE_DIRECTION + Configure the PWM timer1's direction when timer1 mode is up-down mode. 0: increase; 1: decrease. + 20 + 1 + read-write + + + + + TIMER1_STATUS + PWM timer1 status register. + 0x20 + 0x20 + + + TIMER1_VALUE + current PWM timer1 counter value + 0 + 16 + read-only + + + TIMER1_DIRECTION + current PWM timer1 counter direction, 0: increment 1: decrement + 16 + 1 + read-only + + + + + TIMER2_CFG0 + PWM timer2 period and update method configuration register. + 0x24 + 0x20 + 0x0000FF00 + + + TIMER2_PRESCALE + period of PT0_clk = Period of PWM_clk * (PWM_timer2_PRESCALE + 1) + 0 + 8 + read-write + + + TIMER2_PERIOD + period shadow register of PWM timer2 + 8 + 16 + read-write + + + TIMER2_PERIOD_UPMETHOD + Update method for active register of PWM timer2 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + 24 + 2 + read-write + + + + + TIMER2_CFG1 + PWM timer2 working mode and start/stop control configuration register. + 0x28 + 0x20 + + + TIMER2_START + PWM timer2 start and stop control. 0: if PWM timer2 starts, then stops at TEZ, 1: if timer2 starts, then stops at TEP, 2: PWM timer2 starts and runs on, 3: timer2 starts and stops at the next TEZ, 4: timer2 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period + 0 + 3 + read-write + + + TIMER2_MOD + PWM timer2 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode + 3 + 2 + read-write + + + + + TIMER2_SYNC + PWM timer2 sync function configuration register. + 0x2C + 0x20 + + + TIMER2_SYNCI_EN + When set, timer reloading with phase on sync input event is enabled. + 0 + 1 + read-write + + + SW + Toggling this bit will trigger a software sync. + 1 + 1 + read-write + + + TIMER2_SYNCO_SEL + PWM timer2 sync_out selection, 0: synci, 1: TEZ, 2: TEP, otherwise:sync out is software sync + 2 + 2 + read-write + + + TIMER2_PHASE + phase for timer reload on sync event + 4 + 16 + read-write + + + TIMER2_PHASE_DIRECTION + Configure the PWM timer2's direction when timer2 mode is up-down mode. 0: increase; 1: decrease. + 20 + 1 + read-write + + + + + TIMER2_STATUS + PWM timer2 status register. + 0x30 + 0x20 + + + TIMER2_VALUE + current PWM timer2 counter value + 0 + 16 + read-only + + + TIMER2_DIRECTION + current PWM timer2 counter direction, 0: increment 1: decrement + 16 + 1 + read-only + + + + + TIMER_SYNCI_CFG + Synchronization input selection for three PWM timers. + 0x34 + 0x20 + + + TIMER0_SYNCISEL + select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected + 0 + 3 + read-write + + + TIMER1_SYNCISEL + select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected + 3 + 3 + read-write + + + TIMER2_SYNCISEL + select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected + 6 + 3 + read-write + + + EXTERNAL_SYNCI0_INVERT + invert SYNC0 from GPIO matrix + 9 + 1 + read-write + + + EXTERNAL_SYNCI1_INVERT + invert SYNC1 from GPIO matrix + 10 + 1 + read-write + + + EXTERNAL_SYNCI2_INVERT + invert SYNC2 from GPIO matrix + 11 + 1 + read-write + + + + + OPERATOR_TIMERSEL + Select specific timer for PWM operators. + 0x38 + 0x20 + + + OPERATOR0_TIMERSEL + Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2 + 0 + 2 + read-write + + + OPERATOR1_TIMERSEL + Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: timer1, 2: timer2 + 2 + 2 + read-write + + + OPERATOR2_TIMERSEL + Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: timer1, 2: timer2 + 4 + 2 + read-write + + + + + CMPR0_CFG + Transfer status and update method for time stamp registers A and B + 0x3C + 0x20 + + + CMPR0_A_UPMETHOD + Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 0 + 4 + read-write + + + CMPR0_B_UPMETHOD + Update method for PWM generator 0 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 4 + 4 + read-write + + + CMPR0_A_SHDW_FULL + Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value + 8 + 1 + read-write + + + CMPR0_B_SHDW_FULL + Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value + 9 + 1 + read-write + + + + + CMPR0_VALUE0 + Shadow register for register A. + 0x40 + 0x20 + + + CMPR0_A + PWM generator 0 time stamp A's shadow register + 0 + 16 + read-write + + + + + CMPR0_VALUE1 + Shadow register for register B. + 0x44 + 0x20 + + + CMPR0_B + PWM generator 0 time stamp B's shadow register + 0 + 16 + read-write + + + + + GEN0_CFG0 + Fault event T0 and T1 handling + 0x48 + 0x20 + + + GEN0_CFG_UPMETHOD + Update method for PWM generator 0's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: + 0 + 4 + read-write + + + GEN0_T0_SEL + Source selection for PWM generator 0 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 4 + 3 + read-write + + + GEN0_T1_SEL + Source selection for PWM generator 0 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 7 + 3 + read-write + + + + + GEN0_FORCE + Permissives to force PWM0A and PWM0B outputs by software + 0x4C + 0x20 + 0x00000020 + + + GEN0_CNTUFORCE_UPMETHOD + Updating method for continuous software force of PWM generator0. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.) + 0 + 6 + read-write + + + GEN0_A_CNTUFORCE_MODE + Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled + 6 + 2 + read-write + + + GEN0_B_CNTUFORCE_MODE + Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled + 8 + 2 + read-write + + + GEN0_A_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM0A, a toggle will trigger a force event. + 10 + 1 + read-write + + + GEN0_A_NCIFORCE_MODE + non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2: high, 3: disabled + 11 + 2 + read-write + + + GEN0_B_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM0B, a toggle will trigger a force event. + 13 + 1 + read-write + + + GEN0_B_NCIFORCE_MODE + non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2: high, 3: disabled + 14 + 2 + read-write + + + + + GEN0_A + Actions triggered by events on PWM0A + 0x50 + 0x20 + + + UTEZ + Action on PWM0A triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM0A triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM0A triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM0A triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM0A triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM0A triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM0A triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM0A triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM0A triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM0A triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM0A triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + GEN0_B + Actions triggered by events on PWM0B + 0x54 + 0x20 + + + UTEZ + Action on PWM0B triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM0B triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM0B triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM0B triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM0B triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM0B triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM0B triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM0B triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM0B triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM0B triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM0B triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM0B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + DB0_CFG + dead time type selection and configuration + 0x58 + 0x20 + 0x00018000 + + + DB0_FED_UPMETHOD + Update method for FED (falling edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze + 0 + 4 + read-write + + + DB0_RED_UPMETHOD + Update method for RED (rising edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze + 4 + 4 + read-write + + + DB0_DEB_MODE + S8 in documentation, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode + 8 + 1 + read-write + + + DB0_A_OUTSWAP + S6 in documentation + 9 + 1 + read-write + + + DB0_B_OUTSWAP + S7 in documentation + 10 + 1 + read-write + + + DB0_RED_INSEL + S4 in documentation + 11 + 1 + read-write + + + DB0_FED_INSEL + S5 in documentation + 12 + 1 + read-write + + + DB0_RED_OUTINVERT + S2 in documentation + 13 + 1 + read-write + + + DB0_FED_OUTINVERT + S3 in documentation + 14 + 1 + read-write + + + DB0_A_OUTBYPASS + S1 in documentation + 15 + 1 + read-write + + + DB0_B_OUTBYPASS + S0 in documentation + 16 + 1 + read-write + + + DB0_CLK_SEL + Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk + 17 + 1 + read-write + + + + + DB0_FED_CFG + Shadow register for falling edge delay (FED). + 0x5C + 0x20 + + + DB0_FED + Shadow register for FED + 0 + 16 + read-write + + + + + DB0_RED_CFG + Shadow register for rising edge delay (RED). + 0x60 + 0x20 + + + DB0_RED + Shadow register for RED + 0 + 16 + read-write + + + + + CHOPPER0_CFG + Carrier enable and configuratoin + 0x64 + 0x20 + + + CHOPPER0_EN + When set, carrier0 function is enabled. When cleared, carrier0 is bypassed + 0 + 1 + read-write + + + CHOPPER0_PRESCALE + PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + 1 + 4 + read-write + + + CHOPPER0_DUTY + carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + 5 + 3 + read-write + + + CHOPPER0_OSHTWTH + width of the fist pulse in number of periods of the carrier + 8 + 4 + read-write + + + CHOPPER0_OUT_INVERT + when set, invert the output of PWM0A and PWM0B for this submodule + 12 + 1 + read-write + + + CHOPPER0_IN_INVERT + when set, invert the input of PWM0A and PWM0B for this submodule + 13 + 1 + read-write + + + + + TZ0_CFG0 + Actions on PWM0A and PWM0B trip events + 0x68 + 0x20 + + + TZ0_SW_CBC + Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + 0 + 1 + read-write + + + TZ0_F2_CBC + event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 1 + 1 + read-write + + + TZ0_F1_CBC + event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 2 + 1 + read-write + + + TZ0_F0_CBC + event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 3 + 1 + read-write + + + TZ0_SW_OST + Enable register for software force one-shot mode action. 0: disable, 1: enable + 4 + 1 + read-write + + + TZ0_F2_OST + event_f2 will trigger one-shot mode action. 0: disable, 1: enable + 5 + 1 + read-write + + + TZ0_F1_OST + event_f1 will trigger one-shot mode action. 0: disable, 1: enable + 6 + 1 + read-write + + + TZ0_F0_OST + event_f0 will trigger one-shot mode action. 0: disable, 1: enable + 7 + 1 + read-write + + + TZ0_A_CBC_D + Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 8 + 2 + read-write + + + TZ0_A_CBC_U + Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 10 + 2 + read-write + + + TZ0_A_OST_D + One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 12 + 2 + read-write + + + TZ0_A_OST_U + One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 14 + 2 + read-write + + + TZ0_B_CBC_D + Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 16 + 2 + read-write + + + TZ0_B_CBC_U + Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 18 + 2 + read-write + + + TZ0_B_OST_D + One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 20 + 2 + read-write + + + TZ0_B_OST_U + One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 22 + 2 + read-write + + + + + TZ0_CFG1 + Software triggers for fault handler actions + 0x6C + 0x20 + + + TZ0_CLR_OST + a rising edge will clear on going one-shot mode action + 0 + 1 + read-write + + + TZ0_CBCPULSE + cycle-by-cycle mode action refresh moment selection. Bit0: TEZ, bit1:TEP + 1 + 2 + read-write + + + TZ0_FORCE_CBC + a toggle trigger a cycle-by-cycle mode action + 3 + 1 + read-write + + + TZ0_FORCE_OST + a toggle (software negate its value) triggers a one-shot mode action + 4 + 1 + read-write + + + + + TZ0_STATUS + Status of fault events. + 0x70 + 0x20 + + + TZ0_CBC_ON + Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + 0 + 1 + read-only + + + TZ0_OST_ON + Set and reset by hardware. If set, an one-shot mode action is on going + 1 + 1 + read-only + + + + + CMPR1_CFG + Transfer status and update method for time stamp registers A and B + 0x74 + 0x20 + + + CMPR1_A_UPMETHOD + Update method for PWM generator 1 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 0 + 4 + read-write + + + CMPR1_B_UPMETHOD + Update method for PWM generator 1 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 4 + 4 + read-write + + + CMPR1_A_SHDW_FULL + Set and reset by hardware. If set, PWM generator 1 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value + 8 + 1 + read-write + + + CMPR1_B_SHDW_FULL + Set and reset by hardware. If set, PWM generator 1 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value + 9 + 1 + read-write + + + + + CMPR1_VALUE0 + Shadow register for register A. + 0x78 + 0x20 + + + CMPR1_A + PWM generator 1 time stamp A's shadow register + 0 + 16 + read-write + + + + + CMPR1_VALUE1 + Shadow register for register B. + 0x7C + 0x20 + + + CMPR1_B + PWM generator 1 time stamp B's shadow register + 0 + 16 + read-write + + + + + GEN1_CFG0 + Fault event T0 and T1 handling + 0x80 + 0x20 + + + GEN1_CFG_UPMETHOD + Update method for PWM generator 1's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: + 0 + 4 + read-write + + + GEN1_T0_SEL + Source selection for PWM generator 1 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 4 + 3 + read-write + + + GEN1_T1_SEL + Source selection for PWM generator 1 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 7 + 3 + read-write + + + + + GEN1_FORCE + Permissives to force PWM1A and PWM1B outputs by software + 0x84 + 0x20 + 0x00000020 + + + GEN1_CNTUFORCE_UPMETHOD + Updating method for continuous software force of PWM generator 1. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.) + 0 + 6 + read-write + + + GEN1_A_CNTUFORCE_MODE + Continuous software force mode for PWM1A. 0: disabled, 1: low, 2: high, 3: disabled + 6 + 2 + read-write + + + GEN1_B_CNTUFORCE_MODE + Continuous software force mode for PWM1B. 0: disabled, 1: low, 2: high, 3: disabled + 8 + 2 + read-write + + + GEN1_A_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM1A, a toggle will trigger a force event. + 10 + 1 + read-write + + + GEN1_A_NCIFORCE_MODE + non-continuous immediate software force mode for PWM1A, 0: disabled, 1: low, 2: high, 3: disabled + 11 + 2 + read-write + + + GEN1_B_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM1B, a toggle will trigger a force event. + 13 + 1 + read-write + + + GEN1_B_NCIFORCE_MODE + non-continuous immediate software force mode for PWM1B, 0: disabled, 1: low, 2: high, 3: disabled + 14 + 2 + read-write + + + + + GEN1_A + Actions triggered by events on PWM1A + 0x88 + 0x20 + + + UTEZ + Action on PWM1A triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM1A triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM1A triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM1A triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM1A triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM1A triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM1A triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM1A triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM1A triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM1A triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM1A triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM1A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + GEN1_B + Actions triggered by events on PWM1B + 0x8C + 0x20 + + + UTEZ + Action on PWM1B triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM1B triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM1B triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM1B triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM1B triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM1B triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM1B triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM1B triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM1B triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM1B triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM1B triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM1B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + DB1_CFG + dead time type selection and configuration + 0x90 + 0x20 + 0x00018000 + + + DB1_FED_UPMETHOD + Update method for FED (falling edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze + 0 + 4 + read-write + + + DB1_RED_UPMETHOD + Update method for RED (rising edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze + 4 + 4 + read-write + + + DB1_DEB_MODE + S8 in documentation, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode + 8 + 1 + read-write + + + DB1_A_OUTSWAP + S6 in documentation + 9 + 1 + read-write + + + DB1_B_OUTSWAP + S7 in documentation + 10 + 1 + read-write + + + DB1_RED_INSEL + S4 in documentation + 11 + 1 + read-write + + + DB1_FED_INSEL + S5 in documentation + 12 + 1 + read-write + + + DB1_RED_OUTINVERT + S2 in documentation + 13 + 1 + read-write + + + DB1_FED_OUTINVERT + S3 in documentation + 14 + 1 + read-write + + + DB1_A_OUTBYPASS + S1 in documentation + 15 + 1 + read-write + + + DB1_B_OUTBYPASS + S0 in documentation + 16 + 1 + read-write + + + DB1_CLK_SEL + Dead time generator 1 clock selection. 0: PWM_clk, 1: PT_clk + 17 + 1 + read-write + + + + + DB1_FED_CFG + Shadow register for falling edge delay (FED). + 0x94 + 0x20 + + + DB1_FED + Shadow register for FED + 0 + 16 + read-write + + + + + DB1_RED_CFG + Shadow register for rising edge delay (RED). + 0x98 + 0x20 + + + DB1_RED + Shadow register for RED + 0 + 16 + read-write + + + + + CHOPPER1_CFG + Carrier enable and configuratoin + 0x9C + 0x20 + + + CHOPPER1_EN + When set, carrier0 function is enabled. When cleared, carrier0 is bypassed + 0 + 1 + read-write + + + CHOPPER1_PRESCALE + PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + 1 + 4 + read-write + + + CHOPPER1_DUTY + carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + 5 + 3 + read-write + + + CHOPPER1_OSHTWTH + width of the fist pulse in number of periods of the carrier + 8 + 4 + read-write + + + CHOPPER1_OUT_INVERT + when set, invert the output of PWM1A and PWM1B for this submodule + 12 + 1 + read-write + + + CHOPPER1_IN_INVERT + when set, invert the input of PWM1A and PWM1B for this submodule + 13 + 1 + read-write + + + + + TZ1_CFG0 + Actions on PWM1A and PWM1B trip events + 0xA0 + 0x20 + + + TZ1_SW_CBC + Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + 0 + 1 + read-write + + + TZ1_F2_CBC + event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 1 + 1 + read-write + + + TZ1_F1_CBC + event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 2 + 1 + read-write + + + TZ1_F0_CBC + event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 3 + 1 + read-write + + + TZ1_SW_OST + Enable register for software force one-shot mode action. 0: disable, 1: enable + 4 + 1 + read-write + + + TZ1_F2_OST + event_f2 will trigger one-shot mode action. 0: disable, 1: enable + 5 + 1 + read-write + + + TZ1_F1_OST + event_f1 will trigger one-shot mode action. 0: disable, 1: enable + 6 + 1 + read-write + + + TZ1_F0_OST + event_f0 will trigger one-shot mode action. 0: disable, 1: enable + 7 + 1 + read-write + + + TZ1_A_CBC_D + Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 8 + 2 + read-write + + + TZ1_A_CBC_U + Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 10 + 2 + read-write + + + TZ1_A_OST_D + One-shot mode action on PWM1A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 12 + 2 + read-write + + + TZ1_A_OST_U + One-shot mode action on PWM1A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 14 + 2 + read-write + + + TZ1_B_CBC_D + Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 16 + 2 + read-write + + + TZ1_B_CBC_U + Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 18 + 2 + read-write + + + TZ1_B_OST_D + One-shot mode action on PWM1B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 20 + 2 + read-write + + + TZ1_B_OST_U + One-shot mode action on PWM1B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 22 + 2 + read-write + + + + + TZ1_CFG1 + Software triggers for fault handler actions + 0xA4 + 0x20 + + + TZ1_CLR_OST + a rising edge will clear on going one-shot mode action + 0 + 1 + read-write + + + TZ1_CBCPULSE + cycle-by-cycle mode action refresh moment selection. Bit0: TEZ, bit1:TEP + 1 + 2 + read-write + + + TZ1_FORCE_CBC + a toggle trigger a cycle-by-cycle mode action + 3 + 1 + read-write + + + TZ1_FORCE_OST + a toggle (software negate its value) triggers a one-shot mode action + 4 + 1 + read-write + + + + + TZ1_STATUS + Status of fault events. + 0xA8 + 0x20 + + + TZ1_CBC_ON + Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + 0 + 1 + read-only + + + TZ1_OST_ON + Set and reset by hardware. If set, an one-shot mode action is on going + 1 + 1 + read-only + + + + + CMPR2_CFG + Transfer status and update method for time stamp registers A and B + 0xAC + 0x20 + + + CMPR2_A_UPMETHOD + Update method for PWM generator 2 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 0 + 4 + read-write + + + CMPR2_B_UPMETHOD + Update method for PWM generator 2 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 4 + 4 + read-write + + + CMPR2_A_SHDW_FULL + Set and reset by hardware. If set, PWM generator 2 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value + 8 + 1 + read-write + + + CMPR2_B_SHDW_FULL + Set and reset by hardware. If set, PWM generator 2 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value + 9 + 1 + read-write + + + + + CMPR2_VALUE0 + Shadow register for register A. + 0xB0 + 0x20 + + + CMPR2_A + PWM generator 2 time stamp A's shadow register + 0 + 16 + read-write + + + + + CMPR2_VALUE1 + Shadow register for register B. + 0xB4 + 0x20 + + + CMPR2_B + PWM generator 2 time stamp B's shadow register + 0 + 16 + read-write + + + + + GEN2_CFG0 + Fault event T0 and T1 handling + 0xB8 + 0x20 + + + GEN2_CFG_UPMETHOD + Update method for PWM generator 2's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: + 0 + 4 + read-write + + + GEN2_T0_SEL + Source selection for PWM generator 2 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 4 + 3 + read-write + + + GEN2_T1_SEL + Source selection for PWM generator 2 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 7 + 3 + read-write + + + + + GEN2_FORCE + Permissives to force PWM2A and PWM2B outputs by software + 0xBC + 0x20 + 0x00000020 + + + GEN2_CNTUFORCE_UPMETHOD + Updating method for continuous software force of PWM generator 2. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.) + 0 + 6 + read-write + + + GEN2_A_CNTUFORCE_MODE + Continuous software force mode for PWM2A. 0: disabled, 1: low, 2: high, 3: disabled + 6 + 2 + read-write + + + GEN2_B_CNTUFORCE_MODE + Continuous software force mode for PWM2B. 0: disabled, 1: low, 2: high, 3: disabled + 8 + 2 + read-write + + + GEN2_A_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM2A, a toggle will trigger a force event. + 10 + 1 + read-write + + + GEN2_A_NCIFORCE_MODE + non-continuous immediate software force mode for PWM2A, 0: disabled, 1: low, 2: high, 3: disabled + 11 + 2 + read-write + + + GEN2_B_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM2B, a toggle will trigger a force event. + 13 + 1 + read-write + + + GEN2_B_NCIFORCE_MODE + non-continuous immediate software force mode for PWM2B, 0: disabled, 1: low, 2: high, 3: disabled + 14 + 2 + read-write + + + + + GEN2_A + Actions triggered by events on PWM2A + 0xC0 + 0x20 + + + UTEZ + Action on PWM2A triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM2A triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM2A triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM2A triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM2A triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM2A triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM2A triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM2A triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM2A triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM2A triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM2A triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM2A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + GEN2_B + Actions triggered by events on PWM2B + 0xC4 + 0x20 + + + UTEZ + Action on PWM2B triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM2B triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM2B triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM2B triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM2B triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM2B triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM2B triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM2B triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM2B triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM2B triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM2B triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM2B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + DB2_CFG + dead time type selection and configuration + 0xC8 + 0x20 + 0x00018000 + + + DB2_FED_UPMETHOD + Update method for FED (falling edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze + 0 + 4 + read-write + + + DB2_RED_UPMETHOD + Update method for RED (rising edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze + 4 + 4 + read-write + + + DB2_DEB_MODE + S8 in documentation, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode + 8 + 1 + read-write + + + DB2_A_OUTSWAP + S6 in documentation + 9 + 1 + read-write + + + DB2_B_OUTSWAP + S7 in documentation + 10 + 1 + read-write + + + DB2_RED_INSEL + S4 in documentation + 11 + 1 + read-write + + + DB2_FED_INSEL + S5 in documentation + 12 + 1 + read-write + + + DB2_RED_OUTINVERT + S2 in documentation + 13 + 1 + read-write + + + DB2_FED_OUTINVERT + S3 in documentation + 14 + 1 + read-write + + + DB2_A_OUTBYPASS + S1 in documentation + 15 + 1 + read-write + + + DB2_B_OUTBYPASS + S0 in documentation + 16 + 1 + read-write + + + DB2_CLK_SEL + Dead time generator 2 clock selection. 0: PWM_clk, 1: PT_clk + 17 + 1 + read-write + + + + + DB2_FED_CFG + Shadow register for falling edge delay (FED). + 0xCC + 0x20 + + + DB2_FED + Shadow register for FED + 0 + 16 + read-write + + + + + DB2_RED_CFG + Shadow register for rising edge delay (RED). + 0xD0 + 0x20 + + + DB2_RED + Shadow register for RED + 0 + 16 + read-write + + + + + CHOPPER2_CFG + Carrier enable and configuratoin + 0xD4 + 0x20 + + + CHOPPER2_EN + When set, carrier0 function is enabled. When cleared, carrier0 is bypassed + 0 + 1 + read-write + + + CHOPPER2_PRESCALE + PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + 1 + 4 + read-write + + + CHOPPER2_DUTY + carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + 5 + 3 + read-write + + + CHOPPER2_OSHTWTH + width of the fist pulse in number of periods of the carrier + 8 + 4 + read-write + + + CHOPPER2_OUT_INVERT + when set, invert the output of PWM2A and PWM2B for this submodule + 12 + 1 + read-write + + + CHOPPER2_IN_INVERT + when set, invert the input of PWM2A and PWM2B for this submodule + 13 + 1 + read-write + + + + + TZ2_CFG0 + Actions on PWM2A and PWM2B trip events + 0xD8 + 0x20 + + + TZ2_SW_CBC + Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + 0 + 1 + read-write + + + TZ2_F2_CBC + event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 1 + 1 + read-write + + + TZ2_F1_CBC + event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 2 + 1 + read-write + + + TZ2_F0_CBC + event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 3 + 1 + read-write + + + TZ2_SW_OST + Enable register for software force one-shot mode action. 0: disable, 1: enable + 4 + 1 + read-write + + + TZ2_F2_OST + event_f2 will trigger one-shot mode action. 0: disable, 1: enable + 5 + 1 + read-write + + + TZ2_F1_OST + event_f1 will trigger one-shot mode action. 0: disable, 1: enable + 6 + 1 + read-write + + + TZ2_F0_OST + event_f0 will trigger one-shot mode action. 0: disable, 1: enable + 7 + 1 + read-write + + + TZ2_A_CBC_D + Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 8 + 2 + read-write + + + TZ2_A_CBC_U + Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 10 + 2 + read-write + + + TZ2_A_OST_D + One-shot mode action on PWM2A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 12 + 2 + read-write + + + TZ2_A_OST_U + One-shot mode action on PWM2A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 14 + 2 + read-write + + + TZ2_B_CBC_D + Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 16 + 2 + read-write + + + TZ2_B_CBC_U + Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 18 + 2 + read-write + + + TZ2_B_OST_D + One-shot mode action on PWM2B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 20 + 2 + read-write + + + TZ2_B_OST_U + One-shot mode action on PWM2B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 22 + 2 + read-write + + + + + TZ2_CFG1 + Software triggers for fault handler actions + 0xDC + 0x20 + + + TZ2_CLR_OST + a rising edge will clear on going one-shot mode action + 0 + 1 + read-write + + + TZ2_CBCPULSE + cycle-by-cycle mode action refresh moment selection. Bit0: TEZ, bit1:TEP + 1 + 2 + read-write + + + TZ2_FORCE_CBC + a toggle trigger a cycle-by-cycle mode action + 3 + 1 + read-write + + + TZ2_FORCE_OST + a toggle (software negate its value) triggers a one-shot mode action + 4 + 1 + read-write + + + + + TZ2_STATUS + Status of fault events. + 0xE0 + 0x20 + + + TZ2_CBC_ON + Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + 0 + 1 + read-only + + + TZ2_OST_ON + Set and reset by hardware. If set, an one-shot mode action is on going + 1 + 1 + read-only + + + + + FAULT_DETECT + Fault detection configuration and status + 0xE4 + 0x20 + + + F0_EN + When set, event_f0 generation is enabled + 0 + 1 + read-write + + + F1_EN + When set, event_f1 generation is enabled + 1 + 1 + read-write + + + F2_EN + When set, event_f2 generation is enabled + 2 + 1 + read-write + + + F0_POLE + Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high + 3 + 1 + read-write + + + F1_POLE + Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high + 4 + 1 + read-write + + + F2_POLE + Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high + 5 + 1 + read-write + + + EVENT_F0 + Set and reset by hardware. If set, event_f0 is on going + 6 + 1 + read-only + + + EVENT_F1 + Set and reset by hardware. If set, event_f1 is on going + 7 + 1 + read-only + + + EVENT_F2 + Set and reset by hardware. If set, event_f2 is on going + 8 + 1 + read-only + + + + + CAP_TIMER_CFG + Configure capture timer + 0xE8 + 0x20 + + + CAP_TIMER_EN + When set, capture timer incrementing under APB_clk is enabled. + 0 + 1 + read-write + + + CAP_SYNCI_EN + When set, capture timer sync is enabled. + 1 + 1 + read-write + + + CAP_SYNCI_SEL + capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1 sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix + 2 + 3 + read-write + + + CAP_SYNC_SW + Write 1 will force a capture timer sync, capture timer is loaded with value in phase register. + 5 + 1 + write-only + + + + + CAP_TIMER_PHASE + Phase for capture timer sync + 0xEC + 0x20 + + + CAP_PHASE + Phase value for capture timer sync operation. + 0 + 32 + read-write + + + + + CAP_CH0_CFG + Capture channel 0 configuration and enable + 0xF0 + 0x20 + + + CAP0_EN + When set, capture on channel 0 is enabled + 0 + 1 + read-write + + + CAP0_MODE + Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge. + 1 + 2 + read-write + + + CAP0_PRESCALE + Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1 + 3 + 8 + read-write + + + CAP0_IN_INVERT + when set, CAP0 form GPIO matrix is inverted before prescale + 11 + 1 + read-write + + + CAP0_SW + Write 1 will trigger a software forced capture on channel 0 + 12 + 1 + write-only + + + + + CAP_CH1_CFG + Capture channel 1 configuration and enable + 0xF4 + 0x20 + + + CAP1_EN + When set, capture on channel 2 is enabled + 0 + 1 + read-write + + + CAP1_MODE + Edge of capture on channel 1 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge. + 1 + 2 + read-write + + + CAP1_PRESCALE + Value of prescaling on possitive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE + 1 + 3 + 8 + read-write + + + CAP1_IN_INVERT + when set, CAP1 form GPIO matrix is inverted before prescale + 11 + 1 + read-write + + + CAP1_SW + Write 1 will trigger a software forced capture on channel 1 + 12 + 1 + write-only + + + + + CAP_CH2_CFG + Capture channel 2 configuration and enable + 0xF8 + 0x20 + + + CAP2_EN + When set, capture on channel 2 is enabled + 0 + 1 + read-write + + + CAP2_MODE + Edge of capture on channel 2 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge. + 1 + 2 + read-write + + + CAP2_PRESCALE + Value of prescaling on possitive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE + 1 + 3 + 8 + read-write + + + CAP2_IN_INVERT + when set, CAP2 form GPIO matrix is inverted before prescale + 11 + 1 + read-write + + + CAP2_SW + Write 1 will trigger a software forced capture on channel 2 + 12 + 1 + write-only + + + + + CAP_CH0 + Value of last capture on channel 0 + 0xFC + 0x20 + + + CAP0_VALUE + Value of last capture on channel 0 + 0 + 32 + read-only + + + + + CAP_CH1 + Value of last capture on channel 1 + 0x100 + 0x20 + + + CAP1_VALUE + Value of last capture on channel 1 + 0 + 32 + read-only + + + + + CAP_CH2 + Value of last capture on channel 2 + 0x104 + 0x20 + + + CAP2_VALUE + Value of last capture on channel 2 + 0 + 32 + read-only + + + + + CAP_STATUS + Edge of last capture trigger + 0x108 + 0x20 + + + CAP0_EDGE + Edge of last capture trigger on channel 0, 0: posedge, 1: negedge + 0 + 1 + read-only + + + CAP1_EDGE + Edge of last capture trigger on channel 1, 0: posedge, 1: negedge + 1 + 1 + read-only + + + CAP2_EDGE + Edge of last capture trigger on channel 2, 0: posedge, 1: negedge + 2 + 1 + read-only + + + + + UPDATE_CFG + Enable update. + 0x10C + 0x20 + 0x00000055 + + + GLOBAL_UP_EN + The global enable of update of all active registers in MCPWM module + 0 + 1 + read-write + + + GLOBAL_FORCE_UP + a toggle (software invert its value) will trigger a forced update of all active registers in MCPWM module + 1 + 1 + read-write + + + OP0_UP_EN + When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0 are enabled + 2 + 1 + read-write + + + OP0_FORCE_UP + a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 0 + 3 + 1 + read-write + + + OP1_UP_EN + When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1 are enabled + 4 + 1 + read-write + + + OP1_FORCE_UP + a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 1 + 5 + 1 + read-write + + + OP2_UP_EN + When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2 are enabled + 6 + 1 + read-write + + + OP2_FORCE_UP + a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 2 + 7 + 1 + read-write + + + + + INT_ENA + Interrupt enable bits + 0x110 + 0x20 + + + TIMER0_STOP_INT_ENA + The enable bit for the interrupt triggered when the timer 0 stops. + 0 + 1 + read-write + + + TIMER1_STOP_INT_ENA + The enable bit for the interrupt triggered when the timer 1 stops. + 1 + 1 + read-write + + + TIMER2_STOP_INT_ENA + The enable bit for the interrupt triggered when the timer 2 stops. + 2 + 1 + read-write + + + TIMER0_TEZ_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + read-write + + + TIMER1_TEZ_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + read-write + + + TIMER2_TEZ_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + read-write + + + TIMER0_TEP_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + read-write + + + TIMER1_TEP_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + read-write + + + TIMER2_TEP_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + read-write + + + FAULT0_INT_ENA + The enable bit for the interrupt triggered when event_f0 starts. + 9 + 1 + read-write + + + FAULT1_INT_ENA + The enable bit for the interrupt triggered when event_f1 starts. + 10 + 1 + read-write + + + FAULT2_INT_ENA + The enable bit for the interrupt triggered when event_f2 starts. + 11 + 1 + read-write + + + FAULT0_CLR_INT_ENA + The enable bit for the interrupt triggered when event_f0 ends. + 12 + 1 + read-write + + + FAULT1_CLR_INT_ENA + The enable bit for the interrupt triggered when event_f1 ends. + 13 + 1 + read-write + + + FAULT2_CLR_INT_ENA + The enable bit for the interrupt triggered when event_f2 ends. + 14 + 1 + read-write + + + CMPR0_TEA_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + read-write + + + CMPR1_TEA_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + read-write + + + CMPR2_TEA_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + read-write + + + CMPR0_TEB_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + read-write + + + CMPR1_TEB_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + read-write + + + CMPR2_TEB_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + read-write + + + TZ0_CBC_INT_ENA + The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + read-write + + + TZ1_CBC_INT_ENA + The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + read-write + + + TZ2_CBC_INT_ENA + The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + read-write + + + TZ0_OST_INT_ENA + The enable bit for the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + read-write + + + TZ1_OST_INT_ENA + The enable bit for the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + read-write + + + TZ2_OST_INT_ENA + The enable bit for the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + read-write + + + CAP0_INT_ENA + The enable bit for the interrupt triggered by capture on channel 0. + 27 + 1 + read-write + + + CAP1_INT_ENA + The enable bit for the interrupt triggered by capture on channel 1. + 28 + 1 + read-write + + + CAP2_INT_ENA + The enable bit for the interrupt triggered by capture on channel 2. + 29 + 1 + read-write + + + + + INT_RAW + Raw interrupt status + 0x114 + 0x20 + + + TIMER0_STOP_INT_RAW + The raw status bit for the interrupt triggered when the timer 0 stops. + 0 + 1 + read-write + + + TIMER1_STOP_INT_RAW + The raw status bit for the interrupt triggered when the timer 1 stops. + 1 + 1 + read-write + + + TIMER2_STOP_INT_RAW + The raw status bit for the interrupt triggered when the timer 2 stops. + 2 + 1 + read-write + + + TIMER0_TEZ_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + read-write + + + TIMER1_TEZ_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + read-write + + + TIMER2_TEZ_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + read-write + + + TIMER0_TEP_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + read-write + + + TIMER1_TEP_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + read-write + + + TIMER2_TEP_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + read-write + + + FAULT0_INT_RAW + The raw status bit for the interrupt triggered when event_f0 starts. + 9 + 1 + read-write + + + FAULT1_INT_RAW + The raw status bit for the interrupt triggered when event_f1 starts. + 10 + 1 + read-write + + + FAULT2_INT_RAW + The raw status bit for the interrupt triggered when event_f2 starts. + 11 + 1 + read-write + + + FAULT0_CLR_INT_RAW + The raw status bit for the interrupt triggered when event_f0 ends. + 12 + 1 + read-write + + + FAULT1_CLR_INT_RAW + The raw status bit for the interrupt triggered when event_f1 ends. + 13 + 1 + read-write + + + FAULT2_CLR_INT_RAW + The raw status bit for the interrupt triggered when event_f2 ends. + 14 + 1 + read-write + + + CMPR0_TEA_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + read-write + + + CMPR1_TEA_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + read-write + + + CMPR2_TEA_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + read-write + + + CMPR0_TEB_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + read-write + + + CMPR1_TEB_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + read-write + + + CMPR2_TEB_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + read-write + + + TZ0_CBC_INT_RAW + The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + read-write + + + TZ1_CBC_INT_RAW + The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + read-write + + + TZ2_CBC_INT_RAW + The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + read-write + + + TZ0_OST_INT_RAW + The raw status bit for the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + read-write + + + TZ1_OST_INT_RAW + The raw status bit for the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + read-write + + + TZ2_OST_INT_RAW + The raw status bit for the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + read-write + + + CAP0_INT_RAW + The raw status bit for the interrupt triggered by capture on channel 0. + 27 + 1 + read-write + + + CAP1_INT_RAW + The raw status bit for the interrupt triggered by capture on channel 1. + 28 + 1 + read-write + + + CAP2_INT_RAW + The raw status bit for the interrupt triggered by capture on channel 2. + 29 + 1 + read-write + + + + + INT_ST + Masked interrupt status + 0x118 + 0x20 + + + TIMER0_STOP_INT_ST + The masked status bit for the interrupt triggered when the timer 0 stops. + 0 + 1 + read-only + + + TIMER1_STOP_INT_ST + The masked status bit for the interrupt triggered when the timer 1 stops. + 1 + 1 + read-only + + + TIMER2_STOP_INT_ST + The masked status bit for the interrupt triggered when the timer 2 stops. + 2 + 1 + read-only + + + TIMER0_TEZ_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + read-only + + + TIMER1_TEZ_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + read-only + + + TIMER2_TEZ_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + read-only + + + TIMER0_TEP_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + read-only + + + TIMER1_TEP_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + read-only + + + TIMER2_TEP_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + read-only + + + FAULT0_INT_ST + The masked status bit for the interrupt triggered when event_f0 starts. + 9 + 1 + read-only + + + FAULT1_INT_ST + The masked status bit for the interrupt triggered when event_f1 starts. + 10 + 1 + read-only + + + FAULT2_INT_ST + The masked status bit for the interrupt triggered when event_f2 starts. + 11 + 1 + read-only + + + FAULT0_CLR_INT_ST + The masked status bit for the interrupt triggered when event_f0 ends. + 12 + 1 + read-only + + + FAULT1_CLR_INT_ST + The masked status bit for the interrupt triggered when event_f1 ends. + 13 + 1 + read-only + + + FAULT2_CLR_INT_ST + The masked status bit for the interrupt triggered when event_f2 ends. + 14 + 1 + read-only + + + CMPR0_TEA_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + read-only + + + CMPR1_TEA_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + read-only + + + CMPR2_TEA_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + read-only + + + CMPR0_TEB_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + read-only + + + CMPR1_TEB_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + read-only + + + CMPR2_TEB_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + read-only + + + TZ0_CBC_INT_ST + The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + read-only + + + TZ1_CBC_INT_ST + The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + read-only + + + TZ2_CBC_INT_ST + The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + read-only + + + TZ0_OST_INT_ST + The masked status bit for the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + read-only + + + TZ1_OST_INT_ST + The masked status bit for the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + read-only + + + TZ2_OST_INT_ST + The masked status bit for the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + read-only + + + CAP0_INT_ST + The masked status bit for the interrupt triggered by capture on channel 0. + 27 + 1 + read-only + + + CAP1_INT_ST + The masked status bit for the interrupt triggered by capture on channel 1. + 28 + 1 + read-only + + + CAP2_INT_ST + The masked status bit for the interrupt triggered by capture on channel 2. + 29 + 1 + read-only + + + + + INT_CLR + Interrupt clear bits + 0x11C + 0x20 + + + TIMER0_STOP_INT_CLR + Set this bit to clear the interrupt triggered when the timer 0 stops. + 0 + 1 + write-only + + + TIMER1_STOP_INT_CLR + Set this bit to clear the interrupt triggered when the timer 1 stops. + 1 + 1 + write-only + + + TIMER2_STOP_INT_CLR + Set this bit to clear the interrupt triggered when the timer 2 stops. + 2 + 1 + write-only + + + TIMER0_TEZ_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + write-only + + + TIMER1_TEZ_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + write-only + + + TIMER2_TEZ_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + write-only + + + TIMER0_TEP_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + write-only + + + TIMER1_TEP_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + write-only + + + TIMER2_TEP_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + write-only + + + FAULT0_INT_CLR + Set this bit to clear the interrupt triggered when event_f0 starts. + 9 + 1 + write-only + + + FAULT1_INT_CLR + Set this bit to clear the interrupt triggered when event_f1 starts. + 10 + 1 + write-only + + + FAULT2_INT_CLR + Set this bit to clear the interrupt triggered when event_f2 starts. + 11 + 1 + write-only + + + FAULT0_CLR_INT_CLR + Set this bit to clear the interrupt triggered when event_f0 ends. + 12 + 1 + write-only + + + FAULT1_CLR_INT_CLR + Set this bit to clear the interrupt triggered when event_f1 ends. + 13 + 1 + write-only + + + FAULT2_CLR_INT_CLR + Set this bit to clear the interrupt triggered when event_f2 ends. + 14 + 1 + write-only + + + CMPR0_TEA_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + write-only + + + CMPR1_TEA_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + write-only + + + CMPR2_TEA_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + write-only + + + CMPR0_TEB_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + write-only + + + CMPR1_TEB_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + write-only + + + CMPR2_TEB_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + write-only + + + TZ0_CBC_INT_CLR + Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + write-only + + + TZ1_CBC_INT_CLR + Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + write-only + + + TZ2_CBC_INT_CLR + Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + write-only + + + TZ0_OST_INT_CLR + Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + write-only + + + TZ1_OST_INT_CLR + Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + write-only + + + TZ2_OST_INT_CLR + Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + write-only + + + CAP0_INT_CLR + Set this bit to clear the interrupt triggered by capture on channel 0. + 27 + 1 + write-only + + + CAP1_INT_CLR + Set this bit to clear the interrupt triggered by capture on channel 1. + 28 + 1 + write-only + + + CAP2_INT_CLR + Set this bit to clear the interrupt triggered by capture on channel 2. + 29 + 1 + write-only + + + + + CLK + MCPWM APB configuration register + 0x120 + 0x20 + + + EN + Force clock on for this register file + 0 + 1 + read-write + + + + + VERSION + Version register. + 0x124 + 0x20 + 0x01509110 + + + DATE + Version of this register file + 0 + 28 + read-write + + + + + + + MCPWM1 + Motor Control Pulse-Width Modulation 1 + 0x6002C000 + + MCPWM1 + 32 + + + + RMT + Remote Control + RMT + 0x60016000 + + 0x0 + 0xD0 + registers + + + RMT + 40 + + + + 4 + 0x4 + TX_CH%sDATA + The read and write data register for CHANNEL%s by apb fifo access. + 0x0 + 0x20 + + + CHDATA + Read and write data for channel %s via APB FIFO. + 0 + 32 + read-only + + + + + 4 + 0x4 + RX_CH%sDATA + The read and write data register for CHANNEL$n by apb fifo access. + 0x10 + 0x20 + + + CHDATA + Read and write data for channel 0 via APB FIFO. + 0 + 32 + read-only + + + + + 4 + 0x4 + CH%s_TX_CONF0 + Channel %s configure register 0 + 0x20 + 0x20 + 0x00710200 + + + TX_START + Set this bit to start sending data on CHANNEL%s. + 0 + 1 + write-only + + + MEM_RD_RST + Set this bit to reset read ram address for CHANNEL%s by accessing transmitter. + 1 + 1 + write-only + + + APB_MEM_RST + Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + 2 + 1 + write-only + + + TX_CONTI_MODE + Set this bit to restart transmission from the first data to the last data in CHANNEL%s. + 3 + 1 + read-write + + + MEM_TX_WRAP_EN + This is the channel %s enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size. + 4 + 1 + read-write + + + IDLE_OUT_LV + This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state. + 5 + 1 + read-write + + + IDLE_OUT_EN + This is the output enable-control bit for CHANNEL%s in IDLE state. + 6 + 1 + read-write + + + TX_STOP + Set this bit to stop the transmitter of CHANNEL%s sending data out. + 7 + 1 + read-write + + + DIV_CNT + This register is used to configure the divider for clock of CHANNEL%s. + 8 + 8 + read-write + + + MEM_SIZE + This register is used to configure the maximum size of memory allocated to CHANNEL%s. + 16 + 4 + read-write + + + CARRIER_EFF_EN + 1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1. + 20 + 1 + read-write + + + CARRIER_EN + This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. + 21 + 1 + read-write + + + CARRIER_OUT_LV + This bit is used to configure the position of carrier wave for CHANNEL%s. + +1'h0: add carrier wave on low level. + +1'h1: add carrier wave on high level. + 22 + 1 + read-write + + + AFIFO_RST + Reserved + 23 + 1 + write-only + + + CONF_UPDATE + synchronization bit for CHANNEL%s + 24 + 1 + write-only + + + + + 4 + 0x8 + CH%s_RX_CONF0 + Channel %s configure register 0 + 0x30 + 0x20 + 0x317FFF02 + + + DIV_CNT + This register is used to configure the divider for clock of CHANNEL%s. + 0 + 8 + read-write + + + IDLE_THRES + When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished. + 8 + 15 + read-write + + + MEM_SIZE + This register is used to configure the maximum size of memory allocated to CHANNEL%s. + 24 + 4 + read-write + + + CARRIER_EN + This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. + 28 + 1 + read-write + + + CARRIER_OUT_LV + This bit is used to configure the position of carrier wave for CHANNEL%s. + +1'h0: add carrier wave on low level. + +1'h1: add carrier wave on high level. + 29 + 1 + read-write + + + + + 4 + 0x8 + CH%s_RX_CONF1 + Channel %s configure register 1 + 0x34 + 0x20 + 0x000001E8 + + + RX_EN + Set this bit to enable receiver to receive data on CHANNEL%s. + 0 + 1 + read-write + + + MEM_WR_RST + Set this bit to reset write ram address for CHANNEL%s by accessing receiver. + 1 + 1 + write-only + + + APB_MEM_RST + Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + 2 + 1 + write-only + + + MEM_OWNER + This register marks the ownership of CHANNEL%s's ram block. + +1'h1: Receiver is using the ram. + +1'h0: APB bus is using the ram. + 3 + 1 + read-write + + + RX_FILTER_EN + This is the receive filter's enable bit for CHANNEL%s. + 4 + 1 + read-write + + + RX_FILTER_THRES + Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode). + 5 + 8 + read-write + + + MEM_RX_WRAP_EN + This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size. + 13 + 1 + read-write + + + AFIFO_RST + Reserved + 14 + 1 + write-only + + + CONF_UPDATE + synchronization bit for CHANNEL%s + 15 + 1 + write-only + + + + + 4 + 0x4 + CH%s_TX_STATUS + Channel %s status register + 0x50 + 0x20 + + + MEM_RADDR_EX + This register records the memory address offset when transmitter of CHANNEL%s is using the RAM. + 0 + 10 + read-only + + + APB_MEM_WADDR + This register records the memory address offset when writes RAM over APB bus. + 11 + 10 + read-only + + + STATE + This register records the FSM status of CHANNEL%s. + 22 + 3 + read-only + + + MEM_EMPTY + This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled. + 25 + 1 + read-only + + + APB_MEM_WR_ERR + This status bit will be set if the offset address out of memory size when writes via APB bus. + 26 + 1 + read-only + + + + + 4 + 0x4 + CH%s_RX_STATUS + Channel %s status register + 0x60 + 0x20 + 0x000600C0 + + + MEM_WADDR_EX + This register records the memory address offset when receiver of CHANNEL%s is using the RAM. + 0 + 10 + read-only + + + APB_MEM_RADDR + This register records the memory address offset when reads RAM over APB bus. + 11 + 10 + read-only + + + STATE + This register records the FSM status of CHANNEL%s. + 22 + 3 + read-only + + + MEM_OWNER_ERR + This status bit will be set when the ownership of memory block is wrong. + 25 + 1 + read-only + + + MEM_FULL + This status bit will be set if the receiver receives more data than the memory size. + 26 + 1 + read-only + + + APB_MEM_RD_ERR + This status bit will be set if the offset address out of memory size when reads via APB bus. + 27 + 1 + read-only + + + + + INT_RAW + Raw interrupt status + 0x70 + 0x20 + + + 4 + 0x1 + 0-3 + CH%s_TX_END_INT_RAW + The interrupt raw bit for CHANNEL%s. Triggered when transmission done. + 0 + 1 + read-write + + + 4 + 0x1 + 0-3 + CH%s_TX_ERR_INT_RAW + The interrupt raw bit for CHANNEL%s. Triggered when error occurs. + 4 + 1 + read-write + + + 4 + 0x1 + 0-3 + CH%s_TX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL%s. Triggered when transmitter sent more data than configured value. + 8 + 1 + read-write + + + 4 + 0x1 + 0-3 + CH%s_TX_LOOP_INT_RAW + The interrupt raw bit for CHANNEL%s. Triggered when the loop count reaches the configured threshold value. + 12 + 1 + read-write + + + 4 + 0x1 + 4-7 + CH%s_RX_END_INT_RAW + The interrupt raw bit for CHANNEL4. Triggered when reception done. + 16 + 1 + read-write + + + 4 + 0x1 + 4-7 + CH%s_RX_ERR_INT_RAW + The interrupt raw bit for CHANNEL4. Triggered when error occurs. + 20 + 1 + read-write + + + CH4_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than configured value. + 24 + 1 + read-write + + + CH5_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL5. Triggered when receiver receive more data than configured value. + 25 + 1 + read-write + + + CH6_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL6. Triggered when receiver receive more data than configured value. + 26 + 1 + read-write + + + CH7_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL7. Triggered when receiver receive more data than configured value. + 27 + 1 + read-write + + + TX_CH3_DMA_ACCESS_FAIL_INT_RAW + The interrupt raw bit for CHANNEL3. Triggered when dma accessing CHANNEL3 fails. + 28 + 1 + read-write + + + RX_CH7_DMA_ACCESS_FAIL_INT_RAW + The interrupt raw bit for CHANNEL7. Triggered when dma accessing CHANNEL7 fails. + 29 + 1 + read-write + + + + + INT_ST + Masked interrupt status + 0x74 + 0x20 + + + 4 + 0x1 + 0-3 + CH%s_TX_END_INT_ST + The masked interrupt status bit for CH%s_TX_END_INT. + 0 + 1 + read-only + + + 4 + 0x1 + 0-3 + CH%s_TX_ERR_INT_ST + The masked interrupt status bit for CH%s_ERR_INT. + 4 + 1 + read-only + + + 4 + 0x1 + 0-3 + CH%s_TX_THR_EVENT_INT_ST + The masked interrupt status bit for CH%s_TX_THR_EVENT_INT. + 8 + 1 + read-only + + + 4 + 0x1 + 0-3 + CH%s_TX_LOOP_INT_ST + The masked interrupt status bit for CH%s_TX_LOOP_INT. + 12 + 1 + read-only + + + 4 + 0x1 + 4-7 + CH%s_RX_END_INT_ST + The masked interrupt status bit for CH4_RX_END_INT. + 16 + 1 + read-only + + + 4 + 0x1 + 4-7 + CH%s_RX_ERR_INT_ST + The masked interrupt status bit for CH4_ERR_INT. + 20 + 1 + read-only + + + CH4_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH4_RX_THR_EVENT_INT. + 24 + 1 + read-only + + + CH5_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH5_RX_THR_EVENT_INT. + 25 + 1 + read-only + + + CH6_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH6_RX_THR_EVENT_INT. + 26 + 1 + read-only + + + CH7_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH7_RX_THR_EVENT_INT. + 27 + 1 + read-only + + + TX_CH3_DMA_ACCESS_FAIL_INT_ST + The masked interrupt status bit for CH3_DMA_ACCESS_FAIL_INT. + 28 + 1 + read-only + + + RX_CH7_DMA_ACCESS_FAIL_INT_ST + The masked interrupt status bit for CH7_DMA_ACCESS_FAIL_INT. + 29 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0x78 + 0x20 + + + 4 + 0x1 + 0-3 + CH%s_TX_END_INT_ENA + The interrupt enable bit for CH%s_TX_END_INT. + 0 + 1 + read-write + + + 4 + 0x1 + 0-3 + CH%s_TX_ERR_INT_ENA + The interrupt enable bit for CH%s_ERR_INT. + 4 + 1 + read-write + + + 4 + 0x1 + 0-3 + CH%s_TX_THR_EVENT_INT_ENA + The interrupt enable bit for CH%s_TX_THR_EVENT_INT. + 8 + 1 + read-write + + + 4 + 0x1 + 0-3 + CH%s_TX_LOOP_INT_ENA + The interrupt enable bit for CH%s_TX_LOOP_INT. + 12 + 1 + read-write + + + 4 + 0x1 + 4-7 + CH%s_RX_END_INT_ENA + The interrupt enable bit for CH4_RX_END_INT. + 16 + 1 + read-write + + + 4 + 0x1 + 4-7 + CH%s_RX_ERR_INT_ENA + The interrupt enable bit for CH4_ERR_INT. + 20 + 1 + read-write + + + CH4_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH4_RX_THR_EVENT_INT. + 24 + 1 + read-write + + + CH5_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH5_RX_THR_EVENT_INT. + 25 + 1 + read-write + + + CH6_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH6_RX_THR_EVENT_INT. + 26 + 1 + read-write + + + CH7_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH7_RX_THR_EVENT_INT. + 27 + 1 + read-write + + + TX_CH3_DMA_ACCESS_FAIL_INT_ENA + The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT. + 28 + 1 + read-write + + + RX_CH7_DMA_ACCESS_FAIL_INT_ENA + The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT. + 29 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x7C + 0x20 + + + 4 + 0x1 + 0-3 + CH%s_TX_END_INT_CLR + Set this bit to clear theCH%s_TX_END_INT interrupt. + 0 + 1 + write-only + + + 4 + 0x1 + 0-3 + CH%s_TX_ERR_INT_CLR + Set this bit to clear theCH%s_ERR_INT interrupt. + 4 + 1 + write-only + + + 4 + 0x1 + 0-3 + CH%s_TX_THR_EVENT_INT_CLR + Set this bit to clear theCH%s_TX_THR_EVENT_INT interrupt. + 8 + 1 + write-only + + + 4 + 0x1 + 0-3 + CH%s_TX_LOOP_INT_CLR + Set this bit to clear theCH%s_TX_LOOP_INT interrupt. + 12 + 1 + write-only + + + 4 + 0x1 + 4-7 + CH%s_RX_END_INT_CLR + Set this bit to clear theCH4_RX_END_INT interrupt. + 16 + 1 + write-only + + + 4 + 0x1 + RX_CH4,RX_CH5,RX_CH6,RX_CH7 + CH%s_RX_ERR_INT_CLR + Set this bit to clear theCH4_ERR_INT interrupt. + 20 + 1 + write-only + + + CH4_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt. + 24 + 1 + write-only + + + CH5_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt. + 25 + 1 + write-only + + + CH6_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt. + 26 + 1 + write-only + + + CH7_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt. + 27 + 1 + write-only + + + TX_CH3_DMA_ACCESS_FAIL_INT_CLR + Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt. + 28 + 1 + write-only + + + RX_CH7_DMA_ACCESS_FAIL_INT_CLR + Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt. + 29 + 1 + write-only + + + + + 4 + 0x4 + CH%sCARRIER_DUTY + Channel %s duty cycle configuration register + 0x80 + 0x20 + 0x00400040 + + + CARRIER_LOW + This register is used to configure carrier wave 's low level clock period for CHANNEL%s. + 0 + 16 + read-write + + + CARRIER_HIGH + This register is used to configure carrier wave 's high level clock period for CHANNEL%s. + 16 + 16 + read-write + + + + + 4 + 0x4 + CH%s_RX_CARRIER_RM + Channel %s carrier remove register + 0x90 + 0x20 + + + CARRIER_LOW_THRES + The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s. + 0 + 16 + read-write + + + CARRIER_HIGH_THRES + The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s. + 16 + 16 + read-write + + + + + 4 + 0x4 + CH%s_TX_LIM + Channel %s Tx event configuration register + 0xA0 + 0x20 + 0x00000080 + + + TX_LIM + This register is used to configure the maximum entries that CHANNEL%s can send out. + 0 + 9 + read-write + + + TX_LOOP_NUM + This register is used to configure the maximum loop count when tx_conti_mode is valid. + 9 + 10 + read-write + + + TX_LOOP_CNT_EN + This register is the enabled bit for loop count. + 19 + 1 + read-write + + + LOOP_COUNT_RESET + This register is used to reset the loop count when tx_conti_mode is valid. + 20 + 1 + write-only + + + LOOP_STOP_EN + This bit is used to enable the loop send stop function after the loop counter counts to loop number for CHANNEL%s. + 21 + 1 + read-write + + + + + 4 + 0x4 + CH%s_RX_LIM + Channel %s Rx event configuration register + 0xB0 + 0x20 + 0x00000080 + + + RX_LIM + This register is used to configure the maximum entries that CHANNEL%s can receive. + 0 + 9 + read-write + + + + + SYS_CONF + RMT apb configuration register + 0xC0 + 0x20 + 0x05000010 + + + APB_FIFO_MASK + 1'h1: access memory directly. 1'h0: access memory by FIFO. + 0 + 1 + read-write + + + MEM_CLK_FORCE_ON + Set this bit to enable the clock for RMT memory. + 1 + 1 + read-write + + + MEM_FORCE_PD + Set this bit to power down RMT memory. + 2 + 1 + read-write + + + MEM_FORCE_PU + 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode. + 3 + 1 + read-write + + + SCLK_DIV_NUM + the integral part of the fractional divisor + 4 + 8 + read-write + + + SCLK_DIV_A + the numerator of the fractional part of the fractional divisor + 12 + 6 + read-write + + + SCLK_DIV_B + the denominator of the fractional part of the fractional divisor + 18 + 6 + read-write + + + SCLK_SEL + choose the clock source of rmt_sclk. 1:CLK_80Mhz;2:CLK_8MHz; 2:XTAL + 24 + 2 + read-write + + + SCLK_ACTIVE + rmt_sclk switch + 26 + 1 + read-write + + + CLK_EN + RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers + 31 + 1 + read-write + + + + + TX_SIM + RMT TX synchronous register + 0xC4 + 0x20 + + + CH0 + Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels. + 0 + 1 + read-write + + + CH1 + Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels. + 1 + 1 + read-write + + + CH2 + Set this bit to enable CHANNEL2 to start sending data synchronously with other enabled channels. + 2 + 1 + read-write + + + CH3 + Set this bit to enable CHANNEL3 to start sending data synchronously with other enabled channels. + 3 + 1 + read-write + + + EN + This register is used to enable multiple of channels to start sending data synchronously. + 4 + 1 + read-write + + + + + REF_CNT_RST + RMT clock divider reset register + 0xC8 + 0x20 + + + 8 + 0x1 + TX_REF_CNT_RST_CH0,TX_REF_CNT_RST_CH1,TX_REF_CNT_RST_CH2,TX_REF_CNT_RST_CH3,RX_REF_CNT_RST_CH4,RX_REF_CNT_RST_CH5,RX_REF_CNT_RST_CH6,RX_REF_CNT_RST_CH7 + CH%s + This register is used to reset the clock divider of CHANNEL0. + 0 + 1 + write-only + + + + + DATE + RMT version register + 0xCC + 0x20 + 0x02101181 + + + DATE + This is the version register. + 0 + 28 + read-write + + + + + + + RNG + Hardware Random Number Generator + RNG + 0x60034F6C + + 0x0 + 0x4 + registers + + + + DATA + Random number data + 0x110 + 0x20 + read-only + + + + + RSA + RSA (Rivest Shamir Adleman) Accelerator + RSA + 0x6003C000 + + 0x0 + 0x834 + registers + + + RSA + 76 + + + + 512 + 0x1 + M_MEM[%s] + Memory M + 0x0 + 0x8 + write-only + + + 512 + 0x1 + Z_MEM[%s] + Memory Z + 0x200 + 0x8 + read-write + + + 512 + 0x1 + Y_MEM[%s] + Memory Y + 0x400 + 0x8 + write-only + + + 512 + 0x1 + X_MEM[%s] + Memory X + 0x600 + 0x8 + write-only + + + M_PRIME + RSA M' register + 0x800 + 0x20 + + + M_PRIME + Stores M' + 0 + 32 + read-write + + + + + MODE + RSA length mode register + 0x804 + 0x20 + + + MODE + Stores the RSA length mode + 0 + 7 + read-write + + + + + CLEAN + RSA clean register + 0x808 + 0x20 + + + CLEAN + The content of this bit is 1 when memories complete initialization. + 0 + 1 + read-only + + + + + MODEXP_START + Modular exponentiation trigger register. + 0x80C + 0x20 + + + MODEXP_START + Set this bit to 1 to start the modular exponentiation. + 0 + 1 + write-only + + + + + MODMULT_START + Modular multiplication trigger register. + 0x810 + 0x20 + + + MODMULT_START + Set this bit to 1 to start the modular multiplication + 0 + 1 + write-only + + + + + MULT_START + Normal multiplication trigger register. + 0x814 + 0x20 + + + MULT_START + Set this bit to 1 to start the multiplicaiton. + 0 + 1 + write-only + + + + + IDLE + RSA idle register + 0x818 + 0x20 + + + IDLE + The content of this bit is 1 when the RSA accelerator is idle. + 0 + 1 + read-only + + + + + CLEAR_INTERRUPT + RSA interrupt clear register + 0x81C + 0x20 + + + CLEAR_INTERRUPT + set this bit to 1 to clear the RSA interrupt. + 0 + 1 + write-only + + + + + CONSTANT_TIME + CONSTANT_TIME option control register + 0x820 + 0x20 + 0x00000001 + + + CONSTANT_TIME + Controls the CONSTANT_TIME option. 0: acceleration. 1: no acceleration(by default). + 0 + 1 + read-write + + + + + SEARCH_ENABLE + SEARCH option enable register + 0x824 + 0x20 + + + SEARCH_ENABLE + Controls the SEARCH option. 0: no acceleration(by default). 1: acceleration. + 0 + 1 + read-write + + + + + SEARCH_POS + RSA search position configure register + 0x828 + 0x20 + + + SEARCH_POS + This field is used to configure the starting search position when the acceleration option of SEARCH is used. + 0 + 12 + read-write + + + + + INTERRUPT_ENA + RSA interrupt enable register + 0x82C + 0x20 + + + INTERRUPT_ENA + Set this bit to 1 to enable the RSA interrupt. This option is enabled by default. + 0 + 1 + read-write + + + + + DATE + RSA version control register + 0x830 + 0x20 + 0x20191231 + + + DATE + rsa version information + 0 + 30 + read-write + + + + + + + RTC_CNTL + Real-Time Clock Control + RTC_CNTL + 0x60008000 + + 0x0 + 0x15C + registers + + + RTC_CORE + 39 + + + + OPTIONS0 + RTC common configure register + 0x0 + 0x20 + 0x1C00A000 + + + SW_STALL_APPCPU_C0 + {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU + 0 + 2 + read-write + + + SW_STALL_PROCPU_C0 + {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU + 2 + 2 + read-write + + + SW_APPCPU_RST + APP CPU SW reset + 4 + 1 + write-only + + + SW_PROCPU_RST + PRO CPU SW reset + 5 + 1 + write-only + + + BB_I2C_FORCE_PD + BB_I2C force power down + 6 + 1 + read-write + + + BB_I2C_FORCE_PU + BB_I2C force power up + 7 + 1 + read-write + + + BBPLL_I2C_FORCE_PD + BB_PLL _I2C force power down + 8 + 1 + read-write + + + BBPLL_I2C_FORCE_PU + BB_PLL_I2C force power up + 9 + 1 + read-write + + + BBPLL_FORCE_PD + BB_PLL force power down + 10 + 1 + read-write + + + BBPLL_FORCE_PU + BB_PLL force power up + 11 + 1 + read-write + + + XTL_FORCE_PD + crystall force power down + 12 + 1 + read-write + + + XTL_FORCE_PU + crystall force power up + 13 + 1 + read-write + + + XTL_EN_WAIT + wait bias_sleep and current source wakeup + 14 + 4 + read-write + + + XTL_FORCE_ISO + No public + 23 + 1 + read-write + + + PLL_FORCE_ISO + No public + 24 + 1 + read-write + + + ANALOG_FORCE_ISO + No public + 25 + 1 + read-write + + + XTL_FORCE_NOISO + No public + 26 + 1 + read-write + + + PLL_FORCE_NOISO + No public + 27 + 1 + read-write + + + ANALOG_FORCE_NOISO + No public + 28 + 1 + read-write + + + DG_WRAP_FORCE_RST + digital wrap force reset in deep sleep + 29 + 1 + read-write + + + DG_WRAP_FORCE_NORST + digital core force no reset in deep sleep + 30 + 1 + read-write + + + SW_SYS_RST + SW system reset + 31 + 1 + write-only + + + + + SLP_TIMER0 + configure min sleep time + 0x4 + 0x20 + + + SLP_VAL_LO + RTC sleep timer low 32 bits + 0 + 32 + read-write + + + + + SLP_TIMER1 + configure sleep time hi + 0x8 + 0x20 + + + SLP_VAL_HI + RTC sleep timer high 16 bits + 0 + 16 + read-write + + + MAIN_TIMER_ALARM_EN + timer alarm enable bit + 16 + 1 + write-only + + + + + TIME_UPDATE + update rtc main timer + 0xC + 0x20 + + + TIMER_SYS_STALL + Enable to record system stall time + 27 + 1 + read-write + + + TIMER_XTL_OFF + Enable to record 40M XTAL OFF time + 28 + 1 + read-write + + + TIMER_SYS_RST + enable to record system reset time + 29 + 1 + read-write + + + TIME_UPDATE + Set 1: to update register with RTC timer + 31 + 1 + write-only + + + + + TIME_LOW0 + read rtc_main timer low bits + 0x10 + 0x20 + + + TIMER_VALUE0_LOW + RTC timer low 32 bits + 0 + 32 + read-only + + + + + TIME_HIGH0 + read rtc_main timer high bits + 0x14 + 0x20 + + + TIMER_VALUE0_HIGH + RTC timer high 16 bits + 0 + 16 + read-only + + + + + STATE0 + configure chip sleep + 0x18 + 0x20 + + + SW_CPU_INT + rtc software interrupt to main cpu + 0 + 1 + write-only + + + SLP_REJECT_CAUSE_CLR + clear rtc sleep reject cause + 1 + 1 + write-only + + + APB2RTC_BRIDGE_SEL + 1: APB to RTC using bridge, 0: APB to RTC using sync + 22 + 1 + read-write + + + SDIO_ACTIVE_IND + SDIO active indication + 28 + 1 + read-only + + + SLP_WAKEUP + leep wakeup bit + 29 + 1 + read-write + + + SLP_REJECT + leep reject bit + 30 + 1 + read-write + + + SLEEP_EN + sleep enable bit + 31 + 1 + read-write + + + + + TIMER1 + rtc state wait time + 0x1C + 0x20 + 0x28140403 + + + CPU_STALL_EN + CPU stall enable bit + 0 + 1 + read-write + + + CPU_STALL_WAIT + CPU stall wait cycles in fast_clk_rtc + 1 + 5 + read-write + + + CK8M_WAIT + CK8M wait cycles in slow_clk_rtc + 6 + 8 + read-write + + + XTL_BUF_WAIT + XTAL wait cycles in slow_clk_rtc + 14 + 10 + read-write + + + PLL_BUF_WAIT + PLL wait cycles in slow_clk_rtc + 24 + 8 + read-write + + + + + TIMER2 + rtc monitor state delay time + 0x20 + 0x20 + 0x01080000 + + + ULPCP_TOUCH_START_WAIT + wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work + 15 + 9 + read-write + + + MIN_TIME_CK8M_OFF + minimal cycles in slow_clk_rtc for CK8M in power down state + 24 + 8 + read-write + + + + + TIMER3 + No public + 0x24 + 0x20 + 0x14160A08 + + + WIFI_WAIT_TIMER + No public + 0 + 9 + read-write + + + WIFI_POWERUP_TIMER + No public + 9 + 7 + read-write + + + BT_WAIT_TIMER + No public + 16 + 9 + read-write + + + BT_POWERUP_TIMER + No public + 25 + 7 + read-write + + + + + TIMER4 + No public + 0x28 + 0x20 + 0x10200A08 + + + WAIT_TIMER + No public + 0 + 9 + read-write + + + POWERUP_TIMER + No public + 9 + 7 + read-write + + + DG_WRAP_WAIT_TIMER + No public + 16 + 9 + read-write + + + DG_WRAP_POWERUP_TIMER + No public + 25 + 7 + read-write + + + + + TIMER5 + configure min sleep time + 0x2C + 0x20 + 0x00008000 + + + MIN_SLP_VAL + minimal sleep cycles in slow_clk_rtc + 8 + 8 + read-write + + + + + TIMER6 + No public + 0x30 + 0x20 + 0x10200A08 + + + CPU_TOP_WAIT_TIMER + No public + 0 + 9 + read-write + + + CPU_TOP_POWERUP_TIMER + No public + 9 + 7 + read-write + + + DG_PERI_WAIT_TIMER + No public + 16 + 9 + read-write + + + DG_PERI_POWERUP_TIMER + No public + 25 + 7 + read-write + + + + + ANA_CONF + analog configure register + 0x34 + 0x20 + 0x00440000 + + + I2C_RESET_POR_FORCE_PD + force down I2C_RESET_POR + 18 + 1 + read-write + + + I2C_RESET_POR_FORCE_PU + force on I2C_RESET_POR + 19 + 1 + read-write + + + GLITCH_RST_EN + enable clk glitch + 20 + 1 + read-write + + + SAR_I2C_PU + PLLA force power up + 22 + 1 + read-write + + + ANALOG_TOP_ISO_SLEEP + PLLA force power down + 23 + 1 + read-write + + + ANALOG_TOP_ISO_MONITOR + PLLA force power up + 24 + 1 + read-write + + + BBPLL_CAL_SLP_START + start BBPLL calibration during sleep + 25 + 1 + read-write + + + PVTMON_PU + 1: PVTMON power up, otherwise power down + 26 + 1 + read-write + + + TXRF_I2C_PU + 1: TXRF_I2C power up, otherwise power down + 27 + 1 + read-write + + + RFRX_PBUS_PU + 1: RFRX_PBUS power up, otherwise power down + 28 + 1 + read-write + + + CKGEN_I2C_PU + 1: CKGEN_I2C power up, otherwise power down + 30 + 1 + read-write + + + PLL_I2C_PU + power on pll i2c + 31 + 1 + read-write + + + + + RESET_STATE + get reset state + 0x38 + 0x20 + 0x00003000 + + + RESET_CAUSE_PROCPU + reset cause of PRO CPU + 0 + 6 + read-only + + + RESET_CAUSE_APPCPU + reset cause of APP CPU + 6 + 6 + read-only + + + APPCPU_STAT_VECTOR_SEL + APP CPU state vector sel + 12 + 1 + read-write + + + PROCPU_STAT_VECTOR_SEL + PRO CPU state vector sel + 13 + 1 + read-write + + + RESET_FLAG_PROCPU + PRO CPU reset_flag + 14 + 1 + read-only + + + RESET_FLAG_APPCPU + APP CPU reset flag + 15 + 1 + read-only + + + RESET_FLAG_PROCPU_CLR + clear PRO CPU reset_flag + 16 + 1 + write-only + + + RESET_FLAG_APPCPU_CLR + clear APP CPU reset flag + 17 + 1 + write-only + + + APPCPU_OCD_HALT_ON_RESET + APPCPU OcdHaltOnReset + 18 + 1 + read-write + + + PROCPU_OCD_HALT_ON_RESET + PROCPU OcdHaltOnReset + 19 + 1 + read-write + + + RESET_FLAG_JTAG_PROCPU + jtag reset flag + 20 + 1 + read-only + + + RESET_FLAG_JTAG_APPCPU + jtag reset flag + 21 + 1 + read-only + + + RESET_FLAG_JTAG_PROCPU_CLR + clear jtag reset flag + 22 + 1 + write-only + + + RESET_FLAG_JTAG_APPCPU_CLR + clear jtag reset flag + 23 + 1 + write-only + + + APP_DRESET_MASK + bypass cpu1 dreset + 24 + 1 + read-write + + + PRO_DRESET_MASK + bypass cpu0 dreset + 25 + 1 + read-write + + + + + WAKEUP_STATE + configure wakeup state + 0x3C + 0x20 + 0x00060000 + + + WAKEUP_ENA + wakeup enable bitmap + 15 + 17 + read-write + + + + + INT_ENA_RTC + configure rtc interrupt register + 0x40 + 0x20 + + + SLP_WAKEUP_INT_ENA + enable sleep wakeup interrupt + 0 + 1 + read-write + + + SLP_REJECT_INT_ENA + enable sleep reject interrupt + 1 + 1 + read-write + + + SDIO_IDLE_INT_ENA + enable SDIO idle interrupt + 2 + 1 + read-write + + + WDT_INT_ENA + enable RTC WDT interrupt + 3 + 1 + read-write + + + TOUCH_SCAN_DONE_INT_ENA + enable touch scan done interrupt + 4 + 1 + read-write + + + ULP_CP_INT_ENA + enable ULP-coprocessor interrupt + 5 + 1 + read-write + + + TOUCH_DONE_INT_ENA + enable touch done interrupt + 6 + 1 + read-write + + + TOUCH_ACTIVE_INT_ENA + enable touch active interrupt + 7 + 1 + read-write + + + TOUCH_INACTIVE_INT_ENA + enable touch inactive interrupt + 8 + 1 + read-write + + + BROWN_OUT_INT_ENA + enable brown out interrupt + 9 + 1 + read-write + + + MAIN_TIMER_INT_ENA + enable RTC main timer interrupt + 10 + 1 + read-write + + + SARADC1_INT_ENA + enable saradc1 interrupt + 11 + 1 + read-write + + + TSENS_INT_ENA + enable tsens interrupt + 12 + 1 + read-write + + + COCPU_INT_ENA + enable riscV cocpu interrupt + 13 + 1 + read-write + + + SARADC2_INT_ENA + enable saradc2 interrupt + 14 + 1 + read-write + + + SWD_INT_ENA + enable super watch dog interrupt + 15 + 1 + read-write + + + XTAL32K_DEAD_INT_ENA + enable xtal32k_dead interrupt + 16 + 1 + read-write + + + COCPU_TRAP_INT_ENA + enable cocpu trap interrupt + 17 + 1 + read-write + + + TOUCH_TIMEOUT_INT_ENA + enable touch timeout interrupt + 18 + 1 + read-write + + + GLITCH_DET_INT_ENA + enbale gitch det interrupt + 19 + 1 + read-write + + + TOUCH_APPROACH_LOOP_DONE_INT_ENA + touch approach mode loop interrupt + 20 + 1 + read-write + + + + + INT_RAW_RTC + rtc interrupt register + 0x44 + 0x20 + + + SLP_WAKEUP_INT_RAW + sleep wakeup interrupt raw + 0 + 1 + read-only + + + SLP_REJECT_INT_RAW + sleep reject interrupt raw + 1 + 1 + read-only + + + SDIO_IDLE_INT_RAW + SDIO idle interrupt raw + 2 + 1 + read-only + + + WDT_INT_RAW + RTC WDT interrupt raw + 3 + 1 + read-only + + + TOUCH_SCAN_DONE_INT_RAW + enable touch scan done interrupt raw + 4 + 1 + read-only + + + ULP_CP_INT_RAW + ULP-coprocessor interrupt raw + 5 + 1 + read-only + + + TOUCH_DONE_INT_RAW + touch interrupt raw + 6 + 1 + read-only + + + TOUCH_ACTIVE_INT_RAW + touch active interrupt raw + 7 + 1 + read-only + + + TOUCH_INACTIVE_INT_RAW + touch inactive interrupt raw + 8 + 1 + read-only + + + BROWN_OUT_INT_RAW + brown out interrupt raw + 9 + 1 + read-only + + + MAIN_TIMER_INT_RAW + RTC main timer interrupt raw + 10 + 1 + read-only + + + SARADC1_INT_RAW + saradc1 interrupt raw + 11 + 1 + read-only + + + TSENS_INT_RAW + tsens interrupt raw + 12 + 1 + read-only + + + COCPU_INT_RAW + riscV cocpu interrupt raw + 13 + 1 + read-only + + + SARADC2_INT_RAW + saradc2 interrupt raw + 14 + 1 + read-only + + + SWD_INT_RAW + super watch dog interrupt raw + 15 + 1 + read-only + + + XTAL32K_DEAD_INT_RAW + xtal32k dead detection interrupt raw + 16 + 1 + read-only + + + COCPU_TRAP_INT_RAW + cocpu trap interrupt raw + 17 + 1 + read-only + + + TOUCH_TIMEOUT_INT_RAW + touch timeout interrupt raw + 18 + 1 + read-only + + + GLITCH_DET_INT_RAW + glitch_det_interrupt_raw + 19 + 1 + read-only + + + TOUCH_APPROACH_LOOP_DONE_INT_RAW + touch approach mode loop interrupt raw + 20 + 1 + read-write + + + + + INT_ST_RTC + rtc interrupt register + 0x48 + 0x20 + + + SLP_WAKEUP_INT_ST + sleep wakeup interrupt state + 0 + 1 + read-only + + + SLP_REJECT_INT_ST + sleep reject interrupt state + 1 + 1 + read-only + + + SDIO_IDLE_INT_ST + SDIO idle interrupt state + 2 + 1 + read-only + + + WDT_INT_ST + RTC WDT interrupt state + 3 + 1 + read-only + + + TOUCH_SCAN_DONE_INT_ST + enable touch scan done interrupt raw + 4 + 1 + read-only + + + ULP_CP_INT_ST + ULP-coprocessor interrupt state + 5 + 1 + read-only + + + TOUCH_DONE_INT_ST + touch done interrupt state + 6 + 1 + read-only + + + TOUCH_ACTIVE_INT_ST + touch active interrupt state + 7 + 1 + read-only + + + TOUCH_INACTIVE_INT_ST + touch inactive interrupt state + 8 + 1 + read-only + + + BROWN_OUT_INT_ST + brown out interrupt state + 9 + 1 + read-only + + + MAIN_TIMER_INT_ST + RTC main timer interrupt state + 10 + 1 + read-only + + + SARADC1_INT_ST + saradc1 interrupt state + 11 + 1 + read-only + + + TSENS_INT_ST + tsens interrupt state + 12 + 1 + read-only + + + COCPU_INT_ST + riscV cocpu interrupt state + 13 + 1 + read-only + + + SARADC2_INT_ST + saradc2 interrupt state + 14 + 1 + read-only + + + SWD_INT_ST + super watch dog interrupt state + 15 + 1 + read-only + + + XTAL32K_DEAD_INT_ST + xtal32k dead detection interrupt state + 16 + 1 + read-only + + + COCPU_TRAP_INT_ST + cocpu trap interrupt state + 17 + 1 + read-only + + + TOUCH_TIMEOUT_INT_ST + Touch timeout interrupt state + 18 + 1 + read-only + + + GLITCH_DET_INT_ST + glitch_det_interrupt state + 19 + 1 + read-only + + + TOUCH_APPROACH_LOOP_DONE_INT_ST + touch approach mode loop interrupt state + 20 + 1 + read-only + + + + + INT_CLR_RTC + rtc interrupt register + 0x4C + 0x20 + + + SLP_WAKEUP_INT_CLR + Clear sleep wakeup interrupt state + 0 + 1 + write-only + + + SLP_REJECT_INT_CLR + Clear sleep reject interrupt state + 1 + 1 + write-only + + + SDIO_IDLE_INT_CLR + Clear SDIO idle interrupt state + 2 + 1 + write-only + + + WDT_INT_CLR + Clear RTC WDT interrupt state + 3 + 1 + write-only + + + TOUCH_SCAN_DONE_INT_CLR + clear touch scan done interrupt raw + 4 + 1 + write-only + + + ULP_CP_INT_CLR + Clear ULP-coprocessor interrupt state + 5 + 1 + write-only + + + TOUCH_DONE_INT_CLR + Clear touch done interrupt state + 6 + 1 + write-only + + + TOUCH_ACTIVE_INT_CLR + Clear touch active interrupt state + 7 + 1 + write-only + + + TOUCH_INACTIVE_INT_CLR + Clear touch inactive interrupt state + 8 + 1 + write-only + + + BROWN_OUT_INT_CLR + Clear brown out interrupt state + 9 + 1 + write-only + + + MAIN_TIMER_INT_CLR + Clear RTC main timer interrupt state + 10 + 1 + write-only + + + SARADC1_INT_CLR + Clear saradc1 interrupt state + 11 + 1 + write-only + + + TSENS_INT_CLR + Clear tsens interrupt state + 12 + 1 + write-only + + + COCPU_INT_CLR + Clear riscV cocpu interrupt state + 13 + 1 + write-only + + + SARADC2_INT_CLR + Clear saradc2 interrupt state + 14 + 1 + write-only + + + SWD_INT_CLR + Clear super watch dog interrupt state + 15 + 1 + write-only + + + XTAL32K_DEAD_INT_CLR + Clear RTC WDT interrupt state + 16 + 1 + write-only + + + COCPU_TRAP_INT_CLR + Clear cocpu trap interrupt state + 17 + 1 + write-only + + + TOUCH_TIMEOUT_INT_CLR + Clear touch timeout interrupt state + 18 + 1 + write-only + + + GLITCH_DET_INT_CLR + Clear glitch det interrupt state + 19 + 1 + write-only + + + TOUCH_APPROACH_LOOP_DONE_INT_CLR + cleartouch approach mode loop interrupt state + 20 + 1 + write-only + + + + + STORE0 + Reserved register + 0x50 + 0x20 + + + SCRATCH0 + Reserved register + 0 + 32 + read-write + + + + + STORE1 + Reserved register + 0x54 + 0x20 + + + SCRATCH1 + Reserved register + 0 + 32 + read-write + + + + + STORE2 + Reserved register + 0x58 + 0x20 + + + SCRATCH2 + Reserved register + 0 + 32 + read-write + + + + + STORE3 + Reserved register + 0x5C + 0x20 + + + SCRATCH3 + Reserved register + 0 + 32 + read-write + + + + + EXT_XTL_CONF + Reserved register + 0x60 + 0x20 + 0x00066C80 + + + XTAL32K_WDT_EN + xtal 32k watch dog enable + 0 + 1 + read-write + + + XTAL32K_WDT_CLK_FO + xtal 32k watch dog clock force on + 1 + 1 + read-write + + + XTAL32K_WDT_RESET + xtal 32k watch dog sw reset + 2 + 1 + read-write + + + XTAL32K_EXT_CLK_FO + xtal 32k external xtal clock force on + 3 + 1 + read-write + + + XTAL32K_AUTO_BACKUP + xtal 32k switch to back up clock when xtal is dead + 4 + 1 + read-write + + + XTAL32K_AUTO_RESTART + xtal 32k restart xtal when xtal is dead + 5 + 1 + read-write + + + XTAL32K_AUTO_RETURN + xtal 32k switch back xtal when xtal is restarted + 6 + 1 + read-write + + + XTAL32K_XPD_FORCE + Xtal 32k xpd control by sw or fsm + 7 + 1 + read-write + + + ENCKINIT_XTAL_32K + apply an internal clock to help xtal 32k to start + 8 + 1 + read-write + + + DBUF_XTAL_32K + 0: single-end buffer 1: differential buffer + 9 + 1 + read-write + + + DGM_XTAL_32K + xtal_32k gm control + 10 + 3 + read-write + + + DRES_XTAL_32K + DRES_XTAL_32K + 13 + 3 + read-write + + + XPD_XTAL_32K + XPD_XTAL_32K + 16 + 1 + read-write + + + DAC_XTAL_32K + DAC_XTAL_32K + 17 + 3 + read-write + + + WDT_STATE + state of 32k_wdt + 20 + 3 + read-only + + + XTAL32K_GPIO_SEL + XTAL_32K sel. 0: external XTAL_32K, 1: CLK from RTC pad X32P_C + 23 + 1 + read-write + + + XTL_EXT_CTR_LV + 0: power down XTAL at high level, 1: power down XTAL at low level + 30 + 1 + read-write + + + XTL_EXT_CTR_EN + Reserved register + 31 + 1 + read-write + + + + + EXT_WAKEUP_CONF + ext wakeup configure + 0x64 + 0x20 + + + GPIO_WAKEUP_FILTER + enable filter for gpio wakeup event + 29 + 1 + read-write + + + EXT_WAKEUP0_LV + 0: external wakeup at low level, 1: external wakeup at high level + 30 + 1 + read-write + + + EXT_WAKEUP1_LV + 0: external wakeup at low level, 1: external wakeup at high level + 31 + 1 + read-write + + + + + SLP_REJECT_CONF + reject sleep register + 0x68 + 0x20 + + + SLEEP_REJECT_ENA + sleep reject enable + 12 + 18 + read-write + + + LIGHT_SLP_REJECT_EN + enable reject for light sleep + 30 + 1 + read-write + + + DEEP_SLP_REJECT_EN + enable reject for deep sleep + 31 + 1 + read-write + + + + + CPU_PERIOD_CONF + conigure cpu freq + 0x6C + 0x20 + + + CPUSEL_CONF + CPU sel option + 29 + 1 + read-write + + + CPUPERIOD_SEL + conigure cpu freq + 30 + 2 + read-write + + + + + SDIO_ACT_CONF + No public + 0x70 + 0x20 + + + SDIO_ACT_DNUM + No public + 22 + 10 + read-write + + + + + CLK_CONF + configure clock register + 0x74 + 0x20 + 0x1158321C + + + EFUSE_CLK_FORCE_GATING + force efuse clk gating + 1 + 1 + read-write + + + EFUSE_CLK_FORCE_NOGATING + force efuse clk nogating + 2 + 1 + read-write + + + CK8M_DIV_SEL_VLD + used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel, then set vld to actually switch the clk + 3 + 1 + read-write + + + CK8M_DIV + CK8M_D256_OUT divider. 00: div128, 01: div256, 10: div512, 11: div1024. + 4 + 2 + read-write + + + ENB_CK8M + disable CK8M and CK8M_D256_OUT + 6 + 1 + read-write + + + ENB_CK8M_DIV + 1: CK8M_D256_OUT is actually CK8M, 0: CK8M_D256_OUT is CK8M divided by 256 + 7 + 1 + read-write + + + DIG_XTAL32K_EN + enable CK_XTAL_32K for digital core (no relationship with RTC core) + 8 + 1 + read-write + + + DIG_CLK8M_D256_EN + enable CK8M_D256_OUT for digital core (no relationship with RTC core) + 9 + 1 + read-write + + + DIG_CLK8M_EN + enable CK8M for digital core (no relationship with RTC core) + 10 + 1 + read-write + + + CK8M_DIV_SEL + divider = reg_ck8m_div_sel + 1 + 12 + 3 + read-write + + + XTAL_FORCE_NOGATING + XTAL force no gating during sleep + 15 + 1 + read-write + + + CK8M_FORCE_NOGATING + CK8M force no gating during sleep + 16 + 1 + read-write + + + CK8M_DFREQ + CK8M_DFREQ + 17 + 8 + read-write + + + CK8M_FORCE_PD + CK8M force power down + 25 + 1 + read-write + + + CK8M_FORCE_PU + CK8M force power up + 26 + 1 + read-write + + + XTAL_GLOBAL_FORCE_GATING + force global xtal gating + 27 + 1 + read-write + + + XTAL_GLOBAL_FORCE_NOGATING + force global xtal no gating + 28 + 1 + read-write + + + FAST_CLK_RTC_SEL + fast_clk_rtc sel. 0: XTAL div 4, 1: CK8M + 29 + 1 + read-write + + + ANA_CLK_RTC_SEL + select slow clock + 30 + 2 + read-write + + + + + SLOW_CLK_CONF + configure slow clk + 0x78 + 0x20 + 0x00400000 + + + ANA_CLK_DIV_VLD + used to sync div bus. clear vld before set reg_rtc_ana_clk_div, then set vld to actually switch the clk + 22 + 1 + read-write + + + ANA_CLK_DIV + rtc clk div + 23 + 8 + read-write + + + SLOW_CLK_NEXT_EDGE + No public + 31 + 1 + read-write + + + + + SDIO_CONF + configure flash power + 0x7C + 0x20 + 0x0AB0BE0A + + + SDIO_TIMER_TARGET + timer count to apply reg_sdio_dcap after sdio power on + 0 + 8 + read-write + + + SDIO_DTHDRV + Tieh = 1 mode drive ability. Initially set to 0 to limit charge current, set to 3 after several us. + 9 + 2 + read-write + + + SDIO_DCAP + ability to prevent LDO from overshoot + 11 + 2 + read-write + + + SDIO_INITI + add resistor from ldo output to ground. 0: no res, 1: 6k,2:4k,3:2k + 13 + 2 + read-write + + + SDIO_EN_INITI + 0 to set init[1:0]=0 + 15 + 1 + read-write + + + SDIO_DCURLIM + tune current limit threshold when tieh = 0. About 800mA/(8+d) + 16 + 3 + read-write + + + SDIO_MODECURLIM + select current limit mode + 19 + 1 + read-write + + + SDIO_ENCURLIM + enable current limit + 20 + 1 + read-write + + + SDIO_REG_PD_EN + power down SDIO_REG in sleep. Only active when reg_sdio_force = 0 + 21 + 1 + read-write + + + SDIO_FORCE + 1: use SW option to control SDIO_REG, 0: use state machine + 22 + 1 + read-write + + + SDIO_TIEH + SW option for SDIO_TIEH. Only active when reg_sdio_force = 1 + 23 + 1 + read-write + + + REG1P8_READY + read only register for REG1P8_READY + 24 + 1 + read-only + + + DREFL_SDIO + SW option for DREFL_SDIO. Only active when reg_sdio_force = 1 + 25 + 2 + read-write + + + DREFM_SDIO + SW option for DREFM_SDIO. Only active when reg_sdio_force = 1 + 27 + 2 + read-write + + + DREFH_SDIO + SW option for DREFH_SDIO. Only active when reg_sdio_force = 1 + 29 + 2 + read-write + + + XPD_SDIO + power on flash regulator + 31 + 1 + read-write + + + + + BIAS_CONF + No public + 0x80 + 0x20 + 0x00010800 + + + BIAS_BUF_IDLE + No public + 10 + 1 + read-write + + + BIAS_BUF_WAKE + No public + 11 + 1 + read-write + + + BIAS_BUF_DEEP_SLP + No public + 12 + 1 + read-write + + + BIAS_BUF_MONITOR + No public + 13 + 1 + read-write + + + PD_CUR_DEEP_SLP + xpd cur when rtc in sleep_state + 14 + 1 + read-write + + + PD_CUR_MONITOR + xpd cur when rtc in monitor state + 15 + 1 + read-write + + + BIAS_SLEEP_DEEP_SLP + bias_sleep when rtc in sleep_state + 16 + 1 + read-write + + + BIAS_SLEEP_MONITOR + bias_sleep when rtc in monitor state + 17 + 1 + read-write + + + DBG_ATTEN_DEEP_SLP + DBG_ATTEN when rtc in sleep state + 18 + 4 + read-write + + + DBG_ATTEN_MONITOR + DBG_ATTEN when rtc in monitor state + 22 + 4 + read-write + + + DBG_ATTEN_WAKEUP + No public + 26 + 4 + read-write + + + + + RTC + configure rtc regulator + 0x84 + 0x20 + 0xA0000000 + + + DIG_REG_CAL_EN + enable dig regulator cali + 7 + 1 + read-write + + + SCK_DCAP + SCK_DCAP + 14 + 8 + read-write + + + DBOOST_FORCE_PD + RTC_DBOOST force power down + 28 + 1 + read-write + + + DBOOST_FORCE_PU + RTC_DBOOST force power up + 29 + 1 + read-write + + + REGULATOR_FORCE_PD + RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower ) + 30 + 1 + read-write + + + REGULATOR_FORCE_PU + RTC_REG force power on (for RTC_REG power down means decrease the voltage to 0.8v or lower ) + 31 + 1 + read-write + + + + + PWC + configure rtc power + 0x88 + 0x20 + 0x00000925 + + + FASTMEM_FORCE_NOISO + Fast RTC memory force no ISO + 0 + 1 + read-write + + + FASTMEM_FORCE_ISO + Fast RTC memory force ISO + 1 + 1 + read-write + + + SLOWMEM_FORCE_NOISO + RTC memory force no ISO + 2 + 1 + read-write + + + SLOWMEM_FORCE_ISO + RTC memory force ISO + 3 + 1 + read-write + + + FORCE_ISO + rtc_peri force ISO + 4 + 1 + read-write + + + FORCE_NOISO + rtc_peri force no ISO + 5 + 1 + read-write + + + FASTMEM_FOLW_CPU + 1: Fast RTC memory PD following CPU, 0: fast RTC memory PD following RTC state machine + 6 + 1 + read-write + + + FASTMEM_FORCE_LPD + Fast RTC memory force PD + 7 + 1 + read-write + + + FASTMEM_FORCE_LPU + Fast RTC memory force no PD + 8 + 1 + read-write + + + SLOWMEM_FOLW_CPU + 1: RTC memory PD following CPU, 0: RTC memory PD following RTC state machine + 9 + 1 + read-write + + + SLOWMEM_FORCE_LPD + RTC memory force PD + 10 + 1 + read-write + + + SLOWMEM_FORCE_LPU + RTC memory force no PD + 11 + 1 + read-write + + + FORCE_PD + rtc_peri force power down + 18 + 1 + read-write + + + FORCE_PU + rtc_peri force power up + 19 + 1 + read-write + + + PD_EN + enable power down rtc_peri in sleep + 20 + 1 + read-write + + + PAD_FORCE_HOLD + rtc pad force hold + 21 + 1 + read-write + + + + + REGULATOR_DRV_CTRL + No public + 0x8C + 0x20 + + + REGULATOR_DRV_B_MONITOR + No public + 0 + 6 + read-write + + + REGULATOR_DRV_B_SLP + No public + 6 + 6 + read-write + + + DG_VDD_DRV_B_SLP + No public + 12 + 8 + read-write + + + DG_VDD_DRV_B_MONITOR + No public + 20 + 8 + read-write + + + + + DIG_PWC + configure digital power + 0x90 + 0x20 + 0x00545010 + + + LSLP_MEM_FORCE_PD + memories in digital core force PD in sleep + 3 + 1 + read-write + + + LSLP_MEM_FORCE_PU + memories in digital core force no PD in sleep + 4 + 1 + read-write + + + BT_FORCE_PD + internal SRAM 2 force power down + 11 + 1 + read-write + + + BT_FORCE_PU + internal SRAM 2 force power up + 12 + 1 + read-write + + + DG_PERI_FORCE_PD + internal SRAM 3 force power down + 13 + 1 + read-write + + + DG_PERI_FORCE_PU + internal SRAM 3 force power up + 14 + 1 + read-write + + + WIFI_FORCE_PD + wifi force power down + 17 + 1 + read-write + + + WIFI_FORCE_PU + wifi force power up + 18 + 1 + read-write + + + DG_WRAP_FORCE_PD + digital core force power down + 19 + 1 + read-write + + + DG_WRAP_FORCE_PU + digital core force power up + 20 + 1 + read-write + + + CPU_TOP_FORCE_PD + digital dcdc force power down + 21 + 1 + read-write + + + CPU_TOP_FORCE_PU + digital dcdc force power up + 22 + 1 + read-write + + + BT_PD_EN + enable power down internal SRAM 2 in sleep + 27 + 1 + read-write + + + DG_PERI_PD_EN + enable power down internal SRAM 3 in sleep + 28 + 1 + read-write + + + CPU_TOP_PD_EN + enable power down internal SRAM 4 in sleep + 29 + 1 + read-write + + + WIFI_PD_EN + enable power down wifi in sleep + 30 + 1 + read-write + + + DG_WRAP_PD_EN + enable power down all digital logic + 31 + 1 + read-write + + + + + DIG_ISO + congigure digital power isolation + 0x94 + 0x20 + 0xAA805080 + + + FORCE_OFF + No public + 7 + 1 + read-write + + + FORCE_ON + No public + 8 + 1 + read-write + + + DG_PAD_AUTOHOLD + read only register to indicate digital pad auto-hold status + 9 + 1 + read-only + + + CLR_DG_PAD_AUTOHOLD + wtite only register to clear digital pad auto-hold + 10 + 1 + write-only + + + DG_PAD_AUTOHOLD_EN + digital pad enable auto-hold + 11 + 1 + read-write + + + DG_PAD_FORCE_NOISO + digital pad force no ISO + 12 + 1 + read-write + + + DG_PAD_FORCE_ISO + digital pad force ISO + 13 + 1 + read-write + + + DG_PAD_FORCE_UNHOLD + digital pad force un-hold + 14 + 1 + read-write + + + DG_PAD_FORCE_HOLD + digital pad force hold + 15 + 1 + read-write + + + BT_FORCE_ISO + internal SRAM 2 force ISO + 22 + 1 + read-write + + + BT_FORCE_NOISO + internal SRAM 2 force no ISO + 23 + 1 + read-write + + + DG_PERI_FORCE_ISO + internal SRAM 3 force ISO + 24 + 1 + read-write + + + DG_PERI_FORCE_NOISO + internal SRAM 3 force no ISO + 25 + 1 + read-write + + + CPU_TOP_FORCE_ISO + internal SRAM 4 force ISO + 26 + 1 + read-write + + + CPU_TOP_FORCE_NOISO + internal SRAM 4 force no ISO + 27 + 1 + read-write + + + WIFI_FORCE_ISO + wifi force ISO + 28 + 1 + read-write + + + WIFI_FORCE_NOISO + wifi force no ISO + 29 + 1 + read-write + + + DG_WRAP_FORCE_ISO + digital core force ISO + 30 + 1 + read-write + + + DG_WRAP_FORCE_NOISO + digita core force no ISO + 31 + 1 + read-write + + + + + WDTCONFIG0 + configure rtc watch dog + 0x98 + 0x20 + 0x00013214 + + + WDT_CHIP_RESET_WIDTH + chip reset siginal pulse width + 0 + 8 + read-write + + + WDT_CHIP_RESET_EN + wdt reset whole chip enable + 8 + 1 + read-write + + + WDT_PAUSE_IN_SLP + pause WDT in sleep + 9 + 1 + read-write + + + WDT_APPCPU_RESET_EN + enable WDT reset APP CPU + 10 + 1 + read-write + + + WDT_PROCPU_RESET_EN + enable WDT reset PRO CPU + 11 + 1 + read-write + + + WDT_FLASHBOOT_MOD_EN + enable WDT in flash boot + 12 + 1 + read-write + + + WDT_SYS_RESET_LENGTH + system reset counter length + 13 + 3 + read-write + + + WDT_CPU_RESET_LENGTH + CPU reset counter length + 16 + 3 + read-write + + + WDT_STG3 + 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en + 19 + 3 + read-write + + + WDT_STG2 + 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en + 22 + 3 + read-write + + + WDT_STG1 + 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en + 25 + 3 + read-write + + + WDT_STG0 + 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en + 28 + 3 + read-write + + + WDT_EN + enable rtc watch dog + 31 + 1 + read-write + + + + + WDTCONFIG1 + stage0 hold time + 0x9C + 0x20 + 0x00030D40 + + + WDT_STG0_HOLD + stage0 hold time + 0 + 32 + read-write + + + + + WDTCONFIG2 + stage1 hold time + 0xA0 + 0x20 + 0x00013880 + + + WDT_STG1_HOLD + stage1 hold time + 0 + 32 + read-write + + + + + WDTCONFIG3 + stage2 hold time + 0xA4 + 0x20 + 0x00000FFF + + + WDT_STG2_HOLD + stage2 hold time + 0 + 32 + read-write + + + + + WDTCONFIG4 + stage3 hold time + 0xA8 + 0x20 + 0x00000FFF + + + WDT_STG3_HOLD + stage3 hold time + 0 + 32 + read-write + + + + + WDTFEED + rtc wdt feed + 0xAC + 0x20 + + + WDT_FEED + rtc wdt feed + 31 + 1 + write-only + + + + + WDTWPROTECT + configure rtc watch dog + 0xB0 + 0x20 + 0x50D83AA1 + + + WDT_WKEY + rtc watch dog key + 0 + 32 + read-write + + + + + SWD_CONF + congfigure super watch dog + 0xB4 + 0x20 + 0x04B00000 + + + SWD_RESET_FLAG + swd reset flag + 0 + 1 + read-only + + + SWD_FEED_INT + swd interrupt for feeding + 1 + 1 + read-only + + + SWD_BYPASS_RST + bypass super watch dog reset + 17 + 1 + read-write + + + SWD_SIGNAL_WIDTH + adjust signal width send to swd + 18 + 10 + read-write + + + SWD_RST_FLAG_CLR + reset swd reset flag + 28 + 1 + write-only + + + SWD_FEED + Sw feed swd + 29 + 1 + write-only + + + SWD_DISABLE + disabel SWD + 30 + 1 + read-write + + + SWD_AUTO_FEED_EN + automatically feed swd when int comes + 31 + 1 + read-write + + + + + SWD_WPROTECT + super watch dog key + 0xB8 + 0x20 + 0x8F1D312A + + + SWD_WKEY + super watch dog key + 0 + 32 + read-write + + + + + SW_CPU_STALL + configure cpu stall by sw + 0xBC + 0x20 + + + SW_STALL_APPCPU_C1 + {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU + 20 + 6 + read-write + + + SW_STALL_PROCPU_C1 + {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU + 26 + 6 + read-write + + + + + STORE4 + reserved register + 0xC0 + 0x20 + + + SCRATCH4 + reserved register + 0 + 32 + read-write + + + + + STORE5 + reserved register + 0xC4 + 0x20 + + + SCRATCH5 + reserved register + 0 + 32 + read-write + + + + + STORE6 + reserved register + 0xC8 + 0x20 + + + SCRATCH6 + reserved register + 0 + 32 + read-write + + + + + STORE7 + reserved register + 0xCC + 0x20 + + + SCRATCH7 + reserved register + 0 + 32 + read-write + + + + + LOW_POWER_ST + reserved register + 0xD0 + 0x20 + + + XPD_ROM0 + rom0 power down + 0 + 1 + read-only + + + XPD_DIG_DCDC + External DCDC power down + 2 + 1 + read-only + + + PERI_ISO + rtc peripheral iso + 3 + 1 + read-only + + + XPD_RTC_PERI + rtc peripheral power down + 4 + 1 + read-only + + + WIFI_ISO + wifi iso + 5 + 1 + read-only + + + XPD_WIFI + wifi wrap power down + 6 + 1 + read-only + + + DIG_ISO + digital wrap iso + 7 + 1 + read-only + + + XPD_DIG + digital wrap power down + 8 + 1 + read-only + + + TOUCH_STATE_START + touch should start to work + 9 + 1 + read-only + + + TOUCH_STATE_SWITCH + touch is about to working. Switch rtc main state + 10 + 1 + read-only + + + TOUCH_STATE_SLP + touch is in sleep state + 11 + 1 + read-only + + + TOUCH_STATE_DONE + touch is done + 12 + 1 + read-only + + + COCPU_STATE_START + ulp/cocpu should start to work + 13 + 1 + read-only + + + COCPU_STATE_SWITCH + ulp/cocpu is about to working. Switch rtc main state + 14 + 1 + read-only + + + COCPU_STATE_SLP + ulp/cocpu is in sleep state + 15 + 1 + read-only + + + COCPU_STATE_DONE + ulp/cocpu is done + 16 + 1 + read-only + + + MAIN_STATE_XTAL_ISO + no use any more + 17 + 1 + read-only + + + MAIN_STATE_PLL_ON + rtc main state machine is in states that pll should be running + 18 + 1 + read-only + + + RDY_FOR_WAKEUP + rtc is ready to receive wake up trigger from wake up source + 19 + 1 + read-only + + + MAIN_STATE_WAIT_END + rtc main state machine has been waited for some cycles + 20 + 1 + read-only + + + IN_WAKEUP_STATE + rtc main state machine is in the states of wakeup process + 21 + 1 + read-only + + + IN_LOW_POWER_STATE + rtc main state machine is in the states of low power + 22 + 1 + read-only + + + MAIN_STATE_IN_WAIT_8M + rtc main state machine is in wait 8m state + 23 + 1 + read-only + + + MAIN_STATE_IN_WAIT_PLL + rtc main state machine is in wait pll state + 24 + 1 + read-only + + + MAIN_STATE_IN_WAIT_XTL + rtc main state machine is in wait xtal state + 25 + 1 + read-only + + + MAIN_STATE_IN_SLP + rtc main state machine is in sleep state + 26 + 1 + read-only + + + MAIN_STATE_IN_IDLE + rtc main state machine is in idle state + 27 + 1 + read-only + + + MAIN_STATE + rtc main state machine status + 28 + 4 + read-only + + + + + DIAG0 + No public + 0xD4 + 0x20 + + + LOW_POWER_DIAG1 + No public + 0 + 32 + read-only + + + + + PAD_HOLD + rtc pad hold configure + 0xD8 + 0x20 + + + TOUCH_PAD0_HOLD + hold rtc pad0 + 0 + 1 + read-write + + + TOUCH_PAD1_HOLD + hold rtc pad-1 + 1 + 1 + read-write + + + TOUCH_PAD2_HOLD + hold rtc pad-2 + 2 + 1 + read-write + + + TOUCH_PAD3_HOLD + hold rtc pad-3 + 3 + 1 + read-write + + + TOUCH_PAD4_HOLD + hold rtc pad-4 + 4 + 1 + read-write + + + TOUCH_PAD5_HOLD + hold rtc pad-5 + 5 + 1 + read-write + + + TOUCH_PAD6_HOLD + hold rtc pad-6 + 6 + 1 + read-write + + + TOUCH_PAD7_HOLD + hold rtc pad-7 + 7 + 1 + read-write + + + TOUCH_PAD8_HOLD + hold rtc pad-8 + 8 + 1 + read-write + + + TOUCH_PAD9_HOLD + hold rtc pad-9 + 9 + 1 + read-write + + + TOUCH_PAD10_HOLD + hold rtc pad-10 + 10 + 1 + read-write + + + TOUCH_PAD11_HOLD + hold rtc pad-11 + 11 + 1 + read-write + + + TOUCH_PAD12_HOLD + hold rtc pad-12 + 12 + 1 + read-write + + + TOUCH_PAD13_HOLD + hold rtc pad-13 + 13 + 1 + read-write + + + TOUCH_PAD14_HOLD + hold rtc pad-14 + 14 + 1 + read-write + + + X32P_HOLD + hold rtc pad-15 + 15 + 1 + read-write + + + X32N_HOLD + hold rtc pad-16 + 16 + 1 + read-write + + + PDAC1_HOLD + hold rtc pad-17 + 17 + 1 + read-write + + + PDAC2_HOLD + hold rtc pad-18 + 18 + 1 + read-write + + + PAD19_HOLD + hold rtc pad-19 + 19 + 1 + read-write + + + PAD20_HOLD + hold rtc pad-20 + 20 + 1 + read-write + + + PAD21_HOLD + hold rtc pad-21 + 21 + 1 + read-write + + + + + DIG_PAD_HOLD + configure digtal pad hold + 0xDC + 0x20 + + + DIG_PAD_HOLD + configure digtal pad hold + 0 + 32 + read-write + + + + + EXT_WAKEUP1 + configure ext1 wakeup + 0xE0 + 0x20 + + + EXT_WAKEUP1_SEL + Bitmap to select RTC pads for ext wakeup1 + 0 + 22 + read-write + + + EXT_WAKEUP1_STATUS_CLR + clear ext wakeup1 status + 22 + 1 + write-only + + + + + EXT_WAKEUP1_STATUS + check ext wakeup1 status + 0xE4 + 0x20 + + + EXT_WAKEUP1_STATUS + ext wakeup1 status + 0 + 22 + read-only + + + + + BROWN_OUT + congfigure brownout + 0xE8 + 0x20 + 0x43FF0010 + + + BROWN_OUT_INT_WAIT + brown out interrupt wait cycles + 4 + 10 + read-write + + + BROWN_OUT_CLOSE_FLASH_ENA + enable close flash when brown out happens + 14 + 1 + read-write + + + BROWN_OUT_PD_RF_ENA + enable power down RF when brown out happens + 15 + 1 + read-write + + + BROWN_OUT_RST_WAIT + brown out reset wait cycles + 16 + 10 + read-write + + + BROWN_OUT_RST_ENA + enable brown out reset + 26 + 1 + read-write + + + BROWN_OUT_RST_SEL + 1: 4-pos reset, 0: sys_reset + 27 + 1 + read-write + + + BROWN_OUT_ANA_RST_EN + enable brown out reset en + 28 + 1 + read-write + + + BROWN_OUT_CNT_CLR + clear brown out counter + 29 + 1 + write-only + + + BROWN_OUT_ENA + enable brown out + 30 + 1 + read-write + + + DET + get brown out detect + 31 + 1 + read-only + + + + + TIME_LOW1 + RTC timer low 32 bits + 0xEC + 0x20 + + + TIMER_VALUE1_LOW + RTC timer low 32 bits + 0 + 32 + read-only + + + + + TIME_HIGH1 + RTC timer high 16 bits + 0xF0 + 0x20 + + + TIMER_VALUE1_HIGH + RTC timer high 16 bits + 0 + 16 + read-only + + + + + XTAL32K_CLK_FACTOR + xtal 32k watch dog backup clock factor + 0xF4 + 0x20 + + + XTAL32K_CLK_FACTOR + xtal 32k watch dog backup clock factor + 0 + 32 + read-write + + + + + XTAL32K_CONF + configure xtal32k + 0xF8 + 0x20 + 0x0FF00000 + + + XTAL32K_RETURN_WAIT + cycles to wait to return noral xtal 32k + 0 + 4 + read-write + + + XTAL32K_RESTART_WAIT + cycles to wait to repower on xtal 32k + 4 + 16 + read-write + + + XTAL32K_WDT_TIMEOUT + If no clock detected for this amount of time 32k is regarded as dead + 20 + 8 + read-write + + + XTAL32K_STABLE_THRES + if restarted xtal32k period is smaller than this, it is regarded as stable + 28 + 4 + read-write + + + + + ULP_CP_TIMER + configure ulp + 0xFC + 0x20 + + + ULP_CP_PC_INIT + ULP-coprocessor PC initial address + 0 + 11 + read-write + + + ULP_CP_GPIO_WAKEUP_ENA + ULP-coprocessor wakeup by GPIO enable + 29 + 1 + read-write + + + ULP_CP_GPIO_WAKEUP_CLR + ULP-coprocessor wakeup by GPIO state clear + 30 + 1 + write-only + + + ULP_CP_SLP_TIMER_EN + ULP-coprocessor timer enable bit + 31 + 1 + read-write + + + + + ULP_CP_CTRL + configure ulp + 0x100 + 0x20 + 0x00100200 + + + ULP_CP_MEM_ADDR_INIT + No public + 0 + 11 + read-write + + + ULP_CP_MEM_ADDR_SIZE + No public + 11 + 11 + read-write + + + ULP_CP_MEM_OFFST_CLR + No public + 22 + 1 + write-only + + + ULP_CP_CLK_FO + ulp coprocessor clk force on + 28 + 1 + read-write + + + ULP_CP_RESET + ulp coprocessor clk software reset + 29 + 1 + read-write + + + ULP_CP_FORCE_START_TOP + 1: ULP-coprocessor is started by SW + 30 + 1 + read-write + + + ULP_CP_START_TOP + Write 1 to start ULP-coprocessor + 31 + 1 + read-write + + + + + COCPU_CTRL + configure ulp-riscv + 0x104 + 0x20 + 0x008A0810 + + + COCPU_CLK_FO + cocpu clk force on + 0 + 1 + read-write + + + COCPU_START_2_RESET_DIS + time from start cocpu to pull down reset + 1 + 6 + read-write + + + COCPU_START_2_INTR_EN + time from start cocpu to give start interrupt + 7 + 6 + read-write + + + COCPU_SHUT + to shut cocpu + 13 + 1 + read-write + + + COCPU_SHUT_2_CLK_DIS + time from shut cocpu to disable clk + 14 + 8 + read-write + + + COCPU_SHUT_RESET_EN + to reset cocpu + 22 + 1 + read-write + + + COCPU_SEL + 1: old ULP 0: new riscV + 23 + 1 + read-write + + + COCPU_DONE_FORCE + 1: select riscv done 0: select ulp done + 24 + 1 + read-write + + + COCPU_DONE + done signal used by riscv to control timer. + 25 + 1 + read-write + + + COCPU_SW_INT_TRIGGER + trigger cocpu register interrupt + 26 + 1 + write-only + + + COCPU_CLKGATE_EN + open ulp-riscv clk gate + 27 + 1 + read-write + + + + + TOUCH_CTRL1 + configure touch controller + 0x108 + 0x20 + 0x10000100 + + + TOUCH_SLEEP_CYCLES + sleep cycles for timer + 0 + 16 + read-write + + + TOUCH_MEAS_NUM + the meas length (in 8MHz) + 16 + 16 + read-write + + + + + TOUCH_CTRL2 + configure touch controller + 0x10C + 0x20 + 0x000840CC + + + TOUCH_DRANGE + TOUCH_DRANGE + 2 + 2 + read-write + + + TOUCH_DREFL + TOUCH_DREFL + 4 + 2 + read-write + + + TOUCH_DREFH + TOUCH_DREFH + 6 + 2 + read-write + + + TOUCH_XPD_BIAS + TOUCH_XPD_BIAS + 8 + 1 + read-write + + + TOUCH_REFC + TOUCH pad0 reference cap + 9 + 3 + read-write + + + TOUCH_DBIAS + 1:use self bias 0:use bandgap bias + 12 + 1 + read-write + + + TOUCH_SLP_TIMER_EN + touch timer enable bit + 13 + 1 + read-write + + + TOUCH_START_FSM_EN + 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm + 14 + 1 + read-write + + + TOUCH_START_EN + 1: start touch fsm + 15 + 1 + read-write + + + TOUCH_START_FORCE + 1: to start touch fsm by SW + 16 + 1 + read-write + + + TOUCH_XPD_WAIT + the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD + 17 + 8 + read-write + + + TOUCH_SLP_CYC_DIV + when a touch pad is active sleep cycle could be divided by this number + 25 + 2 + read-write + + + TOUCH_TIMER_FORCE_DONE + force touch timer done + 27 + 2 + read-write + + + TOUCH_RESET + reset upgrade touch + 29 + 1 + read-write + + + TOUCH_CLK_FO + touch clock force on + 30 + 1 + read-write + + + TOUCH_CLKGATE_EN + touch clock enable + 31 + 1 + read-write + + + + + TOUCH_SCAN_CTRL + configure touch controller + 0x110 + 0x20 + 0xF0000102 + + + TOUCH_DENOISE_RES + De-noise resolution: 12/10/8/4 bit + 0 + 2 + read-write + + + TOUCH_DENOISE_EN + touch pad0 will be used to de-noise + 2 + 1 + read-write + + + TOUCH_INACTIVE_CONNECTION + inactive touch pads connect to 1: gnd 0: HighZ + 8 + 1 + read-write + + + TOUCH_SHIELD_PAD_EN + touch pad14 will be used as shield + 9 + 1 + read-write + + + TOUCH_SCAN_PAD_MAP + touch scan mode pad enable map + 10 + 15 + read-write + + + TOUCH_BUFDRV + touch7 buffer driver strength + 25 + 3 + read-write + + + TOUCH_OUT_RING + select out ring pad + 28 + 4 + read-write + + + + + TOUCH_SLP_THRES + configure touch controller + 0x114 + 0x20 + 0x78000000 + + + TOUCH_SLP_TH + the threshold for sleep touch pad + 0 + 22 + read-write + + + TOUCH_SLP_APPROACH_EN + sleep pad approach function enable + 26 + 1 + read-write + + + TOUCH_SLP_PAD + configure which pad as slp pad + 27 + 5 + read-write + + + + + TOUCH_APPROACH + configure touch controller + 0x118 + 0x20 + 0x50000000 + + + TOUCH_SLP_CHANNEL_CLR + clear touch slp channel + 23 + 1 + write-only + + + TOUCH_APPROACH_MEAS_TIME + approach pads total meas times + 24 + 8 + read-write + + + + + TOUCH_FILTER_CTRL + configure touch controller + 0x11C + 0x20 + 0x96AA8800 + + + TOUCH_BYPASS_NEG_NOISE_THRES + bypass neg noise thres + 7 + 1 + read-write + + + TOUCH_BYPASS_NOISE_THRES + bypaas noise thres + 8 + 1 + read-write + + + TOUCH_SMOOTH_LVL + smooth filter factor + 9 + 2 + read-write + + + TOUCH_JITTER_STEP + touch jitter step + 11 + 4 + read-write + + + TOUCH_NEG_NOISE_LIMIT + negative threshold counter limit + 15 + 4 + read-write + + + TOUCH_NEG_NOISE_THRES + neg noise thres + 19 + 2 + read-write + + + TOUCH_NOISE_THRES + noise thres + 21 + 2 + read-write + + + TOUCH_HYSTERESIS + hysteresis + 23 + 2 + read-write + + + TOUCH_DEBOUNCE + debounce counter + 25 + 3 + read-write + + + TOUCH_FILTER_MODE + 0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter + 28 + 3 + read-write + + + TOUCH_FILTER_EN + touch filter enable + 31 + 1 + read-write + + + + + USB_CONF + usb configure + 0x120 + 0x20 + + + USB_VREFH + reg_usb_vrefh + 0 + 2 + read-write + + + USB_VREFL + reg_usb_vrefl + 2 + 2 + read-write + + + USB_VREF_OVERRIDE + reg_usb_vref_override + 4 + 1 + read-write + + + USB_PAD_PULL_OVERRIDE + reg_usb_pad_pull_override + 5 + 1 + read-write + + + USB_DP_PULLUP + reg_usb_dp_pullup + 6 + 1 + read-write + + + USB_DP_PULLDOWN + reg_usb_dp_pulldown + 7 + 1 + read-write + + + USB_DM_PULLUP + reg_usb_dm_pullup + 8 + 1 + read-write + + + USB_DM_PULLDOWN + reg_usb_dm_pulldown + 9 + 1 + read-write + + + USB_PULLUP_VALUE + reg_usb_pullup_value + 10 + 1 + read-write + + + USB_PAD_ENABLE_OVERRIDE + reg_usb_pad_enable_override + 11 + 1 + read-write + + + USB_PAD_ENABLE + reg_usb_pad_enable + 12 + 1 + read-write + + + USB_TXM + reg_usb_txm + 13 + 1 + read-write + + + USB_TXP + reg_usb_txp + 14 + 1 + read-write + + + USB_TX_EN + reg_usb_tx_en + 15 + 1 + read-write + + + USB_TX_EN_OVERRIDE + reg_usb_tx_en_override + 16 + 1 + read-write + + + USB_RESET_DISABLE + reg_usb_reset_disable + 17 + 1 + read-write + + + IO_MUX_RESET_DISABLE + reg_io_mux_reset_disable + 18 + 1 + read-write + + + SW_USB_PHY_SEL + reg_sw_usb_phy_sel + 19 + 1 + read-write + + + SW_HW_USB_PHY_SEL + reg_sw_hw_usb_phy_sel + 20 + 1 + read-write + + + + + TOUCH_TIMEOUT_CTRL + configure touch controller + 0x124 + 0x20 + 0x007FFFFF + + + TOUCH_TIMEOUT_NUM + configure touch timerout time + 0 + 22 + read-write + + + TOUCH_TIMEOUT_EN + enable touch timerout + 22 + 1 + read-write + + + + + SLP_REJECT_CAUSE + get reject casue + 0x128 + 0x20 + + + REJECT_CAUSE + sleep reject cause + 0 + 18 + read-only + + + + + OPTION1 + rtc common configure + 0x12C + 0x20 + + + FORCE_DOWNLOAD_BOOT + force chip entry download boot by sw + 0 + 1 + read-write + + + + + SLP_WAKEUP_CAUSE + get wakeup cause + 0x130 + 0x20 + + + WAKEUP_CAUSE + sleep wakeup cause + 0 + 17 + read-only + + + + + ULP_CP_TIMER_1 + configure ulp sleep time + 0x134 + 0x20 + 0x0000C800 + + + ULP_CP_TIMER_SLP_CYCLE + sleep cycles for ULP-coprocessor timer + 8 + 24 + read-write + + + + + INT_ENA_RTC_W1TS + oneset rtc interrupt + 0x138 + 0x20 + + + SLP_WAKEUP_INT_ENA_W1TS + enable sleep wakeup interrupt + 0 + 1 + write-only + + + SLP_REJECT_INT_ENA_W1TS + enable sleep reject interrupt + 1 + 1 + write-only + + + SDIO_IDLE_INT_ENA_W1TS + enable SDIO idle interrupt + 2 + 1 + write-only + + + WDT_INT_ENA_W1TS + enable RTC WDT interrupt + 3 + 1 + write-only + + + TOUCH_SCAN_DONE_INT_ENA_W1TS + enable touch scan done interrupt + 4 + 1 + write-only + + + ULP_CP_INT_ENA_W1TS + enable ULP-coprocessor interrupt + 5 + 1 + write-only + + + TOUCH_DONE_INT_ENA_W1TS + enable touch done interrupt + 6 + 1 + write-only + + + TOUCH_ACTIVE_INT_ENA_W1TS + enable touch active interrupt + 7 + 1 + write-only + + + TOUCH_INACTIVE_INT_ENA_W1TS + enable touch inactive interrupt + 8 + 1 + write-only + + + BROWN_OUT_INT_ENA_W1TS + enable brown out interrupt + 9 + 1 + write-only + + + MAIN_TIMER_INT_ENA_W1TS + enable RTC main timer interrupt + 10 + 1 + write-only + + + SARADC1_INT_ENA_W1TS + enable saradc1 interrupt + 11 + 1 + write-only + + + TSENS_INT_ENA_W1TS + enable tsens interrupt + 12 + 1 + write-only + + + COCPU_INT_ENA_W1TS + enable riscV cocpu interrupt + 13 + 1 + write-only + + + SARADC2_INT_ENA_W1TS + enable saradc2 interrupt + 14 + 1 + write-only + + + SWD_INT_ENA_W1TS + enable super watch dog interrupt + 15 + 1 + write-only + + + XTAL32K_DEAD_INT_ENA_W1TS + enable xtal32k_dead interrupt + 16 + 1 + write-only + + + COCPU_TRAP_INT_ENA_W1TS + enable cocpu trap interrupt + 17 + 1 + write-only + + + TOUCH_TIMEOUT_INT_ENA_W1TS + enable touch timeout interrupt + 18 + 1 + write-only + + + GLITCH_DET_INT_ENA_W1TS + enbale gitch det interrupt + 19 + 1 + write-only + + + TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS + enbale touch approach_loop done interrupt + 20 + 1 + write-only + + + + + INT_ENA_RTC_W1TC + oneset clr rtc interrupt enable + 0x13C + 0x20 + + + SLP_WAKEUP_INT_ENA_W1TC + enable sleep wakeup interrupt + 0 + 1 + write-only + + + SLP_REJECT_INT_ENA_W1TC + enable sleep reject interrupt + 1 + 1 + write-only + + + SDIO_IDLE_INT_ENA_W1TC + enable SDIO idle interrupt + 2 + 1 + write-only + + + WDT_INT_ENA_W1TC + enable RTC WDT interrupt + 3 + 1 + write-only + + + TOUCH_SCAN_DONE_INT_ENA_W1TC + enable touch scan done interrupt + 4 + 1 + write-only + + + ULP_CP_INT_ENA_W1TC + enable ULP-coprocessor interrupt + 5 + 1 + write-only + + + TOUCH_DONE_INT_ENA_W1TC + enable touch done interrupt + 6 + 1 + write-only + + + TOUCH_ACTIVE_INT_ENA_W1TC + enable touch active interrupt + 7 + 1 + write-only + + + TOUCH_INACTIVE_INT_ENA_W1TC + enable touch inactive interrupt + 8 + 1 + write-only + + + BROWN_OUT_INT_ENA_W1TC + enable brown out interrupt + 9 + 1 + write-only + + + MAIN_TIMER_INT_ENA_W1TC + enable RTC main timer interrupt + 10 + 1 + write-only + + + SARADC1_INT_ENA_W1TC + enable saradc1 interrupt + 11 + 1 + write-only + + + TSENS_INT_ENA_W1TC + enable tsens interrupt + 12 + 1 + write-only + + + COCPU_INT_ENA_W1TC + enable riscV cocpu interrupt + 13 + 1 + write-only + + + SARADC2_INT_ENA_W1TC + enable saradc2 interrupt + 14 + 1 + write-only + + + SWD_INT_ENA_W1TC + enable super watch dog interrupt + 15 + 1 + write-only + + + XTAL32K_DEAD_INT_ENA_W1TC + enable xtal32k_dead interrupt + 16 + 1 + write-only + + + COCPU_TRAP_INT_ENA_W1TC + enable cocpu trap interrupt + 17 + 1 + write-only + + + TOUCH_TIMEOUT_INT_ENA_W1TC + enable touch timeout interrupt + 18 + 1 + write-only + + + GLITCH_DET_INT_ENA_W1TC + enbale gitch det interrupt + 19 + 1 + write-only + + + TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC + enbale touch approach_loop done interrupt + 20 + 1 + write-only + + + + + RETENTION_CTRL + configure retention + 0x140 + 0x20 + 0x28340000 + + + RETENTION_TAG_MODE + No public + 10 + 4 + read-write + + + RETENTION_TARGET + congfigure retention target cpu and/or tag + 14 + 2 + read-write + + + RETENTION_CLK_SEL + No public + 16 + 1 + read-write + + + RETENTION_DONE_WAIT + wait retention done cycle + 17 + 3 + read-write + + + RETENTION_CLKOFF_WAIT + wait clk off cycle + 20 + 4 + read-write + + + RETENTION_EN + enable retention + 24 + 1 + read-write + + + RETENTION_WAIT + wait cycles for rention operation + 25 + 7 + read-write + + + + + PG_CTRL + configure power glitch + 0x144 + 0x20 + + + POWER_GLITCH_DSENSE + GLITCH_DSENSE + 26 + 2 + read-write + + + POWER_GLITCH_FORCE_PD + force power glitch disable + 28 + 1 + read-write + + + POWER_GLITCH_FORCE_PU + force power glitch enable + 29 + 1 + read-write + + + POWER_GLITCH_EFUSE_SEL + select use analog fib signal + 30 + 1 + read-write + + + POWER_GLITCH_EN + enable power glitch + 31 + 1 + read-write + + + + + FIB_SEL + No public + 0x148 + 0x20 + 0x00000007 + + + FIB_SEL + No public + 0 + 3 + read-write + + + + + TOUCH_DAC + configure touch dac + 0x14C + 0x20 + + + TOUCH_PAD9_DAC + configure touch pad dac9 + 2 + 3 + read-write + + + TOUCH_PAD8_DAC + configure touch pad dac8 + 5 + 3 + read-write + + + TOUCH_PAD7_DAC + configure touch pad dac7 + 8 + 3 + read-write + + + TOUCH_PAD6_DAC + configure touch pad dac6 + 11 + 3 + read-write + + + TOUCH_PAD5_DAC + configure touch pad dac5 + 14 + 3 + read-write + + + TOUCH_PAD4_DAC + configure touch pad dac4 + 17 + 3 + read-write + + + TOUCH_PAD3_DAC + configure touch pad dac3 + 20 + 3 + read-write + + + TOUCH_PAD2_DAC + configure touch pad dac2 + 23 + 3 + read-write + + + TOUCH_PAD1_DAC + configure touch pad dac1 + 26 + 3 + read-write + + + TOUCH_PAD0_DAC + configure touch pad dac0 + 29 + 3 + read-write + + + + + TOUCH_DAC1 + configure touch dac + 0x150 + 0x20 + + + TOUCH_PAD14_DAC + configure touch pad dac14 + 17 + 3 + read-write + + + TOUCH_PAD13_DAC + configure touch pad dac13 + 20 + 3 + read-write + + + TOUCH_PAD12_DAC + configure touch pad dac12 + 23 + 3 + read-write + + + TOUCH_PAD11_DAC + configure touch pad dac11 + 26 + 3 + read-write + + + TOUCH_PAD10_DAC + configure touch pad dac10 + 29 + 3 + read-write + + + + + COCPU_DISABLE + configure ulp diable + 0x154 + 0x20 + + + DISABLE_RTC_CPU + configure ulp diable + 31 + 1 + read-write + + + + + DATE + version register + 0x1FC + 0x20 + 0x02101271 + + + DATE + version register + 0 + 28 + read-write + + + + + + + RTC_I2C + RTC_I2C Peripheral + RTC_I2C + 0x60008C00 + + 0x0 + 0x7C + registers + + + + SCL_LOW + configure low scl period + 0x0 + 0x20 + 0x00000100 + + + PERIOD + time period that scl =0 + 0 + 20 + read-write + + + + + CTRL + configure i2c ctrl + 0x4 + 0x20 + + + SDA_FORCE_OUT + 1=push pull,0=open drain + 0 + 1 + read-write + + + SCL_FORCE_OUT + 1=push pull,0=open drain + 1 + 1 + read-write + + + MS_MODE + 1=master,0=slave + 2 + 1 + read-write + + + TRANS_START + force start + 3 + 1 + read-write + + + TX_LSB_FIRST + transit lsb first + 4 + 1 + read-write + + + RX_LSB_FIRST + receive lsb first + 5 + 1 + read-write + + + I2C_CTRL_CLK_GATE_EN + configure i2c ctrl clk enable + 29 + 1 + read-write + + + I2C_RESET + rtc i2c sw reset + 30 + 1 + read-write + + + I2CCLK_EN + rtc i2c reg clk gating + 31 + 1 + read-write + + + + + STATUS + get i2c status + 0x8 + 0x20 + + + ACK_REC + ack response + 0 + 1 + read-only + + + SLAVE_RW + slave read or write + 1 + 1 + read-only + + + ARB_LOST + arbitration is lost + 2 + 1 + read-only + + + BUS_BUSY + bus is busy + 3 + 1 + read-only + + + SLAVE_ADDRESSED + slave reg sub address + 4 + 1 + read-only + + + BYTE_TRANS + One byte transit done + 5 + 1 + read-only + + + OP_CNT + which operation is working + 6 + 2 + read-only + + + SHIFT + shifter content + 16 + 8 + read-only + + + SCL_MAIN_STATE_LAST + i2c last main status + 24 + 3 + read-only + + + SCL_STATE_LAST + scl last status + 28 + 3 + read-only + + + + + TO + configure time out + 0xC + 0x20 + 0x00010000 + + + TIME_OUT + time out threshold + 0 + 20 + read-write + + + + + SLAVE_ADDR + configure slave id + 0x10 + 0x20 + + + SLAVE_ADDR + slave address + 0 + 15 + read-write + + + ADDR_10BIT_EN + i2c 10bit mode enable + 31 + 1 + read-write + + + + + SCL_HIGH + configure high scl period + 0x14 + 0x20 + 0x00000100 + + + PERIOD + time period that scl = 1 + 0 + 20 + read-write + + + + + SDA_DUTY + configure sda duty + 0x18 + 0x20 + 0x00000010 + + + NUM + time period for SDA to toggle after SCL goes low + 0 + 20 + read-write + + + + + SCL_START_PERIOD + configure scl start period + 0x1C + 0x20 + 0x00000008 + + + SCL_START_PERIOD + time period for SCL to toggle after I2C start is triggered + 0 + 20 + read-write + + + + + SCL_STOP_PERIOD + configure scl stop period + 0x20 + 0x20 + 0x00000008 + + + SCL_STOP_PERIOD + time period for SCL to stop after I2C end is triggered + 0 + 20 + read-write + + + + + INT_CLR + interrupt clear register + 0x24 + 0x20 + + + SLAVE_TRAN_COMP_INT_CLR + clear slave transit complete interrupt + 0 + 1 + write-only + + + ARBITRATION_LOST_INT_CLR + clear arbitration lost interrupt + 1 + 1 + write-only + + + MASTER_TRAN_COMP_INT_CLR + clear master transit complete interrupt + 2 + 1 + write-only + + + TRANS_COMPLETE_INT_CLR + clear transit complete interrupt + 3 + 1 + write-only + + + TIME_OUT_INT_CLR + clear time out interrupt + 4 + 1 + write-only + + + ACK_ERR_INT_CLR + clear ack error interrupt + 5 + 1 + write-only + + + RX_DATA_INT_CLR + clear receive data interrupt + 6 + 1 + write-only + + + TX_DATA_INT_CLR + clear transit load data complete interrupt + 7 + 1 + write-only + + + DETECT_START_INT_CLR + clear detect start interrupt + 8 + 1 + write-only + + + + + INT_RAW + interrupt raw register + 0x28 + 0x20 + + + SLAVE_TRAN_COMP_INT_RAW + slave transit complete interrupt raw + 0 + 1 + read-only + + + ARBITRATION_LOST_INT_RAW + arbitration lost interrupt raw + 1 + 1 + read-only + + + MASTER_TRAN_COMP_INT_RAW + master transit complete interrupt raw + 2 + 1 + read-only + + + TRANS_COMPLETE_INT_RAW + transit complete interrupt raw + 3 + 1 + read-only + + + TIME_OUT_INT_RAW + time out interrupt raw + 4 + 1 + read-only + + + ACK_ERR_INT_RAW + ack error interrupt raw + 5 + 1 + read-only + + + RX_DATA_INT_RAW + receive data interrupt raw + 6 + 1 + read-only + + + TX_DATA_INT_RAW + transit data interrupt raw + 7 + 1 + read-only + + + DETECT_START_INT_RAW + detect start interrupt raw + 8 + 1 + read-only + + + + + INT_ST + interrupt state register + 0x2C + 0x20 + + + SLAVE_TRAN_COMP_INT_ST + slave transit complete interrupt state + 0 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + arbitration lost interrupt state + 1 + 1 + read-only + + + MASTER_TRAN_COMP_INT_ST + master transit complete interrupt state + 2 + 1 + read-only + + + TRANS_COMPLETE_INT_ST + transit complete interrupt state + 3 + 1 + read-only + + + TIME_OUT_INT_ST + time out interrupt state + 4 + 1 + read-only + + + ACK_ERR_INT_ST + ack error interrupt state + 5 + 1 + read-only + + + RX_DATA_INT_ST + receive data interrupt state + 6 + 1 + read-only + + + TX_DATA_INT_ST + transit data interrupt state + 7 + 1 + read-only + + + DETECT_START_INT_ST + detect start interrupt state + 8 + 1 + read-only + + + + + INT_ENA + interrupt enable register + 0x30 + 0x20 + + + SLAVE_TRAN_COMP_INT_ENA + enable slave transit complete interrupt + 0 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + enable arbitration lost interrupt + 1 + 1 + read-write + + + MASTER_TRAN_COMP_INT_ENA + enable master transit complete interrupt + 2 + 1 + read-write + + + TRANS_COMPLETE_INT_ENA + enable transit complete interrupt + 3 + 1 + read-write + + + TIME_OUT_INT_ENA + enable time out interrupt + 4 + 1 + read-write + + + ACK_ERR_INT_ENA + enable eack error interrupt + 5 + 1 + read-write + + + RX_DATA_INT_ENA + enable receive data interrupt + 6 + 1 + read-write + + + TX_DATA_INT_ENA + enable transit data interrupt + 7 + 1 + read-write + + + DETECT_START_INT_ENA + enable detect start interrupt + 8 + 1 + read-write + + + + + DATA + get i2c data status + 0x34 + 0x20 + + + I2C_RDATA + data received + 0 + 8 + read-only + + + SLAVE_TX_DATA + data sent by slave + 8 + 8 + read-write + + + I2C_DONE + i2c done + 31 + 1 + read-only + + + + + CMD0 + i2c commond0 register + 0x38 + 0x20 + 0x00000903 + + + COMMAND0 + command0 + 0 + 14 + read-write + + + COMMAND0_DONE + command0_done + 31 + 1 + read-only + + + + + CMD1 + i2c commond1 register + 0x3C + 0x20 + 0x00001901 + + + COMMAND1 + command1 + 0 + 14 + read-write + + + COMMAND1_DONE + command1_done + 31 + 1 + read-only + + + + + CMD2 + i2c commond2 register + 0x40 + 0x20 + 0x00000902 + + + COMMAND2 + command2 + 0 + 14 + read-write + + + COMMAND2_DONE + command2_done + 31 + 1 + read-only + + + + + CMD3 + i2c commond3 register + 0x44 + 0x20 + 0x00000101 + + + COMMAND3 + command3 + 0 + 14 + read-write + + + COMMAND3_DONE + command3_done + 31 + 1 + read-only + + + + + CMD4 + i2c commond4 register + 0x48 + 0x20 + 0x00000901 + + + COMMAND4 + command4 + 0 + 14 + read-write + + + COMMAND4_DONE + command4_done + 31 + 1 + read-only + + + + + CMD5 + i2c commond5_register + 0x4C + 0x20 + 0x00001701 + + + COMMAND5 + command5 + 0 + 14 + read-write + + + COMMAND5_DONE + command5_done + 31 + 1 + read-only + + + + + CMD6 + i2c commond6 register + 0x50 + 0x20 + 0x00001901 + + + COMMAND6 + command6 + 0 + 14 + read-write + + + COMMAND6_DONE + command6_done + 31 + 1 + read-only + + + + + CMD7 + i2c commond7 register + 0x54 + 0x20 + 0x00000904 + + + COMMAND7 + command7 + 0 + 14 + read-write + + + COMMAND7_DONE + command7_done + 31 + 1 + read-only + + + + + CMD8 + i2c commond8 register + 0x58 + 0x20 + 0x00001901 + + + COMMAND8 + command8 + 0 + 14 + read-write + + + COMMAND8_DONE + command8_done + 31 + 1 + read-only + + + + + CMD9 + i2c commond9 register + 0x5C + 0x20 + 0x00000903 + + + COMMAND9 + command9 + 0 + 14 + read-write + + + COMMAND9_DONE + command9_done + 31 + 1 + read-only + + + + + CMD10 + i2c commond10 register + 0x60 + 0x20 + 0x00000101 + + + COMMAND10 + command10 + 0 + 14 + read-write + + + COMMAND10_DONE + command10_done + 31 + 1 + read-only + + + + + CMD11 + i2c commond11 register + 0x64 + 0x20 + 0x00000901 + + + COMMAND11 + command11 + 0 + 14 + read-write + + + COMMAND11_DONE + command11_done + 31 + 1 + read-only + + + + + CMD12 + i2c commond12 register + 0x68 + 0x20 + 0x00001701 + + + COMMAND12 + command12 + 0 + 14 + read-write + + + COMMAND12_DONE + command12_done + 31 + 1 + read-only + + + + + CMD13 + i2c commond13 register + 0x6C + 0x20 + 0x00001901 + + + COMMAND13 + command13 + 0 + 14 + read-write + + + COMMAND13_DONE + command13_done + 31 + 1 + read-only + + + + + CMD14 + i2c commond14 register + 0x70 + 0x20 + + + COMMAND14 + command14 + 0 + 14 + read-write + + + COMMAND14_DONE + command14_done + 31 + 1 + read-only + + + + + CMD15 + i2c commond15 register + 0x74 + 0x20 + + + COMMAND15 + command15 + 0 + 14 + read-write + + + COMMAND15_DONE + command15_done + 31 + 1 + read-only + + + + + DATE + version register + 0xFC + 0x20 + 0x01905310 + + + I2C_DATE + version + 0 + 28 + read-write + + + + + + + RTC_IO + RTC_IO Peripheral + RTC_IO + 0x60008400 + + 0x0 + 0xF0 + registers + + + + RTC_GPIO_OUT + RTC GPIO 0 ~ 21 output data register + 0x0 + 0x20 + + + DATA + RTC GPIO 0 ~ 21 output data + 10 + 22 + read-write + + + + + RTC_GPIO_OUT_W1TS + one set RTC GPIO output data + 0x4 + 0x20 + + + RTC_GPIO_OUT_DATA_W1TS + RTC GPIO 0 ~ 21 output data write 1 to set + 10 + 22 + write-only + + + + + RTC_GPIO_OUT_W1TC + one clear RTC GPIO output data + 0x8 + 0x20 + + + RTC_GPIO_OUT_DATA_W1TC + RTC GPIO 0 ~ 21 output data write 1 to clear + 10 + 22 + write-only + + + + + RTC_GPIO_ENABLE + Configure RTC GPIO output enable + 0xC + 0x20 + + + RTC_GPIO_ENABLE + RTC GPIO 0 ~ 21 enable + 10 + 22 + read-write + + + + + RTC_GPIO_ENABLE_W1TS + one set RTC GPIO output enable + 0x10 + 0x20 + + + RTC_GPIO_ENABLE_W1TS + RTC GPIO 0 ~ 21 enable write 1 to set + 10 + 22 + write-only + + + + + ENABLE_W1TC + one clear RTC GPIO output enable + 0x14 + 0x20 + + + ENABLE_W1TC + RTC GPIO 0 ~ 21 enable write 1 to clear + 10 + 22 + write-only + + + + + RTC_GPIO_STATUS + RTC GPIO 0 ~ 21 interrupt status + 0x18 + 0x20 + + + INT + RTC GPIO 0 ~ 21 interrupt status + 10 + 22 + read-write + + + + + RTC_GPIO_STATUS_W1TS + One set RTC GPIO 0 ~ 21 interrupt status + 0x1C + 0x20 + + + RTC_GPIO_STATUS_INT_W1TS + RTC GPIO 0 ~ 21 interrupt status write 1 to set + 10 + 22 + write-only + + + + + RTC_GPIO_STATUS_W1TC + One clear RTC GPIO 0 ~ 21 interrupt status + 0x20 + 0x20 + + + RTC_GPIO_STATUS_INT_W1TC + RTC GPIO 0 ~ 21 interrupt status write 1 to clear + 10 + 22 + write-only + + + + + RTC_GPIO_IN + RTC GPIO input data + 0x24 + 0x20 + + + NEXT + RTC GPIO input data + 10 + 22 + read-only + + + + + 22 + 0x4 + 0-21 + PIN%s + configure RTC GPIO%s + 0x28 + 0x20 + + + PAD_DRIVER + if set to 0: normal output, if set to 1: open drain + 2 + 1 + read-write + + + INT_TYPE + if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger + 7 + 3 + read-write + + + WAKEUP_ENABLE + RTC GPIO wakeup enable bit + 10 + 1 + read-write + + + + + RTC_DEBUG_SEL + configure rtc debug + 0x80 + 0x20 + + + RTC_DEBUG_SEL0 + configure rtc debug + 0 + 5 + read-write + + + RTC_DEBUG_SEL1 + configure rtc debug + 5 + 5 + read-write + + + RTC_DEBUG_SEL2 + configure rtc debug + 10 + 5 + read-write + + + RTC_DEBUG_SEL3 + configure rtc debug + 15 + 5 + read-write + + + RTC_DEBUG_SEL4 + configure rtc debug + 20 + 5 + read-write + + + RTC_DEBUG_12M_NO_GATING + configure rtc debug + 25 + 1 + read-write + + + + + TOUCH_PAD0 + configure RTC PAD0 + 0x84 + 0x20 + 0x50000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD1 + configure RTC PAD1 + 0x88 + 0x20 + 0x48000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD2 + configure RTC PAD2 + 0x8C + 0x20 + 0x50000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD3 + configure RTC PAD3 + 0x90 + 0x20 + 0x48000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD4 + configure RTC PAD4 + 0x94 + 0x20 + 0x50000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD5 + configure RTC PAD5 + 0x98 + 0x20 + 0x50000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD6 + configure RTC PAD6 + 0x9C + 0x20 + 0x48000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD7 + configure RTC PAD7 + 0xA0 + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD8 + configure RTC PAD8 + 0xA4 + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD9 + configure RTC PAD9 + 0xA8 + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD10 + configure RTC PAD10 + 0xAC + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD11 + configure RTC PAD11 + 0xB0 + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD12 + configure RTC PAD12 + 0xB4 + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD13 + configure RTC PAD13 + 0xB8 + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD14 + configure RTC PAD14 + 0xBC + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + XTAL_32P_PAD + configure RTC PAD15 + 0xC0 + 0x20 + 0x40000000 + + + X32P_FUN_IE + input enable in work mode + 13 + 1 + read-write + + + X32P_SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + X32P_SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + X32P_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + X32P_FUN_SEL + function sel + 17 + 2 + read-write + + + X32P_MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + X32P_RUE + RUE + 27 + 1 + read-write + + + X32P_RDE + RDE + 28 + 1 + read-write + + + X32P_DRV + DRV + 29 + 2 + read-write + + + + + XTAL_32N_PAD + configure RTC PAD16 + 0xC4 + 0x20 + 0x40000000 + + + X32N_FUN_IE + input enable in work mode + 13 + 1 + read-write + + + X32N_SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + X32N_SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + X32N_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + X32N_FUN_SEL + function sel + 17 + 2 + read-write + + + X32N_MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + X32N_RUE + RUE + 27 + 1 + read-write + + + X32N_RDE + RDE + 28 + 1 + read-write + + + X32N_DRV + DRV + 29 + 2 + read-write + + + + + PAD_DAC1 + configure RTC PAD17 + 0xC8 + 0x20 + 0x40000000 + + + PDAC1_DAC + PDAC1_DAC + 3 + 8 + read-write + + + PDAC1_XPD_DAC + PDAC1_XPD_DAC + 11 + 1 + read-write + + + PDAC1_DAC_XPD_FORCE + 1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC,0: use SAR ADC FSM to control PDAC1_XPD_DAC + 12 + 1 + read-write + + + PDAC1_FUN_IE + input enable in work mode + 13 + 1 + read-write + + + PDAC1_SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + PDAC1_SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + PDAC1_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + PDAC1_FUN_SEL + PDAC1 function sel + 17 + 2 + read-write + + + PDAC1_MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + PDAC1_RUE + PDAC1_RUE + 27 + 1 + read-write + + + PDAC1_RDE + PDAC1_RDE + 28 + 1 + read-write + + + PDAC1_DRV + PDAC1_DRV + 29 + 2 + read-write + + + + + PAD_DAC2 + configure RTC PAD18 + 0xCC + 0x20 + 0x40000000 + + + PDAC2_DAC + PDAC2_DAC + 3 + 8 + read-write + + + PDAC2_XPD_DAC + PDAC2_XPD_DAC + 11 + 1 + read-write + + + PDAC2_DAC_XPD_FORCE + 1: use reg_pdac2_xpd_dac to control PDAC2_XPD_DAC,0: use SAR ADC FSM to control PDAC2_XPD_DAC + 12 + 1 + read-write + + + PDAC2_FUN_IE + input enable in work mode + 13 + 1 + read-write + + + PDAC2_SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + PDAC2_SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + PDAC2_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + PDAC2_FUN_SEL + PDAC1 function sel + 17 + 2 + read-write + + + PDAC2_MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + PDAC2_RUE + PDAC2_RUE + 27 + 1 + read-write + + + PDAC2_RDE + PDAC2_RDE + 28 + 1 + read-write + + + PDAC2_DRV + PDAC2_DRV + 29 + 2 + read-write + + + + + RTC_PAD19 + configure RTC PAD19 + 0xD0 + 0x20 + 0x50000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + RTC_PAD20 + configure RTC PAD20 + 0xD4 + 0x20 + 0x50000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + RTC_PAD21 + configure RTC PAD21 + 0xD8 + 0x20 + 0x50000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + EXT_WAKEUP0 + configure EXT0 wakeup + 0xDC + 0x20 + + + SEL + ******* Description configure*** + 27 + 5 + read-write + + + + + XTL_EXT_CTR + configure gpio pd XTAL + 0xE0 + 0x20 + + + SEL + select RTC GPIO 0 ~ 17 to control XTAL + 27 + 5 + read-write + + + + + SAR_I2C_IO + configure rtc i2c mux + 0xE4 + 0x20 + + + SAR_DEBUG_BIT_SEL + ******* Description configure*** + 23 + 5 + read-write + + + SAR_I2C_SCL_SEL + ******* Description configure*** + 28 + 2 + read-write + + + SAR_I2C_SDA_SEL + ******* Description configure*** + 30 + 2 + read-write + + + + + TOUCH_CTRL + configure touch pad bufmode + 0xE8 + 0x20 + + + IO_TOUCH_BUFSEL + BUF_SEL when touch work without fsm + 0 + 4 + read-write + + + IO_TOUCH_BUFMODE + BUF_MODE when touch work without fsm + 4 + 1 + read-write + + + + + DATE + version + 0x1FC + 0x20 + 0x02101180 + + + DATE + version + 0 + 28 + read-write + + + + + + + SENS + SENS Peripheral + SENS + 0x60008800 + + 0x0 + 0x11C + registers + + + + SAR_READER1_CTRL + configure saradc1 reader + 0x0 + 0x20 + 0x20040002 + + + SAR_SAR1_CLK_DIV + clock divider + 0 + 8 + read-write + + + SAR_SAR1_CLK_GATED + no public + 18 + 1 + read-write + + + SAR_SAR1_SAMPLE_NUM + no public + 19 + 8 + read-write + + + SAR_SAR1_DATA_INV + Invert SAR ADC1 data + 28 + 1 + read-write + + + SAR_SAR1_INT_EN + enable saradc1 to send out interrupt + 29 + 1 + read-write + + + + + SAR_READER1_STATUS + get saradc1 reader controller status + 0x4 + 0x20 + + + SAR_SAR1_READER_STATUS + get saradc1 reader controller status + 0 + 32 + read-only + + + + + SAR_MEAS1_CTRL1 + no public + 0x8 + 0x20 + + + FORCE_XPD_AMP + no public + 24 + 2 + read-write + + + AMP_RST_FB_FORCE + no public + 26 + 2 + read-write + + + AMP_SHORT_REF_FORCE + no public + 28 + 2 + read-write + + + AMP_SHORT_REF_GND_FORCE + no public + 30 + 2 + read-write + + + + + SAR_MEAS1_CTRL2 + configure saradc1 controller + 0xC + 0x20 + + + MEAS1_DATA_SAR + SAR ADC1 data + 0 + 16 + read-only + + + MEAS1_DONE_SAR + SAR ADC1 conversion done indication + 16 + 1 + read-only + + + MEAS1_START_SAR + SAR ADC1 controller (in RTC) starts conversion + 17 + 1 + read-write + + + MEAS1_START_FORCE + 1: SAR ADC1 controller (in RTC) is started by SW + 18 + 1 + read-write + + + SAR1_EN_PAD + SAR ADC1 pad enable bitmap + 19 + 12 + read-write + + + SAR1_EN_PAD_FORCE + 1: SAR ADC1 pad enable bitmap is controlled by SW + 31 + 1 + read-write + + + + + SAR_MEAS1_MUX + configure saradc1 controller + 0x10 + 0x20 + + + SAR1_DIG_FORCE + 1: SAR ADC1 controlled by DIG ADC1 CTRL + 31 + 1 + read-write + + + + + SAR_ATTEN1 + configure saradc1 controller + 0x14 + 0x20 + 0xFFFFFFFF + + + SAR1_ATTEN + 2-bit attenuation for each pad + 0 + 32 + read-write + + + + + SAR_AMP_CTRL1 + no public + 0x18 + 0x20 + 0x000A000A + + + SAR_AMP_WAIT1 + no public + 0 + 16 + read-write + + + SAR_AMP_WAIT2 + no public + 16 + 16 + read-write + + + + + SAR_AMP_CTRL2 + no public + 0x1C + 0x20 + 0x000A0000 + + + SAR_SAR1_DAC_XPD_FSM_IDLE + no public + 0 + 1 + read-write + + + SAR_XPD_SAR_AMP_FSM_IDLE + no public + 1 + 1 + read-write + + + SAR_AMP_RST_FB_FSM_IDLE + no public + 2 + 1 + read-write + + + SAR_AMP_SHORT_REF_FSM_IDLE + no public + 3 + 1 + read-write + + + SAR_AMP_SHORT_REF_GND_FSM_IDLE + no public + 4 + 1 + read-write + + + SAR_XPD_SAR_FSM_IDLE + no public + 5 + 1 + read-write + + + SAR_RSTB_FSM_IDLE + no public + 6 + 1 + read-write + + + SAR_AMP_WAIT3 + no public + 16 + 16 + read-write + + + + + SAR_AMP_CTRL3 + no public + 0x20 + 0x20 + 0x007338F3 + + + SAR1_DAC_XPD_FSM + no public + 0 + 4 + read-write + + + XPD_SAR_AMP_FSM + no public + 4 + 4 + read-write + + + AMP_RST_FB_FSM + no public + 8 + 4 + read-write + + + AMP_SHORT_REF_FSM + no public + 12 + 4 + read-write + + + AMP_SHORT_REF_GND_FSM + no public + 16 + 4 + read-write + + + XPD_SAR_FSM + no public + 20 + 4 + read-write + + + RSTB_FSM + no public + 24 + 4 + read-write + + + + + SAR_READER2_CTRL + configure saradc2 reader + 0x24 + 0x20 + 0x40050002 + + + SAR_SAR2_CLK_DIV + clock divider + 0 + 8 + read-write + + + SAR_SAR2_WAIT_ARB_CYCLE + wait arbit stable after sar_done + 16 + 2 + read-write + + + SAR_SAR2_CLK_GATED + ******* Description *********** + 18 + 1 + read-write + + + SAR_SAR2_SAMPLE_NUM + ******* Description *********** + 19 + 8 + read-write + + + SAR_SAR2_DATA_INV + Invert SAR ADC2 data + 29 + 1 + read-write + + + SAR_SAR2_INT_EN + enable saradc2 to send out interrupt + 30 + 1 + read-write + + + + + SAR_READER2_STATUS + get saradc1 reader controller status + 0x28 + 0x20 + + + SAR_SAR2_READER_STATUS + get saradc1 reader controller status + 0 + 32 + read-only + + + + + SAR_MEAS2_CTRL1 + configure saradc2 controller + 0x2C + 0x20 + 0x07020200 + + + SAR_SAR2_CNTL_STATE + saradc2_cntl_fsm + 0 + 3 + read-only + + + SAR_SAR2_PWDET_CAL_EN + rtc control pwdet enable + 3 + 1 + read-write + + + SAR_SAR2_PKDET_CAL_EN + rtc control pkdet enable + 4 + 1 + read-write + + + SAR_SAR2_EN_TEST + SAR2_EN_TEST + 5 + 1 + read-write + + + SAR_SAR2_RSTB_FORCE + no public + 6 + 2 + read-write + + + SAR_SAR2_STANDBY_WAIT + no public + 8 + 8 + read-write + + + SAR_SAR2_RSTB_WAIT + no public + 16 + 8 + read-write + + + SAR_SAR2_XPD_WAIT + no public + 24 + 8 + read-write + + + + + SAR_MEAS2_CTRL2 + configure saradc2 controller + 0x30 + 0x20 + + + MEAS2_DATA_SAR + SAR ADC2 data + 0 + 16 + read-only + + + MEAS2_DONE_SAR + SAR ADC2 conversion done indication + 16 + 1 + read-only + + + MEAS2_START_SAR + SAR ADC2 controller (in RTC) starts conversion + 17 + 1 + read-write + + + MEAS2_START_FORCE + 1: SAR ADC2 controller (in RTC) is started by SW + 18 + 1 + read-write + + + SAR2_EN_PAD + SAR ADC2 pad enable bitmap + 19 + 12 + read-write + + + SAR2_EN_PAD_FORCE + 1: SAR ADC2 pad enable bitmap is controlled by SW + 31 + 1 + read-write + + + + + SAR_MEAS2_MUX + configure saradc2 controller + 0x34 + 0x20 + + + SAR2_PWDET_CCT + SAR2_PWDET_CCT + 28 + 3 + read-write + + + SAR2_RTC_FORCE + in sleep, force to use rtc to control ADC + 31 + 1 + read-write + + + + + SAR_ATTEN2 + configure saradc2 controller + 0x38 + 0x20 + 0xFFFFFFFF + + + SAR2_ATTEN + 2-bit attenuation for each pad + 0 + 32 + read-write + + + + + SAR_POWER_XPD_SAR + configure power of saradc + 0x3C + 0x20 + + + FORCE_XPD_SAR + force power on/off saradc + 29 + 2 + read-write + + + SARCLK_EN + no public + 31 + 1 + read-write + + + + + SAR_SLAVE_ADDR1 + configure i2c slave address + 0x40 + 0x20 + + + SAR_I2C_SLAVE_ADDR1 + configure i2c slave address1 + 0 + 11 + read-write + + + SAR_I2C_SLAVE_ADDR0 + configure i2c slave address0 + 11 + 11 + read-write + + + SAR_SARADC_MEAS_STATUS + no public + 22 + 8 + read-only + + + + + SAR_SLAVE_ADDR2 + configure i2c slave address + 0x44 + 0x20 + + + SAR_I2C_SLAVE_ADDR3 + configure i2c slave address3 + 0 + 11 + read-write + + + SAR_I2C_SLAVE_ADDR2 + configure i2c slave address2 + 11 + 11 + read-write + + + + + SAR_SLAVE_ADDR3 + configure i2c slave address + 0x48 + 0x20 + + + SAR_I2C_SLAVE_ADDR5 + configure i2c slave address5 + 0 + 11 + read-write + + + SAR_I2C_SLAVE_ADDR4 + configure i2c slave address4 + 11 + 11 + read-write + + + + + SAR_SLAVE_ADDR4 + configure i2c slave address + 0x4C + 0x20 + + + SAR_I2C_SLAVE_ADDR7 + configure i2c slave address7 + 0 + 11 + read-write + + + SAR_I2C_SLAVE_ADDR6 + configure i2c slave address6 + 11 + 11 + read-write + + + + + SAR_TSENS_CTRL + configure tsens controller + 0x50 + 0x20 + 0x00019000 + + + SAR_TSENS_OUT + temperature sensor data out + 0 + 8 + read-only + + + SAR_TSENS_READY + indicate temperature sensor out ready + 8 + 1 + read-only + + + SAR_TSENS_INT_EN + enable temperature sensor to send out interrupt + 12 + 1 + read-write + + + SAR_TSENS_IN_INV + invert temperature sensor data + 13 + 1 + read-write + + + SAR_TSENS_CLK_DIV + temperature sensor clock divider + 14 + 8 + read-write + + + SAR_TSENS_POWER_UP + temperature sensor power up + 22 + 1 + read-write + + + SAR_TSENS_POWER_UP_FORCE + 1: dump out & power up controlled by SW 0: by FSM + 23 + 1 + read-write + + + SAR_TSENS_DUMP_OUT + temperature sensor dump out only active when reg_tsens_power_up_force = 1 + 24 + 1 + read-write + + + + + SAR_TSENS_CTRL2 + configure tsens controller + 0x54 + 0x20 + 0x00004002 + + + SAR_TSENS_XPD_WAIT + no public + 0 + 12 + read-write + + + SAR_TSENS_XPD_FORCE + no public + 12 + 2 + read-write + + + SAR_TSENS_CLK_INV + no public + 14 + 1 + read-write + + + + + SAR_I2C_CTRL + configure rtc i2c controller by sw + 0x58 + 0x20 + + + SAR_I2C_CTRL + I2C control data only active when reg_sar_i2c_start_force = 1 + 0 + 28 + read-write + + + SAR_I2C_START + start I2C only active when reg_sar_i2c_start_force = 1 + 28 + 1 + read-write + + + SAR_I2C_START_FORCE + 1: I2C started by SW 0: I2C started by FSM + 29 + 1 + read-write + + + + + SAR_TOUCH_CONF + configure touch controller + 0x5C + 0x20 + 0xFFF07FFF + + + SAR_TOUCH_OUTEN + touch controller output enable + 0 + 15 + read-write + + + SAR_TOUCH_STATUS_CLR + clear all touch active status + 15 + 1 + write-only + + + SAR_TOUCH_DATA_SEL + 3: smooth data 2: baseline 1,0: raw_data + 16 + 2 + read-write + + + SAR_TOUCH_DENOISE_END + touch_denoise_done + 18 + 1 + read-only + + + SAR_TOUCH_UNIT_END + touch_unit_done + 19 + 1 + read-only + + + SAR_TOUCH_APPROACH_PAD2 + indicate which pad is approach pad2 + 20 + 4 + read-write + + + SAR_TOUCH_APPROACH_PAD1 + indicate which pad is approach pad1 + 24 + 4 + read-write + + + SAR_TOUCH_APPROACH_PAD0 + indicate which pad is approach pad0 + 28 + 4 + read-write + + + + + SAR_TOUCH_DENOISE + configure touch controller + 0x60 + 0x20 + + + DATA + configure touch controller + 0 + 22 + read-only + + + + + SAR_TOUCH_THRES1 + configure touch thres of touch pad + 0x64 + 0x20 + + + SAR_TOUCH_OUT_TH1 + Finger threshold for touch pad 1 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES2 + configure touch thres of touch pad + 0x68 + 0x20 + + + SAR_TOUCH_OUT_TH2 + Finger threshold for touch pad 2 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES3 + configure touch thres of touch pad + 0x6C + 0x20 + + + SAR_TOUCH_OUT_TH3 + Finger threshold for touch pad 3 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES4 + configure touch thres of touch pad + 0x70 + 0x20 + + + SAR_TOUCH_OUT_TH4 + Finger threshold for touch pad 4 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES5 + configure touch thres of touch pad + 0x74 + 0x20 + + + SAR_TOUCH_OUT_TH5 + Finger threshold for touch pad 5 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES6 + configure touch thres of touch pad + 0x78 + 0x20 + + + SAR_TOUCH_OUT_TH6 + Finger threshold for touch pad 6 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES7 + configure touch thres of touch pad + 0x7C + 0x20 + + + SAR_TOUCH_OUT_TH7 + Finger threshold for touch pad 7 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES8 + configure touch thres of touch pad + 0x80 + 0x20 + + + SAR_TOUCH_OUT_TH8 + Finger threshold for touch pad 8 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES9 + configure touch thres of touch pad + 0x84 + 0x20 + + + SAR_TOUCH_OUT_TH9 + Finger threshold for touch pad 9 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES10 + configure touch thres of touch pad + 0x88 + 0x20 + + + SAR_TOUCH_OUT_TH10 + Finger threshold for touch pad 10 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES11 + configure touch thres of touch pad + 0x8C + 0x20 + + + SAR_TOUCH_OUT_TH11 + Finger threshold for touch pad 11 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES12 + configure touch thres of touch pad + 0x90 + 0x20 + + + SAR_TOUCH_OUT_TH12 + Finger threshold for touch pad 12 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES13 + configure touch thres of touch pad + 0x94 + 0x20 + + + SAR_TOUCH_OUT_TH13 + Finger threshold for touch pad 13 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES14 + configure touch thres of touch pad + 0x98 + 0x20 + + + SAR_TOUCH_OUT_TH14 + Finger threshold for touch pad 14 + 0 + 22 + read-write + + + + + SAR_TOUCH_CHN_ST + Get touch channel status + 0x9C + 0x20 + + + SAR_TOUCH_PAD_ACTIVE + touch active status + 0 + 15 + read-only + + + SAR_TOUCH_CHANNEL_CLR + Clear touch channel + 15 + 15 + write-only + + + SAR_TOUCH_MEAS_DONE + get touch meas done + 31 + 1 + read-only + + + + + SAR_TOUCH_STATUS0 + get touch scan status + 0xA0 + 0x20 + + + SAR_TOUCH_SCAN_CURR + current sample channel + 22 + 4 + read-only + + + + + SAR_TOUCH_STATUS1 + touch channel status of touch pad 1 + 0xA4 + 0x20 + + + SAR_TOUCH_PAD1_DATA + touch data debounce of touch pad 1 + 0 + 22 + read-only + + + SAR_TOUCH_PAD1_DEBOUNCE + touch current debounce of touch pad 1 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS2 + touch channel status of touch pad 2 + 0xA8 + 0x20 + + + SAR_TOUCH_PAD2_DATA + touch data debounce of touch pad 2 + 0 + 22 + read-only + + + SAR_TOUCH_PAD2_DEBOUNCE + touch current debounce of touch pad 2 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS3 + touch channel status of touch pad 3 + 0xAC + 0x20 + + + SAR_TOUCH_PAD3_DATA + touch data debounce of touch pad 3 + 0 + 22 + read-only + + + SAR_TOUCH_PAD3_DEBOUNCE + touch current debounce of touch pad 3 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS4 + touch channel status of touch pad 4 + 0xB0 + 0x20 + + + SAR_TOUCH_PAD4_DATA + touch data debounce of touch pad 4 + 0 + 22 + read-only + + + SAR_TOUCH_PAD4_DEBOUNCE + touch current debounce of touch pad 4 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS5 + touch channel status of touch pad 5 + 0xB4 + 0x20 + + + SAR_TOUCH_PAD5_DATA + touch data debounce of touch pad 5 + 0 + 22 + read-only + + + SAR_TOUCH_PAD5_DEBOUNCE + touch current debounce of touch pad 5 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS6 + touch channel status of touch pad 6 + 0xB8 + 0x20 + + + SAR_TOUCH_PAD6_DATA + touch data debounce of touch pad 6 + 0 + 22 + read-only + + + SAR_TOUCH_PAD6_DEBOUNCE + touch current debounce of touch pad 6 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS7 + touch channel status of touch pad 7 + 0xBC + 0x20 + + + SAR_TOUCH_PAD7_DATA + touch data debounce of touch pad 7 + 0 + 22 + read-only + + + SAR_TOUCH_PAD7_DEBOUNCE + touch current debounce of touch pad 7 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS8 + touch channel status of touch pad 8 + 0xC0 + 0x20 + + + SAR_TOUCH_PAD8_DATA + touch data debounce of touch pad 8 + 0 + 22 + read-only + + + SAR_TOUCH_PAD8_DEBOUNCE + touch current debounce of touch pad 8 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS9 + touch channel status of touch pad 9 + 0xC4 + 0x20 + + + SAR_TOUCH_PAD9_DATA + touch data debounce of touch pad 9 + 0 + 22 + read-only + + + SAR_TOUCH_PAD9_DEBOUNCE + touch current debounce of touch pad 9 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS10 + touch channel status of touch pad 10 + 0xC8 + 0x20 + + + SAR_TOUCH_PAD10_DATA + touch data debounce of touch pad 10 + 0 + 22 + read-only + + + SAR_TOUCH_PAD10_DEBOUNCE + touch current debounce of touch pad 10 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS11 + touch channel status of touch pad 11 + 0xCC + 0x20 + + + SAR_TOUCH_PAD11_DATA + touch data debounce of touch pad 11 + 0 + 22 + read-only + + + SAR_TOUCH_PAD11_DEBOUNCE + touch current debounce of touch pad 11 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS12 + touch channel status of touch pad 12 + 0xD0 + 0x20 + + + SAR_TOUCH_PAD12_DATA + touch data debounce of touch pad 12 + 0 + 22 + read-only + + + SAR_TOUCH_PAD12_DEBOUNCE + touch current debounce of touch pad 12 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS13 + touch channel status of touch pad 13 + 0xD4 + 0x20 + + + SAR_TOUCH_PAD13_DATA + touch data debounce of touch pad 13 + 0 + 22 + read-only + + + SAR_TOUCH_PAD13_DEBOUNCE + touch current debounce of touch pad 13 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS14 + touch channel status of touch pad 14 + 0xD8 + 0x20 + + + SAR_TOUCH_PAD14_DATA + touch data debounce of touch pad 14 + 0 + 22 + read-only + + + SAR_TOUCH_PAD14_DEBOUNCE + touch current debounce of touch pad 14 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS15 + touch channel status of sleep pad + 0xDC + 0x20 + + + SAR_TOUCH_SLP_DATA + touch data debounce of sleep pad + 0 + 22 + read-only + + + SAR_TOUCH_SLP_DEBOUNCE + touch current debounce of sleep pad + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS16 + touch channel status of approach mode + 0xE0 + 0x20 + + + SAR_TOUCH_APPROACH_PAD2_CNT + touch current approach count of approach pad2 + 0 + 8 + read-only + + + SAR_TOUCH_APPROACH_PAD1_CNT + touch current approach count of approach pad1 + 8 + 8 + read-only + + + SAR_TOUCH_APPROACH_PAD0_CNT + touch current approach count of approach pad0 + 16 + 8 + read-only + + + SAR_TOUCH_SLP_APPROACH_CNT + touch current approach count of slp pad + 24 + 8 + read-only + + + + + SAR_COCPU_STATE + get cocpu status + 0xE4 + 0x20 + + + SAR_COCPU_DBG_TRIGGER + trigger cocpu debug registers + 25 + 1 + write-only + + + SAR_COCPU_CLK_EN_ST + check cocpu whether clk on + 26 + 1 + read-only + + + SAR_COCPU_RESET_N + check cocpu whether in reset state + 27 + 1 + read-only + + + SAR_COCPU_EOI + check cocpu whether in interrupt state + 28 + 1 + read-only + + + SAR_COCPU_TRAP + check cocpu whether in trap state + 29 + 1 + read-only + + + SAR_COCPU_EBREAK + check cocpu whether in ebreak + 30 + 1 + read-only + + + + + SAR_COCPU_INT_RAW + the interrupt raw of ulp + 0xE8 + 0x20 + + + SAR_COCPU_TOUCH_DONE_INT_RAW + int from touch done + 0 + 1 + read-only + + + SAR_COCPU_TOUCH_INACTIVE_INT_RAW + int from touch inactive + 1 + 1 + read-only + + + SAR_COCPU_TOUCH_ACTIVE_INT_RAW + int from touch active + 2 + 1 + read-only + + + SAR_COCPU_SARADC1_INT_RAW + int from saradc1 + 3 + 1 + read-only + + + SAR_COCPU_SARADC2_INT_RAW + int from saradc2 + 4 + 1 + read-only + + + SAR_COCPU_TSENS_INT_RAW + int from tsens + 5 + 1 + read-only + + + SAR_COCPU_START_INT_RAW + int from start + 6 + 1 + read-only + + + SAR_COCPU_SW_INT_RAW + int from software + 7 + 1 + read-only + + + SAR_COCPU_SWD_INT_RAW + int from super watch dog + 8 + 1 + read-only + + + SAR_COCPU_TOUCH_TIMEOUT_INT_RAW + int from timeout done + 9 + 1 + read-only + + + SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW + int from approach loop done + 10 + 1 + read-only + + + SAR_COCPU_TOUCH_SCAN_DONE_INT_RAW + int from touch scan done + 11 + 1 + read-only + + + + + SAR_COCPU_INT_ENA + the interrupt enable of ulp + 0xEC + 0x20 + + + SAR_COCPU_TOUCH_DONE_INT_ENA + int enable of touch done + 0 + 1 + read-write + + + SAR_COCPU_TOUCH_INACTIVE_INT_ENA + int enable of from touch inactive + 1 + 1 + read-write + + + SAR_COCPU_TOUCH_ACTIVE_INT_ENA + int enable of touch active + 2 + 1 + read-write + + + SAR_COCPU_SARADC1_INT_ENA + int enable of from saradc1 + 3 + 1 + read-write + + + SAR_COCPU_SARADC2_INT_ENA + int enable of from saradc2 + 4 + 1 + read-write + + + SAR_COCPU_TSENS_INT_ENA + int enable of tsens + 5 + 1 + read-write + + + SAR_COCPU_START_INT_ENA + int enable of start + 6 + 1 + read-write + + + SAR_COCPU_SW_INT_ENA + int enable of software + 7 + 1 + read-write + + + SAR_COCPU_SWD_INT_ENA + int enable of super watch dog + 8 + 1 + read-write + + + SAR_COCPU_TOUCH_TIMEOUT_INT_ENA + int enable of timeout done + 9 + 1 + read-write + + + SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA + int enable of approach loop done + 10 + 1 + read-write + + + SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA + int enable of touch scan done + 11 + 1 + read-write + + + + + SAR_COCPU_INT_ST + the interrupt state of ulp + 0xF0 + 0x20 + + + SAR_COCPU_TOUCH_DONE_INT_ST + int state of touch done + 0 + 1 + read-only + + + SAR_COCPU_TOUCH_INACTIVE_INT_ST + int state of from touch inactive + 1 + 1 + read-only + + + SAR_COCPU_TOUCH_ACTIVE_INT_ST + int state of touch active + 2 + 1 + read-only + + + SAR_COCPU_SARADC1_INT_ST + int state of from saradc1 + 3 + 1 + read-only + + + SAR_COCPU_SARADC2_INT_ST + int state of from saradc2 + 4 + 1 + read-only + + + SAR_COCPU_TSENS_INT_ST + int state of tsens + 5 + 1 + read-only + + + SAR_COCPU_START_INT_ST + int state of start + 6 + 1 + read-only + + + SAR_COCPU_SW_INT_ST + int state of software + 7 + 1 + read-only + + + SAR_COCPU_SWD_INT_ST + int state of super watch dog + 8 + 1 + read-only + + + SAR_COCPU_TOUCH_TIMEOUT_INT_ST + int state of timeout done + 9 + 1 + read-only + + + SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST + int state of approach loop done + 10 + 1 + read-only + + + SAR_COCPU_TOUCH_SCAN_DONE_INT_ST + int state of touch scan done + 11 + 1 + read-only + + + + + SAR_COCPU_INT_CLR + the interrupt clear of ulp + 0xF4 + 0x20 + + + SAR_COCPU_TOUCH_DONE_INT_CLR + int clear of touch done + 0 + 1 + write-only + + + SAR_COCPU_TOUCH_INACTIVE_INT_CLR + int clear of from touch inactive + 1 + 1 + write-only + + + SAR_COCPU_TOUCH_ACTIVE_INT_CLR + int clear of touch active + 2 + 1 + write-only + + + SAR_COCPU_SARADC1_INT_CLR + int clear of from saradc1 + 3 + 1 + write-only + + + SAR_COCPU_SARADC2_INT_CLR + int clear of from saradc2 + 4 + 1 + write-only + + + SAR_COCPU_TSENS_INT_CLR + int clear of tsens + 5 + 1 + write-only + + + SAR_COCPU_START_INT_CLR + int clear of start + 6 + 1 + write-only + + + SAR_COCPU_SW_INT_CLR + int clear of software + 7 + 1 + write-only + + + SAR_COCPU_SWD_INT_CLR + int clear of super watch dog + 8 + 1 + write-only + + + SAR_COCPU_TOUCH_TIMEOUT_INT_CLR + int clear of timeout done + 9 + 1 + write-only + + + SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR + int clear of approach loop done + 10 + 1 + write-only + + + SAR_COCPU_TOUCH_SCAN_DONE_INT_CLR + int clear of touch scan done + 11 + 1 + write-only + + + + + SAR_COCPU_DEBUG + Ulp-riscv debug signal + 0xF8 + 0x20 + + + SAR_COCPU_PC + cocpu Program counter + 0 + 13 + read-only + + + SAR_COCPU_MEM_VLD + cocpu mem valid output + 13 + 1 + read-only + + + SAR_COCPU_MEM_RDY + cocpu mem ready input + 14 + 1 + read-only + + + SAR_COCPU_MEM_WEN + cocpu mem write enable output + 15 + 4 + read-only + + + SAR_COCPU_MEM_ADDR + cocpu mem address output + 19 + 13 + read-only + + + + + SAR_HALL_CTRL + no public + 0xFC + 0x20 + 0xA0000000 + + + XPD_HALL + Power on hall sensor and connect to VP and VN + 28 + 1 + read-write + + + XPD_HALL_FORCE + 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor + 29 + 1 + read-write + + + HALL_PHASE + Reverse phase of hall sensor + 30 + 1 + read-write + + + HALL_PHASE_FORCE + 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor + 31 + 1 + read-write + + + + + SAR_NOUSE + no public + 0x100 + 0x20 + + + SAR_NOUSE + no public + 0 + 32 + read-write + + + + + SAR_PERI_CLK_GATE_CONF + the peri clock gate of rtc peri + 0x104 + 0x20 + + + RTC_I2C_CLK_EN + enable rtc i2c clock + 27 + 1 + read-write + + + TSENS_CLK_EN + enable tsens clock + 29 + 1 + read-write + + + SARADC_CLK_EN + enbale saradc clock + 30 + 1 + read-write + + + IOMUX_CLK_EN + enable io_mux clock + 31 + 1 + read-write + + + + + SAR_PERI_RESET_CONF + the peri reset of rtc peri + 0x108 + 0x20 + + + SAR_COCPU_RESET + enable ulp-riscv reset + 25 + 1 + read-write + + + SAR_RTC_I2C_RESET + Reserved. + 27 + 1 + read-write + + + SAR_TSENS_RESET + enbale saradc reset + 29 + 1 + read-write + + + SAR_SARADC_RESET + enable io_mux reset + 30 + 1 + read-write + + + + + SAR_COCPU_INT_ENA_W1TS + the interrupt enable of ulp + 0x10C + 0x20 + + + SAR_COCPU_TOUCH_DONE_INT_ENA_W1TS + int enable of touch done + 0 + 1 + write-only + + + SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS + int enable of from touch inactive + 1 + 1 + write-only + + + SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS + int enable of touch active + 2 + 1 + write-only + + + SAR_COCPU_SARADC1_INT_ENA_W1TS + int enable of from saradc1 + 3 + 1 + write-only + + + SAR_COCPU_SARADC2_INT_ENA_W1TS + int enable of from saradc2 + 4 + 1 + write-only + + + SAR_COCPU_TSENS_INT_ENA_W1TS + int enable of tsens + 5 + 1 + write-only + + + SAR_COCPU_START_INT_ENA_W1TS + int enable of start + 6 + 1 + write-only + + + SAR_COCPU_SW_INT_ENA_W1TS + int enable of software + 7 + 1 + write-only + + + SAR_COCPU_SWD_INT_ENA_W1TS + int enable of super watch dog + 8 + 1 + write-only + + + SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS + int enable of timeout done + 9 + 1 + write-only + + + SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS + int enable of approach loop done + 10 + 1 + write-only + + + SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS + int enable of touch scan done + 11 + 1 + write-only + + + + + SAR_COCPU_INT_ENA_W1TC + the interrupt enable clear of ulp + 0x110 + 0x20 + + + SAR_COCPU_TOUCH_DONE_INT_ENA_W1TC + Clear int enable of touch done + 0 + 1 + write-only + + + SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC + Clear int enable of from touch inactive + 1 + 1 + write-only + + + SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC + Clear int enable of touch active + 2 + 1 + write-only + + + SAR_COCPU_SARADC1_INT_ENA_W1TC + Clear int enable of from saradc1 + 3 + 1 + write-only + + + SAR_COCPU_SARADC2_INT_ENA_W1TC + Clear int enable of from saradc2 + 4 + 1 + write-only + + + SAR_COCPU_TSENS_INT_ENA_W1TC + Clear int enable of tsens + 5 + 1 + write-only + + + SAR_COCPU_START_INT_ENA_W1TC + Clear int enable of start + 6 + 1 + write-only + + + SAR_COCPU_SW_INT_ENA_W1TC + Clear int enable of software + 7 + 1 + write-only + + + SAR_COCPU_SWD_INT_ENA_W1TC + Clear int enable of super watch dog + 8 + 1 + write-only + + + SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC + Clear int enable of timeout done + 9 + 1 + write-only + + + SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC + Clear int enable of approach loop done + 10 + 1 + write-only + + + SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC + Clear int enable of touch scan done + 11 + 1 + write-only + + + + + SAR_DEBUG_CONF + rtc peri debug configure + 0x114 + 0x20 + + + SAR_DEBUG_BIT_SEL + no public + 0 + 5 + read-write + + + + + SAR_SARDATE + version + 0x1FC + 0x20 + 0x02101180 + + + SAR_DATE + version + 0 + 28 + read-write + + + + + + + SENSITIVE + SENSITIVE Peripheral + SENSITIVE + 0x600C1000 + + 0x0 + 0x314 + registers + + + + CACHE_DATAARRAY_CONNECT_0 + Cache data array configuration register 0. + 0x0 + 0x20 + + + CACHE_DATAARRAY_CONNECT_LOCK + Set 1 to lock cache data array registers. + 0 + 1 + read-write + + + + + CACHE_DATAARRAY_CONNECT_1 + Cache data array configuration register 1. + 0x4 + 0x20 + 0x000000FF + + + CACHE_DATAARRAY_CONNECT_FLATTEN + Cache data array connection configuration. + 0 + 8 + read-write + + + + + APB_PERIPHERAL_ACCESS_0 + APB peripheral configuration register 0. + 0x8 + 0x20 + + + APB_PERIPHERAL_ACCESS_LOCK + Set 1 to lock APB peripheral Configuration Register. + 0 + 1 + read-write + + + + + APB_PERIPHERAL_ACCESS_1 + APB peripheral configuration register 1. + 0xC + 0x20 + 0x00000001 + + + APB_PERIPHERAL_ACCESS_SPLIT_BURST + Set 1 to support split function for AHB access to APB peripherals. + 0 + 1 + read-write + + + + + INTERNAL_SRAM_USAGE_0 + Internal SRAM configuration register 0. + 0x10 + 0x20 + + + INTERNAL_SRAM_USAGE_LOCK + Set 1 to lock internal SRAM Configuration Register. + 0 + 1 + read-write + + + + + INTERNAL_SRAM_USAGE_1 + Internal SRAM configuration register 1. + 0x14 + 0x20 + 0x000007FF + + + INTERNAL_SRAM_ICACHE_USAGE + Set 1 to someone bit means corresponding internal SRAM level can be accessed by icache. + 0 + 2 + read-write + + + INTERNAL_SRAM_DCACHE_USAGE + Set 1 to someone bit means corresponding internal SRAM level can be accessed by dcache. + 2 + 2 + read-write + + + INTERNAL_SRAM_CPU_USAGE + Set 1 to someone bit means corresponding internal SRAM level can be accessed by cpu. + 4 + 7 + read-write + + + + + INTERNAL_SRAM_USAGE_2 + Internal SRAM configuration register 2. + 0x18 + 0x20 + + + INTERNAL_SRAM_CORE0_TRACE_USAGE + Set 1 to someone bit means corresponding internal SRAM level can be accessed by core0 trace bus. + 0 + 7 + read-write + + + INTERNAL_SRAM_CORE1_TRACE_USAGE + Set 1 to someone bit means corresponding internal SRAM level can be accessed by core1 trace bus. + 7 + 7 + read-write + + + INTERNAL_SRAM_CORE0_TRACE_ALLOC + Which internal SRAM bank (16KB) of 64KB can be accessed by core0 trace bus. + 14 + 2 + read-write + + + INTERNAL_SRAM_CORE1_TRACE_ALLOC + Which internal SRAM bank (16KB) of 64KB can be accessed by core1 trace bus. + 16 + 2 + read-write + + + + + INTERNAL_SRAM_USAGE_3 + Internal SRAM configuration register 3. + 0x1C + 0x20 + + + INTERNAL_SRAM_MAC_DUMP_USAGE + Set 1 to someone bit means corresponding internal SRAM level can be accessed by mac dump. + 0 + 4 + read-write + + + + + INTERNAL_SRAM_USAGE_4 + Internal SRAM configuration register 4. + 0x20 + 0x20 + + + INTERNAL_SRAM_LOG_USAGE + Set 1 to someone bit means corresponding internal SRAM level can be accessed by log bus. + 0 + 7 + read-write + + + + + RETENTION_DISABLE + Retention configuration register. + 0x24 + 0x20 + + + RETENTION_DISABLE + Set 1 to disable retention function and lock disable state. + 0 + 1 + read-write + + + + + CACHE_TAG_ACCESS_0 + Cache tag configuration register 0. + 0x28 + 0x20 + + + CACHE_TAG_ACCESS_LOCK + Set 1 to lock cache tag Configuration Register. + 0 + 1 + read-write + + + + + CACHE_TAG_ACCESS_1 + Cache tag configuration register 1. + 0x2C + 0x20 + 0x0000000F + + + PRO_I_TAG_RD_ACS + Set 1 to enable Icache read access tag memory. + 0 + 1 + read-write + + + PRO_I_TAG_WR_ACS + Set 1 to enable Icache wrtie access tag memory. + 1 + 1 + read-write + + + PRO_D_TAG_RD_ACS + Set 1 to enable Dcache read access tag memory. + 2 + 1 + read-write + + + PRO_D_TAG_WR_ACS + Set 1 to enable Dcache wrtie access tag memory. + 3 + 1 + read-write + + + + + CACHE_MMU_ACCESS_0 + Cache MMU configuration register 0. + 0x30 + 0x20 + + + CACHE_MMU_ACCESS_LOCK + Set 1 to lock cache MMU registers. + 0 + 1 + read-write + + + + + CACHE_MMU_ACCESS_1 + Cache MMU configuration register 1. + 0x34 + 0x20 + 0x00000003 + + + PRO_MMU_RD_ACS + Set 1 to enable read access MMU memory. + 0 + 1 + read-write + + + PRO_MMU_WR_ACS + Set 1 to enable write access MMU memory. + 1 + 1 + read-write + + + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_0 + spi2 dma permission configuration register 0. + 0x38 + 0x20 + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK + Set 1 to lock spi2 dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_1 + spi2 dma permission configuration register 1. + 0x3C + 0x20 + 0x00000FFF + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0 + spi2's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1 + spi2's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2 + spi2's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3 + spi2's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + spi2's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + spi2's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_SPI3_PMS_CONSTRAIN_0 + spi3 dma permission configuration register 0. + 0x40 + 0x20 + + + DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK + Set 1 to lock spi3 dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_SPI3_PMS_CONSTRAIN_1 + spi3 dma permission configuration register 1. + 0x44 + 0x20 + 0x00000FFF + + + DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0 + spi3's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1 + spi3's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2 + spi3's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3 + spi3's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + spi3's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + spi3's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0 + uhci0 dma permission configuration register 0. + 0x48 + 0x20 + + + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK + Set 1 to lock uhci0 dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1 + uhci0 dma permission configuration register 1. + 0x4C + 0x20 + 0x00000FFF + + + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0 + uhci0's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1 + uhci0's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2 + uhci0's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3 + uhci0's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + uhci0's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + uhci0's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_0 + i2s0 dma permission configuration register 0. + 0x50 + 0x20 + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK + Set 1 to lock i2s0 dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_1 + i2s0 dma permission configuration register 1. + 0x54 + 0x20 + 0x00000FFF + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0 + i2s0's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1 + i2s0's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2 + i2s0's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3 + i2s0's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + i2s0's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + i2s0's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_I2S1_PMS_CONSTRAIN_0 + i2s1 dma permission configuration register 0. + 0x58 + 0x20 + + + DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK + Set 1 to lock i2s1 dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_I2S1_PMS_CONSTRAIN_1 + i2s1 dma permission configuration register 1. + 0x5C + 0x20 + 0x00000FFF + + + DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0 + i2s1's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1 + i2s1's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2 + i2s1's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3 + i2s1's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + i2s1's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + i2s1's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_0 + mac dma permission configuration register 0. + 0x60 + 0x20 + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK + Set 1 to lock mac dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_1 + mac dma permission configuration register 1. + 0x64 + 0x20 + 0x00000FFF + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0 + mac's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1 + mac's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2 + mac's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3 + mac's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + mac's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + mac's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0 + backup dma permission configuration register 0. + 0x68 + 0x20 + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK + Set 1 to lock backup dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1 + backup dma permission configuration register 1. + 0x6C + 0x20 + 0x00000FFF + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0 + backup's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1 + backup's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2 + backup's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3 + backup's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + backup's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + backup's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_AES_PMS_CONSTRAIN_0 + aes dma permission configuration register 0. + 0x70 + 0x20 + + + DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK + Set 1 to lock aes dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_AES_PMS_CONSTRAIN_1 + aes dma permission configuration register 1. + 0x74 + 0x20 + 0x00000FFF + + + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0 + aes's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1 + aes's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2 + aes's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3 + aes's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + aes's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + aes's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_0 + sha dma permission configuration register 0. + 0x78 + 0x20 + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK + Set 1 to lock sha dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_1 + sha dma permission configuration register 1. + 0x7C + 0x20 + 0x00000FFF + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0 + sha's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1 + sha's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2 + sha's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3 + sha's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + sha's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + sha's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0 + adc_dac dma permission configuration register 0. + 0x80 + 0x20 + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK + Set 1 to lock adc_dac dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1 + adc_dac dma permission configuration register 1. + 0x84 + 0x20 + 0x00000FFF + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0 + adc_dac's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1 + adc_dac's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2 + adc_dac's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3 + adc_dac's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + adc_dac's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + adc_dac's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_RMT_PMS_CONSTRAIN_0 + rmt dma permission configuration register 0. + 0x88 + 0x20 + + + DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK + Set 1 to lock rmt dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_RMT_PMS_CONSTRAIN_1 + rmt dma permission configuration register 1. + 0x8C + 0x20 + 0x00000FFF + + + DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0 + rmt's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1 + rmt's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2 + rmt's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3 + rmt's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + rmt's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + rmt's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0 + lcd_cam dma permission configuration register 0. + 0x90 + 0x20 + + + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK + Set 1 to lock lcd_cam dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1 + lcd_cam dma permission configuration register 1. + 0x94 + 0x20 + 0x00000FFF + + + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0 + lcd_cam's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1 + lcd_cam's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2 + lcd_cam's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3 + lcd_cam's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + lcd_cam's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + lcd_cam's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_USB_PMS_CONSTRAIN_0 + usb dma permission configuration register 0. + 0x98 + 0x20 + + + DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK + Set 1 to lock usb dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_USB_PMS_CONSTRAIN_1 + usb dma permission configuration register 1. + 0x9C + 0x20 + 0x00000FFF + + + DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0 + usb's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1 + usb's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2 + usb's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3 + usb's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + usb's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + usb's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_LC_PMS_CONSTRAIN_0 + lc dma permission configuration register 0. + 0xA0 + 0x20 + + + DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK + Set 1 to lock lc dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_LC_PMS_CONSTRAIN_1 + lc dma permission configuration register 1. + 0xA4 + 0x20 + 0x00000FFF + + + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0 + lc's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1 + lc's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2 + lc's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3 + lc's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + lc's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + lc's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_SDIO_PMS_CONSTRAIN_0 + sdio dma permission configuration register 0. + 0xA8 + 0x20 + + + DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK + Set 1 to lock sdio dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_SDIO_PMS_CONSTRAIN_1 + sdio dma permission configuration register 1. + 0xAC + 0x20 + 0x00000FFF + + + DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0 + sdio's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1 + sdio's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2 + sdio's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3 + sdio's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + sdio's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + sdio's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_PMS_MONITOR_0 + dma permission monitor configuration register 0. + 0xB0 + 0x20 + + + DMA_APBPERI_PMS_MONITOR_LOCK + Set 1 to lock dma permission monitor Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_PMS_MONITOR_1 + dma permission monitor configuration register 1. + 0xB4 + 0x20 + 0x00000003 + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear dma_pms_monitor_violate interrupt + 0 + 1 + read-write + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_EN + Set 1 to enable dma pms monitor, if dma access violated permission, will trigger interrupt. + 1 + 1 + read-write + + + + + DMA_APBPERI_PMS_MONITOR_2 + dma permission monitor configuration register 2. + 0xB8 + 0x20 + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR + recorded dma's interrupt status when dma access violated permission + 0 + 1 + read-only + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD + recorded dma's world status when dma access violated permission + 1 + 2 + read-only + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR + recorded dma's address bit[25:4] status when dma access violated permission, real address is 0x3c00_0000+addr*16 + 3 + 22 + read-only + + + + + DMA_APBPERI_PMS_MONITOR_3 + dma permission monitor configuration register 3. + 0xBC + 0x20 + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR + recorded dma's write status when dma access violated permission, 1(write), 0(read) + 0 + 1 + read-only + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN + recorded dma's byte enable status when dma access violated permission + 1 + 16 + read-only + + + + + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0 + sram split line configuration register 0 + 0xC0 + 0x20 + + + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK + Set 1 to lock sram split configuration register + 0 + 1 + read-write + + + + + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1 + sram split line configuration register 1 + 0xC4 + 0x20 + + + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 + category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00 + 0 + 2 + read-write + + + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 + category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00 + 2 + 2 + read-write + + + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 + category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00 + 4 + 2 + read-write + + + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3 + category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00 + 6 + 2 + read-write + + + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4 + category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00 + 8 + 2 + read-write + + + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5 + category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00 + 10 + 2 + read-write + + + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6 + category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00 + 12 + 2 + read-write + + + CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR + splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address + 14 + 8 + read-write + + + + + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2 + sram split line configuration register 1 + 0xC8 + 0x20 + + + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 + category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00 + 0 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 + category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00 + 2 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 + category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00 + 4 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3 + category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00 + 6 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4 + category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00 + 8 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5 + category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00 + 10 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6 + category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00 + 12 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR + splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address + 14 + 8 + read-write + + + + + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3 + sram split line configuration register 1 + 0xCC + 0x20 + + + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 + category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00 + 0 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 + category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00 + 2 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 + category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00 + 4 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3 + category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00 + 6 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4 + category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00 + 8 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5 + category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00 + 10 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6 + category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00 + 12 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR + splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address + 14 + 8 + read-write + + + + + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4 + sram split line configuration register 1 + 0xD0 + 0x20 + + + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 + category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00 + 0 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 + category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00 + 2 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 + category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00 + 4 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3 + category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00 + 6 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4 + category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00 + 8 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5 + category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00 + 10 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6 + category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00 + 12 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR + splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address + 14 + 8 + read-write + + + + + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5 + sram split line configuration register 1 + 0xD4 + 0x20 + + + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 + category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00 + 0 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 + category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00 + 2 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 + category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00 + 4 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3 + category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00 + 6 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4 + category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00 + 8 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5 + category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00 + 10 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6 + category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00 + 12 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR + splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address + 14 + 8 + read-write + + + + + CORE_X_IRAM0_PMS_CONSTRAIN_0 + corex iram0 permission configuration register 0 + 0xD8 + 0x20 + + + CORE_X_IRAM0_PMS_CONSTRAIN_LOCK + Set 1 to lock corex iram0 permission configuration register + 0 + 1 + read-write + + + + + CORE_X_IRAM0_PMS_CONSTRAIN_1 + corex iram0 permission configuration register 0 + 0xDC + 0x20 + 0x001FFFFF + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + core0/core1's permission of instruction region0 of SRAM in world1 + 0 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + core0/core1's permission of instruction region1 of SRAM in world1 + 3 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + core0/core1's permission of instruction region2 of SRAM in world1 + 6 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + core0/core1's permission of instruction region3 of SRAM in world1 + 9 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 + core0/core1's permission of icache data sram block0 in world1 + 12 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 + core0/core1's permission of icache data sram block1 in world1 + 15 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS + core0/core1's permission of rom in world1 + 18 + 3 + read-write + + + + + CORE_X_IRAM0_PMS_CONSTRAIN_2 + corex iram0 permission configuration register 1 + 0xE0 + 0x20 + 0x001FFFFF + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + core0/core1's permission of instruction region0 of SRAM in world1 + 0 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + core0/core1's permission of instruction region1 of SRAM in world1 + 3 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + core0/core1's permission of instruction region2 of SRAM in world1 + 6 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + core0/core1's permission of instruction region3 of SRAM in world1 + 9 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 + core0/core1's permission of icache data sram block0 in world1 + 12 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 + core0/core1's permission of icache data sram block1 in world1 + 15 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS + core0/core1's permission of rom in world1 + 18 + 3 + read-write + + + + + CORE_0_IRAM0_PMS_MONITOR_0 + core0 iram0 permission monitor configuration register 0 + 0xE4 + 0x20 + + + CORE_0_IRAM0_PMS_MONITOR_LOCK + Set 1 to lock core0 iram0 permission monitor register + 0 + 1 + read-write + + + + + CORE_0_IRAM0_PMS_MONITOR_1 + core0 iram0 permission monitor configuration register 1 + 0xE8 + 0x20 + 0x00000003 + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear core0 iram0 permission violated interrupt + 0 + 1 + read-write + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN + Set 1 to enable core0 iram0 permission monitor, when core0_iram violated permission, will trigger interrupt + 1 + 1 + read-write + + + + + CORE_0_IRAM0_PMS_MONITOR_2 + core0 iram0 permission monitor configuration register 2 + 0xEC + 0x20 + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR + recorded core0 iram0 pms monitor interrupt status. + 0 + 1 + read-only + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR + recorded core0 iram0 wr status, only if loadstore is 1 have meaning, 1(store), 0(load). + 1 + 1 + read-only + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE + recorded core0 iram0 loadstore status, indicated the type of operation, 0(fetch), 1(load/store). + 2 + 1 + read-only + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD + recorded core0 iram0 world status, 0x01 means world0, 0x10 means world1. + 3 + 2 + read-only + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR + recorded core0 iram0 address [25:2] status when core0 iram0 violated permission, the real address is 0x40000000+addr*4 + 5 + 24 + read-only + + + + + CORE_1_IRAM0_PMS_MONITOR_0 + core1 iram0 permission monitor configuration register 0 + 0xF0 + 0x20 + + + CORE_1_IRAM0_PMS_MONITOR_LOCK + Set 1 to lock core1 iram0 permission monitor register + 0 + 1 + read-write + + + + + CORE_1_IRAM0_PMS_MONITOR_1 + core1 iram0 permission monitor configuration register 1 + 0xF4 + 0x20 + 0x00000003 + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear core1 iram0 permission violated interrupt + 0 + 1 + read-write + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN + Set 1 to enable core1 iram0 permission monitor, when core1_iram violated permission, will trigger interrupt + 1 + 1 + read-write + + + + + CORE_1_IRAM0_PMS_MONITOR_2 + core1 iram0 permission monitor configuration register 2 + 0xF8 + 0x20 + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR + recorded core1 iram0 pms monitor interrupt status. + 0 + 1 + read-only + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR + recorded core1 iram0 wr status, only if loadstore is 1 have meaning, 1(store), 0(load). + 1 + 1 + read-only + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE + recorded core1 iram0 loadstore status, indicated the type of operation, 0(fetch), 1(load/store). + 2 + 1 + read-only + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD + recorded core1 iram0 world status, 0x01 means world0, 0x10 means world1. + 3 + 2 + read-only + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR + recorded core1 iram0 address [25:2] status when core1 iram0 violated permission, the real address is 0x40000000+addr*4 + 5 + 24 + read-only + + + + + CORE_X_DRAM0_PMS_CONSTRAIN_0 + corex dram0 permission configuration register 0 + 0xFC + 0x20 + + + CORE_X_DRAM0_PMS_CONSTRAIN_LOCK + Set 1 to lock corex dram0 permission configuration register + 0 + 1 + read-write + + + + + CORE_X_DRAM0_PMS_CONSTRAIN_1 + corex dram0 permission configuration register 1 + 0x100 + 0x20 + 0x0FFFFFFF + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + core0/core1's permission of data region0 of SRAM in world0. + 0 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + core0/core1's permission of data region1 of SRAM in world0. + 2 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + core0/core1's permission of data region2 of SRAM in world0. + 4 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + core0/core1's permission of data region3 of SRAM in world0. + 6 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 + core0/core1's permission of dcache data sram block0 in world0. + 8 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 + core0/core1's permission of dcache data sram block1 in world0. + 10 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + core0/core1's permission of data region0 of SRAM in world1. + 12 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + core0/core1's permission of data region1 of SRAM in world1. + 14 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + core0/core1's permission of data region2 of SRAM in world1. + 16 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + core0/core1's permission of data region3 of SRAM in world1. + 18 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 + core0/core1's permission of dcache data sram block0 in world1. + 20 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 + core0/core1's permission of dcache data sram block1 in world1. + 22 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS + core0/core1's permission(sotre,load) of rom in world0. + 24 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS + core0/core1's permission(sotre,load) of rom in world1. + 26 + 2 + read-write + + + + + CORE_0_DRAM0_PMS_MONITOR_0 + core0 dram0 permission monitor configuration register 0 + 0x104 + 0x20 + + + CORE_0_DRAM0_PMS_MONITOR_LOCK + Set 1 to lock core0 dram0 permission monitor configuration register. + 0 + 1 + read-write + + + + + CORE_0_DRAM0_PMS_MONITOR_1 + core0 dram0 permission monitor configuration register 1 + 0x108 + 0x20 + 0x00000003 + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear core0 dram0 permission monior interrupt. + 0 + 1 + read-write + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN + Set 1 to enable core0 dram0 permission monitor interrupt. + 1 + 1 + read-write + + + + + CORE_0_DRAM0_PMS_MONITOR_2 + core0 dram0 permission monitor configuration register 2. + 0x10C + 0x20 + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR + recorded core0 dram0 permission monitor interrupt status. + 0 + 1 + read-only + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK + recorded core0 dram0 lock status, 1 means s32c1i access. + 1 + 1 + read-only + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD + recorded core0 dram0 world status, 0x1 means world0, 0x2 means world1. + 2 + 2 + read-only + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR + recorded core0 dram0 address[25:4] status when core0 dram0 violated permission,the real address is 0x3c000000+addr*16 + 4 + 22 + read-only + + + + + CORE_0_DRAM0_PMS_MONITOR_3 + core0 dram0 permission monitor configuration register 3. + 0x110 + 0x20 + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR + recorded core0 dram0 wr status, 1 means store, 0 means load. + 0 + 1 + read-only + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN + recorded core0 dram0 byteen status. + 1 + 16 + read-only + + + + + CORE_1_DRAM0_PMS_MONITOR_0 + core1 dram0 permission monitor configuration register 0 + 0x114 + 0x20 + + + CORE_1_DRAM0_PMS_MONITOR_LOCK + Set 1 to lock core1 dram0 permission monitor configuration register. + 0 + 1 + read-write + + + + + CORE_1_DRAM0_PMS_MONITOR_1 + core1 dram0 permission monitor configuration register 1 + 0x118 + 0x20 + 0x00000003 + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear core1 dram0 permission monior interrupt. + 0 + 1 + read-write + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN + Set 1 to enable core1 dram0 permission monitor interrupt. + 1 + 1 + read-write + + + + + CORE_1_DRAM0_PMS_MONITOR_2 + core1 dram0 permission monitor configuration register 2. + 0x11C + 0x20 + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR + recorded core1 dram0 permission monitor interrupt status. + 0 + 1 + read-only + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK + recorded core1 dram0 lock status, 1 means s32c1i access. + 1 + 1 + read-only + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD + recorded core1 dram0 world status, 0x1 means world0, 0x2 means world1. + 2 + 2 + read-only + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR + recorded core1 dram0 address[25:4] status when core1 dram0 violated permission,the real address is 0x3c000000+addr*16 + 4 + 22 + read-only + + + + + CORE_1_DRAM0_PMS_MONITOR_3 + core1 dram0 permission monitor configuration register 3. + 0x120 + 0x20 + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR + recorded core1 dram0 wr status, 1 means store, 0 means load. + 0 + 1 + read-only + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN + recorded core1 dram0 byteen status. + 1 + 16 + read-only + + + + + CORE_0_PIF_PMS_CONSTRAIN_0 + Core0 access peripherals permission configuration register 0. + 0x124 + 0x20 + + + CORE_0_PIF_PMS_CONSTRAIN_LOCK + Set 1 to lock core0 access peripherals permission Configuration Register. + 0 + 1 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_1 + Core0 access peripherals permission configuration register 1. + 0x128 + 0x20 + 0xFF33CFFF + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART + Core0 access uart permission in world0. + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 + Core0 access g0spi_1 permission in world0. + 2 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 + Core0 access g0spi_0 permission in world0. + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO + Core0 access gpio permission in world0. + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 + Core0 access fe2 permission in world0. + 8 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE + Core0 access fe permission in world0. + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC + Core0 access rtc permission in world0. + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX + Core0 access io_mux permission in world0. + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF + Core0 access hinf permission in world0. + 20 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC + Core0 access misc permission in world0. + 24 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C + Core0 access i2c permission in world0. + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 + Core0 access i2s0 permission in world0. + 28 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 + Core0 access uart1 permission in world0. + 30 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_2 + Core0 access peripherals permission configuration register 2. + 0x12C + 0x20 + 0xFFCFFFF3 + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT + Core0 access bt permission in world0. + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 + Core0 access i2c_ext0 permission in world0. + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 + Core0 access uhci0 permission in world0. + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST + Core0 access slchost permission in world0. + 8 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT + Core0 access rmt permission in world0. + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT + Core0 access pcnt permission in world0. + 12 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC + Core0 access slc permission in world0. + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC + Core0 access ledc permission in world0. + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP + Core0 access backup permission in world0. + 18 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB + Core0 access bb permission in world0. + 22 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 + Core0 access pwm0 permission in world0. + 24 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP + Core0 access timergroup permission in world0. + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 + Core0 access timergroup1 permission in world0. + 28 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER + Core0 access systimer permission in world0. + 30 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_3 + Core0 access peripherals permission configuration register 3. + 0x130 + 0x20 + 0x3CC3FFFF + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 + Core0 access spi_2 permission in world0. + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 + Core0 access spi_3 permission in world0. + 2 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL + Core0 access apb_ctrl permission in world0. + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 + Core0 access i2c_ext1 permission in world0. + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST + Core0 access sdio_host permission in world0. + 8 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN + Core0 access can permission in world0. + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 + Core0 access pwm1 permission in world0. + 12 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 + Core0 access i2s1 permission in world0. + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2 + Core0 access uart2 permission in world0. + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT + Core0 access rwbt permission in world0. + 22 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC + Core0 access wifimac permission in world0. + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR + Core0 access pwr permission in world0. + 28 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_4 + Core0 access peripherals permission configuration register 4. + 0x134 + 0x20 + 0xFFFFFFFF + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE + Core0 access usb_device permission in world0. + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP + Core0 access usb_wrap permission in world0. + 2 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI + Core0 access crypto_peri permission in world0. + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA + Core0 access crypto_dma permission in world0. + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC + Core0 access apb_adc permission in world0. + 8 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM + Core0 access lcd_cam permission in world0. + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR + Core0 access bt_pwr permission in world0. + 12 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB + Core0 access usb permission in world0. + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM + Core0 access system permission in world0. + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE + Core0 access sensitive permission in world0. + 18 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT + Core0 access interrupt permission in world0. + 20 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY + Core0 access dma_copy permission in world0. + 22 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG + Core0 access cache_config permission in world0. + 24 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD + Core0 access ad permission in world0. + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO + Core0 access dio permission in world0. + 28 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER + Core0 access world_controller permission in world0. + 30 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_5 + Core0 access peripherals permission configuration register 5. + 0x138 + 0x20 + 0xFF33CFFF + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART + Core0 access uart permission in world1. + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 + Core0 access g0spi_1 permission in world1. + 2 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 + Core0 access g0spi_0 permission in world1. + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO + Core0 access gpio permission in world1. + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 + Core0 access fe2 permission in world1. + 8 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE + Core0 access fe permission in world1. + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC + Core0 access rtc permission in world1. + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX + Core0 access io_mux permission in world1. + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF + Core0 access hinf permission in world1. + 20 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC + Core0 access misc permission in world1. + 24 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C + Core0 access i2c permission in world1. + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 + Core0 access i2s0 permission in world1. + 28 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 + Core0 access uart1 permission in world1. + 30 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_6 + Core0 access peripherals permission configuration register 6. + 0x13C + 0x20 + 0xFFCFFFF3 + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT + Core0 access bt permission in world1. + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 + Core0 access i2c_ext0 permission in world1. + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 + Core0 access uhci0 permission in world1. + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST + Core0 access slchost permission in world1. + 8 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT + Core0 access rmt permission in world1. + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT + Core0 access pcnt permission in world1. + 12 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC + Core0 access slc permission in world1. + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC + Core0 access ledc permission in world1. + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP + Core0 access backup permission in world1. + 18 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB + Core0 access bb permission in world1. + 22 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 + Core0 access pwm0 permission in world1. + 24 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP + Core0 access timergroup permission in world1. + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 + Core0 access timergroup1 permission in world1. + 28 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER + Core0 access systimer permission in world1. + 30 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_7 + Core0 access peripherals permission configuration register 7. + 0x140 + 0x20 + 0x3CC3FFFF + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 + Core0 access spi_2 permission in world1. + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 + Core0 access spi_3 permission in world1. + 2 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL + Core0 access apb_ctrl permission in world1. + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 + Core0 access i2c_ext1 permission in world1. + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST + Core0 access sdio_host permission in world1. + 8 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN + Core0 access can permission in world1. + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 + Core0 access pwm1 permission in world1. + 12 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 + Core0 access i2s1 permission in world1. + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2 + Core0 access uart2 permission in world1. + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT + Core0 access rwbt permission in world1. + 22 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC + Core0 access wifimac permission in world1. + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR + Core0 access pwr permission in world1. + 28 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_8 + Core0 access peripherals permission configuration register 8. + 0x144 + 0x20 + 0xFFFFFFFF + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE + Core0 access usb_device permission in world1. + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP + Core0 access usb_wrap permission in world1. + 2 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI + Core0 access crypto_peri permission in world1. + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA + Core0 access crypto_dma permission in world1. + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC + Core0 access apb_adc permission in world1. + 8 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM + Core0 access lcd_cam permission in world1. + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR + Core0 access bt_pwr permission in world1. + 12 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB + Core0 access usb permission in world1. + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM + Core0 access system permission in world1. + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE + Core0 access sensitive permission in world1. + 18 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT + Core0 access interrupt permission in world1. + 20 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY + Core0 access dma_copy permission in world1. + 22 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG + Core0 access cache_config permission in world1. + 24 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD + Core0 access ad permission in world1. + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO + Core0 access dio permission in world1. + 28 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER + Core0 access world_controller permission in world1. + 30 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_9 + Core0 access peripherals permission configuration register 9. + 0x148 + 0x20 + 0x003FFFFF + + + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 + RTCFast memory split address in world 0 for core0. + 0 + 11 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 + RTCFast memory split address in world 1 for core0. + 11 + 11 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_10 + Core0 access peripherals permission configuration register 10. + 0x14C + 0x20 + 0x00000FFF + + + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L + RTCFast memory low region permission in world 0 for core0. + 0 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H + RTCFast memory high region permission in world 0 for core0. + 3 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L + RTCFast memory low region permission in world 1 for core0. + 6 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H + RTCFast memory high region permission in world 1 for core0. + 9 + 3 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_11 + Core0 access peripherals permission configuration register 11. + 0x150 + 0x20 + 0x003FFFFF + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 + RTCSlow_0 memory split address in world 0 for core0. + 0 + 11 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 + RTCSlow_0 memory split address in world 1 for core0. + 11 + 11 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_12 + Core0 access peripherals permission configuration register 12. + 0x154 + 0x20 + 0x00000FFF + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L + RTCSlow_0 memory low region permission in world 0 for core0. + 0 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H + RTCSlow_0 memory high region permission in world 0 for core0. + 3 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L + RTCSlow_0 memory low region permission in world 1 for core0. + 6 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H + RTCSlow_0 memory high region permission in world 1 for core0. + 9 + 3 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_13 + Core0 access peripherals permission configuration register 13. + 0x158 + 0x20 + 0x003FFFFF + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 + RTCSlow_1 memory split address in world 0 for core0. + 0 + 11 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 + RTCSlow_1 memory split address in world 1 for core0. + 11 + 11 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_14 + Core0 access peripherals permission configuration register 14. + 0x15C + 0x20 + 0x00000FFF + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L + RTCSlow_1 memory low region permission in world 0 for core0. + 0 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H + RTCSlow_1 memory high region permission in world 0 for core0. + 3 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L + RTCSlow_1 memory low region permission in world 1 for core0. + 6 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H + RTCSlow_1 memory high region permission in world 1 for core0. + 9 + 3 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_0 + Core0 region permission register 0. + 0x160 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_LOCK + Set 1 to lock core0 region permission registers. + 0 + 1 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_1 + Core0 region permission register 1. + 0x164 + 0x20 + 0x003FFFFF + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 + Region 0 permission in world 0 for core0. + 0 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 + Region 1 permission in world 0 for core0. + 2 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 + Region 2 permission in world 0 for core0. + 4 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 + Region 3 permission in world 0 for core0. + 6 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 + Region 4 permission in world 0 for core0. + 8 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 + Region 5 permission in world 0 for core0. + 10 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 + Region 6 permission in world 0 for core0. + 12 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 + Region 7 permission in world 0 for core0. + 14 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 + Region 8 permission in world 0 for core0. + 16 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 + Region 9 permission in world 0 for core0. + 18 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 + Region 10 permission in world 0 for core0. + 20 + 2 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_2 + Core0 region permission register 2. + 0x168 + 0x20 + 0x003FFFFF + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 + Region 0 permission in world 1 for core0. + 0 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 + Region 1 permission in world 1 for core0. + 2 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 + Region 2 permission in world 1 for core0. + 4 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 + Region 3 permission in world 1 for core0. + 6 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 + Region 4 permission in world 1 for core0. + 8 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 + Region 5 permission in world 1 for core0. + 10 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 + Region 6 permission in world 1 for core0. + 12 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 + Region 7 permission in world 1 for core0. + 14 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 + Region 8 permission in world 1 for core0. + 16 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 + Region 9 permission in world 1 for core0. + 18 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 + Region 10 permission in world 1 for core0. + 20 + 2 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_3 + Core0 region permission register 3. + 0x16C + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_0 + Region 0 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_4 + Core0 region permission register 4. + 0x170 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_1 + Region 0 end address and Region 1 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_5 + Core0 region permission register 5. + 0x174 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_2 + Region 1 end address and Region 2 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_6 + Core0 region permission register 6. + 0x178 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_3 + Region 2 end address and Region 3 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_7 + Core0 region permission register 7. + 0x17C + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_4 + Region 3 end address and Region 4 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_8 + Core0 region permission register 8. + 0x180 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_5 + Region 4 end address and Region 5 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_9 + Core0 region permission register 9. + 0x184 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_6 + Region 5 end address and Region 6 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_10 + Core0 region permission register 10. + 0x188 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_7 + Region 6 end address and Region 7 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_11 + Core0 region permission register 11. + 0x18C + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_8 + Region 7 end address and Region 8 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_12 + Core0 region permission register 12. + 0x190 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_9 + Region 8 end address and Region 9 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_13 + Core0 region permission register 13. + 0x194 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_10 + Region 9 end address and Region 10 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_14 + Core0 region permission register 14. + 0x198 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_11 + Region 10 end address for core0. + 0 + 30 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_0 + Core0 permission report register 0. + 0x19C + 0x20 + + + CORE_0_PIF_PMS_MONITOR_LOCK + Set 1 to lock core0 permission report registers. + 0 + 1 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_1 + Core0 permission report register 1. + 0x1A0 + 0x20 + 0x00000003 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear interrupt that core0 initiate illegal PIF bus access. + 0 + 1 + read-write + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_EN + Set 1 to enable interrupt that core0 initiate illegal PIF bus access. + 1 + 1 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_2 + Core0 permission report register 2. + 0x1A4 + 0x20 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR + Record core0 illegal access interrupt state. + 0 + 1 + read-only + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 + Record hport information when core0 initiate illegal access. + 1 + 1 + read-only + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE + Record access type when core0 initate illegal access. + 2 + 3 + read-only + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE + Record access direction when core0 initiate illegal access. + 5 + 1 + read-only + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD + Record world information when core0 initiate illegal access. + 6 + 2 + read-only + + + + + CORE_0_PIF_PMS_MONITOR_3 + Core0 permission report register 3. + 0x1A8 + 0x20 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR + Record address information when core0 initiate illegal access. + 0 + 32 + read-only + + + + + CORE_0_PIF_PMS_MONITOR_4 + Core0 permission report register 4. + 0x1AC + 0x20 + 0x00000003 + + + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR + Set 1 to clear interrupt that core0 initiate unsupported access type. + 0 + 1 + read-write + + + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN + Set 1 to enable interrupt that core0 initiate unsupported access type. + 1 + 1 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_5 + Core0 permission report register 5. + 0x1B0 + 0x20 + + + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR + Record core0 unsupported access type interrupt state. + 0 + 1 + read-only + + + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE + Record access type when core0 initiate unsupported access type. + 1 + 2 + read-only + + + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD + Record world information when core0 initiate unsupported access type. + 3 + 2 + read-only + + + + + CORE_0_PIF_PMS_MONITOR_6 + Core0 permission report register 6. + 0x1B4 + 0x20 + + + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR + Record address information when core0 initiate unsupported access type. + 0 + 32 + read-only + + + + + CORE_0_VECBASE_OVERRIDE_LOCK + core0 vecbase override configuration register 0 + 0x1B8 + 0x20 + + + CORE_0_VECBASE_OVERRIDE_LOCK + Set 1 to lock core0 vecbase configuration register + 0 + 1 + read-write + + + + + CORE_0_VECBASE_OVERRIDE_0 + core0 vecbase override configuration register 0 + 0x1BC + 0x20 + 0x00000001 + + + CORE_0_VECBASE_WORLD_MASK + Set 1 to mask world, then only world0_value will work. + 0 + 1 + read-write + + + + + CORE_0_VECBASE_OVERRIDE_1 + core0 vecbase override configuration register 1 + 0x1C0 + 0x20 + + + CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE + world0 vecbase_override register, when core0 in world0 use this register to override vecbase register. + 0 + 22 + read-write + + + CORE_0_VECBASE_OVERRIDE_SEL + Set 0x3 to sel vecbase_override to override vecbase register. + 22 + 2 + read-write + + + + + CORE_0_VECBASE_OVERRIDE_2 + core0 vecbase override configuration register 1 + 0x1C4 + 0x20 + + + CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE + world1 vecbase_override register, when core0 in world1 use this register to override vecbase register. + 0 + 22 + read-write + + + + + CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0 + core0 toomanyexception override configuration register 0. + 0x1C8 + 0x20 + + + CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK + Set 1 to lock core0 toomanyexception override configuration register + 0 + 1 + read-write + + + + + CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1 + core0 toomanyexception override configuration register 1. + 0x1CC + 0x20 + 0x00000001 + + + CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE + Set 1 to mask toomanyexception. + 0 + 1 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_0 + Core1 access peripherals permission configuration register 0. + 0x1D0 + 0x20 + + + CORE_1_PIF_PMS_CONSTRAIN_LOCK + Set 1 to lock core1 pif permission configuration register. + 0 + 1 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_1 + Core1 access peripherals permission configuration register 1. + 0x1D4 + 0x20 + 0xFF33CFFF + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART + Core1 access uart permission in world0. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 + Core1 access g0spi_1 permission in world0. + 2 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 + Core1 access g0spi_0 permission in world0. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO + Core1 access gpio permission in world0. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2 + Core1 access fe2 permission in world0. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE + Core1 access fe permission in world0. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC + Core1 access rtc permission in world0. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX + Core1 access io_mux permission in world0. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF + Core1 access hinf permission in world0. + 20 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC + Core1 access misc permission in world0. + 24 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C + Core1 access i2c permission in world0. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 + Core1 access i2s0 permission in world0. + 28 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1 + Core1 access uart1 permission in world0. + 30 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_2 + Core1 access peripherals permission configuration register 2. + 0x1D8 + 0x20 + 0xFFCFFFF3 + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT + Core1 access bt permission in world0. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 + Core1 access i2c_ext0 permission in world0. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 + Core1 access uhci0 permission in world0. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST + Core1 access slchost permission in world0. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT + Core1 access rmt permission in world0. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT + Core1 access pcnt permission in world0. + 12 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC + Core1 access slc permission in world0. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC + Core1 access ledc permission in world0. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP + Core1 access backup permission in world0. + 18 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB + Core1 access bb permission in world0. + 22 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 + Core1 access pwm0 permission in world0. + 24 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP + Core1 access timergroup permission in world0. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 + Core1 access timergroup1 permission in world0. + 28 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER + Core1 access systimer permission in world0. + 30 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_3 + Core1 access peripherals permission configuration register 3. + 0x1DC + 0x20 + 0x3CC3FFFF + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 + Core1 access spi_2 permission in world0. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 + Core1 access spi_3 permission in world0. + 2 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL + Core1 access apb_ctrl permission in world0. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 + Core1 access i2c_ext1 permission in world0. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST + Core1 access sdio_host permission in world0. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN + Core1 access can permission in world0. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 + Core1 access pwm1 permission in world0. + 12 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 + Core1 access i2s1 permission in world0. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2 + Core1 access uart2 permission in world0. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT + Core1 access rwbt permission in world0. + 22 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC + Core1 access wifimac permission in world0. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR + Core1 access pwr permission in world0. + 28 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_4 + Core1 access peripherals permission configuration register 4. + 0x1E0 + 0x20 + 0xFFFFFFFF + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE + Core1 access usb_device permission in world0. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP + Core1 access usb_wrap permission in world0. + 2 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI + Core1 access crypto_peri permission in world0. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA + Core1 access crypto_dma permission in world0. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC + Core1 access apb_adc permission in world0. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM + Core1 access lcd_cam permission in world0. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR + Core1 access bt_pwr permission in world0. + 12 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB + Core1 access usb permission in world0. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM + Core1 access system permission in world0. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE + Core1 access sensitive permission in world0. + 18 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT + Core1 access interrupt permission in world0. + 20 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY + Core1 access dma_copy permission in world0. + 22 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG + Core1 access cache_config permission in world0. + 24 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD + Core1 access ad permission in world0. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO + Core1 access dio permission in world0. + 28 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER + Core1 access world_controller permission in world0. + 30 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_5 + Core1 access peripherals permission configuration register 5. + 0x1E4 + 0x20 + 0xFF33CFFF + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART + Core1 access uart permission in world1. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 + Core1 access g0spi_1 permission in world1. + 2 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 + Core1 access g0spi_0 permission in world1. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO + Core1 access gpio permission in world1. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2 + Core1 access fe2 permission in world1. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE + Core1 access fe permission in world1. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC + Core1 access rtc permission in world1. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX + Core1 access io_mux permission in world1. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF + Core1 access hinf permission in world1. + 20 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC + Core1 access misc permission in world1. + 24 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C + Core1 access i2c permission in world1. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 + Core1 access i2s0 permission in world1. + 28 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1 + Core1 access uart1 permission in world1. + 30 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_6 + Core1 access peripherals permission configuration register 6. + 0x1E8 + 0x20 + 0xFFCFFFF3 + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT + Core1 access bt permission in world1. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 + Core1 access i2c_ext0 permission in world1. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 + Core1 access uhci0 permission in world1. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST + Core1 access slchost permission in world1. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT + Core1 access rmt permission in world1. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT + Core1 access pcnt permission in world1. + 12 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC + Core1 access slc permission in world1. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC + Core1 access ledc permission in world1. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP + Core1 access backup permission in world1. + 18 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB + Core1 access bb permission in world1. + 22 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 + Core1 access pwm0 permission in world1. + 24 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP + Core1 access timergroup permission in world1. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 + Core1 access timergroup1 permission in world1. + 28 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER + Core1 access systimer permission in world1. + 30 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_7 + Core1 access peripherals permission configuration register 7. + 0x1EC + 0x20 + 0x3CC3FFFF + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 + Core1 access spi_2 permission in world1. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 + Core1 access spi_3 permission in world1. + 2 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL + Core1 access apb_ctrl permission in world1. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 + Core1 access i2c_ext1 permission in world1. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST + Core1 access sdio_host permission in world1. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN + Core1 access can permission in world1. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 + Core1 access pwm1 permission in world1. + 12 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 + Core1 access i2s1 permission in world1. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2 + Core1 access uart2 permission in world1. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT + Core1 access rwbt permission in world1. + 22 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC + Core1 access wifimac permission in world1. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR + Core1 access pwr permission in world1. + 28 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_8 + Core1 access peripherals permission configuration register 8. + 0x1F0 + 0x20 + 0xFFFFFFFF + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE + Core1 access usb_device permission in world1. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP + Core1 access usb_wrap permission in world1. + 2 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI + Core1 access crypto_peri permission in world1. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA + Core1 access crypto_dma permission in world1. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC + Core1 access apb_adc permission in world1. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM + Core1 access lcd_cam permission in world1. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR + Core1 access bt_pwr permission in world1. + 12 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB + Core1 access usb permission in world1. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM + Core1 access system permission in world1. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE + Core1 access sensitive permission in world1. + 18 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT + Core1 access interrupt permission in world1. + 20 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY + Core1 access dma_copy permission in world1. + 22 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG + Core1 access cache_config permission in world1. + 24 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD + Core1 access ad permission in world1. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO + Core1 access dio permission in world1. + 28 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER + Core1 access world_controller permission in world1. + 30 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_9 + Core1 access peripherals permission configuration register 9. + 0x1F4 + 0x20 + 0x003FFFFF + + + CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 + RTCFast memory split address in world 0 for core1. + 0 + 11 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 + RTCFast memory split address in world 1 for core1. + 11 + 11 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_10 + core1 access peripherals permission configuration register 10. + 0x1F8 + 0x20 + 0x00000FFF + + + CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L + RTCFast memory low region permission in world 0 for core1. + 0 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H + RTCFast memory high region permission in world 0 for core1. + 3 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L + RTCFast memory low region permission in world 1 for core1. + 6 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H + RTCFast memory high region permission in world 1 for core1. + 9 + 3 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_11 + core1 access peripherals permission configuration register 11. + 0x1FC + 0x20 + 0x003FFFFF + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 + RTCSlow_0 memory split address in world 0 for core1. + 0 + 11 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 + RTCSlow_0 memory split address in world 1 for core1. + 11 + 11 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_12 + core1 access peripherals permission configuration register 12. + 0x200 + 0x20 + 0x00000FFF + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L + RTCSlow_0 memory low region permission in world 0 for core1. + 0 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H + RTCSlow_0 memory high region permission in world 0 for core1. + 3 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L + RTCSlow_0 memory low region permission in world 1 for core1. + 6 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H + RTCSlow_0 memory high region permission in world 1 for core1. + 9 + 3 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_13 + core1 access peripherals permission configuration register 13. + 0x204 + 0x20 + 0x003FFFFF + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 + RTCSlow_1 memory split address in world 0 for core1. + 0 + 11 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 + RTCSlow_1 memory split address in world 1 for core1. + 11 + 11 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_14 + core1 access peripherals permission configuration register 14. + 0x208 + 0x20 + 0x00000FFF + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L + RTCSlow_1 memory low region permission in world 0 for core1. + 0 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H + RTCSlow_1 memory high region permission in world 0 for core1. + 3 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L + RTCSlow_1 memory low region permission in world 1 for core1. + 6 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H + RTCSlow_1 memory high region permission in world 1 for core1. + 9 + 3 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_0 + core1 region permission register 0. + 0x20C + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_LOCK + Set 1 to lock core1 region permission registers. + 0 + 1 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_1 + core1 region permission register 1. + 0x210 + 0x20 + 0x003FFFFF + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 + Region 0 permission in world 0 for core1. + 0 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 + Region 1 permission in world 0 for core1. + 2 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 + Region 2 permission in world 0 for core1. + 4 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 + Region 3 permission in world 0 for core1. + 6 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 + Region 4 permission in world 0 for core1. + 8 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 + Region 5 permission in world 0 for core1. + 10 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 + Region 6 permission in world 0 for core1. + 12 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 + Region 7 permission in world 0 for core1. + 14 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 + Region 8 permission in world 0 for core1. + 16 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 + Region 9 permission in world 0 for core1. + 18 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 + Region 10 permission in world 0 for core1. + 20 + 2 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_2 + core1 region permission register 2. + 0x214 + 0x20 + 0x003FFFFF + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 + Region 0 permission in world 1 for core1. + 0 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 + Region 1 permission in world 1 for core1. + 2 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 + Region 2 permission in world 1 for core1. + 4 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 + Region 3 permission in world 1 for core1. + 6 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 + Region 4 permission in world 1 for core1. + 8 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 + Region 5 permission in world 1 for core1. + 10 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 + Region 6 permission in world 1 for core1. + 12 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 + Region 7 permission in world 1 for core1. + 14 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 + Region 8 permission in world 1 for core1. + 16 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 + Region 9 permission in world 1 for core1. + 18 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 + Region 10 permission in world 1 for core1. + 20 + 2 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_3 + core1 region permission register 3. + 0x218 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_0 + Region 0 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_4 + core1 region permission register 4. + 0x21C + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_1 + Region 0 end address and Region 1 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_5 + core1 region permission register 5. + 0x220 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_2 + Region 1 end address and Region 2 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_6 + core1 region permission register 6. + 0x224 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_3 + Region 2 end address and Region 3 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_7 + core1 region permission register 7. + 0x228 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_4 + Region 3 end address and Region 4 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_8 + core1 region permission register 8. + 0x22C + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_5 + Region 4 end address and Region 5 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_9 + core1 region permission register 9. + 0x230 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_6 + Region 5 end address and Region 6 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_10 + core1 region permission register 10. + 0x234 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_7 + Region 6 end address and Region 7 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_11 + core1 region permission register 11. + 0x238 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_8 + Region 7 end address and Region 8 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_12 + core1 region permission register 12. + 0x23C + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_9 + Region 8 end address and Region 9 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_13 + core1 region permission register 13. + 0x240 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_10 + Region 9 end address and Region 10 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_14 + core1 region permission register 14. + 0x244 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_11 + Region 10 end address for core1. + 0 + 30 + read-write + + + + + CORE_1_PIF_PMS_MONITOR_0 + core1 permission report register 0. + 0x248 + 0x20 + + + CORE_1_PIF_PMS_MONITOR_LOCK + Set 1 to lock core1 permission report registers. + 0 + 1 + read-write + + + + + CORE_1_PIF_PMS_MONITOR_1 + core1 permission report register 1. + 0x24C + 0x20 + 0x00000003 + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear interrupt that core1 initiate illegal PIF bus access. + 0 + 1 + read-write + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_EN + Set 1 to enable interrupt that core1 initiate illegal PIF bus access. + 1 + 1 + read-write + + + + + CORE_1_PIF_PMS_MONITOR_2 + core1 permission report register 2. + 0x250 + 0x20 + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR + Record core1 illegal access interrupt state. + 0 + 1 + read-only + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 + Record hport information when core1 initiate illegal access. + 1 + 1 + read-only + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE + Record access type when core1 initate illegal access. + 2 + 3 + read-only + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE + Record access direction when core1 initiate illegal access. + 5 + 1 + read-only + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD + Record world information when core1 initiate illegal access. + 6 + 2 + read-only + + + + + CORE_1_PIF_PMS_MONITOR_3 + core1 permission report register 3. + 0x254 + 0x20 + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR + Record address information when core1 initiate illegal access. + 0 + 32 + read-only + + + + + CORE_1_PIF_PMS_MONITOR_4 + core1 permission report register 4. + 0x258 + 0x20 + 0x00000003 + + + CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR + Set 1 to clear interrupt that core1 initiate unsupported access type. + 0 + 1 + read-write + + + CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN + Set 1 to enable interrupt that core1 initiate unsupported access type. + 1 + 1 + read-write + + + + + CORE_1_PIF_PMS_MONITOR_5 + core1 permission report register 5. + 0x25C + 0x20 + + + CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR + Record core1 unsupported access type interrupt state. + 0 + 1 + read-only + + + CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE + Record access type when core1 initiate unsupported access type. + 1 + 2 + read-only + + + CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD + Record world information when core1 initiate unsupported access type. + 3 + 2 + read-only + + + + + CORE_1_PIF_PMS_MONITOR_6 + core1 permission report register 6. + 0x260 + 0x20 + + + CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR + Record address information when core1 initiate unsupported access type. + 0 + 32 + read-only + + + + + CORE_1_VECBASE_OVERRIDE_LOCK + core1 vecbase override configuration register 0 + 0x264 + 0x20 + + + CORE_1_VECBASE_OVERRIDE_LOCK + Set 1 to lock core1 vecbase configuration register + 0 + 1 + read-write + + + + + CORE_1_VECBASE_OVERRIDE_0 + core1 vecbase override configuration register 0 + 0x268 + 0x20 + 0x00000001 + + + CORE_1_VECBASE_WORLD_MASK + Set 1 to mask world, then only world0_value will work. + 0 + 1 + read-write + + + + + CORE_1_VECBASE_OVERRIDE_1 + core1 vecbase override configuration register 1 + 0x26C + 0x20 + + + CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE + world0 vecbase_override register, when core1 in world0 use this register to override vecbase register. + 0 + 22 + read-write + + + CORE_1_VECBASE_OVERRIDE_SEL + Set 0x3 to sel vecbase_override to override vecbase register. + 22 + 2 + read-write + + + + + CORE_1_VECBASE_OVERRIDE_2 + core1 vecbase override configuration register 1 + 0x270 + 0x20 + + + CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE + world1 vecbase_override register, when core1 in world1 use this register to override vecbase register. + 0 + 22 + read-write + + + + + CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0 + core1 toomanyexception override configuration register 0. + 0x274 + 0x20 + + + CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK + Set 1 to lock core1 toomanyexception override configuration register + 0 + 1 + read-write + + + + + CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1 + core1 toomanyexception override configuration register 1. + 0x278 + 0x20 + 0x00000001 + + + CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE + Set 1 to mask toomanyexception. + 0 + 1 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_0 + BackUp access peripherals permission configuration register 0. + 0x27C + 0x20 + + + BACKUP_BUS_PMS_CONSTRAIN_LOCK + Set 1 to lock BackUp permission configuration registers. + 0 + 1 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_1 + BackUp access peripherals permission configuration register 1. + 0x280 + 0x20 + 0xFF33CFFF + + + BACKUP_BUS_PMS_CONSTRAIN_UART + BackUp access uart permission. + 0 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 + BackUp access g0spi_1 permission. + 2 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 + BackUp access g0spi_0 permission. + 4 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_GPIO + BackUp access gpio permission. + 6 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_FE2 + BackUp access fe2 permission. + 8 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_FE + BackUp access fe permission. + 10 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_RTC + BackUp access rtc permission. + 14 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_IO_MUX + BackUp access io_mux permission. + 16 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_HINF + BackUp access hinf permission. + 20 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_MISC + BackUp access misc permission. + 24 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_I2C + BackUp access i2c permission. + 26 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_I2S0 + BackUp access i2s0 permission. + 28 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_UART1 + BackUp access uart1 permission. + 30 + 2 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_2 + BackUp access peripherals permission configuration register 2. + 0x284 + 0x20 + 0xFFCFFFF3 + + + BACKUP_BUS_PMS_CONSTRAIN_BT + BackUp access bt permission. + 0 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 + BackUp access i2c_ext0 permission. + 4 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_UHCI0 + BackUp access uhci0 permission. + 6 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_SLCHOST + BackUp access slchost permission. + 8 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_RMT + BackUp access rmt permission. + 10 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_PCNT + BackUp access pcnt permission. + 12 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_SLC + BackUp access slc permission. + 14 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_LEDC + BackUp access ledc permission. + 16 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_BACKUP + BackUp access backup permission. + 18 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_BB + BackUp access bb permission. + 22 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_PWM0 + BackUp access pwm0 permission. + 24 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP + BackUp access timergroup permission. + 26 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 + BackUp access timergroup1 permission. + 28 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER + BackUp access systimer permission. + 30 + 2 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_3 + BackUp access peripherals permission configuration register 3. + 0x288 + 0x20 + 0x3CC3FFFF + + + BACKUP_BUS_PMS_CONSTRAIN_SPI_2 + BackUp access spi_2 permission. + 0 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_SPI_3 + BackUp access spi_3 permission. + 2 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL + BackUp access apb_ctrl permission. + 4 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1 + BackUp access i2c_ext1 permission. + 6 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST + BackUp access sdio_host permission. + 8 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_CAN + BackUp access can permission. + 10 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_PWM1 + BackUp access pwm1 permission. + 12 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_I2S1 + BackUp access i2s1 permission. + 14 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_UART2 + BackUp access uart2 permission. + 16 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_RWBT + BackUp access rwbt permission. + 22 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC + BackUp access wifimac permission. + 26 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_PWR + BackUp access pwr permission. + 28 + 2 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_4 + BackUp access peripherals permission configuration register 4. + 0x28C + 0x20 + 0xFFFFFFFF + + + BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE + BackUp access usb_device permission. + 0 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP + BackUp access usb_wrap permission. + 2 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI + BackUp access crypto_peri permission. + 4 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA + BackUp access crypto_dma permission. + 6 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_APB_ADC + BackUp access apb_adc permission. + 8 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM + BackUp access lcd_cam permission. + 10 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_BT_PWR + BackUp access bt_pwr permission. + 12 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_USB + BackUp access usb permission. + 14 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_SYSTEM + BackUp access system permission. + 16 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE + BackUp access sensitive permission. + 18 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT + BackUp access interrupt permission. + 20 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY + BackUp access dma_copy permission. + 22 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG + BackUp access cache_config permission. + 24 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_AD + BackUp access ad permission. + 26 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_DIO + BackUp access dio permission. + 28 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER + BackUp access world_controller permission. + 30 + 2 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_5 + BackUp access peripherals permission configuration register 5. + 0x290 + 0x20 + 0x000007FF + + + BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR + BackUp access rtcfast_spltaddr permission. + 0 + 11 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_6 + BackUp access peripherals permission configuration register 6. + 0x294 + 0x20 + 0x0000003F + + + BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L + BackUp access rtcfast_l permission. + 0 + 3 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H + BackUp access rtcfast_h permission. + 3 + 3 + read-write + + + + + BACKUP_BUS_PMS_MONITOR_0 + BackUp permission report register 0. + 0x298 + 0x20 + + + BACKUP_BUS_PMS_MONITOR_LOCK + Set 1 to lock BackUp permission report registers. + 0 + 1 + read-write + + + + + BACKUP_BUS_PMS_MONITOR_1 + BackUp permission report register 1. + 0x29C + 0x20 + 0x00000003 + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear interrupt that BackUp initiate illegal access. + 0 + 1 + read-write + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_EN + Set 1 to enable interrupt that BackUp initiate illegal access. + 1 + 1 + read-write + + + + + BACKUP_BUS_PMS_MONITOR_2 + BackUp permission report register 2. + 0x2A0 + 0x20 + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR + Record BackUp illegal access interrupt state. + 0 + 1 + read-only + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS + Record htrans when BackUp initate illegal access. + 1 + 2 + read-only + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE + Record access type when BackUp initate illegal access. + 3 + 3 + read-only + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE + Record access direction when BackUp initiate illegal access. + 6 + 1 + read-only + + + + + BACKUP_BUS_PMS_MONITOR_3 + BackUp permission report register 3. + 0x2A4 + 0x20 + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR + Record address information when BackUp initiate illegal access. + 0 + 32 + read-only + + + + + EDMA_BOUNDARY_LOCK + EDMA boundary lock register. + 0x2A8 + 0x20 + + + EDMA_BOUNDARY_LOCK + Set 1 to lock EDMA boundary registers. + 0 + 1 + read-write + + + + + EDMA_BOUNDARY_0 + EDMA boundary 0 configuration + 0x2AC + 0x20 + + + EDMA_BOUNDARY_0 + This field is used to configure the boundary 0 of external RAM. The unit is 4K. For example, set this field to 0x80, then the address boundary 0 would be 0x3C080000 (0x3C000000 + 0x80 * 4K). + 0 + 14 + read-write + + + + + EDMA_BOUNDARY_1 + EDMA boundary 1 configuration + 0x2B0 + 0x20 + 0x00002000 + + + EDMA_BOUNDARY_1 + This field is used to configure the boundary 1 of external RAM. The unit is 4K. For example, set this field to 0x80, then the address boundary 0 would be 0x3C080000 (0x3C000000 + 0x80 * 4K). + 0 + 14 + read-write + + + + + EDMA_BOUNDARY_2 + EDMA boundary 2 configuration + 0x2B4 + 0x20 + 0x00002000 + + + EDMA_BOUNDARY_2 + This field is used to configure the boundary 2 of external RAM. The unit is 4K. For example, set this field to 0x80, then the address boundary 0 would be 0x3C080000 (0x3C000000 + 0x80 * 4K). + 0 + 14 + read-write + + + + + EDMA_PMS_SPI2_LOCK + EDMA-SPI2 permission lock register. + 0x2B8 + 0x20 + + + EDMA_PMS_SPI2_LOCK + Set 1 to lock EDMA-SPI2 permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_SPI2 + EDMA-SPI2 permission control register. + 0x2BC + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of SPI2 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of SPI2 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_SPI3_LOCK + EDMA-SPI3 permission lock register. + 0x2C0 + 0x20 + + + EDMA_PMS_SPI3_LOCK + Set 1 to lock EDMA-SPI3 permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_SPI3 + EDMA-SPI3 permission control register. + 0x2C4 + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of SPI3 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of SPI3 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_UHCI0_LOCK + EDMA-UHCI0 permission lock register. + 0x2C8 + 0x20 + + + EDMA_PMS_UHCI0_LOCK + Set 1 to lock EDMA-UHCI0 permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_UHCI0 + EDMA-UHCI0 permission control register. + 0x2CC + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of UHCI0 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of UHCI0 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_I2S0_LOCK + EDMA-I2S0 permission lock register. + 0x2D0 + 0x20 + + + EDMA_PMS_I2S0_LOCK + Set 1 to lock EDMA-I2S0 permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_I2S0 + EDMA-I2S0 permission control register. + 0x2D4 + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of I2S0 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of I2S0 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_I2S1_LOCK + EDMA-I2S1 permission lock register. + 0x2D8 + 0x20 + + + EDMA_PMS_I2S1_LOCK + Set 1 to lock EDMA-I2S1 permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_I2S1 + EDMA-I2S1 permission control register. + 0x2DC + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of I2S1 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of I2S1 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_LCD_CAM_LOCK + EDMA-LCD/CAM permission lock register. + 0x2E0 + 0x20 + + + EDMA_PMS_LCD_CAM_LOCK + Set 1 to lock EDMA-LCD/CAM permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_LCD_CAM + EDMA-LCD/CAM permission control register. + 0x2E4 + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of LCD/CAM accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of LCD/CAM accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_AES_LOCK + EDMA-AES permission lock register. + 0x2E8 + 0x20 + + + EDMA_PMS_AES_LOCK + Set 1 to lock EDMA-AES permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_AES + EDMA-AES permission control register. + 0x2EC + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of AES accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of AES accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_SHA_LOCK + EDMA-SHA permission lock register. + 0x2F0 + 0x20 + + + EDMA_PMS_SHA_LOCK + Set 1 to lock EDMA-SHA permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_SHA + EDMA-SHA permission control register. + 0x2F4 + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of SHA accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of SHA accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_ADC_DAC_LOCK + EDMA-ADC/DAC permission lock register. + 0x2F8 + 0x20 + + + EDMA_PMS_ADC_DAC_LOCK + Set 1 to lock EDMA-ADC/DAC permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_ADC_DAC + EDMA-ADC/DAC permission control register. + 0x2FC + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of ADC/DAC accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of ADC/DAC accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_RMT_LOCK + EDMA-RMT permission lock register. + 0x300 + 0x20 + + + EDMA_PMS_RMT_LOCK + Set 1 to lock EDMA-RMT permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_RMT + EDMA-RMT permission control register. + 0x304 + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of RMT accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of RMT accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + CLOCK_GATE + Sensitive module clock gate configuration register. + 0x308 + 0x20 + 0x00000001 + + + REG_CLK_EN + Set 1 to enable clock gate function. + 0 + 1 + read-write + + + + + RTC_PMS + RTC coprocessor permission register. + 0x30C + 0x20 + + + DIS_RTC_CPU + Set 1 to disable rtc coprocessor. + 0 + 1 + read-write + + + + + DATE + Sensitive version register. + 0xFFC + 0x20 + 0x02101280 + + + DATE + Sensitive Date register. + 0 + 28 + read-write + + + + + + + SHA + SHA (Secure Hash Algorithm) Accelerator + SHA + 0x6003B000 + + 0x0 + 0xB0 + registers + + + SHA + 77 + + + + MODE + Initial configuration register. + 0x0 + 0x20 + + + MODE + sha mode + 0 + 3 + read-write + + + + + T_STRING + SHA 512/t configuration register 0. + 0x4 + 0x20 + + + T_STRING + sha t_string(used if and only if mode == sha_256/t) + 0 + 32 + read-write + + + + + T_LENGTH + SHA 512/t configuration register 1. + 0x8 + 0x20 + + + T_LENGTH + sha t_length(used if and only if mode == sha_256/t) + 0 + 6 + read-write + + + + + DMA_BLOCK_NUM + DMA configuration register 0. + 0xC + 0x20 + + + DMA_BLOCK_NUM + dma-sha block number + 0 + 6 + read-write + + + + + START + Typical SHA configuration register 0. + 0x10 + 0x20 + + + START + reserved. + 1 + 31 + read-only + + + + + CONTINUE + Typical SHA configuration register 1. + 0x14 + 0x20 + + + CONTINUE + reserved. + 1 + 31 + read-only + + + + + BUSY + Busy register. + 0x18 + 0x20 + + + STATE + sha busy state. 1'b0: idle 1'b1: busy + 0 + 1 + read-only + + + + + DMA_START + DMA configuration register 1. + 0x1C + 0x20 + + + DMA_START + start dma-sha + 0 + 1 + write-only + + + + + DMA_CONTINUE + DMA configuration register 2. + 0x20 + 0x20 + + + DMA_CONTINUE + continue dma-sha + 0 + 1 + write-only + + + + + CLEAR_IRQ + Interrupt clear register. + 0x24 + 0x20 + + + CLEAR_INTERRUPT + clear sha interrupt + 0 + 1 + write-only + + + + + IRQ_ENA + Interrupt enable register. + 0x28 + 0x20 + + + INTERRUPT_ENA + sha interrupt enable register. 1'b0: disable(default) 1'b1: enable + 0 + 1 + read-write + + + + + DATE + Date register. + 0x2C + 0x20 + 0x20190402 + + + DATE + sha date information/ sha version information + 0 + 30 + read-write + + + + + 64 + 0x1 + H_MEM[%s] + Sha H memory which contains intermediate hash or finial hash. + 0x40 + 0x8 + + + 64 + 0x1 + M_MEM[%s] + Sha M memory which contains message. + 0x80 + 0x8 + + + + + SPI0 + SPI (Serial Peripheral Interface) Controller 0 + SPI0 + 0x60003000 + + 0x0 + 0x98 + registers + + + SPI_MEM_REJECT_CACHE + 60 + + + + CTRL + SPI0 control register. + 0x8 + 0x20 + 0x002C2000 + + + FDUMMY_OUT + In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller. + 3 + 1 + read-write + + + FDOUT_OCT + Set this bit to enable 8-bit-mode(8-bm) in DOUT phase. + 4 + 1 + read-write + + + FDIN_OCT + Set this bit to enable 8-bit-mode(8-bm) in DIN phase. + 5 + 1 + read-write + + + FADDR_OCT + Set this bit to enable 8-bit-mode(8-bm) in ADDR phase. + 6 + 1 + read-write + + + FCMD_DUAL + Set this bit to enable 2-bit-mode(2-bm) in CMD phase. + 7 + 1 + read-write + + + FCMD_QUAD + Set this bit to enable 4-bit-mode(4-bm) in CMD phase. + 8 + 1 + read-write + + + FCMD_OCT + Set this bit to enable 8-bit-mode(8-bm) in CMD phase. + 9 + 1 + read-write + + + FASTRD_MODE + This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set. + 13 + 1 + read-write + + + FREAD_DUAL + In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable. + 14 + 1 + read-write + + + Q_POL + The bit is used to set MISO line polarity, 1: high 0, low + 18 + 1 + read-write + + + D_POL + The bit is used to set MOSI line polarity, 1: high 0, low + 19 + 1 + read-write + + + FREAD_QUAD + In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. + 20 + 1 + read-write + + + WP + Write protect signal output when SPI is idle. 1: output high, 0: output low. + 21 + 1 + read-write + + + FREAD_DIO + In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable. + 23 + 1 + read-write + + + FREAD_QIO + In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. + 24 + 1 + read-write + + + + + CTRL1 + SPI0 control 1 register. + 0xC + 0x20 + + + CLK_MODE + SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on. + 0 + 2 + read-write + + + RXFIFO_RST + SPI0 RX FIFO reset signal. Set this bit and clear it before SPI0 transfer starts. + 30 + 1 + read-write + + + + + CTRL2 + SPI0 control 2 register. + 0x10 + 0x20 + 0x00002C21 + + + CS_SETUP_TIME + (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit. + 0 + 5 + read-write + + + CS_HOLD_TIME + SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit. + 5 + 5 + read-write + + + ECC_CS_HOLD_TIME + SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI_CS hold cycle in ECC mode when accessed flash. + 10 + 3 + read-write + + + ECC_SKIP_PAGE_CORNER + 1: MSPI skips page corner when accesses flash. 0: Not skip page corner when accesses flash. + 13 + 1 + read-write + + + ECC_16TO18_BYTE_EN + Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses flash. + 14 + 1 + read-write + + + CS_HOLD_DELAY + These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. + 25 + 6 + read-write + + + SYNC_RESET + The FSM will be reset. + 31 + 1 + read-write + + + + + CLOCK + SPI_CLK clock division register when SPI0 accesses to flash. + 0x14 + 0x20 + 0x00030103 + + + CLKCNT_L + It must equal to the value of SPI_MEM_CLKCNT_N. + 0 + 8 + read-write + + + CLKCNT_H + It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1). + 8 + 8 + read-write + + + CLKCNT_N + When SPI0 accesses flash, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLKCNT_N+1) + 16 + 8 + read-write + + + CLK_EQU_SYSCLK + When SPI0 accesses flash, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK. + 31 + 1 + read-write + + + + + USER + SPI0 user register. + 0x18 + 0x20 + + + CS_HOLD + Set this bit to keep SPI_CS low when MSPI is in DONE state. + 6 + 1 + read-write + + + CS_SETUP + Set this bit to keep SPI_CS low when MSPI is in PREP state. + 7 + 1 + read-write + + + CK_OUT_EDGE + This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK. + 9 + 1 + read-write + + + USR_DUMMY_IDLE + SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable. + 26 + 1 + read-write + + + USR_DUMMY + This bit enable the DUMMY phase of an SPI transfer. + 29 + 1 + read-write + + + + + USER1 + SPI0 user1 register. + 0x1C + 0x20 + 0x5C000007 + + + USR_DUMMY_CYCLELEN + The SPI_CLK cycle length minus 1 of DUMMY phase. + 0 + 6 + read-write + + + USR_ADDR_BITLEN + The length in bits of ADDR phase. The register value shall be (bit_num-1). + 26 + 6 + read-write + + + + + USER2 + SPI0 user2 register. + 0x20 + 0x20 + 0x70000000 + + + USR_COMMAND_VALUE + The value of user defined(USR) command. + 0 + 16 + read-write + + + USR_COMMAND_BITLEN + The length in bits of CMD phase. The register value shall be (bit_num-1) + 28 + 4 + read-write + + + + + RD_STATUS + SPI0 read control register. + 0x2C + 0x20 + + + WB_MODE + Mode bits in the flash fast read mode it is combined with SPI_MEM_FASTRD_MODE bit. + 16 + 8 + read-write + + + + + EXT_ADDR + SPI0 extended address register. + 0x30 + 0x20 + + + EXT_ADDR + The register are the higher 32bits in the 64 bits address mode. + 0 + 32 + read-write + + + + + MISC + SPI0 misc register + 0x34 + 0x20 + + + FSUB_PIN + Flash is connected to SPI SUBPIN bus. + 7 + 1 + read-write + + + SSUB_PIN + Ext_RAM is connected to SPI SUBPIN bus. + 8 + 1 + read-write + + + CK_IDLE_EDGE + 1: SPI_CLK line is high when idle. 0: SPI_CLK line is low when idle + 9 + 1 + read-write + + + CS_KEEP_ACTIVE + SPI_CS line keep low when the bit is set. + 10 + 1 + read-write + + + + + CACHE_FCTRL + SPI0 external RAM bit mode control register. + 0x3C + 0x20 + + + CACHE_REQ_EN + Set this bit to enable Cache's access and SPI0's transfer. + 0 + 1 + read-write + + + CACHE_USR_CMD_4BYTE + Set this bit to enable SPI0 read flash with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31. + 1 + 1 + read-write + + + CACHE_FLASH_USR_CMD + 1: The command value of SPI0 reads flash is SPI_MEM_USR_COMMAND_VALUE. 0: Hardware read command value, controlled by SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and SPI_MEM_FASTRD_MODE bits. + 2 + 1 + read-write + + + FDIN_DUAL + When SPI0 accesses to flash, set this bit to enable 2-bm in DIN phase. + 3 + 1 + read-write + + + FDOUT_DUAL + When SPI0 accesses to flash, set this bit to enable 2-bm in DOUT phase. + 4 + 1 + read-write + + + FADDR_DUAL + When SPI0 accesses to flash, set this bit to enable 2-bm in ADDR phase. + 5 + 1 + read-write + + + FDIN_QUAD + When SPI0 accesses to flash, set this bit to enable 4-bm in DIN phase. + 6 + 1 + read-write + + + FDOUT_QUAD + When SPI0 accesses to flash, set this bit to enable 4-bm in DOUT phase. + 7 + 1 + read-write + + + FADDR_QUAD + When SPI0 accesses to flash, set this bit to enable 4-bm in ADDR phase. + 8 + 1 + read-write + + + + + CACHE_SCTRL + SPI0 external RAM control register + 0x40 + 0x20 + 0x0055C070 + + + CACHE_USR_SCMD_4BYTE + Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31. + 0 + 1 + read-write + + + USR_SRAM_DIO + Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer. + 1 + 1 + read-write + + + USR_SRAM_QIO + Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer. + 2 + 1 + read-write + + + USR_WR_SRAM_DUMMY + When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in write operations. + 3 + 1 + read-write + + + USR_RD_SRAM_DUMMY + When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in read operations. + 4 + 1 + read-write + + + CACHE_SRAM_USR_RCMD + 1: The command value of SPI0 read Ext_RAM is SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE. 0: The value is 0x2. + 5 + 1 + read-write + + + SRAM_RDUMMY_CYCLELEN + When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in read data transfer. + 6 + 6 + read-write + + + SRAM_ADDR_BITLEN + When SPI0 accesses to Ext_RAM, it is the length in bits of ADDR phase. The register value shall be (bit_num-1). + 14 + 6 + read-write + + + CACHE_SRAM_USR_WCMD + 1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. 0: The value is 0x3. + 20 + 1 + read-write + + + SRAM_OCT + Set the bit to enable OPI mode in all SPI0 Ext_RAM transfer. + 21 + 1 + read-write + + + SRAM_WDUMMY_CYCLELEN + When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in write data transfer. + 22 + 6 + read-write + + + + + SRAM_CMD + SPI0 external RAM mode control register + 0x44 + 0x20 + + + SCLK_MODE + SPI_CLK mode bits when SPI0 accesses to Ext_RAM. 0: SPI_CLK is off when CS inactive 1: SPI_CLK is delayed one cycle after CS inactive 2: SPI_CLK is delayed two cycles after CS inactive 3: SPI_CLK is always on. + 0 + 2 + read-write + + + SWB_MODE + Mode bits when SPI0 accesses to Ext_RAM. + 2 + 8 + read-write + + + SDIN_DUAL + When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DIN phase. + 10 + 1 + read-write + + + SDOUT_DUAL + When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DOUT phase. + 11 + 1 + read-write + + + SADDR_DUAL + When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in ADDR phase. + 12 + 1 + read-write + + + SCMD_DUAL + When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in CMD phase. + 13 + 1 + read-write + + + SDIN_QUAD + When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DIN phase. + 14 + 1 + read-write + + + SDOUT_QUAD + When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DOUT phase. + 15 + 1 + read-write + + + SADDR_QUAD + When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in ADDR phase. + 16 + 1 + read-write + + + SCMD_QUAD + When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in CMD phase. + 17 + 1 + read-write + + + SDIN_OCT + When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DIN phase. + 18 + 1 + read-write + + + SDOUT_OCT + When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DOUT phase. + 19 + 1 + read-write + + + SADDR_OCT + When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in ADDR phase. + 20 + 1 + read-write + + + SCMD_OCT + When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in CMD phase. + 21 + 1 + read-write + + + SDUMMY_OUT + When SPI0 accesses to Ext_RAM, in the DUMMY phase the signal level of SPI bus is output by the SPI0 controller. + 22 + 1 + read-write + + + + + SRAM_DRD_CMD + SPI0 external RAM DDR read command control register + 0x48 + 0x20 + + + CACHE_SRAM_USR_RD_CMD_VALUE + When SPI0 reads Ext_RAM, it is the command value of CMD phase. + 0 + 16 + read-write + + + CACHE_SRAM_USR_RD_CMD_BITLEN + When SPI0 reads Ext_RAM, it is the length in bits of CMD phase. The register value shall be (bit_num-1). + 28 + 4 + read-write + + + + + SRAM_DWR_CMD + SPI0 external RAM DDR write command control register + 0x4C + 0x20 + + + CACHE_SRAM_USR_WR_CMD_VALUE + When SPI0 writes Ext_RAM, it is the command value of CMD phase. + 0 + 16 + read-write + + + CACHE_SRAM_USR_WR_CMD_BITLEN + When SPI0 writes Ext_RAM, it is the length in bits of CMD phase. The register value shall be (bit_num-1). + 28 + 4 + read-write + + + + + SRAM_CLK + SPI_CLK clock division register when SPI0 accesses to Ext_RAM. + 0x50 + 0x20 + 0x00030103 + + + SCLKCNT_L + It must equal to the value of SPI_MEM_SCLKCNT_N. + 0 + 8 + read-write + + + SCLKCNT_H + It must be a floor value of ((SPI_MEM_SCLKCNT_N+1)/2-1). + 8 + 8 + read-write + + + SCLKCNT_N + When SPI0 accesses to Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_SCLKCNT_N+1) + 16 + 8 + read-write + + + SCLK_EQU_SYSCLK + When SPI0 accesses to Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK. + 31 + 1 + read-write + + + + + FSM + SPI0 state machine(FSM) status register. + 0x54 + 0x20 + + + ST + The status of SPI0 state machine. 0: idle state(IDLE), 1: preparation state(PREP), 2: send command state(CMD), 3: send address state(ADDR), 4: red data state(DIN), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE). + 0 + 3 + read-only + + + + + TIMING_CALI + SPI0 timing compensation register when accesses to flash. + 0xA8 + 0x20 + + + TIMING_CLK_ENA + Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL. + 0 + 1 + read-write + + + TIMING_CALI + Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations. + 1 + 1 + read-write + + + EXTRA_DUMMY_CYCLELEN + Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to flash. Active when SPI_MEM_TIMING_CALI bit is set. + 2 + 3 + read-write + + + + + DIN_MODE + MSPI input timing delay mode control register when accesses to flash. + 0xAC + 0x20 + + + DIN0_MODE + SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN0_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 0 + 3 + read-write + + + DIN1_MODE + SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN3_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 3 + 3 + read-write + + + DIN2_MODE + SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN6_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 6 + 3 + read-write + + + DIN3_MODE + SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN9_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 9 + 3 + read-write + + + DIN4_MODE + SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN12_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 12 + 3 + read-write + + + DIN5_MODE + SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN15_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 15 + 3 + read-write + + + DIN6_MODE + SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN18_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 18 + 3 + read-write + + + DIN7_MODE + SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN21_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 21 + 3 + read-write + + + DINS_MODE + SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 24 + 3 + read-write + + + + + DIN_NUM + MSPI input timing delay number control register when accesses to flash. + 0xB0 + 0x20 + + + DIN0_NUM + SPI_D input delay number. + 0 + 2 + read-write + + + DIN1_NUM + SPI_Q input delay number. + 2 + 2 + read-write + + + DIN2_NUM + SPI_WP input delay number. + 4 + 2 + read-write + + + DIN3_NUM + SPI_HD input delay number. + 6 + 2 + read-write + + + DIN4_NUM + SPI_IO4 input delay number. + 8 + 2 + read-write + + + DIN5_NUM + SPI_IO5 input delay number. + 10 + 2 + read-write + + + DIN6_NUM + SPI_IO6 input delay number. + 12 + 2 + read-write + + + DIN7_NUM + SPI_IO7 input delay number. + 14 + 2 + read-write + + + DINS_NUM + SPI_DQS input delay number. + 16 + 2 + read-write + + + + + DOUT_MODE + MSPI output timing delay mode control register when accesses to flash. + 0xB4 + 0x20 + + + DOUT0_MODE + SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 0 + 1 + read-write + + + DOUT1_MODE + SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 1 + 1 + read-write + + + DOUT2_MODE + SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 2 + 1 + read-write + + + DOUT3_MODE + SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 3 + 1 + read-write + + + DOUT4_MODE + SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 4 + 1 + read-write + + + DOUT5_MODE + SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 5 + 1 + read-write + + + DOUT6_MODE + SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 6 + 1 + read-write + + + DOUT7_MODE + SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 7 + 1 + read-write + + + DOUTS_MODE + SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 8 + 1 + read-write + + + + + SPI_SMEM_TIMING_CALI + SPI0 Ext_RAM timing compensation register. + 0xBC + 0x20 + + + SPI_SMEM_TIMING_CLK_ENA + Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL. + 0 + 1 + read-write + + + SPI_SMEM_TIMING_CALI + Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations. + 1 + 1 + read-write + + + SPI_SMEM_EXTRA_DUMMY_CYCLELEN + Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to Ext_RAM. Active when SPI_SMEM_TIMING_CALI bit is set. + 2 + 3 + read-write + + + + + SPI_SMEM_DIN_MODE + MSPI input timing delay mode control register when accesses to Ext_RAM. + 0xC0 + 0x20 + + + SPI_SMEM_DIN0_MODE + SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 0 + 3 + read-write + + + SPI_SMEM_DIN1_MODE + SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 3 + 3 + read-write + + + SPI_SMEM_DIN2_MODE + SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 6 + 3 + read-write + + + SPI_SMEM_DIN3_MODE + SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 9 + 3 + read-write + + + SPI_SMEM_DIN4_MODE + SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 12 + 3 + read-write + + + SPI_SMEM_DIN5_MODE + SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 15 + 3 + read-write + + + SPI_SMEM_DIN6_MODE + SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 18 + 3 + read-write + + + SPI_SMEM_DIN7_MODE + SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 21 + 3 + read-write + + + SPI_SMEM_DINS_MODE + SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 24 + 3 + read-write + + + + + SPI_SMEM_DIN_NUM + MSPI input timing delay number control register when accesses to Ext_RAM. + 0xC4 + 0x20 + + + SPI_SMEM_DIN0_NUM + SPI_D input delay number. + 0 + 2 + read-write + + + SPI_SMEM_DIN1_NUM + SPI_Q input delay number. + 2 + 2 + read-write + + + SPI_SMEM_DIN2_NUM + SPI_WP input delay number. + 4 + 2 + read-write + + + SPI_SMEM_DIN3_NUM + SPI_HD input delay number. + 6 + 2 + read-write + + + SPI_SMEM_DIN4_NUM + SPI_IO4 input delay number. + 8 + 2 + read-write + + + SPI_SMEM_DIN5_NUM + SPI_IO5 input delay number. + 10 + 2 + read-write + + + SPI_SMEM_DIN6_NUM + SPI_IO6 input delay number. + 12 + 2 + read-write + + + SPI_SMEM_DIN7_NUM + SPI_IO7 input delay number. + 14 + 2 + read-write + + + SPI_SMEM_DINS_NUM + SPI_DQS input delay number. + 16 + 2 + read-write + + + + + SPI_SMEM_DOUT_MODE + MSPI output timing delay mode control register when accesses to Ext_RAM. + 0xC8 + 0x20 + + + SPI_SMEM_DOUT0_MODE + SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 0 + 1 + read-write + + + SPI_SMEM_DOUT1_MODE + SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 1 + 1 + read-write + + + SPI_SMEM_DOUT2_MODE + SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 2 + 1 + read-write + + + SPI_SMEM_DOUT3_MODE + SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 3 + 1 + read-write + + + SPI_SMEM_DOUT4_MODE + SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 4 + 1 + read-write + + + SPI_SMEM_DOUT5_MODE + SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 5 + 1 + read-write + + + SPI_SMEM_DOUT6_MODE + SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 6 + 1 + read-write + + + SPI_SMEM_DOUT7_MODE + SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 7 + 1 + read-write + + + SPI_SMEM_DOUTS_MODE + SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 8 + 1 + read-write + + + + + ECC_CTRL + MSPI ECC control register + 0xCC + 0x20 + 0x0000000A + + + ECC_ERR_INT_NUM + Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. + 0 + 8 + read-write + + + SPI_FMEM_ECC_ERR_INT_EN + Set this bit to calculate the error times of MSPI ECC read when accesses to flash. + 8 + 1 + read-write + + + + + ECC_ERR_ADDR + MSPI ECC error address register + 0xD0 + 0x20 + + + ECC_ERR_ADDR + These bits show the first MSPI ECC error address when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM, including ECC byte error and data error. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. + 0 + 32 + read-only + + + + + ECC_ERR_BIT + MSPI ECC error bits register + 0xD4 + 0x20 + + + ECC_DATA_ERR_BIT + It records the first ECC data error bit number when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. The value ranges from 0~127, corresponding to the bit number in 16 data bytes. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit. + 6 + 7 + read-only + + + ECC_CHK_ERR_BIT + When SPI_MEM_ECC_BYTE_ERR is set, these bits show the error bit number of ECC byte. + 13 + 3 + read-only + + + ECC_BYTE_ERR + It records the first ECC byte error when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit. + 16 + 1 + read-only + + + ECC_ERR_CNT + This bits show the error times of MSPI ECC read, including ECC byte error and data byte error. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. + 17 + 8 + read-only + + + + + SPI_SMEM_AC + MSPI external RAM ECC and SPI CS timing control register + 0xDC + 0x20 + 0x0000B084 + + + SPI_SMEM_CS_SETUP + Set this bit to keep SPI_CS low when MSPI is in PREP state. + 0 + 1 + read-write + + + SPI_SMEM_CS_HOLD + Set this bit to keep SPI_CS low when MSPI is in DONE state. + 1 + 1 + read-write + + + SPI_SMEM_CS_SETUP_TIME + (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit. + 2 + 5 + read-write + + + SPI_SMEM_CS_HOLD_TIME + SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit. + 7 + 5 + read-write + + + SPI_SMEM_ECC_CS_HOLD_TIME + SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycles in ECC mode when accesses to external RAM. + 12 + 3 + read-write + + + SPI_SMEM_ECC_SKIP_PAGE_CORNER + 1: MSPI skips page corner when accesses to external RAM. 0: Not skip page corner when accesses to external RAM. + 15 + 1 + read-write + + + SPI_SMEM_ECC_16TO18_BYTE_EN + Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses to external RAM. + 16 + 1 + read-write + + + SPI_SMEM_ECC_ERR_INT_EN + Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM. + 24 + 1 + read-write + + + SPI_SMEM_CS_HOLD_DELAY + These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. + 25 + 6 + read-write + + + + + DDR + SPI0 flash DDR mode control register + 0xE0 + 0x20 + 0x00003020 + + + SPI_FMEM_DDR_EN + 1: in ddr mode, 0 in sdr mode + 0 + 1 + read-write + + + SPI_FMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in DDR mode. + 1 + 1 + read-write + + + SPI_FMEM_DDR_RDAT_SWP + Set the bit to reorder RX data of the word in DDR mode. + 2 + 1 + read-write + + + SPI_FMEM_DDR_WDAT_SWP + Set the bit to swap TX data of a word in DDR mode. + 3 + 1 + read-write + + + SPI_FMEM_DDR_CMD_DIS + the bit is used to disable dual edge in CMD phase when ddr mode. + 4 + 1 + read-write + + + SPI_FMEM_OUTMINBYTELEN + It is the minimum output data length in the panda device. + 5 + 7 + read-write + + + SPI_FMEM_TX_DDR_MSK_EN + Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to flash. + 12 + 1 + read-write + + + SPI_FMEM_RX_DDR_MSK_EN + Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to flash. + 13 + 1 + read-write + + + SPI_FMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI_CLK. + 14 + 7 + read-write + + + SPI_FMEM_DDR_DQS_LOOP + 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module + 21 + 1 + read-write + + + SPI_FMEM_DDR_DQS_LOOP_MODE + When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active. + 22 + 1 + read-write + + + SPI_FMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-write + + + SPI_FMEM_HYPERBUS_MODE + Set this bit to enable the SPI HyperBus mode. + 25 + 1 + read-write + + + SPI_FMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-write + + + SPI_FMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram. + 27 + 1 + read-write + + + SPI_FMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to flash. . + 28 + 1 + read-write + + + SPI_FMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-write + + + SPI_FMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-write + + + + + SPI_SMEM_DDR + SPI0 external RAM DDR mode control register + 0xE4 + 0x20 + 0x00003020 + + + EN + 1: in ddr mode, 0 in sdr mode + 0 + 1 + read-write + + + SPI_SMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in spi ddr mode. + 1 + 1 + read-write + + + RDAT_SWP + Set the bit to reorder rx data of the word in spi ddr mode. + 2 + 1 + read-write + + + WDAT_SWP + Set the bit to reorder tx data of the word in spi ddr mode. + 3 + 1 + read-write + + + CMD_DIS + the bit is used to disable dual edge in CMD phase when ddr mode. + 4 + 1 + read-write + + + SPI_SMEM_OUTMINBYTELEN + It is the minimum output data length in the ddr psram. + 5 + 7 + read-write + + + SPI_SMEM_TX_DDR_MSK_EN + Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to external RAM. + 12 + 1 + read-write + + + SPI_SMEM_RX_DDR_MSK_EN + Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to external RAM. + 13 + 1 + read-write + + + SPI_SMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI_CLK. + 14 + 7 + read-write + + + DQS_LOOP + 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module + 21 + 1 + read-write + + + DQS_LOOP_MODE + When SPI_SMEM_DDR_DQS_LOOP and SPI_SMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active. + 22 + 1 + read-write + + + SPI_SMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-write + + + SPI_SMEM_HYPERBUS_MODE + Set this bit to enable the SPI HyperBus mode. + 25 + 1 + read-write + + + SPI_SMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-write + + + SPI_SMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram. + 27 + 1 + read-write + + + SPI_SMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to external RAM. . + 28 + 1 + read-write + + + SPI_SMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-write + + + SPI_SMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-write + + + + + CLOCK_GATE + SPI0 clk_gate register + 0xE8 + 0x20 + 0x00000001 + + + CLK_EN + Register clock gate enable signal. 1: Enable. 0: Disable. + 0 + 1 + read-write + + + + + CORE_CLK_SEL + SPI0 module clock select register + 0xEC + 0x20 + + + CORE_CLK_SEL + When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of SPI_MEM_CORE_CLK_SEL: 0: SPI0/1 module clock (MSPI_CORE_CLK) is 80MHz. 1: MSPI_CORE_CLK is 120MHz. 2: MSPI_CORE_CLK is 160MHz. 3: MSPI_CORE_CLK is 240MHz. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of SPI_MEM_CORE_CLK_SEL: 0: MSPI_CORE_CLK is 80MHz. 1: MSPI_CORE_CLK is 80MHz. 2: MSPI_CORE_CLK 160MHz. 3: Not used. + 0 + 2 + read-write + + + + + INT_ENA + SPI1 interrupt enable register + 0xF0 + 0x20 + + + TOTAL_TRANS_END_INT_ENA + The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + 2 + 1 + read-write + + + ECC_ERR_INT_ENA + The enable bit for SPI_MEM_ECC_ERR_INT interrupt. + 4 + 1 + read-write + + + + + INT_CLR + SPI1 interrupt clear register + 0xF4 + 0x20 + + + TOTAL_TRANS_END_INT_CLR + The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + 2 + 1 + write-only + + + ECC_ERR_INT_CLR + The clear bit for SPI_MEM_ECC_ERR_INT interrupt. SPI_MEM_ECC_ERR_ADDR and SPI_MEM_ECC_ERR_CNT will be cleared by the pulse of this bit. + 4 + 1 + write-only + + + + + INT_RAW + SPI1 interrupt raw register + 0xF8 + 0x20 + + + TOTAL_TRANS_END_INT_RAW + The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 transfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success. 0: Others. + 2 + 1 + read-write + + + ECC_ERR_INT_RAW + The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When APB_CTRL_FECC_ERR_INT_EN is set and APB_CTRL_SECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN is cleared and APB_CTRL_SECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN are cleared, this bit will not be triggered. + 4 + 1 + read-write + + + + + INT_ST + SPI1 interrupt status register + 0xFC + 0x20 + + + TOTAL_TRANS_END_INT_ST + The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + 2 + 1 + read-only + + + ECC_ERR_INT_ST + The status bit for SPI_MEM_ECC_ERR_INT interrupt. + 4 + 1 + read-only + + + + + DATE + SPI0 version control register + 0x3FC + 0x20 + 0x02101040 + + + SPI_SMEM_SPICLK_FUN_DRV + The driver of SPI_CLK PAD is controlled by the bits SPI_SMEM_SPICLK_FUN_DRV[1:0] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to external RAM. + 0 + 2 + read-write + + + SPI_FMEM_SPICLK_FUN_DRV + The driver of SPI_CLK PAD is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV[1:0] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to flash. + 2 + 2 + read-write + + + SPI_SPICLK_PAD_DRV_CTL_EN + SPI_CLK PAD driver control signal. 1: The driver of SPI_CLK PAD is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV[1:0] and SPI_SMEM_SPICLK_FUN_DRV[1:0]. 0: The driver of SPI_CLK PAD is controlled by the bits IO_MUX_FUNC_DRV[1:0] of SPICLK PAD. + 4 + 1 + read-write + + + DATE + SPI register version. + 5 + 23 + read-write + + + + + + + SPI1 + SPI (Serial Peripheral Interface) Controller 1 + SPI1 + 0x60002000 + + 0x0 + 0xB4 + registers + + + SPI1 + 20 + + + + CMD + SPI1 memory command register + 0x0 + 0x20 + + + FLASH_PE + In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with SPI_MEM_USR bit. The bit will be cleared once the operation done.1: enable 0: disable. + 17 + 1 + read-write + + + USR + User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 18 + 1 + read-write + + + FLASH_HPM + Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. + 19 + 1 + read-write + + + FLASH_RES + This bit combined with SPI_MEM_RESANDRES bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. + 20 + 1 + read-write + + + FLASH_DP + Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 21 + 1 + read-write + + + FLASH_CE + Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 22 + 1 + read-write + + + FLASH_BE + Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 23 + 1 + read-write + + + FLASH_SE + Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 24 + 1 + read-write + + + FLASH_PP + Page program enable(1 byte ~64 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. + 25 + 1 + read-write + + + FLASH_WRSR + Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 26 + 1 + read-write + + + FLASH_RDSR + Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 27 + 1 + read-write + + + FLASH_RDID + Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 28 + 1 + read-write + + + FLASH_WRDI + Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 29 + 1 + read-write + + + FLASH_WREN + Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 30 + 1 + read-write + + + FLASH_READ + Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 31 + 1 + read-write + + + + + ADDR + SPI1 address register + 0x4 + 0x20 + + + USR_ADDR_VALUE + In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer. + 0 + 32 + read-write + + + + + CTRL + SPI1 control register + 0x8 + 0x20 + 0x002CA000 + + + FDUMMY_OUT + In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller. + 3 + 1 + read-write + + + FDOUT_OCT + Set this bit to enable 8-bit-mode(8-bm) in DOUT phase. + 4 + 1 + read-write + + + FDIN_OCT + Set this bit to enable 8-bit-mode(8-bm) in DIN phase. + 5 + 1 + read-write + + + FADDR_OCT + Set this bit to enable 8-bit-mode(8-bm) in ADDR phase. + 6 + 1 + read-write + + + FCMD_DUAL + Set this bit to enable 2-bit-mode(2-bm) in CMD phase. + 7 + 1 + read-write + + + FCMD_QUAD + Set this bit to enable 4-bit-mode(4-bm) in CMD phase. + 8 + 1 + read-write + + + FCMD_OCT + Set this bit to enable 8-bit-mode(8-bm) in CMD phase. + 9 + 1 + read-write + + + FCS_CRC_EN + For SPI1, initialize crc32 module before writing encrypted data to flash. Active low. + 10 + 1 + read-write + + + TX_CRC_EN + For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + 11 + 1 + read-write + + + FASTRD_MODE + This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set. + 13 + 1 + read-write + + + FREAD_DUAL + In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable. + 14 + 1 + read-write + + + RESANDRES + The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. + 15 + 1 + read-write + + + Q_POL + The bit is used to set MISO line polarity, 1: high 0, low + 18 + 1 + read-write + + + D_POL + The bit is used to set MOSI line polarity, 1: high 0, low + 19 + 1 + read-write + + + FREAD_QUAD + In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. + 20 + 1 + read-write + + + WP + Write protect signal output when SPI is idle. 1: output high, 0: output low. + 21 + 1 + read-write + + + WRSR_2B + Two bytes data will be written to status register when it is set. 1: enable 0: disable. + 22 + 1 + read-write + + + FREAD_DIO + In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable. + 23 + 1 + read-write + + + FREAD_QIO + In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. + 24 + 1 + read-write + + + + + CTRL1 + SPI1 control1 register + 0xC + 0x20 + 0x00000FFC + + + CLK_MODE + SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on. + 0 + 2 + read-write + + + CS_HOLD_DLY_RES + After RES/DP/HPM/PES/PER command is sent, SPI1 may waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or * 256) SPI_CLK cycles. + 2 + 10 + read-write + + + + + CTRL2 + SPI1 control2 register + 0x10 + 0x20 + + + SYNC_RESET + The FSM will be reset. + 31 + 1 + read-write + + + + + CLOCK + SPI_CLK clock division register when SPI1 accesses to flash or Ext_RAM. + 0x14 + 0x20 + 0x00030103 + + + CLKCNT_L + It must equal to the value of SPI_MEM_CLKCNT_N. + 0 + 8 + read-write + + + CLKCNT_H + It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1). + 8 + 8 + read-write + + + CLKCNT_N + When SPI1 accesses to flash or Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLKCNT_N+1) + 16 + 8 + read-write + + + CLK_EQU_SYSCLK + When SPI1 access to flash or Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK. + 31 + 1 + read-write + + + + + USER + SPI1 user register. + 0x18 + 0x20 + 0x80000000 + + + CK_OUT_EDGE + This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK. + 9 + 1 + read-write + + + FWRITE_DUAL + Set this bit to enable 2-bm in DOUT phase in SPI1 write operation. + 12 + 1 + read-write + + + FWRITE_QUAD + Set this bit to enable 4-bm in DOUT phase in SPI1 write operation. + 13 + 1 + read-write + + + FWRITE_DIO + Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 write operation. + 14 + 1 + read-write + + + FWRITE_QIO + Set this bit to enable 4-bit-mode(4-bm) in ADDR and DOUT phase in SPI1 write operation. + 15 + 1 + read-write + + + USR_MISO_HIGHPART + DIN phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable. + 24 + 1 + read-write + + + USR_MOSI_HIGHPART + DOUT phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable. + 25 + 1 + read-write + + + USR_DUMMY_IDLE + SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable. + 26 + 1 + read-write + + + USR_MOSI + Set this bit to enable the DOUT phase of an write-data operation. + 27 + 1 + read-write + + + USR_MISO + Set this bit to enable enable the DIN phase of a read-data operation. + 28 + 1 + read-write + + + USR_DUMMY + Set this bit to enable enable the DUMMY phase of an operation. + 29 + 1 + read-write + + + USR_ADDR + Set this bit to enable enable the ADDR phase of an operation. + 30 + 1 + read-write + + + USR_COMMAND + Set this bit to enable enable the CMD phase of an operation. + 31 + 1 + read-write + + + + + USER1 + SPI1 user1 register. + 0x1C + 0x20 + 0x5C000007 + + + USR_DUMMY_CYCLELEN + The SPI_CLK cycle length minus 1 of DUMMY phase. + 0 + 6 + read-write + + + USR_ADDR_BITLEN + The length in bits of ADDR phase. The register value shall be (bit_num-1). + 26 + 6 + read-write + + + + + USER2 + SPI1 user2 register. + 0x20 + 0x20 + 0x70000000 + + + USR_COMMAND_VALUE + The value of user defined(USR) command. + 0 + 16 + read-write + + + USR_COMMAND_BITLEN + The length in bits of CMD phase. The register value shall be (bit_num-1) + 28 + 4 + read-write + + + + + MOSI_DLEN + SPI1 write-data bit length register. + 0x24 + 0x20 + + + USR_MOSI_DBITLEN + The length in bits of DOUT phase. The register value shall be (bit_num-1). + 0 + 10 + read-write + + + + + MISO_DLEN + SPI1 read-data bit length register. + 0x28 + 0x20 + + + USR_MISO_DBITLEN + The length in bits of DIN phase. The register value shall be (bit_num-1). + 0 + 10 + read-write + + + + + RD_STATUS + SPI1 read control register. + 0x2C + 0x20 + + + STATUS + The value is stored when set SPI_MEM_FLASH_RDSR bit and SPI_MEM_FLASH_RES bit. + 0 + 16 + read-write + + + WB_MODE + Mode bits in the flash fast read mode it is combined with SPI_MEM_FASTRD_MODE bit. + 16 + 8 + read-write + + + + + EXT_ADDR + SPI1 extended address register. + 0x30 + 0x20 + + + EXT_ADDR + The register are the higher 32bits in the 64 bits address mode. + 0 + 32 + read-write + + + + + MISC + SPI1 misc register. + 0x34 + 0x20 + 0x00000002 + + + CS0_DIS + Set this bit to raise high SPI_CS pin, which means that the SPI device(flash) connected to SPI_CS is in low level when SPI1 transfer starts. + 0 + 1 + read-write + + + CS1_DIS + Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM) connected to SPI_CS1 is in low level when SPI1 transfer starts. + 1 + 1 + read-write + + + CK_IDLE_EDGE + 1: SPI_CLK line is high when MSPI is idle. 0: SPI_CLK line is low when MSPI is idle. + 9 + 1 + read-write + + + CS_KEEP_ACTIVE + SPI_CS line keep low when the bit is set. + 10 + 1 + read-write + + + AUTO_PER + Set this bit to enable auto PER function. Hardware will sent out PER command if PES command is sent. + 11 + 1 + read-write + + + + + TX_CRC + SPI1 CRC data register. + 0x38 + 0x20 + 0xFFFFFFFF + + + DATA + For SPI1, the value of crc32. + 0 + 32 + read-only + + + + + CACHE_FCTRL + SPI1 bit mode control register. + 0x3C + 0x20 + + + CACHE_USR_CMD_4BYTE + Set this bit to enable SPI1 transfer with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31. + 1 + 1 + read-write + + + FDIN_DUAL + When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DIN phase. + 3 + 1 + read-write + + + FDOUT_DUAL + When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DOUT phase. + 4 + 1 + read-write + + + FADDR_DUAL + When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in ADDR phase. + 5 + 1 + read-write + + + FDIN_QUAD + When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DIN phase. + 6 + 1 + read-write + + + FDOUT_QUAD + When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DOUT phase. + 7 + 1 + read-write + + + FADDR_QUAD + When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in ADDR phase. + 8 + 1 + read-write + + + + + FSM + SPI1 state machine(FSM) status register. + 0x54 + 0x20 + + + ST + The status of SPI1 state machine. 0: idle state(IDLE), 1: preparation state(PREP), 2: send command state(CMD), 3: send address state(ADDR), 4: red data state(DIN), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE). + 0 + 3 + read-only + + + + + W0 + SPI1 memory data buffer0 + 0x58 + 0x20 + + + BUF0 + data buffer + 0 + 32 + read-write + + + + + W1 + SPI1 memory data buffer1 + 0x5C + 0x20 + + + BUF1 + data buffer + 0 + 32 + read-write + + + + + W2 + SPI1 memory data buffer2 + 0x60 + 0x20 + + + BUF2 + data buffer + 0 + 32 + read-write + + + + + W3 + SPI1 memory data buffer3 + 0x64 + 0x20 + + + BUF3 + data buffer + 0 + 32 + read-write + + + + + W4 + SPI1 memory data buffer4 + 0x68 + 0x20 + + + BUF4 + data buffer + 0 + 32 + read-write + + + + + W5 + SPI1 memory data buffer5 + 0x6C + 0x20 + + + BUF5 + data buffer + 0 + 32 + read-write + + + + + W6 + SPI1 memory data buffer6 + 0x70 + 0x20 + + + BUF6 + data buffer + 0 + 32 + read-write + + + + + W7 + SPI1 memory data buffer7 + 0x74 + 0x20 + + + BUF7 + data buffer + 0 + 32 + read-write + + + + + W8 + SPI1 memory data buffer8 + 0x78 + 0x20 + + + BUF8 + data buffer + 0 + 32 + read-write + + + + + W9 + SPI1 memory data buffer9 + 0x7C + 0x20 + + + BUF9 + data buffer + 0 + 32 + read-write + + + + + W10 + SPI1 memory data buffer10 + 0x80 + 0x20 + + + BUF10 + data buffer + 0 + 32 + read-write + + + + + W11 + SPI1 memory data buffer11 + 0x84 + 0x20 + + + BUF11 + data buffer + 0 + 32 + read-write + + + + + W12 + SPI1 memory data buffer12 + 0x88 + 0x20 + + + BUF12 + data buffer + 0 + 32 + read-write + + + + + W13 + SPI1 memory data buffer13 + 0x8C + 0x20 + + + BUF13 + data buffer + 0 + 32 + read-write + + + + + W14 + SPI1 memory data buffer14 + 0x90 + 0x20 + + + BUF14 + data buffer + 0 + 32 + read-write + + + + + W15 + SPI1 memory data buffer15 + 0x94 + 0x20 + + + BUF15 + data buffer + 0 + 32 + read-write + + + + + FLASH_WAITI_CTRL + SPI1 wait idle control register + 0x98 + 0x20 + 0x00000014 + + + WAITI_EN + Set this bit to enable auto-waiting flash idle operation when PP/SE/BE/CE/WRSR/PES command is sent. + 0 + 1 + read-write + + + WAITI_DUMMY + Set this bit to enable DUMMY phase in auto wait flash idle transfer(RDSR). + 1 + 1 + read-write + + + WAITI_CMD + The command value of auto wait flash idle transfer(RDSR). + 2 + 8 + read-write + + + WAITI_DUMMY_CYCLELEN + The dummy cycle length when wait flash idle(RDSR). + 10 + 6 + read-write + + + + + FLASH_SUS_CMD + SPI1 flash suspend control register + 0x9C + 0x20 + + + FLASH_PER + program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 0 + 1 + read-write + + + FLASH_PES + program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 1 + 1 + read-write + + + FLASH_PER_WAIT_EN + Set this bit to add delay time after program erase resume(PER) is sent. + 2 + 1 + read-write + + + FLASH_PES_WAIT_EN + Set this bit to add delay time after program erase suspend(PES) command is sent. + 3 + 1 + read-write + + + PES_PER_EN + Set this bit to enable PES transfer trigger PES transfer option. + 4 + 1 + read-write + + + PESR_IDLE_EN + 1: Separate PER flash wait idle and PES flash wait idle. 0: Not separate. + 5 + 1 + read-write + + + + + FLASH_SUS_CTRL + SPI1 flash suspend command register + 0xA0 + 0x20 + 0x0000EAF4 + + + FLASH_PES_EN + Set this bit to enable auto-suspend function. + 0 + 1 + read-write + + + FLASH_PER_COMMAND + Program/Erase resume command value. + 1 + 8 + read-write + + + FLASH_PES_COMMAND + Program/Erase suspend command value. + 9 + 8 + read-write + + + + + SUS_STATUS + SPI1 flash suspend status register + 0xA4 + 0x20 + + + FLASH_SUS + The status of flash suspend. This bit is set when PES command is sent, and cleared when PER is sent. Only used in SPI1. + 0 + 1 + read-write + + + FLASH_HPM_DLY_256 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent. + 2 + 1 + read-write + + + FLASH_RES_DLY_256 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent. + 3 + 1 + read-write + + + FLASH_DP_DLY_256 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent. + 4 + 1 + read-write + + + FLASH_PER_DLY_256 + Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent. + 5 + 1 + read-write + + + FLASH_PES_DLY_256 + Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent. + 6 + 1 + read-write + + + + + TIMING_CALI + SPI1 timing compensation register when accesses to flash or Ext_RAM. + 0xA8 + 0x20 + + + TIMING_CALI + Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations. + 1 + 1 + read-write + + + EXTRA_DUMMY_CYCLELEN + Extra SPI_CLK cycles added in DUMMY phase for timing compensation. Active when SPI_MEM_TIMING_CALI bit is set. + 2 + 3 + read-write + + + + + DDR + SPI1 DDR control register + 0xE0 + 0x20 + 0x00000020 + + + SPI_FMEM_DDR_EN + 1: in DDR mode, 0: in SDR mode. + 0 + 1 + read-write + + + SPI_FMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in DDRmode. + 1 + 1 + read-write + + + SPI_FMEM_DDR_RDAT_SWP + Set the bit to reorder RX data of the word in DDR mode. + 2 + 1 + read-write + + + SPI_FMEM_DDR_WDAT_SWP + Set the bit to reorder TX data of the word in DDR mode. + 3 + 1 + read-write + + + SPI_FMEM_DDR_CMD_DIS + the bit is used to disable dual edge in command phase when DDR mode. + 4 + 1 + read-write + + + SPI_FMEM_OUTMINBYTELEN + It is the minimum output data length in the panda device. + 5 + 7 + read-write + + + SPI_FMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI_CLK. + 14 + 7 + read-write + + + SPI_FMEM_DDR_DQS_LOOP + 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module + 21 + 1 + read-write + + + SPI_FMEM_DDR_DQS_LOOP_MODE + When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active. + 22 + 1 + read-write + + + SPI_FMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-write + + + SPI_FMEM_HYPERBUS_MODE + Set this bit to enable the SPI HyperBus mode. + 25 + 1 + read-write + + + SPI_FMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-write + + + SPI_FMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. + 27 + 1 + read-write + + + SPI_FMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to flash. . + 28 + 1 + read-write + + + SPI_FMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-write + + + SPI_FMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-write + + + + + CLOCK_GATE + SPI1 clk_gate register + 0xE8 + 0x20 + 0x00000001 + + + CLK_EN + Register clock gate enable signal. 1: Enable. 0: Disable. + 0 + 1 + read-write + + + + + INT_ENA + SPI1 interrupt enable register + 0xF0 + 0x20 + + + PER_END_INT_ENA + The enable bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + read-write + + + PES_END_INT_ENA + The enable bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + read-write + + + TOTAL_TRANS_END_INT_ENA + The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + 2 + 1 + read-write + + + BROWN_OUT_INT_ENA + The enable bit for SPI_MEM_BROWN_OUT_INT interrupt. + 3 + 1 + read-write + + + + + INT_CLR + SPI1 interrupt clear register + 0xF4 + 0x20 + + + PER_END_INT_CLR + The clear bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + write-only + + + PES_END_INT_CLR + The clear bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + write-only + + + TOTAL_TRANS_END_INT_CLR + The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + 2 + 1 + write-only + + + BROWN_OUT_INT_CLR + The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + 3 + 1 + write-only + + + + + INT_RAW + SPI1 interrupt raw register + 0xF8 + 0x20 + + + PER_END_INT_RAW + The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others. + 0 + 1 + read-write + + + PES_END_INT_RAW + The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others. + 1 + 1 + read-write + + + TOTAL_TRANS_END_INT_RAW + The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 transfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success. 0: Others. + 2 + 1 + read-write + + + BROWN_OUT_INT_RAW + The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others. + 3 + 1 + read-write + + + + + INT_ST + SPI1 interrupt status register + 0xFC + 0x20 + + + PER_END_INT_ST + The status bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + read-only + + + PES_END_INT_ST + The status bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + read-only + + + TOTAL_TRANS_END_INT_ST + The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + 2 + 1 + read-only + + + BROWN_OUT_INT_ST + The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + 3 + 1 + read-only + + + + + DATE + SPI0 version control register + 0x3FC + 0x20 + 0x02101040 + + + DATE + SPI register version. + 0 + 28 + read-write + + + + + + + SPI2 + SPI (Serial Peripheral Interface) Controller 2 + SPI2 + 0x60024000 + + 0x0 + 0x98 + registers + + + SPI2 + 21 + + + SPI2_DMA + 44 + + + + CMD + Command control register + 0x0 + 0x20 + + + CONF_BITLEN + Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + 0 + 18 + read-write + + + UPDATE + Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode. + 23 + 1 + read-write + + + USR + User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf. + 24 + 1 + read-write + + + + + ADDR + Address value register + 0x4 + 0x20 + + + USR_ADDR_VALUE + Address to slave. Can be configured in CONF state. + 0 + 32 + read-write + + + + + CTRL + SPI control register + 0x8 + 0x20 + 0x003C0000 + + + DUMMY_OUT + 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state. + 3 + 1 + read-write + + + FADDR_DUAL + Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 5 + 1 + read-write + + + FADDR_QUAD + Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + FADDR_OCT + Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 7 + 1 + read-write + + + FCMD_DUAL + Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 8 + 1 + read-write + + + FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 9 + 1 + read-write + + + FCMD_OCT + Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 10 + 1 + read-write + + + FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state. + 14 + 1 + read-write + + + FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state. + 15 + 1 + read-write + + + FREAD_OCT + In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state. + 16 + 1 + read-write + + + Q_POL + The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state. + 18 + 1 + read-write + + + D_POL + The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state. + 19 + 1 + read-write + + + HOLD_POL + SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 20 + 1 + read-write + + + WP_POL + Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 21 + 1 + read-write + + + RD_BIT_ORDER + In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state. + 23 + 2 + read-write + + + WR_BIT_ORDER + In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state. + 25 + 2 + read-write + + + + + CLOCK + SPI clock control register + 0xC + 0x20 + 0x80003043 + + + CLKCNT_L + In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state. + 0 + 6 + read-write + + + CLKCNT_H + In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. + 6 + 6 + read-write + + + CLKCNT_N + In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + 12 + 6 + read-write + + + CLKDIV_PRE + In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + 18 + 4 + read-write + + + CLK_EQU_SYSCLK + In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state. + 31 + 1 + read-write + + + + + USER + SPI USER control register + 0x10 + 0x20 + 0x800000C0 + + + DOUTDIN + Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state. + 0 + 1 + read-write + + + QPI_MODE + Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state. + 3 + 1 + read-write + + + OPI_MODE + Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state. + 4 + 1 + read-write + + + TSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. + 5 + 1 + read-write + + + CS_HOLD + spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + CS_SETUP + spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state. + 7 + 1 + read-write + + + RSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. + 8 + 1 + read-write + + + CK_OUT_EDGE + the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. + 9 + 1 + read-write + + + FWRITE_DUAL + In the write operations read-data phase apply 2 signals. Can be configured in CONF state. + 12 + 1 + read-write + + + FWRITE_QUAD + In the write operations read-data phase apply 4 signals. Can be configured in CONF state. + 13 + 1 + read-write + + + FWRITE_OCT + In the write operations read-data phase apply 8 signals. Can be configured in CONF state. + 14 + 1 + read-write + + + USR_CONF_NXT + 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state. + 15 + 1 + read-write + + + SIO + Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state. + 17 + 1 + read-write + + + USR_MISO_HIGHPART + read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 24 + 1 + read-write + + + USR_MOSI_HIGHPART + write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 25 + 1 + read-write + + + USR_DUMMY_IDLE + spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. + 26 + 1 + read-write + + + USR_MOSI + This bit enable the write-data phase of an operation. Can be configured in CONF state. + 27 + 1 + read-write + + + USR_MISO + This bit enable the read-data phase of an operation. Can be configured in CONF state. + 28 + 1 + read-write + + + USR_DUMMY + This bit enable the dummy phase of an operation. Can be configured in CONF state. + 29 + 1 + read-write + + + USR_ADDR + This bit enable the address phase of an operation. Can be configured in CONF state. + 30 + 1 + read-write + + + USR_COMMAND + This bit enable the command phase of an operation. Can be configured in CONF state. + 31 + 1 + read-write + + + + + USER1 + SPI USER control register 1 + 0x14 + 0x20 + 0xB8410007 + + + USR_DUMMY_CYCLELEN + The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. + 0 + 8 + read-write + + + MST_WFULL_ERR_END_EN + 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. + 16 + 1 + read-write + + + CS_SETUP_TIME + (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state. + 17 + 5 + read-write + + + CS_HOLD_TIME + delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state. + 22 + 5 + read-write + + + USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 27 + 5 + read-write + + + + + USER2 + SPI USER control register 2 + 0x18 + 0x20 + 0x78000000 + + + USR_COMMAND_VALUE + The value of command. Can be configured in CONF state. + 0 + 16 + read-write + + + MST_REMPTY_ERR_END_EN + 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. + 27 + 1 + read-write + + + USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 28 + 4 + read-write + + + + + MS_DLEN + SPI data bit length control register + 0x1C + 0x20 + + + MS_DATA_BITLEN + The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state. + 0 + 18 + read-write + + + + + MISC + SPI misc register + 0x20 + 0x20 + 0x0000003E + + + CS0_DIS + SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state. + 0 + 1 + read-write + + + CS1_DIS + SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state. + 1 + 1 + read-write + + + CS2_DIS + SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state. + 2 + 1 + read-write + + + CS3_DIS + SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state. + 3 + 1 + read-write + + + CS4_DIS + SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state. + 4 + 1 + read-write + + + CS5_DIS + SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state. + 5 + 1 + read-write + + + CK_DIS + 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + 6 + 1 + read-write + + + MASTER_CS_POL + In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + 7 + 6 + read-write + + + CLK_DATA_DTR_EN + 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. + 16 + 1 + read-write + + + DATA_DTR_EN + 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state. + 17 + 1 + read-write + + + ADDR_DTR_EN + 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state. + 18 + 1 + read-write + + + CMD_DTR_EN + 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state. + 19 + 1 + read-write + + + SLAVE_CS_POL + spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state. + 23 + 1 + read-write + + + DQS_IDLE_EDGE + The default value of spi_dqs. Can be configured in CONF state. + 24 + 1 + read-write + + + CK_IDLE_EDGE + 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state. + 29 + 1 + read-write + + + CS_KEEP_ACTIVE + spi cs line keep low when the bit is set. Can be configured in CONF state. + 30 + 1 + read-write + + + QUAD_DIN_PIN_SWAP + 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state. + 31 + 1 + read-write + + + + + DIN_MODE + SPI input delay mode configuration + 0x24 + 0x20 + + + DIN0_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 0 + 2 + read-write + + + DIN1_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 2 + 2 + read-write + + + DIN2_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 4 + 2 + read-write + + + DIN3_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 6 + 2 + read-write + + + DIN4_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 8 + 2 + read-write + + + DIN5_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 10 + 2 + read-write + + + DIN6_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 12 + 2 + read-write + + + DIN7_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 14 + 2 + read-write + + + TIMING_HCLK_ACTIVE + 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state. + 16 + 1 + read-write + + + + + DIN_NUM + SPI input delay number configuration + 0x28 + 0x20 + + + DIN0_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 0 + 2 + read-write + + + DIN1_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 2 + 2 + read-write + + + DIN2_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 4 + 2 + read-write + + + DIN3_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 6 + 2 + read-write + + + DIN4_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 8 + 2 + read-write + + + DIN5_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 10 + 2 + read-write + + + DIN6_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 12 + 2 + read-write + + + DIN7_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 14 + 2 + read-write + + + + + DOUT_MODE + SPI output delay mode configuration + 0x2C + 0x20 + + + DOUT0_MODE + The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 0 + 1 + read-write + + + DOUT1_MODE + The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 1 + 1 + read-write + + + DOUT2_MODE + The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 2 + 1 + read-write + + + DOUT3_MODE + The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 3 + 1 + read-write + + + DOUT4_MODE + The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 4 + 1 + read-write + + + DOUT5_MODE + The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 5 + 1 + read-write + + + DOUT6_MODE + The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 6 + 1 + read-write + + + DOUT7_MODE + The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 7 + 1 + read-write + + + D_DQS_MODE + The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 8 + 1 + read-write + + + + + DMA_CONF + SPI DMA control register + 0x30 + 0x20 + 0x00000003 + + + DMA_OUTFIFO_EMPTY + Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data. + 0 + 1 + read-only + + + DMA_INFIFO_FULL + Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data. + 1 + 1 + read-only + + + DMA_SLV_SEG_TRANS_EN + Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + 18 + 1 + read-write + + + SLV_RX_SEG_TRANS_CLR_EN + 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done. + 19 + 1 + read-write + + + SLV_TX_SEG_TRANS_CLR_EN + 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + 20 + 1 + read-write + + + RX_EOF_EN + 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. + 21 + 1 + read-write + + + DMA_RX_ENA + Set this bit to enable SPI DMA controlled receive data mode. + 27 + 1 + read-write + + + DMA_TX_ENA + Set this bit to enable SPI DMA controlled send data mode. + 28 + 1 + read-write + + + RX_AFIFO_RST + Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer. + 29 + 1 + write-only + + + BUF_AFIFO_RST + Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer. + 30 + 1 + write-only + + + DMA_AFIFO_RST + Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer. + 31 + 1 + write-only + + + + + DMA_INT_ENA + SPI interrupt enable register + 0x34 + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_ENA + The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-write + + + DMA_OUTFIFO_EMPTY_ERR_INT_ENA + The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-write + + + SLV_EX_QPI_INT_ENA + The enable bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-write + + + SLV_EN_QPI_INT_ENA + The enable bit for SPI slave En_QPI interrupt. + 3 + 1 + read-write + + + SLV_CMD7_INT_ENA + The enable bit for SPI slave CMD7 interrupt. + 4 + 1 + read-write + + + SLV_CMD8_INT_ENA + The enable bit for SPI slave CMD8 interrupt. + 5 + 1 + read-write + + + SLV_CMD9_INT_ENA + The enable bit for SPI slave CMD9 interrupt. + 6 + 1 + read-write + + + SLV_CMDA_INT_ENA + The enable bit for SPI slave CMDA interrupt. + 7 + 1 + read-write + + + SLV_RD_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-write + + + SLV_WR_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-write + + + SLV_RD_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-write + + + SLV_WR_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-write + + + TRANS_DONE_INT_ENA + The enable bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-write + + + DMA_SEG_TRANS_DONE_INT_ENA + The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-write + + + SEG_MAGIC_ERR_INT_ENA + The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + read-write + + + SLV_BUF_ADDR_ERR_INT_ENA + The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-write + + + SLV_CMD_ERR_INT_ENA + The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-write + + + MST_RX_AFIFO_WFULL_ERR_INT_ENA + The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-write + + + MST_TX_AFIFO_REMPTY_ERR_INT_ENA + The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-write + + + APP2_INT_ENA + The enable bit for SPI_APP2_INT interrupt. + 19 + 1 + read-write + + + APP1_INT_ENA + The enable bit for SPI_APP1_INT interrupt. + 20 + 1 + read-write + + + + + DMA_INT_CLR + SPI interrupt clear register + 0x38 + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_CLR + The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + write-only + + + DMA_OUTFIFO_EMPTY_ERR_INT_CLR + The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + write-only + + + SLV_EX_QPI_INT_CLR + The clear bit for SPI slave Ex_QPI interrupt. + 2 + 1 + write-only + + + SLV_EN_QPI_INT_CLR + The clear bit for SPI slave En_QPI interrupt. + 3 + 1 + write-only + + + SLV_CMD7_INT_CLR + The clear bit for SPI slave CMD7 interrupt. + 4 + 1 + write-only + + + SLV_CMD8_INT_CLR + The clear bit for SPI slave CMD8 interrupt. + 5 + 1 + write-only + + + SLV_CMD9_INT_CLR + The clear bit for SPI slave CMD9 interrupt. + 6 + 1 + write-only + + + SLV_CMDA_INT_CLR + The clear bit for SPI slave CMDA interrupt. + 7 + 1 + write-only + + + SLV_RD_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + write-only + + + SLV_WR_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + write-only + + + SLV_RD_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + write-only + + + SLV_WR_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + write-only + + + TRANS_DONE_INT_CLR + The clear bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + write-only + + + DMA_SEG_TRANS_DONE_INT_CLR + The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + write-only + + + SEG_MAGIC_ERR_INT_CLR + The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + write-only + + + SLV_BUF_ADDR_ERR_INT_CLR + The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + write-only + + + SLV_CMD_ERR_INT_CLR + The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + write-only + + + MST_RX_AFIFO_WFULL_ERR_INT_CLR + The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + write-only + + + MST_TX_AFIFO_REMPTY_ERR_INT_CLR + The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + write-only + + + APP2_INT_CLR + The clear bit for SPI_APP2_INT interrupt. + 19 + 1 + write-only + + + APP1_INT_CLR + The clear bit for SPI_APP1_INT interrupt. + 20 + 1 + write-only + + + + + DMA_INT_RAW + SPI interrupt raw register + 0x3C + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_RAW + 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. + 0 + 1 + read-write + + + DMA_OUTFIFO_EMPTY_ERR_INT_RAW + 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. + 1 + 1 + read-write + + + SLV_EX_QPI_INT_RAW + The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others. + 2 + 1 + read-write + + + SLV_EN_QPI_INT_RAW + The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others. + 3 + 1 + read-write + + + SLV_CMD7_INT_RAW + The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others. + 4 + 1 + read-write + + + SLV_CMD8_INT_RAW + The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others. + 5 + 1 + read-write + + + SLV_CMD9_INT_RAW + The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others. + 6 + 1 + read-write + + + SLV_CMDA_INT_RAW + The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others. + 7 + 1 + read-write + + + SLV_RD_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others. + 8 + 1 + read-write + + + SLV_WR_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others. + 9 + 1 + read-write + + + SLV_RD_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others. + 10 + 1 + read-write + + + SLV_WR_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others. + 11 + 1 + read-write + + + TRANS_DONE_INT_RAW + The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others. + 12 + 1 + read-write + + + DMA_SEG_TRANS_DONE_INT_RAW + The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. + 13 + 1 + read-write + + + SEG_MAGIC_ERR_INT_RAW + The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others. + 14 + 1 + read-write + + + SLV_BUF_ADDR_ERR_INT_RAW + The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others. + 15 + 1 + read-write + + + SLV_CMD_ERR_INT_RAW + The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others. + 16 + 1 + read-write + + + MST_RX_AFIFO_WFULL_ERR_INT_RAW + The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others. + 17 + 1 + read-write + + + MST_TX_AFIFO_REMPTY_ERR_INT_RAW + The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + 18 + 1 + read-write + + + APP2_INT_RAW + The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + 19 + 1 + read-write + + + APP1_INT_RAW + The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + 20 + 1 + read-write + + + + + DMA_INT_ST + SPI interrupt status register + 0x40 + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_ST + The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-only + + + DMA_OUTFIFO_EMPTY_ERR_INT_ST + The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-only + + + SLV_EX_QPI_INT_ST + The status bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-only + + + SLV_EN_QPI_INT_ST + The status bit for SPI slave En_QPI interrupt. + 3 + 1 + read-only + + + SLV_CMD7_INT_ST + The status bit for SPI slave CMD7 interrupt. + 4 + 1 + read-only + + + SLV_CMD8_INT_ST + The status bit for SPI slave CMD8 interrupt. + 5 + 1 + read-only + + + SLV_CMD9_INT_ST + The status bit for SPI slave CMD9 interrupt. + 6 + 1 + read-only + + + SLV_CMDA_INT_ST + The status bit for SPI slave CMDA interrupt. + 7 + 1 + read-only + + + SLV_RD_DMA_DONE_INT_ST + The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-only + + + SLV_WR_DMA_DONE_INT_ST + The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-only + + + SLV_RD_BUF_DONE_INT_ST + The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-only + + + SLV_WR_BUF_DONE_INT_ST + The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-only + + + TRANS_DONE_INT_ST + The status bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-only + + + DMA_SEG_TRANS_DONE_INT_ST + The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-only + + + SEG_MAGIC_ERR_INT_ST + The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + read-only + + + SLV_BUF_ADDR_ERR_INT_ST + The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-only + + + SLV_CMD_ERR_INT_ST + The status bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-only + + + MST_RX_AFIFO_WFULL_ERR_INT_ST + The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-only + + + MST_TX_AFIFO_REMPTY_ERR_INT_ST + The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-only + + + APP2_INT_ST + The status bit for SPI_APP2_INT interrupt. + 19 + 1 + read-only + + + APP1_INT_ST + The status bit for SPI_APP1_INT interrupt. + 20 + 1 + read-only + + + + + DMA_INT_SET + SPI interrupt software set register + 0x44 + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_SET + The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + write-only + + + DMA_OUTFIFO_EMPTY_ERR_INT_SET + The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + write-only + + + SLV_EX_QPI_INT_SET + The software set bit for SPI slave Ex_QPI interrupt. + 2 + 1 + write-only + + + SLV_EN_QPI_INT_SET + The software set bit for SPI slave En_QPI interrupt. + 3 + 1 + write-only + + + SLV_CMD7_INT_SET + The software set bit for SPI slave CMD7 interrupt. + 4 + 1 + write-only + + + SLV_CMD8_INT_SET + The software set bit for SPI slave CMD8 interrupt. + 5 + 1 + write-only + + + SLV_CMD9_INT_SET + The software set bit for SPI slave CMD9 interrupt. + 6 + 1 + write-only + + + SLV_CMDA_INT_SET + The software set bit for SPI slave CMDA interrupt. + 7 + 1 + write-only + + + SLV_RD_DMA_DONE_INT_SET + The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + write-only + + + SLV_WR_DMA_DONE_INT_SET + The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + write-only + + + SLV_RD_BUF_DONE_INT_SET + The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + write-only + + + SLV_WR_BUF_DONE_INT_SET + The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + write-only + + + TRANS_DONE_INT_SET + The software set bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + write-only + + + DMA_SEG_TRANS_DONE_INT_SET + The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + write-only + + + SEG_MAGIC_ERR_INT_SET + The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + write-only + + + SLV_BUF_ADDR_ERR_INT_SET + The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + write-only + + + SLV_CMD_ERR_INT_SET + The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + write-only + + + MST_RX_AFIFO_WFULL_ERR_INT_SET + The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + write-only + + + MST_TX_AFIFO_REMPTY_ERR_INT_SET + The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + write-only + + + APP2_INT_SET + The software set bit for SPI_APP2_INT interrupt. + 19 + 1 + write-only + + + APP1_INT_SET + The software set bit for SPI_APP1_INT interrupt. + 20 + 1 + write-only + + + + + W0 + SPI CPU-controlled buffer0 + 0x98 + 0x20 + + + BUF0 + data buffer + 0 + 32 + read-write + + + + + W1 + SPI CPU-controlled buffer1 + 0x9C + 0x20 + + + BUF1 + data buffer + 0 + 32 + read-write + + + + + W2 + SPI CPU-controlled buffer2 + 0xA0 + 0x20 + + + BUF2 + data buffer + 0 + 32 + read-write + + + + + W3 + SPI CPU-controlled buffer3 + 0xA4 + 0x20 + + + BUF3 + data buffer + 0 + 32 + read-write + + + + + W4 + SPI CPU-controlled buffer4 + 0xA8 + 0x20 + + + BUF4 + data buffer + 0 + 32 + read-write + + + + + W5 + SPI CPU-controlled buffer5 + 0xAC + 0x20 + + + BUF5 + data buffer + 0 + 32 + read-write + + + + + W6 + SPI CPU-controlled buffer6 + 0xB0 + 0x20 + + + BUF6 + data buffer + 0 + 32 + read-write + + + + + W7 + SPI CPU-controlled buffer7 + 0xB4 + 0x20 + + + BUF7 + data buffer + 0 + 32 + read-write + + + + + W8 + SPI CPU-controlled buffer8 + 0xB8 + 0x20 + + + BUF8 + data buffer + 0 + 32 + read-write + + + + + W9 + SPI CPU-controlled buffer9 + 0xBC + 0x20 + + + BUF9 + data buffer + 0 + 32 + read-write + + + + + W10 + SPI CPU-controlled buffer10 + 0xC0 + 0x20 + + + BUF10 + data buffer + 0 + 32 + read-write + + + + + W11 + SPI CPU-controlled buffer11 + 0xC4 + 0x20 + + + BUF11 + data buffer + 0 + 32 + read-write + + + + + W12 + SPI CPU-controlled buffer12 + 0xC8 + 0x20 + + + BUF12 + data buffer + 0 + 32 + read-write + + + + + W13 + SPI CPU-controlled buffer13 + 0xCC + 0x20 + + + BUF13 + data buffer + 0 + 32 + read-write + + + + + W14 + SPI CPU-controlled buffer14 + 0xD0 + 0x20 + + + BUF14 + data buffer + 0 + 32 + read-write + + + + + W15 + SPI CPU-controlled buffer15 + 0xD4 + 0x20 + + + BUF15 + data buffer + 0 + 32 + read-write + + + + + SLAVE + SPI slave control register + 0xE0 + 0x20 + 0x02800000 + + + CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state. + 0 + 2 + read-write + + + CLK_MODE_13 + {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + 2 + 1 + read-write + + + RSCK_DATA_OUT + It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge + 3 + 1 + read-write + + + SLV_RDDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others + 8 + 1 + read-write + + + SLV_WRDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others + 9 + 1 + read-write + + + SLV_RDBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others + 10 + 1 + read-write + + + SLV_WRBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others + 11 + 1 + read-write + + + DMA_SEG_MAGIC_VALUE + The magic value of BM table in master DMA seg-trans. + 22 + 4 + read-write + + + MODE + Set SPI work mode. 1: slave mode 0: master mode. + 26 + 1 + read-write + + + SOFT_RESET + Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state. + 27 + 1 + write-only + + + USR_CONF + 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode. + 28 + 1 + read-write + + + + + SLAVE1 + SPI slave control register 1 + 0xE4 + 0x20 + + + SLV_DATA_BITLEN + The transferred data bit length in SPI slave FD and HD mode. + 0 + 18 + read-write + + + SLV_LAST_COMMAND + In the slave mode it is the value of command. + 18 + 8 + read-write + + + SLV_LAST_ADDR + In the slave mode it is the value of address. + 26 + 6 + read-write + + + + + CLK_GATE + SPI module clock and register clock control + 0xE8 + 0x20 + + + CLK_EN + Set this bit to enable clk gate + 0 + 1 + read-write + + + MST_CLK_ACTIVE + Set this bit to power on the SPI module clock. + 1 + 1 + read-write + + + MST_CLK_SEL + This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK. + 2 + 1 + read-write + + + + + DATE + Version control + 0xF0 + 0x20 + 0x02101190 + + + DATE + SPI register version. + 0 + 28 + read-write + + + + + + + SPI3 + SPI (Serial Peripheral Interface) Controller 3 + 0x60025000 + + SPI3 + 22 + + + SPI3_DMA + 45 + + + + SYSTEM + System Configuration Registers + SYSTEM + 0x600C0000 + + 0x0 + 0xA8 + registers + + + + CORE_1_CONTROL_0 + Core0 control regiter 0 + 0x0 + 0x20 + 0x00000004 + + + CONTROL_CORE_1_RUNSTALL + Set 1 to stall core1 + 0 + 1 + read-write + + + CONTROL_CORE_1_CLKGATE_EN + Set 1 to open core1 clock + 1 + 1 + read-write + + + CONTROL_CORE_1_RESETING + Set 1 to let core1 reset + 2 + 1 + read-write + + + + + CORE_1_CONTROL_1 + Core0 control regiter 1 + 0x4 + 0x20 + + + CONTROL_CORE_1_MESSAGE + it's only a R/W register, no function, software can write any value + 0 + 32 + read-write + + + + + CPU_PERI_CLK_EN + cpu_peripheral clock configuration register + 0x8 + 0x20 + + + CLK_EN_ASSIST_DEBUG + Set 1 to open assist_debug module clock + 6 + 1 + read-write + + + CLK_EN_DEDICATED_GPIO + Set 1 to open dedicated_gpio module clk + 7 + 1 + read-write + + + + + CPU_PERI_RST_EN + cpu_peripheral reset configuration regsiter + 0xC + 0x20 + 0x000000C0 + + + RST_EN_ASSIST_DEBUG + Set 1 to let assist_debug module reset + 6 + 1 + read-write + + + RST_EN_DEDICATED_GPIO + Set 1 to let dedicated_gpio module reset + 7 + 1 + read-write + + + + + CPU_PER_CONF + cpu peripheral clock configuration register + 0x10 + 0x20 + 0x0000000C + + + CPUPERIOD_SEL + This field used to sel cpu clock frequent. + 0 + 2 + read-write + + + PLL_FREQ_SEL + This field used to sel pll frequent. + 2 + 1 + read-write + + + CPU_WAIT_MODE_FORCE_ON + Set 1 to force cpu_waiti_clk enable. + 3 + 1 + read-write + + + CPU_WAITI_DELAY_NUM + This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close + 4 + 4 + read-write + + + + + MEM_PD_MASK + memory power down mask configuration register + 0x14 + 0x20 + 0x00000001 + + + LSLP_MEM_PD_MASK + Set 1 to mask memory power down. + 0 + 1 + read-write + + + + + PERIP_CLK_EN0 + peripheral clock configuration regsiter 0 + 0x18 + 0x20 + 0xF9C1E06F + + + TIMERS_CLK_EN + Set 1 to enable TIMERS clock + 0 + 1 + read-write + + + SPI01_CLK_EN + Set 1 to enable SPI01 clock + 1 + 1 + read-write + + + UART_CLK_EN + Set 1 to enable UART clock + 2 + 1 + read-write + + + WDG_CLK_EN + Set 1 to enable WDG clock + 3 + 1 + read-write + + + I2S0_CLK_EN + Set 1 to enable I2S0 clock + 4 + 1 + read-write + + + UART1_CLK_EN + Set 1 to enable UART1 clock + 5 + 1 + read-write + + + SPI2_CLK_EN + Set 1 to enable SPI2 clock + 6 + 1 + read-write + + + I2C_EXT0_CLK_EN + Set 1 to enable I2C_EXT0 clock + 7 + 1 + read-write + + + UHCI0_CLK_EN + Set 1 to enable UHCI0 clock + 8 + 1 + read-write + + + RMT_CLK_EN + Set 1 to enable RMT clock + 9 + 1 + read-write + + + PCNT_CLK_EN + Set 1 to enable PCNT clock + 10 + 1 + read-write + + + LEDC_CLK_EN + Set 1 to enable LEDC clock + 11 + 1 + read-write + + + UHCI1_CLK_EN + Set 1 to enable UHCI1 clock + 12 + 1 + read-write + + + TIMERGROUP_CLK_EN + Set 1 to enable TIMERGROUP clock + 13 + 1 + read-write + + + EFUSE_CLK_EN + Set 1 to enable EFUSE clock + 14 + 1 + read-write + + + TIMERGROUP1_CLK_EN + Set 1 to enable TIMERGROUP1 clock + 15 + 1 + read-write + + + SPI3_CLK_EN + Set 1 to enable SPI3 clock + 16 + 1 + read-write + + + PWM0_CLK_EN + Set 1 to enable PWM0 clock + 17 + 1 + read-write + + + I2C_EXT1_CLK_EN + Set 1 to enable I2C_EXT1 clock + 18 + 1 + read-write + + + TWAI_CLK_EN + Set 1 to enable CAN clock + 19 + 1 + read-write + + + PWM1_CLK_EN + Set 1 to enable PWM1 clock + 20 + 1 + read-write + + + I2S1_CLK_EN + Set 1 to enable I2S1 clock + 21 + 1 + read-write + + + SPI2_DMA_CLK_EN + Set 1 to enable SPI2_DMA clock + 22 + 1 + read-write + + + USB_CLK_EN + Set 1 to enable USB clock + 23 + 1 + read-write + + + UART_MEM_CLK_EN + Set 1 to enable UART_MEM clock + 24 + 1 + read-write + + + PWM2_CLK_EN + Set 1 to enable PWM2 clock + 25 + 1 + read-write + + + PWM3_CLK_EN + Set 1 to enable PWM3 clock + 26 + 1 + read-write + + + SPI3_DMA_CLK_EN + Set 1 to enable SPI4 clock + 27 + 1 + read-write + + + APB_SARADC_CLK_EN + Set 1 to enable APB_SARADC clock + 28 + 1 + read-write + + + SYSTIMER_CLK_EN + Set 1 to enable SYSTEMTIMER clock + 29 + 1 + read-write + + + ADC2_ARB_CLK_EN + Set 1 to enable ADC2_ARB clock + 30 + 1 + read-write + + + SPI4_CLK_EN + Set 1 to enable SPI4 clock + 31 + 1 + read-write + + + + + PERIP_CLK_EN1 + peripheral clock configuration regsiter 1 + 0x1C + 0x20 + 0x00000600 + + + PERI_BACKUP_CLK_EN + Set 1 to enable BACKUP clock + 0 + 1 + read-write + + + CRYPTO_AES_CLK_EN + Set 1 to enable AES clock + 1 + 1 + read-write + + + CRYPTO_SHA_CLK_EN + Set 1 to enable SHA clock + 2 + 1 + read-write + + + CRYPTO_RSA_CLK_EN + Set 1 to enable RSA clock + 3 + 1 + read-write + + + CRYPTO_DS_CLK_EN + Set 1 to enable DS clock + 4 + 1 + read-write + + + CRYPTO_HMAC_CLK_EN + Set 1 to enable HMAC clock + 5 + 1 + read-write + + + DMA_CLK_EN + Set 1 to enable DMA clock + 6 + 1 + read-write + + + SDIO_HOST_CLK_EN + Set 1 to enable SDIO_HOST clock + 7 + 1 + read-write + + + LCD_CAM_CLK_EN + Set 1 to enable LCD_CAM clock + 8 + 1 + read-write + + + UART2_CLK_EN + Set 1 to enable UART2 clock + 9 + 1 + read-write + + + USB_DEVICE_CLK_EN + Set 1 to enable USB_DEVICE clock + 10 + 1 + read-write + + + + + PERIP_RST_EN0 + peripheral reset configuration register0 + 0x20 + 0x20 + + + TIMERS_RST + Set 1 to let TIMERS reset + 0 + 1 + read-write + + + SPI01_RST + Set 1 to let SPI01 reset + 1 + 1 + read-write + + + UART_RST + Set 1 to let UART reset + 2 + 1 + read-write + + + WDG_RST + Set 1 to let WDG reset + 3 + 1 + read-write + + + I2S0_RST + Set 1 to let I2S0 reset + 4 + 1 + read-write + + + UART1_RST + Set 1 to let UART1 reset + 5 + 1 + read-write + + + SPI2_RST + Set 1 to let SPI2 reset + 6 + 1 + read-write + + + I2C_EXT0_RST + Set 1 to let I2C_EXT0 reset + 7 + 1 + read-write + + + UHCI0_RST + Set 1 to let UHCI0 reset + 8 + 1 + read-write + + + RMT_RST + Set 1 to let RMT reset + 9 + 1 + read-write + + + PCNT_RST + Set 1 to let PCNT reset + 10 + 1 + read-write + + + LEDC_RST + Set 1 to let LEDC reset + 11 + 1 + read-write + + + UHCI1_RST + Set 1 to let UHCI1 reset + 12 + 1 + read-write + + + TIMERGROUP_RST + Set 1 to let TIMERGROUP reset + 13 + 1 + read-write + + + EFUSE_RST + Set 1 to let EFUSE reset + 14 + 1 + read-write + + + TIMERGROUP1_RST + Set 1 to let TIMERGROUP1 reset + 15 + 1 + read-write + + + SPI3_RST + Set 1 to let SPI3 reset + 16 + 1 + read-write + + + PWM0_RST + Set 1 to let PWM0 reset + 17 + 1 + read-write + + + I2C_EXT1_RST + Set 1 to let I2C_EXT1 reset + 18 + 1 + read-write + + + TWAI_RST + Set 1 to let CAN reset + 19 + 1 + read-write + + + PWM1_RST + Set 1 to let PWM1 reset + 20 + 1 + read-write + + + I2S1_RST + Set 1 to let I2S1 reset + 21 + 1 + read-write + + + SPI2_DMA_RST + Set 1 to let SPI2 reset + 22 + 1 + read-write + + + USB_RST + Set 1 to let USB reset + 23 + 1 + read-write + + + UART_MEM_RST + Set 1 to let UART_MEM reset + 24 + 1 + read-write + + + PWM2_RST + Set 1 to let PWM2 reset + 25 + 1 + read-write + + + PWM3_RST + Set 1 to let PWM3 reset + 26 + 1 + read-write + + + SPI3_DMA_RST + Set 1 to let SPI3 reset + 27 + 1 + read-write + + + APB_SARADC_RST + Set 1 to let APB_SARADC reset + 28 + 1 + read-write + + + SYSTIMER_RST + Set 1 to let SYSTIMER reset + 29 + 1 + read-write + + + ADC2_ARB_RST + Set 1 to let ADC2_ARB reset + 30 + 1 + read-write + + + SPI4_RST + Set 1 to let SPI4 reset + 31 + 1 + read-write + + + + + PERIP_RST_EN1 + peripheral reset configuration regsiter 1 + 0x24 + 0x20 + 0x000001FE + + + PERI_BACKUP_RST + Set 1 to let BACKUP reset + 0 + 1 + read-write + + + CRYPTO_AES_RST + Set 1 to let CRYPTO_AES reset + 1 + 1 + read-write + + + CRYPTO_SHA_RST + Set 1 to let CRYPTO_SHA reset + 2 + 1 + read-write + + + CRYPTO_RSA_RST + Set 1 to let CRYPTO_RSA reset + 3 + 1 + read-write + + + CRYPTO_DS_RST + Set 1 to let CRYPTO_DS reset + 4 + 1 + read-write + + + CRYPTO_HMAC_RST + Set 1 to let CRYPTO_HMAC reset + 5 + 1 + read-write + + + DMA_RST + Set 1 to let DMA reset + 6 + 1 + read-write + + + SDIO_HOST_RST + Set 1 to let SDIO_HOST reset + 7 + 1 + read-write + + + LCD_CAM_RST + Set 1 to let LCD_CAM reset + 8 + 1 + read-write + + + UART2_RST + Set 1 to let UART2 reset + 9 + 1 + read-write + + + USB_DEVICE_RST + Set 1 to let USB_DEVICE reset + 10 + 1 + read-write + + + + + BT_LPCK_DIV_INT + low power clock frequent division factor configuration regsiter + 0x28 + 0x20 + 0x000000FF + + + BT_LPCK_DIV_NUM + This field is lower power clock frequent division factor + 0 + 12 + read-write + + + + + BT_LPCK_DIV_FRAC + low power clock configuration register + 0x2C + 0x20 + 0x02001001 + + + BT_LPCK_DIV_B + This field is lower power clock frequent division factor b + 0 + 12 + read-write + + + BT_LPCK_DIV_A + This field is lower power clock frequent division factor a + 12 + 12 + read-write + + + LPCLK_SEL_RTC_SLOW + Set 1 to select rtc-slow clock as rtc low power clock + 24 + 1 + read-write + + + LPCLK_SEL_8M + Set 1 to select 8m clock as rtc low power clock + 25 + 1 + read-write + + + LPCLK_SEL_XTAL + Set 1 to select xtal clock as rtc low power clock + 26 + 1 + read-write + + + LPCLK_SEL_XTAL32K + Set 1 to select xtal32k clock as low power clock + 27 + 1 + read-write + + + LPCLK_RTC_EN + Set 1 to enable RTC low power clock + 28 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_0 + interrupt source register 0 + 0x30 + 0x20 + + + CPU_INTR_FROM_CPU_0 + Set 1 to generate cpu interrupt 0 + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_1 + interrupt source register 1 + 0x34 + 0x20 + + + CPU_INTR_FROM_CPU_1 + Set 1 to generate cpu interrupt 1 + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_2 + interrupt source register 2 + 0x38 + 0x20 + + + CPU_INTR_FROM_CPU_2 + Set 1 to generate cpu interrupt 2 + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_3 + interrupt source register 3 + 0x3C + 0x20 + + + CPU_INTR_FROM_CPU_3 + Set 1 to generate cpu interrupt 3 + 0 + 1 + read-write + + + + + RSA_PD_CTRL + rsa memory power control register + 0x40 + 0x20 + 0x00000001 + + + RSA_MEM_PD + Set 1 to power down RSA memory. This bit has the lowest priority.When Digital Signature occupies the RSA, this bit is invalid. + 0 + 1 + read-write + + + RSA_MEM_FORCE_PU + Set 1 to force power up RSA memory, this bit has the second highest priority. + 1 + 1 + read-write + + + RSA_MEM_FORCE_PD + Set 1 to force power down RSA memory,this bit has the highest priority. + 2 + 1 + read-write + + + + + EDMA_CTRL + EDMA control register + 0x44 + 0x20 + 0x00000001 + + + EDMA_CLK_ON + Set 1 to enable EDMA clock. + 0 + 1 + read-write + + + EDMA_RESET + Set 1 to let EDMA reset + 1 + 1 + read-write + + + + + CACHE_CONTROL + Cache control register + 0x48 + 0x20 + 0x00000005 + + + ICACHE_CLK_ON + Set 1 to enable icache clock + 0 + 1 + read-write + + + ICACHE_RESET + Set 1 to let icache reset + 1 + 1 + read-write + + + DCACHE_CLK_ON + Set 1 to enable dcache clock + 2 + 1 + read-write + + + DCACHE_RESET + Set 1 to let dcache reset + 3 + 1 + read-write + + + + + EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL + External memory encrypt and decrypt control register + 0x4C + 0x20 + + + ENABLE_SPI_MANUAL_ENCRYPT + Set 1 to enable the SPI manual encrypt. + 0 + 1 + read-write + + + ENABLE_DOWNLOAD_DB_ENCRYPT + Set 1 to enable download DB encrypt. + 1 + 1 + read-write + + + ENABLE_DOWNLOAD_G0CB_DECRYPT + Set 1 to enable download G0CB decrypt + 2 + 1 + read-write + + + ENABLE_DOWNLOAD_MANUAL_ENCRYPT + Set 1 to enable download manual encrypt + 3 + 1 + read-write + + + + + RTC_FASTMEM_CONFIG + RTC fast memory configuration register + 0x50 + 0x20 + 0x7FF00000 + + + RTC_MEM_CRC_START + Set 1 to start the CRC of RTC memory + 8 + 1 + read-write + + + RTC_MEM_CRC_ADDR + This field is used to set address of RTC memory for CRC. + 9 + 11 + read-write + + + RTC_MEM_CRC_LEN + This field is used to set length of RTC memory for CRC based on start address. + 20 + 11 + read-write + + + RTC_MEM_CRC_FINISH + This bit stores the status of RTC memory CRC.1 means finished. + 31 + 1 + read-only + + + + + RTC_FASTMEM_CRC + RTC fast memory CRC control register + 0x54 + 0x20 + + + RTC_MEM_CRC_RES + This field stores the CRC result of RTC memory. + 0 + 32 + read-only + + + + + REDUNDANT_ECO_CTRL + ******* Description *********** + 0x58 + 0x20 + + + REDUNDANT_ECO_DRIVE + ******* Description *********** + 0 + 1 + read-write + + + REDUNDANT_ECO_RESULT + ******* Description *********** + 1 + 1 + read-only + + + + + CLOCK_GATE + ******* Description *********** + 0x5C + 0x20 + 0x00000001 + + + CLK_EN + ******* Description *********** + 0 + 1 + read-write + + + + + SYSCLK_CONF + System clock configuration register. + 0x60 + 0x20 + 0x00000001 + + + PRE_DIV_CNT + This field is used to set the count of prescaler of XTAL_CLK. + 0 + 10 + read-write + + + SOC_CLK_SEL + This field is used to select soc clock. + 10 + 2 + read-write + + + CLK_XTAL_FREQ + This field is used to read xtal frequency in MHz. + 12 + 7 + read-only + + + CLK_DIV_EN + Reserved. + 19 + 1 + read-only + + + + + MEM_PVT + ******* Description *********** + 0x64 + 0x20 + 0x00000003 + + + MEM_PATH_LEN + ******* Description *********** + 0 + 4 + read-write + + + MEM_ERR_CNT_CLR + ******* Description *********** + 4 + 1 + write-only + + + MONITOR_EN + ******* Description *********** + 5 + 1 + read-write + + + MEM_TIMING_ERR_CNT + ******* Description *********** + 6 + 16 + read-only + + + MEM_VT_SEL + ******* Description *********** + 22 + 2 + read-write + + + + + COMB_PVT_LVT_CONF + ******* Description *********** + 0x68 + 0x20 + 0x00000003 + + + COMB_PATH_LEN_LVT + ******* Description *********** + 0 + 5 + read-write + + + COMB_ERR_CNT_CLR_LVT + ******* Description *********** + 5 + 1 + write-only + + + COMB_PVT_MONITOR_EN_LVT + ******* Description *********** + 6 + 1 + read-write + + + + + COMB_PVT_NVT_CONF + ******* Description *********** + 0x6C + 0x20 + 0x00000003 + + + COMB_PATH_LEN_NVT + ******* Description *********** + 0 + 5 + read-write + + + COMB_ERR_CNT_CLR_NVT + ******* Description *********** + 5 + 1 + write-only + + + COMB_PVT_MONITOR_EN_NVT + ******* Description *********** + 6 + 1 + read-write + + + + + COMB_PVT_HVT_CONF + ******* Description *********** + 0x70 + 0x20 + 0x00000003 + + + COMB_PATH_LEN_HVT + ******* Description *********** + 0 + 5 + read-write + + + COMB_ERR_CNT_CLR_HVT + ******* Description *********** + 5 + 1 + write-only + + + COMB_PVT_MONITOR_EN_HVT + ******* Description *********** + 6 + 1 + read-write + + + + + COMB_PVT_ERR_LVT_SITE0 + ******* Description *********** + 0x74 + 0x20 + + + COMB_TIMING_ERR_CNT_LVT_SITE0 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_NVT_SITE0 + ******* Description *********** + 0x78 + 0x20 + + + COMB_TIMING_ERR_CNT_NVT_SITE0 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_HVT_SITE0 + ******* Description *********** + 0x7C + 0x20 + + + COMB_TIMING_ERR_CNT_HVT_SITE0 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_LVT_SITE1 + ******* Description *********** + 0x80 + 0x20 + + + COMB_TIMING_ERR_CNT_LVT_SITE1 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_NVT_SITE1 + ******* Description *********** + 0x84 + 0x20 + + + COMB_TIMING_ERR_CNT_NVT_SITE1 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_HVT_SITE1 + ******* Description *********** + 0x88 + 0x20 + + + COMB_TIMING_ERR_CNT_HVT_SITE1 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_LVT_SITE2 + ******* Description *********** + 0x8C + 0x20 + + + COMB_TIMING_ERR_CNT_LVT_SITE2 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_NVT_SITE2 + ******* Description *********** + 0x90 + 0x20 + + + COMB_TIMING_ERR_CNT_NVT_SITE2 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_HVT_SITE2 + ******* Description *********** + 0x94 + 0x20 + + + COMB_TIMING_ERR_CNT_HVT_SITE2 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_LVT_SITE3 + ******* Description *********** + 0x98 + 0x20 + + + COMB_TIMING_ERR_CNT_LVT_SITE3 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_NVT_SITE3 + ******* Description *********** + 0x9C + 0x20 + + + COMB_TIMING_ERR_CNT_NVT_SITE3 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_HVT_SITE3 + ******* Description *********** + 0xA0 + 0x20 + + + COMB_TIMING_ERR_CNT_HVT_SITE3 + ******* Description *********** + 0 + 16 + read-only + + + + + DATE + version register + 0xFFC + 0x20 + 0x02101220 + + + DATE + version register + 0 + 28 + read-write + + + + + + + SYSTIMER + System Timer + SYSTIMER + 0x60023000 + + 0x0 + 0x90 + registers + + + SYSTIMER_TARGET0 + 57 + + + SYSTIMER_TARGET1 + 58 + + + SYSTIMER_TARGET2 + 59 + + + + CONF + Configure system timer clock + 0x0 + 0x20 + 0x46000000 + + + SYSTIMER_CLK_FO + systimer clock force on + 0 + 1 + read-write + + + TARGET2_WORK_EN + target2 work enable + 22 + 1 + read-write + + + TARGET1_WORK_EN + target1 work enable + 23 + 1 + read-write + + + TARGET0_WORK_EN + target0 work enable + 24 + 1 + read-write + + + TIMER_UNIT1_CORE1_STALL_EN + If timer unit1 is stalled when core1 stalled + 25 + 1 + read-write + + + TIMER_UNIT1_CORE0_STALL_EN + If timer unit1 is stalled when core0 stalled + 26 + 1 + read-write + + + TIMER_UNIT0_CORE1_STALL_EN + If timer unit0 is stalled when core1 stalled + 27 + 1 + read-write + + + TIMER_UNIT0_CORE0_STALL_EN + If timer unit0 is stalled when core0 stalled + 28 + 1 + read-write + + + TIMER_UNIT1_WORK_EN + timer unit1 work enable + 29 + 1 + read-write + + + TIMER_UNIT0_WORK_EN + timer unit0 work enable + 30 + 1 + read-write + + + CLK_EN + register file clk gating + 31 + 1 + read-write + + + + + UNIT0_OP + system timer unit0 value update register + 0x4 + 0x20 + + + TIMER_UNIT0_VALUE_VALID + timer value is sync and valid + 29 + 1 + read-only + + + TIMER_UNIT0_UPDATE + update timer_unit0 + 30 + 1 + write-only + + + + + UNIT1_OP + system timer unit1 value update register + 0x8 + 0x20 + + + TIMER_UNIT1_VALUE_VALID + timer value is sync and valid + 29 + 1 + read-only + + + TIMER_UNIT1_UPDATE + update timer unit1 + 30 + 1 + write-only + + + + + UNIT0_LOAD_HI + system timer unit0 value high load register + 0xC + 0x20 + + + TIMER_UNIT0_LOAD_HI + timer unit0 load high 20 bits + 0 + 20 + read-write + + + + + UNIT0_LOAD_LO + system timer unit0 value low load register + 0x10 + 0x20 + + + TIMER_UNIT0_LOAD_LO + timer unit0 load low 32 bits + 0 + 32 + read-write + + + + + UNIT1_LOAD_HI + system timer unit1 value high load register + 0x14 + 0x20 + + + TIMER_UNIT1_LOAD_HI + timer unit1 load high 20 bits + 0 + 20 + read-write + + + + + UNIT1_LOAD_LO + system timer unit1 value low load register + 0x18 + 0x20 + + + TIMER_UNIT1_LOAD_LO + timer unit1 load low 32 bits + 0 + 32 + read-write + + + + + TARGET0_HI + system timer comp0 value high register + 0x1C + 0x20 + + + TIMER_TARGET0_HI + timer taget0 high 20 bits + 0 + 20 + read-write + + + + + TARGET0_LO + system timer comp0 value low register + 0x20 + 0x20 + + + TIMER_TARGET0_LO + timer taget0 low 32 bits + 0 + 32 + read-write + + + + + TARGET1_HI + system timer comp1 value high register + 0x24 + 0x20 + + + TIMER_TARGET1_HI + timer taget1 high 20 bits + 0 + 20 + read-write + + + + + TARGET1_LO + system timer comp1 value low register + 0x28 + 0x20 + + + TIMER_TARGET1_LO + timer taget1 low 32 bits + 0 + 32 + read-write + + + + + TARGET2_HI + system timer comp2 value high register + 0x2C + 0x20 + + + TIMER_TARGET2_HI + timer taget2 high 20 bits + 0 + 20 + read-write + + + + + TARGET2_LO + system timer comp2 value low register + 0x30 + 0x20 + + + TIMER_TARGET2_LO + timer taget2 low 32 bits + 0 + 32 + read-write + + + + + TARGET0_CONF + system timer comp0 target mode register + 0x34 + 0x20 + + + TARGET0_PERIOD + target0 period + 0 + 26 + read-write + + + TARGET0_PERIOD_MODE + Set target0 to period mode + 30 + 1 + read-write + + + TARGET0_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + TARGET1_CONF + system timer comp1 target mode register + 0x38 + 0x20 + + + TARGET1_PERIOD + target1 period + 0 + 26 + read-write + + + TARGET1_PERIOD_MODE + Set target1 to period mode + 30 + 1 + read-write + + + TARGET1_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + TARGET2_CONF + system timer comp2 target mode register + 0x3C + 0x20 + + + TARGET2_PERIOD + target2 period + 0 + 26 + read-write + + + TARGET2_PERIOD_MODE + Set target2 to period mode + 30 + 1 + read-write + + + TARGET2_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + UNIT0_VALUE_HI + system timer unit0 value high register + 0x40 + 0x20 + + + TIMER_UNIT0_VALUE_HI + timer read value high 20bits + 0 + 20 + read-only + + + + + UNIT0_VALUE_LO + system timer unit0 value low register + 0x44 + 0x20 + + + TIMER_UNIT0_VALUE_LO + timer read value low 32bits + 0 + 32 + read-only + + + + + UNIT1_VALUE_HI + system timer unit1 value high register + 0x48 + 0x20 + + + TIMER_UNIT1_VALUE_HI + timer read value high 20bits + 0 + 20 + read-only + + + + + UNIT1_VALUE_LO + system timer unit1 value low register + 0x4C + 0x20 + + + TIMER_UNIT1_VALUE_LO + timer read value low 32bits + 0 + 32 + read-only + + + + + COMP0_LOAD + system timer comp0 conf sync register + 0x50 + 0x20 + + + TIMER_COMP0_LOAD + timer comp0 sync enable signal + 0 + 1 + write-only + + + + + COMP1_LOAD + system timer comp1 conf sync register + 0x54 + 0x20 + + + TIMER_COMP1_LOAD + timer comp1 sync enable signal + 0 + 1 + write-only + + + + + COMP2_LOAD + system timer comp2 conf sync register + 0x58 + 0x20 + + + TIMER_COMP2_LOAD + timer comp2 sync enable signal + 0 + 1 + write-only + + + + + UNIT0_LOAD + system timer unit0 conf sync register + 0x5C + 0x20 + + + TIMER_UNIT0_LOAD + timer unit0 sync enable signal + 0 + 1 + write-only + + + + + UNIT1_LOAD + system timer unit1 conf sync register + 0x60 + 0x20 + + + TIMER_UNIT1_LOAD + timer unit1 sync enable signal + 0 + 1 + write-only + + + + + INT_ENA + systimer interrupt enable register + 0x64 + 0x20 + + + TARGET0_INT_ENA + interupt0 enable + 0 + 1 + read-write + + + TARGET1_INT_ENA + interupt1 enable + 1 + 1 + read-write + + + TARGET2_INT_ENA + interupt2 enable + 2 + 1 + read-write + + + + + INT_RAW + systimer interrupt raw register + 0x68 + 0x20 + + + TARGET0_INT_RAW + interupt0 raw + 0 + 1 + read-write + + + TARGET1_INT_RAW + interupt1 raw + 1 + 1 + read-write + + + TARGET2_INT_RAW + interupt2 raw + 2 + 1 + read-write + + + + + INT_CLR + systimer interrupt clear register + 0x6C + 0x20 + + + TARGET0_INT_CLR + interupt0 clear + 0 + 1 + write-only + + + TARGET1_INT_CLR + interupt1 clear + 1 + 1 + write-only + + + TARGET2_INT_CLR + interupt2 clear + 2 + 1 + write-only + + + + + INT_ST + systimer interrupt status register + 0x70 + 0x20 + + + TARGET0_INT_ST + interupt0 status + 0 + 1 + read-only + + + TARGET1_INT_ST + interupt1 status + 1 + 1 + read-only + + + TARGET2_INT_ST + interupt2 status + 2 + 1 + read-only + + + + + REAL_TARGET0_LO + system timer comp0 actual target value low register + 0x74 + 0x20 + + + TARGET0_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET0_HI + system timer comp0 actual target value high register + 0x78 + 0x20 + + + TARGET0_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + REAL_TARGET1_LO + system timer comp1 actual target value low register + 0x7C + 0x20 + + + TARGET1_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET1_HI + system timer comp1 actual target value high register + 0x80 + 0x20 + + + TARGET1_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + REAL_TARGET2_LO + system timer comp2 actual target value low register + 0x84 + 0x20 + + + TARGET2_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET2_HI + system timer comp2 actual target value high register + 0x88 + 0x20 + + + TARGET2_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + DATE + system timer version control register + 0xFC + 0x20 + 0x02012251 + + + DATE + systimer register version + 0 + 32 + read-write + + + + + + + TIMG0 + Timer Group 0 + TIMG + 0x6001F000 + + 0x0 + 0x8C + registers + + + TG0_T0_LEVEL + 50 + + + TG0_T1_LEVEL + 51 + + + TG0_WDT_LEVEL + 52 + + + + 2 + 0x24 + T%sCONFIG + Timer %s configuration register + 0x0 + 0x20 + 0x60002000 + + + USE_XTAL + 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group. + 9 + 1 + read-write + + + ALARM_EN + When set, the alarm is enabled. This bit is automatically cleared once an +alarm occurs. + 10 + 1 + read-write + + + DIVIDER + Timer %s clock (T%s_clk) prescaler value. + 13 + 16 + read-write + + + AUTORELOAD + When set, timer %s auto-reload at alarm is enabled. + 29 + 1 + read-write + + + INCREASE + When set, the timer %s time-base counter will increment every clock tick. When +cleared, the timer %s time-base counter will decrement. + 30 + 1 + read-write + + + EN + When set, the timer %s time-base counter is enabled. + 31 + 1 + read-write + + + + + 2 + 0x24 + T%sLO + Timer %s current value, low 32 bits + 0x4 + 0x20 + + + LO + After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter +of timer %s can be read here. + 0 + 32 + read-only + + + + + 2 + 0x24 + T%sHI + Timer %s current value, high 22 bits + 0x8 + 0x20 + + + HI + After writing to TIMG_T%sUPDATE_REG, the high 22 bits of the time-base counter +of timer %s can be read here. + 0 + 22 + read-only + + + + + 2 + 0x24 + T%sUPDATE + Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG + 0xC + 0x20 + + + UPDATE + After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched. + 31 + 1 + read-write + + + + + 2 + 0x24 + T%sALARMLO + Timer %s alarm value, low 32 bits + 0x10 + 0x20 + + + ALARM_LO + Timer %s alarm trigger time-base counter value, low 32 bits. + 0 + 32 + read-write + + + + + 2 + 0x24 + T%sALARMHI + Timer %s alarm value, high bits + 0x14 + 0x20 + + + ALARM_HI + Timer %s alarm trigger time-base counter value, high 22 bits. + 0 + 22 + read-write + + + + + 2 + 0x24 + T%sLOADLO + Timer %s reload value, low 32 bits + 0x18 + 0x20 + + + LOAD_LO + Low 32 bits of the value that a reload will load onto timer %s time-base +Counter. + 0 + 32 + read-write + + + + + 2 + 0x24 + T%sLOADHI + Timer %s reload value, high 22 bits + 0x1C + 0x20 + + + LOAD_HI + High 22 bits of the value that a reload will load onto timer %s time-base +counter. + 0 + 22 + read-write + + + + + 2 + 0x24 + T%sLOAD + Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG + 0x20 + 0x20 + + + LOAD + +Write any value to trigger a timer %s time-base counter reload. + 0 + 32 + write-only + + + + + WDTCONFIG0 + Watchdog timer configuration register + 0x48 + 0x20 + 0x0004C000 + + + WDT_APPCPU_RESET_EN + Reserved + 12 + 1 + read-write + + + WDT_PROCPU_RESET_EN + WDT reset CPU enable. + 13 + 1 + read-write + + + WDT_FLASHBOOT_MOD_EN + When set, Flash boot protection is enabled. + 14 + 1 + read-write + + + WDT_SYS_RESET_LENGTH + System reset signal length selection. 0: 100 ns, 1: 200 ns, +2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + 15 + 3 + read-write + + + WDT_CPU_RESET_LENGTH + CPU reset signal length selection. 0: 100 ns, 1: 200 ns, +2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + 18 + 3 + read-write + + + WDT_STG3 + Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + + 23 + 2 + read-write + + + WDT_STG2 + Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + + 25 + 2 + read-write + + + WDT_STG1 + Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + + 27 + 2 + read-write + + + WDT_STG0 + Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + + 29 + 2 + read-write + + + WDT_EN + When set, MWDT is enabled. + 31 + 1 + read-write + + + + + WDTCONFIG1 + Watchdog timer prescaler register + 0x4C + 0x20 + 0x00010000 + + + WDT_CLK_PRESCALE + MWDT clock prescaler value. MWDT clock period = 12.5 ns * +TIMG_WDT_CLK_PRESCALE. + 16 + 16 + read-write + + + + + WDTCONFIG2 + Watchdog timer stage 0 timeout value + 0x50 + 0x20 + 0x018CBA80 + + + WDT_STG0_HOLD + Stage 0 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG3 + Watchdog timer stage 1 timeout value + 0x54 + 0x20 + 0x07FFFFFF + + + WDT_STG1_HOLD + Stage 1 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG4 + Watchdog timer stage 2 timeout value + 0x58 + 0x20 + 0x000FFFFF + + + WDT_STG2_HOLD + Stage 2 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG5 + Watchdog timer stage 3 timeout value + 0x5C + 0x20 + 0x000FFFFF + + + WDT_STG3_HOLD + Stage 3 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTFEED + Write to feed the watchdog timer + 0x60 + 0x20 + + + WDT_FEED + Write any value to feed the MWDT. (WO) + 0 + 32 + write-only + + + + + WDTWPROTECT + Watchdog write protect register + 0x64 + 0x20 + 0x50D83AA1 + + + WDT_WKEY + If the register contains a different value than its reset value, write +protection is enabled. + 0 + 32 + read-write + + + + + RTCCALICFG + RTC calibration configure register + 0x68 + 0x20 + 0x00013000 + + + RTC_CALI_START_CYCLING + Reserved + 12 + 1 + read-write + + + RTC_CALI_CLK_SEL + 0:rtc slow clock. 1:clk_80m. 2:xtal_32k. + 13 + 2 + read-write + + + RTC_CALI_RDY + Reserved + 15 + 1 + read-only + + + RTC_CALI_MAX + Reserved + 16 + 15 + read-write + + + RTC_CALI_START + Reserved + 31 + 1 + read-write + + + + + RTCCALICFG1 + RTC calibration configure1 register + 0x6C + 0x20 + + + RTC_CALI_CYCLING_DATA_VLD + Reserved + 0 + 1 + read-only + + + RTC_CALI_VALUE + Reserved + 7 + 25 + read-only + + + + + INT_ENA_TIMERS + Interrupt enable bits + 0x70 + 0x20 + + + T0_INT_ENA + The interrupt enable bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-write + + + T1_INT_ENA + The interrupt enable bit for the TIMG_T1_INT interrupt. + 1 + 1 + read-write + + + WDT_INT_ENA + The interrupt enable bit for the TIMG_WDT_INT interrupt. + 2 + 1 + read-write + + + + + INT_RAW_TIMERS + Raw interrupt status + 0x74 + 0x20 + + + T0_INT_RAW + The raw interrupt status bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-write + + + T1_INT_RAW + The raw interrupt status bit for the TIMG_T1_INT interrupt. + 1 + 1 + read-write + + + WDT_INT_RAW + The raw interrupt status bit for the TIMG_WDT_INT interrupt. + 2 + 1 + read-write + + + + + INT_ST_TIMERS + Masked interrupt status + 0x78 + 0x20 + + + T0_INT_ST + The masked interrupt status bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-only + + + T1_INT_ST + The masked interrupt status bit for the TIMG_T1_INT interrupt. + 1 + 1 + read-only + + + WDT_INT_ST + The masked interrupt status bit for the TIMG_WDT_INT interrupt. + 2 + 1 + read-only + + + + + INT_CLR_TIMERS + Interrupt clear bits + 0x7C + 0x20 + + + T0_INT_CLR + Set this bit to clear the TIMG_T0_INT interrupt. + 0 + 1 + write-only + + + T1_INT_CLR + Set this bit to clear the TIMG_T1_INT interrupt. + 1 + 1 + write-only + + + WDT_INT_CLR + Set this bit to clear the TIMG_WDT_INT interrupt. + 2 + 1 + write-only + + + + + RTCCALICFG2 + Timer group calibration register + 0x80 + 0x20 + 0xFFFFFF98 + + + RTC_CALI_TIMEOUT + RTC calibration timeout indicator + 0 + 1 + read-only + + + RTC_CALI_TIMEOUT_RST_CNT + Cycles that release calibration timeout reset + 3 + 4 + read-write + + + RTC_CALI_TIMEOUT_THRES + Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered. + 7 + 25 + read-write + + + + + NTIMERS_DATE + Timer version control register + 0xF8 + 0x20 + 0x02003071 + + + NTIMERS_DATE + Timer version control register + 0 + 28 + read-write + + + + + REGCLK + Timer group clock gate register + 0xFC + 0x20 + + + CLK_EN + Register clock gate signal. 1: The clock for software to read and write registers is always on. 0: The clock for software to read and write registers only exits when the operation happens. + 31 + 1 + read-write + + + + + + + TIMG1 + Timer Group 1 + 0x60020000 + + TG1_T0_LEVEL + 53 + + + TG1_T1_LEVEL + 54 + + + TG1_WDT_LEVEL + 55 + + + + TWAI0 + Two-Wire Automotive Interface + TWAI + 0x6002B000 + + 0x0 + 0x6C + registers + + + TWAI0 + 37 + + + + MODE + Mode Register + 0x0 + 0x20 + 0x00000001 + + + RESET_MODE + This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode. + 0 + 1 + read-write + + + LISTEN_ONLY_MODE + 1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter. + 1 + 1 + read-write + + + SELF_TEST_MODE + 1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command. + 2 + 1 + read-write + + + RX_FILTER_MODE + This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode. + 3 + 1 + read-write + + + + + CMD + Command Register + 0x4 + 0x20 + + + TX_REQ + Set the bit to 1 to allow the driving nodes start transmission. + 0 + 1 + write-only + + + ABORT_TX + Set the bit to 1 to cancel a pending transmission request. + 1 + 1 + write-only + + + RELEASE_BUF + Set the bit to 1 to release the RX buffer. + 2 + 1 + write-only + + + CLR_OVERRUN + Set the bit to 1 to clear the data overrun status bit. + 3 + 1 + write-only + + + SELF_RX_REQ + Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously. + 4 + 1 + write-only + + + + + STATUS + Status register + 0x8 + 0x20 + + + RX_BUF_ST + 1: The data in the RX buffer is not empty, with at least one received data packet. + 0 + 1 + read-only + + + OVERRUN_ST + 1: The RX FIFO is full and data overrun has occurred. + 1 + 1 + read-only + + + TX_BUF_ST + 1: The TX buffer is empty, the CPU may write a message into it. + 2 + 1 + read-only + + + TX_COMPLETE + 1: The TWAI controller has successfully received a packet from the bus. + 3 + 1 + read-only + + + RX_ST + 1: The TWAI Controller is receiving a message from the bus. + 4 + 1 + read-only + + + TX_ST + 1: The TWAI Controller is transmitting a message to the bus. + 5 + 1 + read-only + + + ERR_ST + 1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG. + 6 + 1 + read-only + + + BUS_OFF_ST + 1: In bus-off status, the TWAI Controller is no longer involved in bus activities. + 7 + 1 + read-only + + + MISS_ST + This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete + 8 + 1 + read-only + + + + + INT_RAW + Interrupt Register + 0xC + 0x20 + + + RX_INT_ST + Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO. + 0 + 1 + read-only + + + TX_INT_ST + Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute. + 1 + 1 + read-only + + + ERR_WARN_INT_ST + Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0). + 2 + 1 + read-only + + + OVERRUN_INT_ST + Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO. + 3 + 1 + read-only + + + ERR_PASSIVE_INT_ST + Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters. + 5 + 1 + read-only + + + ARB_LOST_INT_ST + Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated. + 6 + 1 + read-only + + + BUS_ERR_INT_ST + Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus. + 7 + 1 + read-only + + + + + INT_ENA + Interrupt Enable Register + 0x10 + 0x20 + + + RX_INT_ENA + Set this bit to 1 to enable receive interrupt. + 0 + 1 + read-write + + + TX_INT_ENA + Set this bit to 1 to enable transmit interrupt. + 1 + 1 + read-write + + + ERR_WARN_INT_ENA + Set this bit to 1 to enable error warning interrupt. + 2 + 1 + read-write + + + OVERRUN_INT_ENA + Set this bit to 1 to enable data overrun interrupt. + 3 + 1 + read-write + + + ERR_PASSIVE_INT_ENA + Set this bit to 1 to enable error passive interrupt. + 5 + 1 + read-write + + + ARB_LOST_INT_ENA + Set this bit to 1 to enable arbitration lost interrupt. + 6 + 1 + read-write + + + BUS_ERR_INT_ENA + Set this bit to 1 to enable error interrupt. + 7 + 1 + read-write + + + + + BUS_TIMING_0 + Bus Timing Register 0 + 0x18 + 0x20 + + + BAUD_PRESC + Baud Rate Prescaler, determines the frequency dividing ratio. + 0 + 14 + read-write + + + SYNC_JUMP_WIDTH + Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide. + 14 + 2 + read-write + + + + + BUS_TIMING_1 + Bus Timing Register 1 + 0x1C + 0x20 + + + TIME_SEG1 + The width of PBS1. + 0 + 4 + read-write + + + TIME_SEG2 + The width of PBS2. + 4 + 3 + read-write + + + TIME_SAMP + The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times + 7 + 1 + read-write + + + + + ARB_LOST_CAP + Arbitration Lost Capture Register + 0x2C + 0x20 + + + ARB_LOST_CAP + This register contains information about the bit position of lost arbitration. + 0 + 5 + read-only + + + + + ERR_CODE_CAP + Error Code Capture Register + 0x30 + 0x20 + + + ECC_SEGMENT + This register contains information about the location of errors, see Table 181 for details. + 0 + 5 + read-only + + + ECC_DIRECTION + This register contains information about transmission direction of the node when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting a message + 5 + 1 + read-only + + + ECC_TYPE + This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error + 6 + 2 + read-only + + + + + ERR_WARNING_LIMIT + Error Warning Limit Register + 0x34 + 0x20 + 0x00000060 + + + ERR_WARNING_LIMIT + Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid). + 0 + 8 + read-write + + + + + RX_ERR_CNT + Receive Error Counter Register + 0x38 + 0x20 + + + RX_ERR_CNT + The RX error counter register, reflects value changes under reception status. + 0 + 8 + read-write + + + + + TX_ERR_CNT + Transmit Error Counter Register + 0x3C + 0x20 + + + TX_ERR_CNT + The TX error counter register, reflects value changes under transmission status. + 0 + 8 + read-write + + + + + DATA_0 + Data register 0 + 0x40 + 0x20 + + + TX_BYTE_0 + In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode. + 0 + 8 + read-write + + + + + DATA_1 + Data register 1 + 0x44 + 0x20 + + + TX_BYTE_1 + In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode. + 0 + 8 + read-write + + + + + DATA_2 + Data register 2 + 0x48 + 0x20 + + + TX_BYTE_2 + In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode. + 0 + 8 + read-write + + + + + DATA_3 + Data register 3 + 0x4C + 0x20 + + + TX_BYTE_3 + In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode. + 0 + 8 + read-write + + + + + DATA_4 + Data register 4 + 0x50 + 0x20 + + + TX_BYTE_4 + In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode. + 0 + 8 + read-write + + + + + DATA_5 + Data register 5 + 0x54 + 0x20 + + + TX_BYTE_5 + In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode. + 0 + 8 + read-write + + + + + DATA_6 + Data register 6 + 0x58 + 0x20 + + + TX_BYTE_6 + In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode. + 0 + 8 + read-write + + + + + DATA_7 + Data register 7 + 0x5C + 0x20 + + + TX_BYTE_7 + In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode. + 0 + 8 + read-write + + + + + DATA_8 + Data register 8 + 0x60 + 0x20 + + + TX_BYTE_8 + Stored the 8th byte information of the data to be transmitted under operating mode. + 0 + 8 + read-write + + + + + DATA_9 + Data register 9 + 0x64 + 0x20 + + + TX_BYTE_9 + Stored the 9th byte information of the data to be transmitted under operating mode. + 0 + 8 + read-write + + + + + DATA_10 + Data register 10 + 0x68 + 0x20 + + + TX_BYTE_10 + Stored the 10th byte information of the data to be transmitted under operating mode. + 0 + 8 + read-write + + + + + DATA_11 + Data register 11 + 0x6C + 0x20 + + + TX_BYTE_11 + Stored the 11th byte information of the data to be transmitted under operating mode. + 0 + 8 + read-write + + + + + DATA_12 + Data register 12 + 0x70 + 0x20 + + + TX_BYTE_12 + Stored the 12th byte information of the data to be transmitted under operating mode. + 0 + 8 + read-write + + + + + RX_MESSAGE_CNT + Receive Message Counter Register + 0x74 + 0x20 + + + RX_MESSAGE_COUNTER + This register reflects the number of messages available within the RX FIFO. + 0 + 7 + read-only + + + + + CLOCK_DIVIDER + Clock Divider register + 0x7C + 0x20 + + + CD + These bits are used to configure frequency dividing coefficients of the external CLKOUT pin. + 0 + 8 + read-write + + + CLOCK_OFF + This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin + 8 + 1 + read-write + + + + + + + UART0 + UART (Universal Asynchronous Receiver-Transmitter) Controller 0 + UART + 0x60000000 + + 0x0 + 0x84 + registers + + + UART0 + 27 + + + + FIFO + FIFO data register + 0x0 + 0x20 + + + RXFIFO_RD_BYTE + UART 0 accesses FIFO via this register. + 0 + 8 + read-write + + + + + INT_RAW + Raw interrupt status + 0x4 + 0x20 + 0x00000002 + + + RXFIFO_FULL_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_RAW + This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . + 1 + 1 + read-write + + + PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error in the data. + 2 + 1 + read-write + + + FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error . + 3 + 1 + read-write + + + RXFIFO_OVF_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. + 4 + 1 + read-write + + + DSR_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. + 5 + 1 + read-write + + + CTS_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. + 6 + 1 + read-write + + + BRK_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. + 7 + 1 + read-write + + + RXFIFO_TOUT_INT_RAW + This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + 8 + 1 + read-write + + + SW_XON_INT_RAW + This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. + 9 + 1 + read-write + + + SW_XOFF_INT_RAW + This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. + 10 + 1 + read-write + + + GLITCH_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. + 11 + 1 + read-write + + + TX_BRK_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter completes sending NULL characters, after all data in Tx-FIFO are sent. + 12 + 1 + read-write + + + TX_BRK_IDLE_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. + 13 + 1 + read-write + + + TX_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. + 14 + 1 + read-write + + + RS485_PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode. + 15 + 1 + read-write + + + RS485_FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode. + 16 + 1 + read-write + + + RS485_CLASH_INT_RAW + This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode. + 17 + 1 + read-write + + + AT_CMD_CHAR_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. + 18 + 1 + read-write + + + WAKEUP_INT_RAW + This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. + 19 + 1 + read-write + + + + + INT_ST + Masked interrupt status + 0x8 + 0x20 + + + RXFIFO_FULL_INT_ST + This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_ST + This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. + 1 + 1 + read-only + + + PARITY_ERR_INT_ST + This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + 2 + 1 + read-only + + + FRM_ERR_INT_ST + This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + 3 + 1 + read-only + + + RXFIFO_OVF_INT_ST + This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + 4 + 1 + read-only + + + DSR_CHG_INT_ST + This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + 5 + 1 + read-only + + + CTS_CHG_INT_ST + This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + 6 + 1 + read-only + + + BRK_DET_INT_ST + This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + 7 + 1 + read-only + + + RXFIFO_TOUT_INT_ST + This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + 8 + 1 + read-only + + + SW_XON_INT_ST + This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + 9 + 1 + read-only + + + SW_XOFF_INT_ST + This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + 10 + 1 + read-only + + + GLITCH_DET_INT_ST + This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + 11 + 1 + read-only + + + TX_BRK_DONE_INT_ST + This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + 12 + 1 + read-only + + + TX_BRK_IDLE_DONE_INT_ST + This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. + 13 + 1 + read-only + + + TX_DONE_INT_ST + This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + 14 + 1 + read-only + + + RS485_PARITY_ERR_INT_ST + This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1. + 15 + 1 + read-only + + + RS485_FRM_ERR_INT_ST + This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1. + 16 + 1 + read-only + + + RS485_CLASH_INT_ST + This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + 17 + 1 + read-only + + + AT_CMD_CHAR_DET_INT_ST + This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. + 18 + 1 + read-only + + + WAKEUP_INT_ST + This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + 19 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC + 0x20 + + + RXFIFO_FULL_INT_ENA + This is the enable bit for rxfifo_full_int_st register. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_ENA + This is the enable bit for txfifo_empty_int_st register. + 1 + 1 + read-write + + + PARITY_ERR_INT_ENA + This is the enable bit for parity_err_int_st register. + 2 + 1 + read-write + + + FRM_ERR_INT_ENA + This is the enable bit for frm_err_int_st register. + 3 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + This is the enable bit for rxfifo_ovf_int_st register. + 4 + 1 + read-write + + + DSR_CHG_INT_ENA + This is the enable bit for dsr_chg_int_st register. + 5 + 1 + read-write + + + CTS_CHG_INT_ENA + This is the enable bit for cts_chg_int_st register. + 6 + 1 + read-write + + + BRK_DET_INT_ENA + This is the enable bit for brk_det_int_st register. + 7 + 1 + read-write + + + RXFIFO_TOUT_INT_ENA + This is the enable bit for rxfifo_tout_int_st register. + 8 + 1 + read-write + + + SW_XON_INT_ENA + This is the enable bit for sw_xon_int_st register. + 9 + 1 + read-write + + + SW_XOFF_INT_ENA + This is the enable bit for sw_xoff_int_st register. + 10 + 1 + read-write + + + GLITCH_DET_INT_ENA + This is the enable bit for glitch_det_int_st register. + 11 + 1 + read-write + + + TX_BRK_DONE_INT_ENA + This is the enable bit for tx_brk_done_int_st register. + 12 + 1 + read-write + + + TX_BRK_IDLE_DONE_INT_ENA + This is the enable bit for tx_brk_idle_done_int_st register. + 13 + 1 + read-write + + + TX_DONE_INT_ENA + This is the enable bit for tx_done_int_st register. + 14 + 1 + read-write + + + RS485_PARITY_ERR_INT_ENA + This is the enable bit for rs485_parity_err_int_st register. + 15 + 1 + read-write + + + RS485_FRM_ERR_INT_ENA + This is the enable bit for rs485_parity_err_int_st register. + 16 + 1 + read-write + + + RS485_CLASH_INT_ENA + This is the enable bit for rs485_clash_int_st register. + 17 + 1 + read-write + + + AT_CMD_CHAR_DET_INT_ENA + This is the enable bit for at_cmd_char_det_int_st register. + 18 + 1 + read-write + + + WAKEUP_INT_ENA + This is the enable bit for uart_wakeup_int_st register. + 19 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x10 + 0x20 + + + RXFIFO_FULL_INT_CLR + Set this bit to clear the rxfifo_full_int_raw interrupt. + 0 + 1 + write-only + + + TXFIFO_EMPTY_INT_CLR + Set this bit to clear txfifo_empty_int_raw interrupt. + 1 + 1 + write-only + + + PARITY_ERR_INT_CLR + Set this bit to clear parity_err_int_raw interrupt. + 2 + 1 + write-only + + + FRM_ERR_INT_CLR + Set this bit to clear frm_err_int_raw interrupt. + 3 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear rxfifo_ovf_int_raw interrupt. + 4 + 1 + write-only + + + DSR_CHG_INT_CLR + Set this bit to clear the dsr_chg_int_raw interrupt. + 5 + 1 + write-only + + + CTS_CHG_INT_CLR + Set this bit to clear the cts_chg_int_raw interrupt. + 6 + 1 + write-only + + + BRK_DET_INT_CLR + Set this bit to clear the brk_det_int_raw interrupt. + 7 + 1 + write-only + + + RXFIFO_TOUT_INT_CLR + Set this bit to clear the rxfifo_tout_int_raw interrupt. + 8 + 1 + write-only + + + SW_XON_INT_CLR + Set this bit to clear the sw_xon_int_raw interrupt. + 9 + 1 + write-only + + + SW_XOFF_INT_CLR + Set this bit to clear the sw_xoff_int_raw interrupt. + 10 + 1 + write-only + + + GLITCH_DET_INT_CLR + Set this bit to clear the glitch_det_int_raw interrupt. + 11 + 1 + write-only + + + TX_BRK_DONE_INT_CLR + Set this bit to clear the tx_brk_done_int_raw interrupt.. + 12 + 1 + write-only + + + TX_BRK_IDLE_DONE_INT_CLR + Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + 13 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the tx_done_int_raw interrupt. + 14 + 1 + write-only + + + RS485_PARITY_ERR_INT_CLR + Set this bit to clear the rs485_parity_err_int_raw interrupt. + 15 + 1 + write-only + + + RS485_FRM_ERR_INT_CLR + Set this bit to clear the rs485_frm_err_int_raw interrupt. + 16 + 1 + write-only + + + RS485_CLASH_INT_CLR + Set this bit to clear the rs485_clash_int_raw interrupt. + 17 + 1 + write-only + + + AT_CMD_CHAR_DET_INT_CLR + Set this bit to clear the at_cmd_char_det_int_raw interrupt. + 18 + 1 + write-only + + + WAKEUP_INT_CLR + Set this bit to clear the uart_wakeup_int_raw interrupt. + 19 + 1 + write-only + + + + + CLKDIV + Clock divider configuration + 0x14 + 0x20 + 0x000002B6 + + + CLKDIV + The integral part of the frequency divider factor. + 0 + 12 + read-write + + + FRAG + The decimal part of the frequency divider factor. + 20 + 4 + read-write + + + + + RX_FILT + Rx Filter configuration + 0x18 + 0x20 + 0x00000008 + + + GLITCH_FILT + when input pulse width is lower than this value, the pulse is ignored. + 0 + 8 + read-write + + + GLITCH_FILT_EN + Set this bit to enable Rx signal filter. + 8 + 1 + read-write + + + + + STATUS + UART status register + 0x1C + 0x20 + 0xE000C000 + + + RXFIFO_CNT + Stores the byte number of valid data in Rx-FIFO. + 0 + 10 + read-only + + + DSRN + The register represent the level value of the internal uart dsr signal. + 13 + 1 + read-only + + + CTSN + This register represent the level value of the internal uart cts signal. + 14 + 1 + read-only + + + RXD + This register represent the level value of the internal uart rxd signal. + 15 + 1 + read-only + + + TXFIFO_CNT + Stores the byte number of data in Tx-FIFO. + 16 + 10 + read-only + + + DTRN + This bit represents the level of the internal uart dtr signal. + 29 + 1 + read-only + + + RTSN + This bit represents the level of the internal uart rts signal. + 30 + 1 + read-only + + + TXD + This bit represents the level of the internal uart txd signal. + 31 + 1 + read-only + + + + + CONF0 + a + 0x20 + 0x20 + 0x1000001C + + + PARITY + This register is used to configure the parity check mode. + 0 + 1 + read-write + + + PARITY_EN + Set this bit to enable uart parity check. + 1 + 1 + read-write + + + BIT_NUM + This register is used to set the length of data. + 2 + 2 + read-write + + + STOP_BIT_NUM + This register is used to set the length of stop bit. + 4 + 2 + read-write + + + SW_RTS + This register is used to configure the software rts signal which is used in software flow control. + 6 + 1 + read-write + + + SW_DTR + This register is used to configure the software dtr signal which is used in software flow control. + 7 + 1 + read-write + + + TXD_BRK + Set this bit to enbale transmitter to send NULL when the process of sending data is done. + 8 + 1 + read-write + + + IRDA_DPLX + Set this bit to enable IrDA loopback mode. + 9 + 1 + read-write + + + IRDA_TX_EN + This is the start enable bit for IrDA transmitter. + 10 + 1 + read-write + + + IRDA_WCTL + 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0. + 11 + 1 + read-write + + + IRDA_TX_INV + Set this bit to invert the level of IrDA transmitter. + 12 + 1 + read-write + + + IRDA_RX_INV + Set this bit to invert the level of IrDA receiver. + 13 + 1 + read-write + + + LOOPBACK + Set this bit to enable uart loopback test mode. + 14 + 1 + read-write + + + TX_FLOW_EN + Set this bit to enable flow control function for transmitter. + 15 + 1 + read-write + + + IRDA_EN + Set this bit to enable IrDA protocol. + 16 + 1 + read-write + + + RXFIFO_RST + Set this bit to reset the uart receive-FIFO. + 17 + 1 + read-write + + + TXFIFO_RST + Set this bit to reset the uart transmit-FIFO. + 18 + 1 + read-write + + + RXD_INV + Set this bit to inverse the level value of uart rxd signal. + 19 + 1 + read-write + + + CTS_INV + Set this bit to inverse the level value of uart cts signal. + 20 + 1 + read-write + + + DSR_INV + Set this bit to inverse the level value of uart dsr signal. + 21 + 1 + read-write + + + TXD_INV + Set this bit to inverse the level value of uart txd signal. + 22 + 1 + read-write + + + RTS_INV + Set this bit to inverse the level value of uart rts signal. + 23 + 1 + read-write + + + DTR_INV + Set this bit to inverse the level value of uart dtr signal. + 24 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 25 + 1 + read-write + + + ERR_WR_MASK + 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong. + 26 + 1 + read-write + + + AUTOBAUD_EN + This is the enable bit for detecting baudrate. + 27 + 1 + read-write + + + MEM_CLK_EN + UART memory clock gate enable signal. + 28 + 1 + read-write + + + + + CONF1 + Configuration register 1 + 0x24 + 0x20 + 0x00018060 + + + RXFIFO_FULL_THRHD + It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. + 0 + 10 + read-write + + + TXFIFO_EMPTY_THRHD + It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. + 10 + 10 + read-write + + + DIS_RX_DAT_OVF + Disable UART Rx data overflow detect. + 20 + 1 + read-write + + + RX_TOUT_FLOW_DIS + Set this bit to stop accumulating idle_cnt when hardware flow control works. + 21 + 1 + read-write + + + RX_FLOW_EN + This is the flow enable bit for UART receiver. + 22 + 1 + read-write + + + RX_TOUT_EN + This is the enble bit for uart receiver's timeout function. + 23 + 1 + read-write + + + + + LOWPULSE + Autobaud minimum low pulse duration register + 0x28 + 0x20 + 0x00000FFF + + + MIN_CNT + This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process. + 0 + 12 + read-only + + + + + HIGHPULSE + Autobaud minimum high pulse duration register + 0x2C + 0x20 + 0x00000FFF + + + MIN_CNT + This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process. + 0 + 12 + read-only + + + + + RXD_CNT + Autobaud edge change count register + 0x30 + 0x20 + + + RXD_EDGE_CNT + This register stores the count of rxd edge change. It is used in baud rate-detect process. + 0 + 10 + read-only + + + + + FLOW_CONF + Software flow-control configuration + 0x34 + 0x20 + + + SW_FLOW_CON_EN + Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. + 0 + 1 + read-write + + + XONOFF_DEL + Set this bit to remove flow control char from the received data. + 1 + 1 + read-write + + + FORCE_XON + Set this bit to enable the transmitter to go on sending data. + 2 + 1 + read-write + + + FORCE_XOFF + Set this bit to stop the transmitter from sending data. + 3 + 1 + read-write + + + SEND_XON + Set this bit to send Xon char. It is cleared by hardware automatically. + 4 + 1 + read-write + + + SEND_XOFF + Set this bit to send Xoff char. It is cleared by hardware automatically. + 5 + 1 + read-write + + + + + SLEEP_CONF + Sleep-mode configuration + 0x38 + 0x20 + 0x000000F0 + + + ACTIVE_THRESHOLD + The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. + 0 + 10 + read-write + + + + + SWFC_CONF0 + Software flow-control character configuration + 0x3C + 0x20 + 0x00004CE0 + + + XOFF_THRESHOLD + When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char. + 0 + 10 + read-write + + + XOFF_CHAR + This register stores the Xoff flow control char. + 10 + 8 + read-write + + + + + SWFC_CONF1 + Software flow-control character configuration + 0x40 + 0x20 + 0x00004400 + + + XON_THRESHOLD + When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char. + 0 + 10 + read-write + + + XON_CHAR + This register stores the Xon flow control char. + 10 + 8 + read-write + + + + + TXBRK_CONF + Tx Break character configuration + 0x44 + 0x20 + 0x0000000A + + + TX_BRK_NUM + This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. + 0 + 8 + read-write + + + + + IDLE_CONF + Frame-end idle configuration + 0x48 + 0x20 + 0x00040100 + + + RX_IDLE_THRHD + It will produce frame end signal when receiver takes more time to receive one byte data than this register value. + 0 + 10 + read-write + + + TX_IDLE_NUM + This register is used to configure the duration time between transfers. + 10 + 10 + read-write + + + + + RS485_CONF + RS485 mode configuration + 0x4C + 0x20 + + + RS485_EN + Set this bit to choose the rs485 mode. + 0 + 1 + read-write + + + DL0_EN + Set this bit to delay the stop bit by 1 bit. + 1 + 1 + read-write + + + DL1_EN + Set this bit to delay the stop bit by 1 bit. + 2 + 1 + read-write + + + RS485TX_RX_EN + Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode. + 3 + 1 + read-write + + + RS485RXBY_TX_EN + 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. + 4 + 1 + read-write + + + RS485_RX_DLY_NUM + This register is used to delay the receiver's internal data signal. + 5 + 1 + read-write + + + RS485_TX_DLY_NUM + This register is used to delay the transmitter's internal data signal. + 6 + 4 + read-write + + + + + AT_CMD_PRECNT + Pre-sequence timing configuration + 0x50 + 0x20 + 0x00000901 + + + PRE_IDLE_NUM + This register is used to configure the idle duration time before the first at_cmd is received by receiver. + 0 + 16 + read-write + + + + + AT_CMD_POSTCNT + Post-sequence timing configuration + 0x54 + 0x20 + 0x00000901 + + + POST_IDLE_NUM + This register is used to configure the duration time between the last at_cmd and the next data. + 0 + 16 + read-write + + + + + AT_CMD_GAPTOUT + Timeout configuration + 0x58 + 0x20 + 0x0000000B + + + RX_GAP_TOUT + This register is used to configure the duration time between the at_cmd chars. + 0 + 16 + read-write + + + + + AT_CMD_CHAR + AT escape sequence detection configuration + 0x5C + 0x20 + 0x0000032B + + + AT_CMD_CHAR + This register is used to configure the content of at_cmd char. + 0 + 8 + read-write + + + CHAR_NUM + This register is used to configure the num of continuous at_cmd chars received by receiver. + 8 + 8 + read-write + + + + + MEM_CONF + UART threshold and allocation configuration + 0x60 + 0x20 + 0x00140012 + + + RX_SIZE + This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes. + 1 + 3 + read-write + + + TX_SIZE + This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes. + 4 + 3 + read-write + + + RX_FLOW_THRHD + This register is used to configure the maximum amount of data that can be received when hardware flow control works. + 7 + 10 + read-write + + + RX_TOUT_THRHD + This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. + 17 + 10 + read-write + + + MEM_FORCE_PD + Set this bit to force power down UART memory. + 27 + 1 + read-write + + + MEM_FORCE_PU + Set this bit to force power up UART memory. + 28 + 1 + read-write + + + + + MEM_TX_STATUS + Tx-FIFO write and read offset address. + 0x64 + 0x20 + + + APB_TX_WADDR + This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB. + 0 + 10 + read-only + + + TX_RADDR + This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl. + 11 + 10 + read-only + + + + + MEM_RX_STATUS + Rx-FIFO write and read offset address. + 0x68 + 0x20 + 0x00100200 + + + APB_RX_RADDR + This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300. + 0 + 10 + read-only + + + RX_WADDR + This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300. + 11 + 10 + read-only + + + + + FSM_STATUS + UART transmit and receive status. + 0x6C + 0x20 + + + ST_URX_OUT + This is the status register of receiver. + 0 + 4 + read-only + + + ST_UTX_OUT + This is the status register of transmitter. + 4 + 4 + read-only + + + + + POSPULSE + Autobaud high pulse register + 0x70 + 0x20 + 0x00000FFF + + + POSEDGE_MIN_CNT + This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process. + 0 + 12 + read-only + + + + + NEGPULSE + Autobaud low pulse register + 0x74 + 0x20 + 0x00000FFF + + + NEGEDGE_MIN_CNT + This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process. + 0 + 12 + read-only + + + + + CLK_CONF + UART core clock configuration + 0x78 + 0x20 + 0x03701000 + + + SCLK_DIV_B + The denominator of the frequency divider factor. + 0 + 6 + read-write + + + SCLK_DIV_A + The numerator of the frequency divider factor. + 6 + 6 + read-write + + + SCLK_DIV_NUM + The integral part of the frequency divider factor. + 12 + 8 + read-write + + + SCLK_SEL + UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL. + 20 + 2 + read-write + + + SCLK_EN + Set this bit to enable UART Tx/Rx clock. + 22 + 1 + read-write + + + RST_CORE + Write 1 then write 0 to this bit, reset UART Tx/Rx. + 23 + 1 + read-write + + + TX_SCLK_EN + Set this bit to enable UART Tx clock. + 24 + 1 + read-write + + + RX_SCLK_EN + Set this bit to enable UART Rx clock. + 25 + 1 + read-write + + + TX_RST_CORE + Write 1 then write 0 to this bit, reset UART Tx. + 26 + 1 + read-write + + + RX_RST_CORE + Write 1 then write 0 to this bit, reset UART Rx. + 27 + 1 + read-write + + + + + DATE + UART Version register + 0x7C + 0x20 + 0x02008270 + + + DATE + This is the version register. + 0 + 32 + read-write + + + + + ID + UART ID register + 0x80 + 0x20 + 0x40000500 + + + ID + This register is used to configure the uart_id. + 0 + 30 + read-write + + + HIGH_SPEED + This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers. + 30 + 1 + read-write + + + REG_UPDATE + Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. + 31 + 1 + read-write + + + + + + + UART1 + UART (Universal Asynchronous Receiver-Transmitter) Controller 1 + 0x60010000 + + UART1 + 28 + + + + UART2 + UART (Universal Asynchronous Receiver-Transmitter) Controller 2 + 0x6002E000 + + UART2 + 29 + + + + UHCI0 + Universal Host Controller Interface 0 + UHCI + 0x60014000 + + 0x0 + 0x88 + registers + + + UHCI0 + 14 + + + + CONF0 + UHCI configuration register + 0x0 + 0x20 + 0x000006E0 + + + TX_RST + Write 1, then write 0 to this bit to reset decode state machine. + 0 + 1 + read-write + + + RX_RST + Write 1, then write 0 to this bit to reset encode state machine. + 1 + 1 + read-write + + + UART0_CE + Set this bit to link up HCI and UART0. + 2 + 1 + read-write + + + UART1_CE + Set this bit to link up HCI and UART1. + 3 + 1 + read-write + + + UART2_CE + Set this bit to link up HCI and UART2. + 4 + 1 + read-write + + + SEPER_EN + Set this bit to separate the data frame using a special char. + 5 + 1 + read-write + + + HEAD_EN + Set this bit to encode the data packet with a formatting header. + 6 + 1 + read-write + + + CRC_REC_EN + Set this bit to enable UHCI to receive the 16 bit CRC. + 7 + 1 + read-write + + + UART_IDLE_EOF_EN + If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state. + 8 + 1 + read-write + + + LEN_EOF_EN + If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received. + 9 + 1 + read-write + + + ENCODE_CRC_EN + Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload. + 10 + 1 + read-write + + + CLK_EN + 1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers. + 11 + 1 + read-write + + + UART_RX_BRK_EOF_EN + If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART. + 12 + 1 + read-write + + + + + INT_RAW + Raw interrupt status + 0x4 + 0x20 + + + RX_START_INT_RAW + This is the interrupt raw bit. Triggered when a separator char has been sent. + 0 + 1 + read-write + + + TX_START_INT_RAW + This is the interrupt raw bit. Triggered when UHCI detects a separator char. + 1 + 1 + read-write + + + RX_HUNG_INT_RAW + This is the interrupt raw bit. Triggered when UHCI takes more time to receive data than configure value. + 2 + 1 + read-write + + + TX_HUNG_INT_RAW + This is the interrupt raw bit. Triggered when UHCI takes more time to read data from RAM than the configured value. + 3 + 1 + read-write + + + SEND_S_REG_Q_INT_RAW + This is the interrupt raw bit. Triggered when UHCI has sent out a short packet using single_send registers. + 4 + 1 + read-write + + + SEND_A_REG_Q_INT_RAW + This is the interrupt raw bit. Triggered when UHCI has sent out a short packet using always_send registers. + 5 + 1 + read-write + + + OUT_EOF_INT_RAW + This is the interrupt raw bit. Triggered when there are some errors in EOF in the transmit data. + 6 + 1 + read-write + + + APP_CTRL0_INT_RAW + This is the interrupt raw bit. Triggered when set UHCI_APP_CTRL0_IN_SET. + 7 + 1 + read-write + + + APP_CTRL1_INT_RAW + This is the interrupt raw bit. Triggered when set UHCI_APP_CTRL1_IN_SET. + 8 + 1 + read-write + + + + + INT_ST + Masked interrupt status + 0x8 + 0x20 + + + RX_START_INT_ST + This is the masked interrupt bit for UHCI_RX_START_INT interrupt when UHCI_RX_START_INT_ENA is set to 1. + 0 + 1 + read-only + + + TX_START_INT_ST + This is the masked interrupt bit for UHCI_TX_START_INT interrupt when UHCI_TX_START_INT_ENA is set to 1. + 1 + 1 + read-only + + + RX_HUNG_INT_ST + This is the masked interrupt bit for UHCI_RX_HUNG_INT interrupt when UHCI_RX_HUNG_INT_ENA is set to 1. + 2 + 1 + read-only + + + TX_HUNG_INT_ST + This is the masked interrupt bit for UHCI_TX_HUNG_INT interrupt when UHCI_TX_HUNG_INT_ENA is set to 1. + 3 + 1 + read-only + + + SEND_S_REG_Q_INT_ST + This is the masked interrupt bit for UHCI_SEND_S_REQ_Q_INT interrupt when UHCI_SEND_S_REQ_Q_INT_ENA is set to 1. + 4 + 1 + read-only + + + SEND_A_REG_Q_INT_ST + This is the masked interrupt bit for UHCI_SEND_A_REQ_Q_INT interrupt when UHCI_SEND_A_REQ_Q_INT_ENA is set to 1. + 5 + 1 + read-only + + + OUTLINK_EOF_ERR_INT_ST + This is the masked interrupt bit for UHCI_OUTLINK_EOF_ERR_INT interrupt when UHCI_OUTLINK_EOF_ERR_INT_ENA is set to 1. + 6 + 1 + read-only + + + APP_CTRL0_INT_ST + This is the masked interrupt bit for UHCI_APP_CTRL0_INT interrupt when UHCI_APP_CTRL0_INT_ENA is set to 1. + 7 + 1 + read-only + + + APP_CTRL1_INT_ST + This is the masked interrupt bit for UHCI_APP_CTRL1_INT interrupt when UHCI_APP_CTRL1_INT_ENA is set to 1. + 8 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC + 0x20 + + + RX_START_INT_ENA + This is the interrupt enable bit for UHCI_RX_START_INT interrupt. + 0 + 1 + read-write + + + TX_START_INT_ENA + This is the interrupt enable bit for UHCI_TX_START_INT interrupt. + 1 + 1 + read-write + + + RX_HUNG_INT_ENA + This is the interrupt enable bit for UHCI_RX_HUNG_INT interrupt. + 2 + 1 + read-write + + + TX_HUNG_INT_ENA + This is the interrupt enable bit for UHCI_TX_HUNG_INT interrupt. + 3 + 1 + read-write + + + SEND_S_REG_Q_INT_ENA + This is the interrupt enable bit for UHCI_SEND_S_REQ_Q_INT interrupt. + 4 + 1 + read-write + + + SEND_A_REG_Q_INT_ENA + This is the interrupt enable bit for UHCI_SEND_A_REQ_Q_INT interrupt. + 5 + 1 + read-write + + + OUTLINK_EOF_ERR_INT_ENA + This is the interrupt enable bit for UHCI_OUTLINK_EOF_ERR_INT interrupt. + 6 + 1 + read-write + + + APP_CTRL0_INT_ENA + This is the interrupt enable bit for UHCI_APP_CTRL0_INT interrupt. + 7 + 1 + read-write + + + APP_CTRL1_INT_ENA + This is the interrupt enable bit for UHCI_APP_CTRL1_INT interrupt. + 8 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x10 + 0x20 + + + RX_START_INT_CLR + Set this bit to clear UHCI_RX_START_INT interrupt. + 0 + 1 + write-only + + + TX_START_INT_CLR + Set this bit to clear UHCI_TX_START_INT interrupt. + 1 + 1 + write-only + + + RX_HUNG_INT_CLR + Set this bit to clear UHCI_RX_HUNG_INT interrupt. + 2 + 1 + write-only + + + TX_HUNG_INT_CLR + Set this bit to clear UHCI_TX_HUNG_INT interrupt. + 3 + 1 + write-only + + + SEND_S_REG_Q_INT_CLR + Set this bit to clear UHCI_SEND_S_REQ_Q_INT interrupt. + 4 + 1 + write-only + + + SEND_A_REG_Q_INT_CLR + Set this bit to clear UHCI_SEND_A_REQ_Q_INT interrupt. + 5 + 1 + write-only + + + OUTLINK_EOF_ERR_INT_CLR + Set this bit to clear UHCI_OUTLINK_EOF_ERR_INT interrupt. + 6 + 1 + write-only + + + APP_CTRL0_INT_CLR + Set this bit to clear UHCI_APP_CTRL0_INT interrupt. + 7 + 1 + write-only + + + APP_CTRL1_INT_CLR + Set this bit to clear UHCI_APP_CTRL1_INT interrupt. + 8 + 1 + write-only + + + + + APP_INT_SET + Software interrupt trigger source + 0x14 + 0x20 + + + APP_CTRL0_INT_SET + This bit is software interrupt trigger source of UHCI_APP_CTRL0_INT. + 0 + 1 + write-only + + + APP_CTRL1_INT_SET + This bit is software interrupt trigger source of UHCI_APP_CTRL1_INT. + 1 + 1 + write-only + + + + + CONF1 + UHCI configuration register + 0x18 + 0x20 + 0x00000033 + + + CHECK_SUM_EN + This is the enable bit to check header checksum when UHCI receives a data packet. + 0 + 1 + read-write + + + CHECK_SEQ_EN + This is the enable bit to check sequence number when UHCI receives a data packet. + 1 + 1 + read-write + + + CRC_DISABLE + Set this bit to support CRC calculation. Data Integrity Check Present bit in UHCI packet frame should be 1. + 2 + 1 + read-write + + + SAVE_HEAD + Set this bit to save the packet header when HCI receives a data packet. + 3 + 1 + read-write + + + TX_CHECK_SUM_RE + Set this bit to encode the data packet with a checksum. + 4 + 1 + read-write + + + TX_ACK_NUM_RE + Set this bit to encode the data packet with an acknowledgment when a reliable packet is to be transmit. + 5 + 1 + read-write + + + WAIT_SW_START + The uhci-encoder will jump to ST_SW_WAIT status if this register is set to 1. + 7 + 1 + read-write + + + SW_START + If current UHCI_ENCODE_STATE is ST_SW_WAIT, the UHCI will start to send data packet out when this bit is set to 1. + 8 + 1 + read-write + + + + + STATE0 + UHCI receive status + 0x1C + 0x20 + + + RX_ERR_CAUSE + This register indicates the error type when DMA has received a packet with error. 3'b001: Checksum error in HCI packet. 3'b010: Sequence number error in HCI packet. 3'b011: CRC bit error in HCI packet. 3'b100: 0xc0 is found but received HCI packet is not end. 3'b101: 0xc0 is not found when receiving HCI packet is end. 3'b110: CRC check error. + 0 + 3 + read-only + + + DECODE_STATE + UHCI decoder status. + 3 + 3 + read-only + + + + + STATE1 + UHCI transmit status + 0x20 + 0x20 + + + ENCODE_STATE + UHCI encoder status. + 0 + 3 + read-only + + + + + ESCAPE_CONF + Escape character configuration + 0x24 + 0x20 + 0x00000033 + + + TX_C0_ESC_EN + Set this bit to enable decoding char 0xc0 when DMA receives data. + 0 + 1 + read-write + + + TX_DB_ESC_EN + Set this bit to enable decoding char 0xdb when DMA receives data. + 1 + 1 + read-write + + + TX_11_ESC_EN + Set this bit to enable decoding flow control char 0x11 when DMA receives data. + 2 + 1 + read-write + + + TX_13_ESC_EN + Set this bit to enable decoding flow control char 0x13 when DMA receives data. + 3 + 1 + read-write + + + RX_C0_ESC_EN + Set this bit to enable replacing 0xc0 by special char when DMA sends data. + 4 + 1 + read-write + + + RX_DB_ESC_EN + Set this bit to enable replacing 0xdb by special char when DMA sends data. + 5 + 1 + read-write + + + RX_11_ESC_EN + Set this bit to enable replacing flow control char 0x11 by special char when DMA sends data. + 6 + 1 + read-write + + + RX_13_ESC_EN + Set this bit to enable replacing flow control char 0x13 by special char when DMA sends data. + 7 + 1 + read-write + + + + + HUNG_CONF + Timeout configuration + 0x28 + 0x20 + 0x00810810 + + + TXFIFO_TIMEOUT + This register stores the timeout value. It will produce the UHCI_TX_HUNG_INT interrupt when DMA takes more time to receive data. + 0 + 8 + read-write + + + TXFIFO_TIMEOUT_SHIFT + This register is used to configure the tick count maximum value. + 8 + 3 + read-write + + + TXFIFO_TIMEOUT_ENA + This is the enable bit for Tx-FIFO receive-data timeout. + 11 + 1 + read-write + + + RXFIFO_TIMEOUT + This register stores the timeout value. It will produce the UHCI_RX_HUNG_INT interrupt when DMA takes more time to read data from RAM. + 12 + 8 + read-write + + + RXFIFO_TIMEOUT_SHIFT + This register is used to configure the tick count maximum value. + 20 + 3 + read-write + + + RXFIFO_TIMEOUT_ENA + This is the enable bit for DMA send-data timeout. + 23 + 1 + read-write + + + + + ACK_NUM + UHCI ACK number configuration + 0x2C + 0x20 + 0x00000008 + + + ACK_NUM + This ACK number used in software flow control. + 0 + 3 + read-write + + + LOAD + Set this bit to 1, the value configured by UHCI_ACK_NUM would be loaded. + 3 + 1 + write-only + + + + + RX_HEAD + UHCI packet header register + 0x30 + 0x20 + + + RX_HEAD + This register stores the header of the current received packet. + 0 + 32 + read-only + + + + + QUICK_SENT + UHCI quick send configuration register + 0x34 + 0x20 + + + SINGLE_SEND_NUM + This register is used to specify the single_send register. + 0 + 3 + read-write + + + SINGLE_SEND_EN + Set this bit to enable single_send mode to send short packet. + 3 + 1 + read-write + + + ALWAYS_SEND_NUM + This register is used to specify the always_send register. + 4 + 3 + read-write + + + ALWAYS_SEND_EN + Set this bit to enable always_send mode to send short packet. + 7 + 1 + read-write + + + + + REG_Q0_WORD0 + Q0_WORD0 quick_sent register + 0x38 + 0x20 + + + SEND_Q0_WORD0 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q0_WORD1 + Q0_WORD1 quick_sent register + 0x3C + 0x20 + + + SEND_Q0_WORD1 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q1_WORD0 + Q1_WORD0 quick_sent register + 0x40 + 0x20 + + + SEND_Q1_WORD0 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q1_WORD1 + Q1_WORD1 quick_sent register + 0x44 + 0x20 + + + SEND_Q1_WORD1 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q2_WORD0 + Q2_WORD0 quick_sent register + 0x48 + 0x20 + + + SEND_Q2_WORD0 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q2_WORD1 + Q2_WORD1 quick_sent register + 0x4C + 0x20 + + + SEND_Q2_WORD1 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q3_WORD0 + Q3_WORD0 quick_sent register + 0x50 + 0x20 + + + SEND_Q3_WORD0 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q3_WORD1 + Q3_WORD1 quick_sent register + 0x54 + 0x20 + + + SEND_Q3_WORD1 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q4_WORD0 + Q4_WORD0 quick_sent register + 0x58 + 0x20 + + + SEND_Q4_WORD0 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q4_WORD1 + Q4_WORD1 quick_sent register + 0x5C + 0x20 + + + SEND_Q4_WORD1 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q5_WORD0 + Q5_WORD0 quick_sent register + 0x60 + 0x20 + + + SEND_Q5_WORD0 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q5_WORD1 + Q5_WORD1 quick_sent register + 0x64 + 0x20 + + + SEND_Q5_WORD1 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q6_WORD0 + Q6_WORD0 quick_sent register + 0x68 + 0x20 + + + SEND_Q6_WORD0 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q6_WORD1 + Q6_WORD1 quick_sent register + 0x6C + 0x20 + + + SEND_Q6_WORD1 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + ESC_CONF0 + Escape sequence configuration register 0 + 0x70 + 0x20 + 0x00DCDBC0 + + + SEPER_CHAR + This register is used to define the separate char that need to be encoded, default is 0xc0. + 0 + 8 + read-write + + + SEPER_ESC_CHAR0 + This register is used to define the first char of slip escape sequence when encoding the separate char, default is 0xdb. + 8 + 8 + read-write + + + SEPER_ESC_CHAR1 + This register is used to define the second char of slip escape sequence when encoding the separate char, default is 0xdc. + 16 + 8 + read-write + + + + + ESC_CONF1 + Escape sequence configuration register 1 + 0x74 + 0x20 + 0x00DDDBDB + + + ESC_SEQ0 + This register is used to define a char that need to be encoded, default is 0xdb that used as the first char of slip escape sequence. + 0 + 8 + read-write + + + ESC_SEQ0_CHAR0 + This register is used to define the first char of slip escape sequence when encoding the UHCI_ESC_SEQ0, default is 0xdb. + 8 + 8 + read-write + + + ESC_SEQ0_CHAR1 + This register is used to define the second char of slip escape sequence when encoding the UHCI_ESC_SEQ0, default is 0xdd. + 16 + 8 + read-write + + + + + ESC_CONF2 + Escape sequence configuration register 2 + 0x78 + 0x20 + 0x00DEDB11 + + + ESC_SEQ1 + This register is used to define a char that need to be encoded, default is 0x11 that used as flow control char. + 0 + 8 + read-write + + + ESC_SEQ1_CHAR0 + This register is used to define the first char of slip escape sequence when encoding the UHCI_ESC_SEQ1, default is 0xdb. + 8 + 8 + read-write + + + ESC_SEQ1_CHAR1 + This register is used to define the second char of slip escape sequence when encoding the UHCI_ESC_SEQ1, default is 0xde. + 16 + 8 + read-write + + + + + ESC_CONF3 + Escape sequence configuration register 3 + 0x7C + 0x20 + 0x00DFDB13 + + + ESC_SEQ2 + This register is used to define a char that need to be decoded, default is 0x13 that used as flow control char. + 0 + 8 + read-write + + + ESC_SEQ2_CHAR0 + This register is used to define the first char of slip escape sequence when encoding the UHCI_ESC_SEQ2, default is 0xdb. + 8 + 8 + read-write + + + ESC_SEQ2_CHAR1 + This register is used to define the second char of slip escape sequence when encoding the UHCI_ESC_SEQ2, default is 0xdf. + 16 + 8 + read-write + + + + + PKT_THRES + Configure register for packet length + 0x80 + 0x20 + 0x00000080 + + + PKT_THRS + This register is used to configure the maximum value of the packet length when UHCI_HEAD_EN is 0. + 0 + 13 + read-write + + + + + DATE + UHCI version control register + 0x84 + 0x20 + 0x02010090 + + + DATE + This is the version control register. + 0 + 32 + read-write + + + + + + + UHCI1 + Universal Host Controller Interface 1 + 0x6000C000 + + UHCI1 + 15 + + + + USB0 + USB OTG (On-The-Go) + USB + 0x60080000 + + 0x0 + 0x2A0 + registers + + + USB + 38 + + + + GOTGCTL + 0x0 + 0x20 + + + SESREQSCS + 0 + 1 + read-only + + + SESREQ + 1 + 1 + read-write + + + VBVALIDOVEN + 2 + 1 + read-write + + + VBVALIDOVVAL + 3 + 1 + read-write + + + AVALIDOVEN + 4 + 1 + read-write + + + AVALIDOVVAL + 5 + 1 + read-write + + + BVALIDOVEN + 6 + 1 + read-write + + + BVALIDOVVAL + 7 + 1 + read-write + + + HSTNEGSCS + 8 + 1 + read-only + + + HNPREQ + 9 + 1 + read-write + + + HSTSETHNPEN + 10 + 1 + read-write + + + DEVHNPEN + 11 + 1 + read-write + + + EHEN + 12 + 1 + read-write + + + DBNCEFLTRBYPASS + 15 + 1 + read-write + + + CONIDSTS + 16 + 1 + read-only + + + DBNCTIME + 17 + 1 + read-only + + + ASESVLD + 18 + 1 + read-only + + + BSESVLD + 19 + 1 + read-only + + + OTGVER + 20 + 1 + read-write + + + CURMOD + 21 + 1 + read-only + + + + + GOTGINT + 0x4 + 0x20 + + + SESENDDET + 2 + 1 + read-write + + + SESREQSUCSTSCHNG + 8 + 1 + read-write + + + HSTNEGSUCSTSCHNG + 9 + 1 + read-write + + + HSTNEGDET + 17 + 1 + read-write + + + ADEVTOUTCHG + 18 + 1 + read-write + + + DBNCEDONE + 19 + 1 + read-write + + + + + GAHBCFG + 0x8 + 0x20 + + + GLBLLNTRMSK + 0 + 1 + read-write + + + HBSTLEN + 1 + 4 + read-write + + + DMAEN + 5 + 1 + read-write + + + NPTXFEMPLVL + 7 + 1 + read-write + + + PTXFEMPLVL + 8 + 1 + read-write + + + REMMEMSUPP + 21 + 1 + read-write + + + NOTIALLDMAWRIT + 22 + 1 + read-write + + + AHBSINGLE + 23 + 1 + read-write + + + INVDESCENDIANESS + 24 + 1 + read-write + + + + + GUSBCFG + 0xC + 0x20 + 0x00001440 + + + TOUTCAL + 0 + 3 + read-write + + + PHYIF + 3 + 1 + read-write + + + ULPI_UTMI_SEL + 4 + 1 + read-only + + + FSINTF + 5 + 1 + read-write + + + PHYSEL + 6 + 1 + read-only + + + SRPCAP + 8 + 1 + read-write + + + HNPCAP + 9 + 1 + read-write + + + USBTRDTIM + 10 + 4 + read-write + + + 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0x20 + + + DMABUFFERADDR1 + 0 + 32 + read-write + + + + + DOEPCTL2 + 0xB40 + 0x20 + 0x00008000 + + + MPS2 + 0 + 11 + read-only + + + USBACTEP2 + 15 + 1 + read-only + + + NAKSTS2 + 17 + 1 + read-only + + + EPTYPE2 + 18 + 2 + read-only + + + SNP2 + 20 + 1 + read-write + + + STALL2 + 21 + 1 + read-write + + + CNAK2 + 26 + 1 + write-only + + + DO_SNAK2 + 27 + 1 + write-only + + + DO_SETD0PID2 + 28 + 1 + write-only + + + DO_SETD1PID2 + 29 + 1 + write-only + + + EPDIS2 + 30 + 1 + read-only + + + EPENA2 + 31 + 1 + read-write + + + + + DOEPINT2 + 0xB48 + 0x20 + + + XFERCOMPL2 + 0 + 1 + read-write + + + EPDISBLD2 + 1 + 1 + read-write + + + AHBERR2 + 2 + 1 + read-write + + + SETUP2 + 3 + 1 + read-write + + + OUTTKNEPDIS2 + 4 + 1 + read-write + + + STSPHSERCVD2 + 5 + 1 + read-write + + + BACK2BACKSETUP2 + 6 + 1 + read-write + + + OUTPKTERR2 + 8 + 1 + read-write + + + BNAINTR2 + 9 + 1 + read-write + + + PKTDRPSTS2 + 11 + 1 + read-write + + + BBLEERR2 + 12 + 1 + read-write + + + NAKINTRPT2 + 13 + 1 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read-write + + + SETUP3 + 3 + 1 + read-write + + + OUTTKNEPDIS3 + 4 + 1 + read-write + + + STSPHSERCVD3 + 5 + 1 + read-write + + + BACK2BACKSETUP3 + 6 + 1 + read-write + + + OUTPKTERR3 + 8 + 1 + read-write + + + BNAINTR3 + 9 + 1 + read-write + + + PKTDRPSTS3 + 11 + 1 + read-write + + + BBLEERR3 + 12 + 1 + read-write + + + NAKINTRPT3 + 13 + 1 + read-write + + + NYEPINTRPT3 + 14 + 1 + read-write + + + STUPPKTRCVD3 + 15 + 1 + read-write + + + + + DOEPTSIZ3 + 0xB70 + 0x20 + + + XFERSIZE3 + 0 + 7 + read-write + + + PKTCNT3 + 19 + 1 + read-write + + + SUPCNT3 + 29 + 2 + read-write + + + + + DOEPDMA3 + 0xB74 + 0x20 + + + DMAADDR3 + 0 + 32 + read-write + + + + + DOEPDMAB3 + 0xB7C + 0x20 + + + DMABUFFERADDR3 + 0 + 32 + read-write + + + + + DOEPCTL4 + 0xB80 + 0x20 + 0x00008000 + + + MPS4 + 0 + 11 + read-only + + + USBACTEP4 + 15 + 1 + read-only + + + NAKSTS4 + 17 + 1 + read-only + + + EPTYPE4 + 18 + 2 + read-only + + + SNP4 + 20 + 1 + read-write + + + STALL4 + 21 + 1 + read-write + + + CNAK4 + 26 + 1 + write-only + + + DO_SNAK4 + 27 + 1 + write-only + + + DO_SETD0PID4 + 28 + 1 + write-only + + + DO_SETD1PID4 + 29 + 1 + write-only + + + EPDIS4 + 30 + 1 + read-only + + + EPENA4 + 31 + 1 + read-write + + + + + DOEPINT4 + 0xB88 + 0x20 + + + XFERCOMPL4 + 0 + 1 + read-write + + + EPDISBLD4 + 1 + 1 + read-write + + + AHBERR4 + 2 + 1 + read-write + + + SETUP4 + 3 + 1 + read-write + + + OUTTKNEPDIS4 + 4 + 1 + read-write + + + STSPHSERCVD4 + 5 + 1 + read-write + + + BACK2BACKSETUP4 + 6 + 1 + read-write + + + OUTPKTERR4 + 8 + 1 + read-write + + + BNAINTR4 + 9 + 1 + read-write + + + PKTDRPSTS4 + 11 + 1 + read-write + + + BBLEERR4 + 12 + 1 + read-write + + + NAKINTRPT4 + 13 + 1 + read-write + + + NYEPINTRPT4 + 14 + 1 + read-write + + + STUPPKTRCVD4 + 15 + 1 + read-write + + + + + DOEPTSIZ4 + 0xB90 + 0x20 + + + XFERSIZE4 + 0 + 7 + read-write + + + PKTCNT4 + 19 + 1 + read-write + + + SUPCNT4 + 29 + 2 + read-write + + + + + DOEPDMA4 + 0xB94 + 0x20 + + + DMAADDR4 + 0 + 32 + read-write + + + + + DOEPDMAB4 + 0xB9C + 0x20 + + + DMABUFFERADDR4 + 0 + 32 + read-write + + + + + DOEPCTL5 + 0xBA0 + 0x20 + 0x00008000 + + + MPS5 + 0 + 11 + read-only + + + USBACTEP5 + 15 + 1 + read-only + + + NAKSTS5 + 17 + 1 + read-only + + + EPTYPE5 + 18 + 2 + read-only + + + SNP5 + 20 + 1 + read-write + + + STALL5 + 21 + 1 + read-write + + + CNAK5 + 26 + 1 + write-only + + + DO_SNAK5 + 27 + 1 + write-only + + + DO_SETD0PID5 + 28 + 1 + write-only + + + DO_SETD1PID5 + 29 + 1 + write-only + + + EPDIS5 + 30 + 1 + read-only + + + EPENA5 + 31 + 1 + read-write + + + + + DOEPINT5 + 0xBA8 + 0x20 + + + XFERCOMPL5 + 0 + 1 + read-write + + + EPDISBLD5 + 1 + 1 + read-write + + + AHBERR5 + 2 + 1 + read-write + + + SETUP5 + 3 + 1 + read-write + + + OUTTKNEPDIS5 + 4 + 1 + read-write + + + STSPHSERCVD5 + 5 + 1 + read-write + + + BACK2BACKSETUP5 + 6 + 1 + read-write + + + OUTPKTERR5 + 8 + 1 + read-write + + + BNAINTR5 + 9 + 1 + read-write + + + PKTDRPSTS5 + 11 + 1 + read-write + + + BBLEERR5 + 12 + 1 + read-write + + + NAKINTRPT5 + 13 + 1 + read-write + + + NYEPINTRPT5 + 14 + 1 + read-write + + + STUPPKTRCVD5 + 15 + 1 + read-write + + + + + DOEPTSIZ5 + 0xBB0 + 0x20 + + + XFERSIZE5 + 0 + 7 + read-write + + + PKTCNT5 + 19 + 1 + read-write + + + SUPCNT5 + 29 + 2 + read-write + + + + + DOEPDMA5 + 0xBB4 + 0x20 + + + DMAADDR5 + 0 + 32 + read-write + + + + + DOEPDMAB5 + 0xBBC + 0x20 + + + DMABUFFERADDR5 + 0 + 32 + read-write + + + + + DOEPCTL6 + 0xBC0 + 0x20 + 0x00008000 + + + MPS6 + 0 + 11 + read-only + + + USBACTEP6 + 15 + 1 + read-only + + + NAKSTS6 + 17 + 1 + read-only + + + EPTYPE6 + 18 + 2 + read-only + + + SNP6 + 20 + 1 + read-write + + + STALL6 + 21 + 1 + read-write + + + CNAK6 + 26 + 1 + write-only + + + DO_SNAK6 + 27 + 1 + write-only + + + DO_SETD0PID6 + 28 + 1 + write-only + + + DO_SETD1PID6 + 29 + 1 + write-only + + + EPDIS6 + 30 + 1 + read-only + + + EPENA6 + 31 + 1 + read-write + + + + + DOEPINT6 + 0xBC8 + 0x20 + + + XFERCOMPL6 + 0 + 1 + read-write + + + EPDISBLD6 + 1 + 1 + read-write + + + AHBERR6 + 2 + 1 + read-write + + + SETUP6 + 3 + 1 + read-write + + + OUTTKNEPDIS6 + 4 + 1 + read-write + + + STSPHSERCVD6 + 5 + 1 + read-write + + + BACK2BACKSETUP6 + 6 + 1 + read-write + + + OUTPKTERR6 + 8 + 1 + read-write + + + BNAINTR6 + 9 + 1 + read-write + + + PKTDRPSTS6 + 11 + 1 + read-write + + + BBLEERR6 + 12 + 1 + read-write + + + NAKINTRPT6 + 13 + 1 + read-write + + + NYEPINTRPT6 + 14 + 1 + read-write + + + STUPPKTRCVD6 + 15 + 1 + read-write + + + + + DOEPTSIZ6 + 0xBD0 + 0x20 + + + XFERSIZE6 + 0 + 7 + read-write + + + PKTCNT6 + 19 + 1 + read-write + + + SUPCNT6 + 29 + 2 + read-write + + + + + DOEPDMA6 + 0xBD4 + 0x20 + + + DMAADDR6 + 0 + 32 + read-write + + + + + DOEPDMAB6 + 0xBDC + 0x20 + + + DMABUFFERADDR6 + 0 + 32 + read-write + + + + + PCGCCTL + 0xE00 + 0x20 + + + STOPPCLK + 0 + 1 + read-write + + + GATEHCLK + 1 + 1 + read-write + + + PWRCLMP + 2 + 1 + read-write + + + RSTPDWNMODULE + 3 + 1 + read-write + + + PHYSLEEP + 6 + 1 + read-only + + + L1SUSPENDED + 7 + 1 + read-only + + + RESETAFTERSUSP + 8 + 1 + read-write + + + + + + + USB_DEVICE + Full-speed USB Serial/JTAG Controller + USB_DEVICE + 0x60038000 + + 0x0 + 0x50 + registers + + + USB_DEVICE + 96 + + + + EP1 + Endpoint 1 FIFO register + 0x0 + 0x20 + + + RDWR_BYTE + Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO. + 0 + 8 + read-write + + + + + EP1_CONF + Endpoint 1 configure and status register + 0x4 + 0x20 + 0x00000002 + + + WR_DONE + Set this bit to indicate writing byte data to UART Tx FIFO is done. + 0 + 1 + write-only + + + SERIAL_IN_EP_DATA_FREE + 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host. + 1 + 1 + read-only + + + SERIAL_OUT_EP_DATA_AVAIL + 1'b1: Indicate there is data in UART Rx FIFO. + 2 + 1 + read-only + + + + + INT_RAW + Raw status interrupt + 0x8 + 0x20 + 0x00000008 + + + JTAG_IN_FLUSH_INT_RAW + The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG. + 0 + 1 + read-write + + + SOF_INT_RAW + The raw interrupt bit turns to high level when SOF frame is received. + 1 + 1 + read-write + + + SERIAL_OUT_RECV_PKT_INT_RAW + The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet. + 2 + 1 + read-write + + + SERIAL_IN_EMPTY_INT_RAW + The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + 3 + 1 + read-write + + + PID_ERR_INT_RAW + The raw interrupt bit turns to high level when pid error is detected. + 4 + 1 + read-write + + + CRC5_ERR_INT_RAW + The raw interrupt bit turns to high level when CRC5 error is detected. + 5 + 1 + read-write + + + CRC16_ERR_INT_RAW + The raw interrupt bit turns to high level when CRC16 error is detected. + 6 + 1 + read-write + + + STUFF_ERR_INT_RAW + The raw interrupt bit turns to high level when stuff error is detected. + 7 + 1 + read-write + + + IN_TOKEN_REC_IN_EP1_INT_RAW + The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received. + 8 + 1 + read-write + + + USB_BUS_RESET_INT_RAW + The raw interrupt bit turns to high level when usb bus reset is detected. + 9 + 1 + read-write + + + OUT_EP1_ZERO_PAYLOAD_INT_RAW + The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload. + 10 + 1 + read-write + + + OUT_EP2_ZERO_PAYLOAD_INT_RAW + The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload. + 11 + 1 + read-write + + + + + INT_ST + Masked interrupt + 0xC + 0x20 + + + JTAG_IN_FLUSH_INT_ST + The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + read-only + + + SOF_INT_ST + The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. + 1 + 1 + read-only + + + SERIAL_OUT_RECV_PKT_INT_ST + The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + read-only + + + SERIAL_IN_EMPTY_INT_ST + The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + read-only + + + PID_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + read-only + + + CRC5_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + read-only + + + CRC16_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + read-only + + + STUFF_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + read-only + + + IN_TOKEN_REC_IN_EP1_INT_ST + The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + 8 + 1 + read-only + + + USB_BUS_RESET_INT_ST + The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + read-only + + + OUT_EP1_ZERO_PAYLOAD_INT_ST + The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + read-only + + + OUT_EP2_ZERO_PAYLOAD_INT_ST + The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0x10 + 0x20 + + + JTAG_IN_FLUSH_INT_ENA + The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + read-write + + + SOF_INT_ENA + The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. + 1 + 1 + read-write + + + SERIAL_OUT_RECV_PKT_INT_ENA + The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + read-write + + + SERIAL_IN_EMPTY_INT_ENA + The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + read-write + + + PID_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + read-write + + + CRC5_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + read-write + + + CRC16_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + read-write + + + STUFF_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + read-write + + + IN_TOKEN_REC_IN_EP1_INT_ENA + The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + 8 + 1 + read-write + + + USB_BUS_RESET_INT_ENA + The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + read-write + + + OUT_EP1_ZERO_PAYLOAD_INT_ENA + The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + read-write + + + OUT_EP2_ZERO_PAYLOAD_INT_ENA + The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x14 + 0x20 + + + JTAG_IN_FLUSH_INT_CLR + Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + write-only + + + SOF_INT_CLR + Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. + 1 + 1 + write-only + + + SERIAL_OUT_RECV_PKT_INT_CLR + Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + write-only + + + SERIAL_IN_EMPTY_INT_CLR + Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + write-only + + + PID_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + write-only + + + CRC5_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + write-only + + + CRC16_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + write-only + + + STUFF_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + write-only + + + IN_TOKEN_REC_IN_EP1_INT_CLR + Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. + 8 + 1 + write-only + + + USB_BUS_RESET_INT_CLR + Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + write-only + + + OUT_EP1_ZERO_PAYLOAD_INT_CLR + Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + write-only + + + OUT_EP2_ZERO_PAYLOAD_INT_CLR + Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + write-only + + + + + CONF0 + Configure 0 register + 0x18 + 0x20 + 0x00004200 + + + PHY_SEL + Select internal/external PHY + 0 + 1 + read-write + + + EXCHG_PINS_OVERRIDE + Enable software control USB D+ D- exchange + 1 + 1 + read-write + + + EXCHG_PINS + USB D+ D- exchange + 2 + 1 + read-write + + + VREFH + Control single-end input high threshold,1.76V to 2V, step 80mV + 3 + 2 + read-write + + + VREFL + Control single-end input low threshold,0.8V to 1.04V, step 80mV + 5 + 2 + read-write + + + VREF_OVERRIDE + Enable software control input threshold + 7 + 1 + read-write + + + PAD_PULL_OVERRIDE + Enable software control USB D+ D- pullup pulldown + 8 + 1 + read-write + + + DP_PULLUP + Control USB D+ pull up. + 9 + 1 + read-write + + + DP_PULLDOWN + Control USB D+ pull down. + 10 + 1 + read-write + + + DM_PULLUP + Control USB D- pull up. + 11 + 1 + read-write + + + DM_PULLDOWN + Control USB D- pull down. + 12 + 1 + read-write + + + PULLUP_VALUE + Control pull up value. + 13 + 1 + read-write + + + USB_PAD_ENABLE + Enable USB pad function. + 14 + 1 + read-write + + + PHY_TX_EDGE_SEL + 0: TX output at clock negedge. 1: Tx output at clock posedge. + 15 + 1 + read-write + + + USB_JTAG_BRIDGE_EN + Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix. + 16 + 1 + read-write + + + + + TEST + USB Internal PHY test register + 0x1C + 0x20 + + + ENABLE + Enable test of the USB pad + 0 + 1 + read-write + + + USB_OE + USB pad oen in test + 1 + 1 + read-write + + + TX_DP + USB D+ tx value in test + 2 + 1 + read-write + + + TX_DM + USB D- tx value in test + 3 + 1 + read-write + + + RX_RCV + USB differential rx value in test + 4 + 1 + read-only + + + RX_DP + USB D+ rx value in test + 5 + 1 + read-only + + + RX_DM + USB D- rx value in test + 6 + 1 + read-only + + + + + JFIFO_ST + USB-JTAG FIFO status + 0x20 + 0x20 + 0x00000044 + + + IN_FIFO_CNT + JTAT in fifo counter. + 0 + 2 + read-only + + + IN_FIFO_EMPTY + 1: JTAG in fifo is empty. + 2 + 1 + read-only + + + IN_FIFO_FULL + 1: JTAG in fifo is full. + 3 + 1 + read-only + + + OUT_FIFO_CNT + JTAT out fifo counter. + 4 + 2 + read-only + + + OUT_FIFO_EMPTY + 1: JTAG out fifo is empty. + 6 + 1 + read-only + + + OUT_FIFO_FULL + 1: JTAG out fifo is full. + 7 + 1 + read-only + + + IN_FIFO_RESET + Write 1 to reset JTAG in fifo. + 8 + 1 + read-write + + + OUT_FIFO_RESET + Write 1 to reset JTAG out fifo. + 9 + 1 + read-write + + + + + FRAM_NUM + SOF frame number + 0x24 + 0x20 + + + SOF_FRAME_INDEX + Frame index of received SOF frame. + 0 + 11 + read-only + + + + + IN_EP0_ST + IN Endpoint 0 status + 0x28 + 0x20 + 0x00000001 + + + IN_EP0_STATE + State of IN Endpoint 0. + 0 + 2 + read-only + + + IN_EP0_WR_ADDR + Write data address of IN endpoint 0. + 2 + 7 + read-only + + + IN_EP0_RD_ADDR + Read data address of IN endpoint 0. + 9 + 7 + read-only + + + + + IN_EP1_ST + IN Endpoint 1 status + 0x2C + 0x20 + 0x00000001 + + + IN_EP1_STATE + State of IN Endpoint 1. + 0 + 2 + read-only + + + IN_EP1_WR_ADDR + Write data address of IN endpoint 1. + 2 + 7 + read-only + + + IN_EP1_RD_ADDR + Read data address of IN endpoint 1. + 9 + 7 + read-only + + + + + IN_EP2_ST + IN Endpoint 2 status + 0x30 + 0x20 + 0x00000001 + + + IN_EP2_STATE + State of IN Endpoint 2. + 0 + 2 + read-only + + + IN_EP2_WR_ADDR + Write data address of IN endpoint 2. + 2 + 7 + read-only + + + IN_EP2_RD_ADDR + Read data address of IN endpoint 2. + 9 + 7 + read-only + + + + + IN_EP3_ST + IN Endpoint 3 status + 0x34 + 0x20 + 0x00000001 + + + IN_EP3_STATE + State of IN Endpoint 3. + 0 + 2 + read-only + + + IN_EP3_WR_ADDR + Write data address of IN endpoint 3. + 2 + 7 + read-only + + + IN_EP3_RD_ADDR + Read data address of IN endpoint 3. + 9 + 7 + read-only + + + + + OUT_EP0_ST + OUT Endpoint 0 status + 0x38 + 0x20 + + + OUT_EP0_STATE + State of OUT Endpoint 0. + 0 + 2 + read-only + + + OUT_EP0_WR_ADDR + Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. + 2 + 7 + read-only + + + OUT_EP0_RD_ADDR + Read data address of OUT endpoint 0. + 9 + 7 + read-only + + + + + OUT_EP1_ST + OUT Endpoint 1 status + 0x3C + 0x20 + + + OUT_EP1_STATE + State of OUT Endpoint 1. + 0 + 2 + read-only + + + OUT_EP1_WR_ADDR + Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. + 2 + 7 + read-only + + + OUT_EP1_RD_ADDR + Read data address of OUT endpoint 1. + 9 + 7 + read-only + + + OUT_EP1_REC_DATA_CNT + Data count in OUT endpoint 1 when one packet is received. + 16 + 7 + read-only + + + + + OUT_EP2_ST + OUT Endpoint 2 status + 0x40 + 0x20 + + + OUT_EP2_STATE + State of OUT Endpoint 2. + 0 + 2 + read-only + + + OUT_EP2_WR_ADDR + Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. + 2 + 7 + read-only + + + OUT_EP2_RD_ADDR + Read data address of OUT endpoint 2. + 9 + 7 + read-only + + + + + MISC_CONF + MISC register + 0x44 + 0x20 + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 0 + 1 + read-write + + + + + MEM_CONF + Power control + 0x48 + 0x20 + 0x00000002 + + + USB_MEM_PD + 1: power down usb memory. + 0 + 1 + read-write + + + USB_MEM_CLK_EN + 1: Force clock on for usb memory. + 1 + 1 + read-write + + + + + DATE + Version control register + 0x80 + 0x20 + 0x02101200 + + + DATE + register version. + 0 + 32 + read-write + + + + + + + USB_WRAP + USB_WRAP Peripheral + USB_WRAP + 0x60039000 + + 0x0 + 0xC + registers + + + + OTG_CONF + USB OTG Wrapper Configure Register + 0x0 + 0x20 + 0x001C0000 + + + SRP_SESSEND_OVERRIDE + This bit is used to enable the software over-ride of srp session end signal. 1'b0: the signal is controlled by the chip input. 1'b1: the signal is controlled by the software. + 0 + 1 + read-write + + + SRP_SESSEND_VALUE + Software over-ride value of srp session end signal. + 1 + 1 + read-write + + + PHY_SEL + Select internal external PHY. 1'b0: Select internal PHY. 1'b1: Select external PHY. + 2 + 1 + read-write + + + DFIFO_FORCE_PD + Force the dfifo to go into low power mode. The data in dfifo will not lost. + 3 + 1 + read-write + + + DBNCE_FLTR_BYPASS + Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals + 4 + 1 + read-write + + + EXCHG_PINS_OVERRIDE + Enable software controlle USB D+ D- exchange + 5 + 1 + read-write + + + EXCHG_PINS + USB D+ D- exchange. 1'b0: don't change. 1'b1: exchange D+ D- + 6 + 1 + read-write + + + VREFH + Control single-end input high threshold,1.76V to 2V, step 80mV + 7 + 2 + read-write + + + VREFL + Control single-end input low threshold,0.8V to 1.04V, step 80mV + 9 + 2 + read-write + + + VREF_OVERRIDE + Enable software controlle input threshold + 11 + 1 + read-write + + + PAD_PULL_OVERRIDE + Enable software controlle USB D+ D- pullup pulldown + 12 + 1 + read-write + + + DP_PULLUP + Controlle USB D+ pullup + 13 + 1 + read-write + + + DP_PULLDOWN + Controlle USB D+ pulldown + 14 + 1 + read-write + + + DM_PULLUP + Controlle USB D+ pullup + 15 + 1 + read-write + + + DM_PULLDOWN + Controlle USB D+ pulldown + 16 + 1 + read-write + + + PULLUP_VALUE + Controlle pullup value. 1'b0: typical value is 2.4K. 1'b1: typical value is 1.2K. + 17 + 1 + read-write + + + USB_PAD_ENABLE + Enable USB pad function + 18 + 1 + read-write + + + AHB_CLK_FORCE_ON + Force ahb clock always on + 19 + 1 + read-write + + + PHY_CLK_FORCE_ON + Force phy clock always on + 20 + 1 + read-write + + + PHY_TX_EDGE_SEL + Select phy tx signal output clock edge. 1'b0: negedge. 1'b1: posedge. + 21 + 1 + read-write + + + DFIFO_FORCE_PU + Disable the dfifo to go into low power mode. The data in dfifo will not lost. + 22 + 1 + read-write + + + CLK_EN + Disable auto clock gating of CSR registers + 31 + 1 + read-write + + + + + TEST_CONF + USB Internal PHY Testing Register + 0x4 + 0x20 + + + TEST_ENABLE + Enable test of the USB pad + 0 + 1 + read-write + + + TEST_USB_OE + USB pad oen in test + 1 + 1 + read-write + + + TEST_TX_DP + USB D+ tx value in test + 2 + 1 + read-write + + + TEST_TX_DM + USB D- tx value in test + 3 + 1 + read-write + + + TEST_RX_RCV + USB differential rx value in test + 4 + 1 + read-only + + + TEST_RX_DP + USB D+ rx value in test + 5 + 1 + read-only + + + TEST_RX_DM + USB D- rx value in test + 6 + 1 + read-only + + + + + DATE + Version Control Register + 0x3FC + 0x20 + 0x02102010 + + + USB_WRAP_DATE + Date register + 0 + 32 + read-write + + + + + + + WCL + WCL Peripheral + WCL + 0x600D0000 + + 0x0 + 0x160 + registers + + + + Core_0_ENTRY_1_ADDR + Core_0 Entry 1 address configuration Register + 0x0 + 0x20 + + + CORE_0_ENTRY_1_ADDR + Core_0 Entry 1 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_2_ADDR + Core_0 Entry 2 address configuration Register + 0x4 + 0x20 + + + CORE_0_ENTRY_2_ADDR + Core_0 Entry 2 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_3_ADDR + Core_0 Entry 3 address configuration Register + 0x8 + 0x20 + + + CORE_0_ENTRY_3_ADDR + Core_0 Entry 3 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_4_ADDR + Core_0 Entry 4 address configuration Register + 0xC + 0x20 + + + CORE_0_ENTRY_4_ADDR + Core_0 Entry 4 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_5_ADDR + Core_0 Entry 5 address configuration Register + 0x10 + 0x20 + + + CORE_0_ENTRY_5_ADDR + Core_0 Entry 5 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_6_ADDR + Core_0 Entry 6 address configuration Register + 0x14 + 0x20 + + + CORE_0_ENTRY_6_ADDR + Core_0 Entry 6 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_7_ADDR + Core_0 Entry 7 address configuration Register + 0x18 + 0x20 + + + CORE_0_ENTRY_7_ADDR + Core_0 Entry 7 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_8_ADDR + Core_0 Entry 8 address configuration Register + 0x1C + 0x20 + + + CORE_0_ENTRY_8_ADDR + Core_0 Entry 8 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_9_ADDR + Core_0 Entry 9 address configuration Register + 0x20 + 0x20 + + + CORE_0_ENTRY_9_ADDR + Core_0 Entry 9 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_10_ADDR + Core_0 Entry 10 address configuration Register + 0x24 + 0x20 + + + CORE_0_ENTRY_10_ADDR + Core_0 Entry 10 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_11_ADDR + Core_0 Entry 11 address configuration Register + 0x28 + 0x20 + + + CORE_0_ENTRY_11_ADDR + Core_0 Entry 11 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_12_ADDR + Core_0 Entry 12 address configuration Register + 0x2C + 0x20 + + + CORE_0_ENTRY_12_ADDR + Core_0 Entry 12 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_13_ADDR + Core_0 Entry 13 address configuration Register + 0x30 + 0x20 + + + CORE_0_ENTRY_13_ADDR + Core_0 Entry 13 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_CHECK + Core_0 Entry check configuration Register + 0x7C + 0x20 + 0x00000002 + + + CORE_0_ENTRY_CHECK + This filed is used to enable entry address check + 1 + 13 + read-write + + + + + Core_0_STATUSTABLE1 + Status register of world switch of entry 1 + 0x80 + 0x20 + + + CORE_0_FROM_WORLD_1 + This bit is used to confirm world before enter entry 1 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_1 + This filed is used to confirm in which entry before enter entry 1 + 1 + 4 + read-write + + + CORE_0_CURRENT_1 + This bit is used to confirm whether the current state is in entry 1 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE2 + Status register of world switch of entry 2 + 0x84 + 0x20 + + + CORE_0_FROM_WORLD_2 + This bit is used to confirm world before enter entry 2 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_2 + This filed is used to confirm in which entry before enter entry 2 + 1 + 4 + read-write + + + CORE_0_CURRENT_2 + This bit is used to confirm whether the current state is in entry 2 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE3 + Status register of world switch of entry 3 + 0x88 + 0x20 + + + CORE_0_FROM_WORLD_3 + This bit is used to confirm world before enter entry 3 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_3 + This filed is used to confirm in which entry before enter entry 3 + 1 + 4 + read-write + + + CORE_0_CURRENT_3 + This bit is used to confirm whether the current state is in entry 3 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE4 + Status register of world switch of entry 4 + 0x8C + 0x20 + + + CORE_0_FROM_WORLD_4 + This bit is used to confirm world before enter entry 4 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_4 + This filed is used to confirm in which entry before enter entry 4 + 1 + 4 + read-write + + + CORE_0_CURRENT_4 + This bit is used to confirm whether the current state is in entry 4 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE5 + Status register of world switch of entry 5 + 0x90 + 0x20 + + + CORE_0_FROM_WORLD_5 + This bit is used to confirm world before enter entry 5 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_5 + This filed is used to confirm in which entry before enter entry 5 + 1 + 4 + read-write + + + CORE_0_CURRENT_5 + This bit is used to confirm whether the current state is in entry 5 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE6 + Status register of world switch of entry 6 + 0x94 + 0x20 + + + CORE_0_FROM_WORLD_6 + This bit is used to confirm world before enter entry 6 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_6 + This filed is used to confirm in which entry before enter entry 6 + 1 + 4 + read-write + + + CORE_0_CURRENT_6 + This bit is used to confirm whether the current state is in entry 6 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE7 + Status register of world switch of entry 7 + 0x98 + 0x20 + + + CORE_0_FROM_WORLD_7 + This bit is used to confirm world before enter entry 7 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_7 + This filed is used to confirm in which entry before enter entry 7 + 1 + 4 + read-write + + + CORE_0_CURRENT_7 + This bit is used to confirm whether the current state is in entry 7 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE8 + Status register of world switch of entry 8 + 0x9C + 0x20 + + + CORE_0_FROM_WORLD_8 + This bit is used to confirm world before enter entry 8 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_8 + This filed is used to confirm in which entry before enter entry 8 + 1 + 4 + read-write + + + CORE_0_CURRENT_8 + This bit is used to confirm whether the current state is in entry 8 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE9 + Status register of world switch of entry 9 + 0xA0 + 0x20 + + + CORE_0_FROM_WORLD_9 + This bit is used to confirm world before enter entry 9 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_9 + This filed is used to confirm in which entry before enter entry 9 + 1 + 4 + read-write + + + CORE_0_CURRENT_9 + This bit is used to confirm whether the current state is in entry 9 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE10 + Status register of world switch of entry 10 + 0xA4 + 0x20 + + + CORE_0_FROM_WORLD_10 + This bit is used to confirm world before enter entry 10 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_10 + This filed is used to confirm in which entry before enter entry 10 + 1 + 4 + read-write + + + CORE_0_CURRENT_10 + This bit is used to confirm whether the current state is in entry 10 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE11 + Status register of world switch of entry 11 + 0xA8 + 0x20 + + + CORE_0_FROM_WORLD_11 + This bit is used to confirm world before enter entry 11 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_11 + This filed is used to confirm in which entry before enter entry 11 + 1 + 4 + read-write + + + CORE_0_CURRENT_11 + This bit is used to confirm whether the current state is in entry 11 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE12 + Status register of world switch of entry 12 + 0xAC + 0x20 + + + CORE_0_FROM_WORLD_12 + This bit is used to confirm world before enter entry 12 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_12 + This filed is used to confirm in which entry before enter entry 12 + 1 + 4 + read-write + + + CORE_0_CURRENT_12 + This bit is used to confirm whether the current state is in entry 12 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE13 + Status register of world switch of entry 13 + 0xB0 + 0x20 + + + CORE_0_FROM_WORLD_13 + This bit is used to confirm world before enter entry 13 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_13 + This filed is used to confirm in which entry before enter entry 13 + 1 + 4 + read-write + + + CORE_0_CURRENT_13 + This bit is used to confirm whether the current state is in entry 13 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE_CURRENT + Status register of statustable current + 0xFC + 0x20 + + + CORE_0_STATUSTABLE_CURRENT + This field is used to quickly read and rewrite the current field of all STATUSTABLE registers,for example,bit 1 represents the current field of STATUSTABLE1,bit2 represents the current field of STATUSTABLE2 + 1 + 13 + read-write + + + + + Core_0_MESSAGE_ADDR + Clear writer_buffer write address configuration register + 0x100 + 0x20 + + + CORE_0_MESSAGE_ADDR + This field is used to set address that need to write when enter WORLD0 + 0 + 32 + read-write + + + + + Core_0_MESSAGE_MAX + Clear writer_buffer write number configuration register + 0x104 + 0x20 + + + CORE_0_MESSAGE_MAX + This filed is used to set the max value of clear write_buffer + 0 + 4 + read-write + + + + + Core_0_MESSAGE_PHASE + Clear writer_buffer status register + 0x108 + 0x20 + + + CORE_0_MESSAGE_MATCH + This bit indicates whether the check is successful + 0 + 1 + read-only + + + CORE_0_MESSAGE_EXPECT + This field indicates the data to be written next time + 1 + 4 + read-only + + + CORE_0_MESSAGE_DATAPHASE + If this bit is 1, it means that is checking clear write_buffer operation,and is checking data + 5 + 1 + read-only + + + CORE_0_MESSAGE_ADDRESSPHASE + If this bit is 1, it means that is checking clear write_buffer operation,and is checking address. + 6 + 1 + read-only + + + + + Core_0_World_TRIGGER_ADDR + Core_0 trigger address configuration Register + 0x140 + 0x20 + + + CORE_0_WORLD_TRIGGER_ADDR + This field is used to configure the entry address from WORLD0 to WORLD1,when the CPU executes to this address,switch to WORLD1 + 0 + 32 + read-write + + + + + Core_0_World_PREPARE + Core_0 prepare world configuration Register + 0x144 + 0x20 + + + CORE_0_WORLD_PREPARE + This field to used to set world to enter, 2'b01 means WORLD0, 2'b10 means WORLD1 + 0 + 2 + read-write + + + + + Core_0_World_UPDATE + Core_0 configuration update register + 0x148 + 0x20 + + + CORE_0_UPDATE + This field is used to update configuration completed, can write any value,the hardware only checks the write operation of this register and does not case about its value + 0 + 32 + write-only + + + + + Core_0_World_Cancel + Core_0 configuration cancel register + 0x14C + 0x20 + + + CORE_0_WORLD_CANCEL + This field is used to cancel switch world configuration,if the trigger address and update configuration complete,use this register to cancel world switch, jujst need write any value,the hardware only checks the write operation of this register and does not case about its value + 0 + 32 + write-only + + + + + Core_0_World_IRam0 + Core_0 Iram0 world register + 0x150 + 0x20 + + + CORE_0_WORLD_IRAM0 + this field is used to read current world of Iram0 bus + 0 + 2 + read-write + + + + + Core_0_World_DRam0_PIF + Core_0 dram0 and PIF world register + 0x154 + 0x20 + + + CORE_0_WORLD_DRAM0_PIF + this field is used to read current world of Dram0 bus and PIF bus + 0 + 2 + read-write + + + + + Core_0_World_Phase + Core_0 world status register + 0x158 + 0x20 + + + CORE_0_WORLD_PHASE + This bit indicates whether is preparing to switch to WORLD1, 1 means value. + 0 + 1 + read-only + + + + + Core_0_NMI_MASK_ENABLE + Core_0 NMI mask enable register + 0x180 + 0x20 + + + CORE_0_NMI_MASK_ENABLE + this field is used to set NMI mask,it can write any value,when write this register,the hardware start masking NMI interrupt + 0 + 32 + write-only + + + + + Core_0_NMI_MASK_TRIGGER_ADDR + Core_0 NMI mask trigger address register + 0x184 + 0x20 + + + CORE_0_NMI_MASK_TRIGGER_ADDR + this field to used to set trigger address, when CPU executes to this address,NMI mask automatically fails + 0 + 32 + read-write + + + + + Core_0_NMI_MASK_DISABLE + Core_0 NMI mask disable register + 0x188 + 0x20 + + + CORE_0_NMI_MASK_DISABLE + this field is used to disable NMI mask,it will not take effect immediately,only when the CPU executes to the trigger address will it start to cancel NMI mask + 0 + 32 + write-only + + + + + Core_0_NMI_MASK_CANCLE + Core_0 NMI mask disable register + 0x18C + 0x20 + + + CORE_0_NMI_MASK_CANCEL + this field is used to cancel NMI mask disable function. + 0 + 32 + write-only + + + + + Core_0_NMI_MASK + Core_0 NMI mask register + 0x190 + 0x20 + + + CORE_0_NMI_MASK + this bit is used to mask NMI interrupt,it can directly mask NMI interrupt + 0 + 1 + read-write + + + + + Core_0_NMI_MASK_PHASE + Core_0 NMI mask phase register + 0x194 + 0x20 + + + CORE_0_NMI_MASK_PHASE + this bit is used to indicates whether the NMI interrupt is being masked, 1 means NMI interrupt is being masked + 0 + 1 + read-only + + + + + Core_1_ENTRY_1_ADDR + Core_1 Entry 1 address configuration Register + 0x400 + 0x20 + + + CORE_1_ENTRY_1_ADDR + Core_1 Entry 1 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_2_ADDR + Core_1 Entry 2 address configuration Register + 0x404 + 0x20 + + + CORE_1_ENTRY_2_ADDR + Core_1 Entry 2 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_3_ADDR + Core_1 Entry 3 address configuration Register + 0x408 + 0x20 + + + CORE_1_ENTRY_3_ADDR + Core_1 Entry 3 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_4_ADDR + Core_1 Entry 4 address configuration Register + 0x40C + 0x20 + + + CORE_1_ENTRY_4_ADDR + Core_1 Entry 4 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_5_ADDR + Core_1 Entry 5 address configuration Register + 0x410 + 0x20 + + + CORE_1_ENTRY_5_ADDR + Core_1 Entry 5 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_6_ADDR + Core_1 Entry 6 address configuration Register + 0x414 + 0x20 + + + CORE_1_ENTRY_6_ADDR + Core_1 Entry 6 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_7_ADDR + Core_1 Entry 7 address configuration Register + 0x418 + 0x20 + + + CORE_1_ENTRY_7_ADDR + Core_1 Entry 7 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_8_ADDR + Core_1 Entry 8 address configuration Register + 0x41C + 0x20 + + + CORE_1_ENTRY_8_ADDR + Core_1 Entry 8 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_9_ADDR + Core_1 Entry 9 address configuration Register + 0x420 + 0x20 + + + CORE_1_ENTRY_9_ADDR + Core_1 Entry 9 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_10_ADDR + Core_1 Entry 10 address configuration Register + 0x424 + 0x20 + + + CORE_1_ENTRY_10_ADDR + Core_1 Entry 10 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_11_ADDR + Core_1 Entry 11 address configuration Register + 0x428 + 0x20 + + + CORE_1_ENTRY_11_ADDR + Core_1 Entry 11 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_12_ADDR + Core_1 Entry 12 address configuration Register + 0x42C + 0x20 + + + CORE_1_ENTRY_12_ADDR + Core_1 Entry 12 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_13_ADDR + Core_1 Entry 13 address configuration Register + 0x430 + 0x20 + + + CORE_1_ENTRY_13_ADDR + Core_1 Entry 13 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_CHECK + Core_1 Entry check configuration Register + 0x47C + 0x20 + 0x00000002 + + + CORE_1_ENTRY_CHECK + This filed is used to enable entry address check + 1 + 13 + read-write + + + + + Core_1_STATUSTABLE1 + Status register of world switch of entry 1 + 0x480 + 0x20 + + + CORE_1_FROM_WORLD_1 + This bit is used to confirm world before enter entry 1 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_1 + This filed is used to confirm in which entry before enter entry 1 + 1 + 4 + read-write + + + CORE_1_CURRENT_1 + This bit is used to confirm whether the current state is in entry 1 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE2 + Status register of world switch of entry 2 + 0x484 + 0x20 + + + CORE_1_FROM_WORLD_2 + This bit is used to confirm world before enter entry 2 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_2 + This filed is used to confirm in which entry before enter entry 2 + 1 + 4 + read-write + + + CORE_1_CURRENT_2 + This bit is used to confirm whether the current state is in entry 2 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE3 + Status register of world switch of entry 3 + 0x488 + 0x20 + + + CORE_1_FROM_WORLD_3 + This bit is used to confirm world before enter entry 3 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_3 + This filed is used to confirm in which entry before enter entry 3 + 1 + 4 + read-write + + + CORE_1_CURRENT_3 + This bit is used to confirm whether the current state is in entry 3 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE4 + Status register of world switch of entry 4 + 0x48C + 0x20 + + + CORE_1_FROM_WORLD_4 + This bit is used to confirm world before enter entry 4 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_4 + This filed is used to confirm in which entry before enter entry 4 + 1 + 4 + read-write + + + CORE_1_CURRENT_4 + This bit is used to confirm whether the current state is in entry 4 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE5 + Status register of world switch of entry 5 + 0x490 + 0x20 + + + CORE_1_FROM_WORLD_5 + This bit is used to confirm world before enter entry 5 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_5 + This filed is used to confirm in which entry before enter entry 5 + 1 + 4 + read-write + + + CORE_1_CURRENT_5 + This bit is used to confirm whether the current state is in entry 5 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE6 + Status register of world switch of entry 6 + 0x494 + 0x20 + + + CORE_1_FROM_WORLD_6 + This bit is used to confirm world before enter entry 6 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_6 + This filed is used to confirm in which entry before enter entry 6 + 1 + 4 + read-write + + + CORE_1_CURRENT_6 + This bit is used to confirm whether the current state is in entry 6 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE7 + Status register of world switch of entry 7 + 0x498 + 0x20 + + + CORE_1_FROM_WORLD_7 + This bit is used to confirm world before enter entry 7 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_7 + This filed is used to confirm in which entry before enter entry 7 + 1 + 4 + read-write + + + CORE_1_CURRENT_7 + This bit is used to confirm whether the current state is in entry 7 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE8 + Status register of world switch of entry 8 + 0x49C + 0x20 + + + CORE_1_FROM_WORLD_8 + This bit is used to confirm world before enter entry 8 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_8 + This filed is used to confirm in which entry before enter entry 8 + 1 + 4 + read-write + + + CORE_1_CURRENT_8 + This bit is used to confirm whether the current state is in entry 8 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE9 + Status register of world switch of entry 9 + 0x4A0 + 0x20 + + + CORE_1_FROM_WORLD_9 + This bit is used to confirm world before enter entry 9 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_9 + This filed is used to confirm in which entry before enter entry 9 + 1 + 4 + read-write + + + CORE_1_CURRENT_9 + This bit is used to confirm whether the current state is in entry 9 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE10 + Status register of world switch of entry 10 + 0x4A4 + 0x20 + + + CORE_1_FROM_WORLD_10 + This bit is used to confirm world before enter entry 10 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_10 + This filed is used to confirm in which entry before enter entry 10 + 1 + 4 + read-write + + + CORE_1_CURRENT_10 + This bit is used to confirm whether the current state is in entry 10 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE11 + Status register of world switch of entry 11 + 0x4A8 + 0x20 + + + CORE_1_FROM_WORLD_11 + This bit is used to confirm world before enter entry 11 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_11 + This filed is used to confirm in which entry before enter entry 11 + 1 + 4 + read-write + + + CORE_1_CURRENT_11 + This bit is used to confirm whether the current state is in entry 11 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE12 + Status register of world switch of entry 12 + 0x4AC + 0x20 + + + CORE_1_FROM_WORLD_12 + This bit is used to confirm world before enter entry 12 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_12 + This filed is used to confirm in which entry before enter entry 12 + 1 + 4 + read-write + + + CORE_1_CURRENT_12 + This bit is used to confirm whether the current state is in entry 12 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE13 + Status register of world switch of entry 13 + 0x4B0 + 0x20 + + + CORE_1_FROM_WORLD_13 + This bit is used to confirm world before enter entry 13 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_13 + This filed is used to confirm in which entry before enter entry 13 + 1 + 4 + read-write + + + CORE_1_CURRENT_13 + This bit is used to confirm whether the current state is in entry 13 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE_CURRENT + Status register of statustable current + 0x4FC + 0x20 + + + CORE_1_STATUSTABLE_CURRENT + This field is used to quickly read and rewrite the current field of all STATUSTABLE registers,for example,bit 1 represents the current field of STATUSTABLE1 + 1 + 13 + read-write + + + + + Core_1_MESSAGE_ADDR + Clear writer_buffer write address configuration register + 0x500 + 0x20 + + + CORE_1_MESSAGE_ADDR + This field is used to set address that need to write when enter WORLD0 + 0 + 32 + read-write + + + + + Core_1_MESSAGE_MAX + Clear writer_buffer write number configuration register + 0x504 + 0x20 + + + CORE_1_MESSAGE_MAX + This filed is used to set the max value of clear write_buffer + 0 + 4 + read-write + + + + + Core_1_MESSAGE_PHASE + Clear writer_buffer status register + 0x508 + 0x20 + + + CORE_1_MESSAGE_MATCH + This bit indicates whether the check is successful + 0 + 1 + read-only + + + CORE_1_MESSAGE_EXPECT + This field indicates the data to be written next time + 1 + 4 + read-only + + + CORE_1_MESSAGE_DATAPHASE + If this bit is 1, it means that is checking clear write_buffer operation, and is checking data + 5 + 1 + read-only + + + CORE_1_MESSAGE_ADDRESSPHASE + If this bit is 1, it means that is checking clear write_buffer operation, and is checking address. + 6 + 1 + read-only + + + + + Core_1_World_TRIGGER_ADDR + Core_1 trigger address configuration Register + 0x540 + 0x20 + + + CORE_1_WORLD_TRIGGER_ADDR + This field is used to configure the entry address from WORLD0 to WORLD1,when the CPU executes to this address,switch to WORLD1 + 0 + 32 + read-write + + + + + Core_1_World_PREPARE + Core_1 prepare world configuration Register + 0x544 + 0x20 + + + CORE_1_WORLD_PREPARE + This field to used to set world to enter,2'b01 means WORLD0, 2'b10 means WORLD1 + 0 + 2 + read-write + + + + + Core_1_World_UPDATE + Core_1 configuration update register + 0x548 + 0x20 + + + CORE_1_UPDATE + This field is used to update configuration completed, can write any value,the hardware only checks the write operation of this register and does not case about its value + 0 + 32 + write-only + + + + + Core_1_World_Cancel + Core_1 configuration cancel register + 0x54C + 0x20 + + + CORE_1_WORLD_CANCEL + This field is used to cancel switch world configuration,if the trigger address and update configuration complete,can use this register to cancel world switch. can write any value, the hardware only checks the write operation of this register and does not case about its value + 0 + 32 + write-only + + + + + Core_1_World_IRam0 + Core_1 Iram0 world register + 0x550 + 0x20 + + + CORE_1_WORLD_IRAM0 + this field is used to read current world of Iram0 bus + 0 + 2 + read-write + + + + + Core_1_World_DRam0_PIF + Core_1 dram0 and PIF world register + 0x554 + 0x20 + + + CORE_1_WORLD_DRAM0_PIF + this field is used to read current world of Dram0 bus and PIF bus + 0 + 2 + read-write + + + + + Core_1_World_Phase + Core_0 world status register + 0x558 + 0x20 + + + CORE_1_WORLD_PHASE + This bit indicates whether is preparing to switch to WORLD1,1 means value. + 0 + 1 + read-only + + + + + Core_1_NMI_MASK_ENABLE + Core_1 NMI mask enable register + 0x580 + 0x20 + + + CORE_1_NMI_MASK_ENABLE + this field is used to set NMI mask, it can write any value, when write this register,the hardware start masking NMI interrupt + 0 + 32 + write-only + + + + + Core_1_NMI_MASK_TRIGGER_ADDR + Core_1 NMI mask trigger addr register + 0x584 + 0x20 + + + CORE_1_NMI_MASK_TRIGGER_ADDR + this field to used to set trigger address + 0 + 32 + read-write + + + + + Core_1_NMI_MASK_DISABLE + Core_1 NMI mask disable register + 0x588 + 0x20 + + + CORE_1_NMI_MASK_DISABLE + this field is used to disable NMI mask, it will not take effect immediately,only when the CPU executes to the trigger address will it start to cancel NMI mask + 0 + 32 + write-only + + + + + Core_1_NMI_MASK_CANCLE + Core_1 NMI mask disable register + 0x58C + 0x20 + + + CORE_1_NMI_MASK_CANCEL + this field is used to cancel NMI mask disable function. + 0 + 32 + write-only + + + + + Core_1_NMI_MASK + Core_1 NMI mask register + 0x590 + 0x20 + + + CORE_1_NMI_MASK + this bit is used to mask NMI interrupt,it can directly mask NMI interrupt + 0 + 1 + read-write + + + + + Core_1_NMI_MASK_PHASE + Core_1 NMI mask phase register + 0x594 + 0x20 + + + CORE_1_NMI_MASK_PHASE + this bit is used to indicates whether the NMI interrupt is being masked, 1 means NMI interrupt is being masked + 0 + 1 + read-only + + + + + + + XTS_AES + XTS-AES-128 Flash Encryption + XTS_AES + 0x600CC000 + + 0x0 + 0x60 + registers + + + + 16 + 0x4 + PLAIN_%s + Plaintext register %s + 0x0 + 0x20 + + + PLAIN_0 + Stores the nth 32-bit piece of plaintext. + 0 + 32 + read-write + + + + + LINESIZE + XTS-AES line-size register + 0x40 + 0x20 + + + LINESIZE + Configures the data size of one encryption. + 0 + 1 + read-write + + + + + DESTINATION + XTS-AES destination register + 0x44 + 0x20 + + + DESTINATION + Configures the type of the external memory. Currently, it must be set to 0, as the Manual Encryption block only supports flash encryption. Errors may occurs if users write 1. 0:flash. 1: external RAM. + 0 + 1 + read-write + + + + + PHYSICAL_ADDRESS + physical address + 0x48 + 0x20 + + + PHYSICAL_ADDRESS + Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes. If linesize is 64-byte, the physical address should be aligned of 64 bytes. + 0 + 30 + read-write + + + + + TRIGGER + XTS-AES trigger register + 0x4C + 0x20 + + + TRIGGER + Write 1 to activate manual encryption. + 0 + 1 + write-only + + + + + RELEASE + XTS-AES release control register + 0x50 + 0x20 + + + RELEASE + Write 1 to grant SPI1 access to encrypted result. + 0 + 1 + write-only + + + + + DESTROY + XTS-AES destroy control register + 0x54 + 0x20 + + + DESTROY + Write 1 to destroy encrypted result. + 0 + 1 + write-only + + + + + STATE + XTS-AES status register + 0x58 + 0x20 + + + STATE + Those bits indicates the status of the Manual Encryption block. 0X0 (XTS_AES_IDLE): idle. 0X1 (XTS_AES_BUSY): busy with encryption. 0X2 (XTS_AES_DONE): encryption is completed, but the encrypted result is not accessible to SPI. 0X3 (XTS_AES_AVAILABLE) encrypted result is accessible and available to SPI. + 0 + 2 + read-only + + + + + DATE + XTS-AES version control register + 0x5C + 0x20 + 0x20200111 + + + DATE + Manual Encryption block version information. + 0 + 30 + read-write + + + + + + + diff --git a/partition-table.bin b/partition-table.bin new file mode 100644 index 0000000..7c55f7e Binary files /dev/null and b/partition-table.bin differ diff --git a/peripherals.csproj.template b/peripherals.csproj.template new file mode 100644 index 0000000..3487dfc --- /dev/null +++ b/peripherals.csproj.template @@ -0,0 +1,144 @@ + + + + netstandard2.1 + AMD64 + $PATH_TO_RENODE + + + + + $(RenodePath)/AdvancedLoggerViewerPlugin.dll + + + $(RenodePath)/AntShell.dll + + + $(RenodePath)/AsyncIO.dll + + + $(RenodePath)/CookComputing.XmlRpcV2.dll + + + $(RenodePath)/cores-arm.dll + + + $(RenodePath)/cores-arm-m.dll + + + $(RenodePath)/cores-i386.dll + + + $(RenodePath)/cores-ppc.dll + + + $(RenodePath)/cores-ppc64.dll + + + $(RenodePath)/cores-riscv.dll + + + $(RenodePath)/cores-riscv64.dll + + + $(RenodePath)/cores-sparc.dll + + + $(RenodePath)/CxxDemangler.dll + + + $(RenodePath)/Dynamitey.dll + + + $(RenodePath)/ELFSharp.dll + + + $(RenodePath)/Emulator.dll + + + $(RenodePath)/Extensions.dll + + + $(RenodePath)/FdtSharp.dll + + + $(RenodePath)/IronPython.dll + + + $(RenodePath)/IronPython.Modules.dll + + + $(RenodePath)/libtftp.dll + + + $(RenodePath)/LLVMDisassembler.dll + + + $(RenodePath)/Lucene.Net.dll + + + $(RenodePath)/LZ4.dll + + + $(RenodePath)/Microsoft.Dynamic.dll + + + $(RenodePath)/Microsoft.Scripting.dll + + + $(RenodePath)/Microsoft.Scripting.Metadata.dll + + + $(RenodePath)/Migrant.dll + + + $(RenodePath)/Mono.Cecil.dll + + + $(RenodePath)/NetMQ.dll + + + $(RenodePath)/Nini.dll + + + $(RenodePath)/OptionsParser.dll + + + $(RenodePath)/PacketDotNet.dll + + + $(RenodePath)/Renode.exe + + + $(RenodePath)/Renode-peripherals.dll + + + $(RenodePath)/SampleCommandPlugin.dll + + + $(RenodePath)/Sprache.dll + + + $(RenodePath)/TermSharp.dll + + + $(RenodePath)/TracePlugin.dll + + + $(RenodePath)/UI.dll + + + $(RenodePath)/VerilatorPlugin.dll + + + $(RenodePath)/WiresharkPlugin.dll + + + $(RenodePath)/Xwt.dll + + + $(RenodePath)/Xwt.WPF.dll + + + + diff --git a/peripherals/ESP32S3_EFUSE.cs b/peripherals/ESP32S3_EFUSE.cs new file mode 100644 index 0000000..5435d3e --- /dev/null +++ b/peripherals/ESP32S3_EFUSE.cs @@ -0,0 +1,109 @@ +// +// Copyright (c) 2010-2023 Antmicro +// Copyright (c) 2011-2015 Realtime Embedded +// +// This file is licensed under the MIT License. +// Full license text is available in 'licenses/MIT.txt'. +// +using System; +using Antmicro.Renode.Peripherals.Bus; +using Antmicro.Renode.Peripherals; +using Antmicro.Renode.Utilities; +using Antmicro.Renode.Logging; +using System.Collections.Generic; + +namespace Antmicro.Renode.Peripherals.Memory +{ + public class ArrayMemory : IBytePeripheral, IWordPeripheral, IDoubleWordPeripheral, IKnownSize, IMemory, IMultibyteWritePeripheral, IQuadWordPeripheral + { + public ArrayMemory(byte[] source) + { + array = source; + } + + public ArrayMemory(int size) + { + array = new byte[size]; + } + + public virtual ulong ReadQuadWord(long offset) + { + var intOffset = (int)offset; + var result = BitConverter.ToUInt64(array, intOffset); + return result; + } + + public virtual void WriteQuadWord(long offset, ulong value) + { + var bytes = BitConverter.GetBytes(value); + bytes.CopyTo(array, offset); + } + + public uint ReadDoubleWord(long offset) + { + var intOffset = (int)offset; + var result = BitConverter.ToUInt32(array, intOffset); + return result; + } + + public virtual void WriteDoubleWord(long offset, uint value) + { + var bytes = BitConverter.GetBytes(value); + bytes.CopyTo(array, offset); + + } + + public void Reset() + { + // nothing happens + } + + public ushort ReadWord(long offset) + { + var intOffset = (int)offset; + var result = BitConverter.ToUInt16(array, intOffset); + return result; + } + + public virtual void WriteWord(long offset, ushort value) + { + var bytes = BitConverter.GetBytes(value); + bytes.CopyTo(array, offset); + } + + public byte ReadByte(long offset) + { + var intOffset = (int)offset; + var result = array[intOffset]; + return result; + } + + public virtual void WriteByte(long offset, byte value) + { + var intOffset = (int)offset; + array[intOffset] = value; + } + + public byte[] ReadBytes(long offset, int count) + { + var result = new byte[count]; + Array.Copy(array, offset, result, 0, count); + return result; + } + + public void WriteBytes(long offset, byte[] bytes, int startingIndex, int count) + { + Array.Copy(bytes, startingIndex, array, offset, count); + } + + public long Size + { + get + { + return array.Length; + } + } + + protected readonly byte[] array; + } +} diff --git a/peripherals/ESP32S3_EXTMEM.cs b/peripherals/ESP32S3_EXTMEM.cs new file mode 100644 index 0000000..a4ed04b --- /dev/null +++ b/peripherals/ESP32S3_EXTMEM.cs @@ -0,0 +1,177 @@ +// +// Copyright (c) 2010-2023 Antmicro +// Copyright (c) 2011-2015 Realtime Embedded +// +// This file is licensed under the MIT License. +// Full license text is available in 'licenses/MIT.txt'. +// +using System; +using Antmicro.Renode.Peripherals.Bus; +using Antmicro.Renode.Core; +using Antmicro.Renode.Peripherals; +using Antmicro.Renode.Utilities; +using Antmicro.Renode.Logging; +using System.Collections.Generic; +using Antmicro.Renode.Core.Structure.Registers; + +namespace Antmicro.Renode.Peripherals.Miscellaneous +{ + public class ESP32S3_EXTMEM : IBytePeripheral, IDoubleWordPeripheral, IKnownSize + { + public ESP32S3_EXTMEM(Machine machine) + { + var registersMap = new Dictionary + { + {(long)Registers.DCACHE_CTRL, new DoubleWordRegister(this) + .WithFlag(0, FieldMode.Read | FieldMode.Write, name: "DCACHE_ENABLE") // The bit is used to activate the data cache. 0: disable, 1: enable + .WithFlag(1, FieldMode.Read | FieldMode.Write, name: "DCACHE_SIZE_MODE") // The bit is used to configure cache memory size.0: 32KB, 1: 64KB + .WithValueField(2, 2, FieldMode.Read | FieldMode.Write, name: "DCACHE_BLOCKSIZE_MODE") // The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2: 64 bytes + }, + {(long)Registers.DCACHE_CTRL1, new DoubleWordRegister(this) + .WithFlag(0, FieldMode.Read | FieldMode.Write, name: "DCACHE_SHUT_CORE0_BUS") // The bit is used to disable core0 dbus, 0: enable, 1: disable + .WithFlag(1, FieldMode.Read | FieldMode.Write, name: "DCACHE_SHUT_CORE1_BUS") // The bit is used to disable core1 dbus, 0: enable, 1: disable + }, + {(long)Registers.DCACHE_SYNC_CTRL, new DoubleWordRegister(this) + .WithFlag(0, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => false, name: "DCACHE_INVALIDATE_ENA") // The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. + .WithFlag(1, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => false, name: "DCACHE_WRITEBACK_ENA") // The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done. + .WithFlag(2, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => false, name: "DCACHE_CLEAN_ENA") // The bit is used to enable clean operation. It will be cleared by hardware after clean operation done. + .WithFlag(3, FieldMode.Read, valueProviderCallback: (_) => true, name: "DCACHE_SYNC_DONE") // The bit is used to indicate clean/writeback/invalidate operation is finished. + }, + {(long)Registers.DCACHE_SYNC_ADDR, new DoubleWordRegister(this) + .WithValueField(0, 32, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => 0, name: "DCACHE_SYNC_ADDR") // The bits are used to configure the start virtual address for clean operations. It should be combined with DCACHE_SYNC_SIZE_REG. + }, + {(long)Registers.DCACHE_SYNC_SIZE, new DoubleWordRegister(this) + .WithValueField(0, 32, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => 0, name: "DCACHE_SYNC_SIZE") // The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG. + }, + {(long)Registers.DCACHE_PRELOAD_CTRL, new DoubleWordRegister(this) + .WithFlag(0, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => false, name: "DCACHE_PRELOAD_ENA") // The bit is used to enable preload operation. It will be cleared by hardware after preload operation done. + .WithFlag(1, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => true, name: "DCACHE_PRELOAD_DONE") // The bit is used to indicate preload operation is finished. + .WithFlag(2, FieldMode.Read | FieldMode.Write, name: "DCACHE_PRELOAD_ORDER") // The bit is used to configure the direction of preload operation. 1: descending, 0: ascending. + }, + {(long)Registers.DCACHE_AUTOLOAD_CTRL, new DoubleWordRegister(this) + .WithFlag(0, FieldMode.Read | FieldMode.Write, name: "DCACHE_AUTOLOAD_SCT0_ENA") // The bits are used to enable the first section for autoload operation. + .WithFlag(1, FieldMode.Read | FieldMode.Write, name: "DCACHE_AUTOLOAD_SCT1_ENA") // The bits are used to enable the second section for autoload operation. + .WithFlag(2, FieldMode.Read | FieldMode.Write, name: "DCACHE_AUTOLOAD_ENA") // The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable, 0: disable. + .WithFlag(3, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => true, name: "DCACHE_AUTOLOAD_DONE") // The bit is used to indicate autoload operation is finished. + .WithFlag(4, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => false, name: "DCACHE_AUTOLOAD_ORDER") // The bits are used to configure the direction of autoload. 1: descending, 0: ascending. + .WithValueField(5, 2, FieldMode.Read | FieldMode.Write, name: "DCACHE_AUTOLOAD_RQST") // The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit. + .WithValueField(7, 2, FieldMode.Read | FieldMode.Write, name: "DCACHE_AUTOLOAD_SIZE") // The bits are used to configure the numbers of the cache block for the issuing autoload operation. + .WithFlag(9, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => false, name: "DCACHE_AUTOLOAD_BUFFER_CLEAR") // The bit is used to clear autoload buffer in dcache. + }, + {(long)Registers.CACHE_ILG_INT_CLR, new DoubleWordRegister(this) + .WithFlag(0, FieldMode.Read | FieldMode.Write, name: "ICACHE_SYNC_OP_FAULT_INT_CLR") // The bit is used to clear interrupt by sync configurations fault. + .WithFlag(1, FieldMode.Read | FieldMode.Write, name: "ICACHE_PRELOAD_OP_FAULT_INT_CLR") // The bit is used to clear interrupt by preload configurations fault. + .WithFlag(2, FieldMode.Read | FieldMode.Write, name: "DCACHE_SYNC_OP_FAULT_INT_CLR") // The bit is used to clear interrupt by sync configurations fault. + .WithFlag(3, FieldMode.Read | FieldMode.Write, name: "DCACHE_PRELOAD_OP_FAULT_INT_CLR") // The bit is used to clear interrupt by preload configurations fault. + .WithFlag(4, FieldMode.Read | FieldMode.Write, name: "DCACHE_WRITE_FLASH_INT_CLR") // The bit is used to clear interrupt by dcache trying to write flash. + .WithFlag(5, FieldMode.Read | FieldMode.Write, name: "MMU_ENTRY_FAULT_INT_CLR") // The bit is used to clear interrupt by mmu entry fault. + .WithFlag(6, FieldMode.Read | FieldMode.Write, name: "DCACHE_OCCUPY_EXC_INT_CLR") // The bit is used to clear interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode. + .WithFlag(7, FieldMode.Read | FieldMode.Write, name: "IBUS_CNT_OVF_INT_CLR") // The bit is used to clear interrupt by ibus counter overflow. + .WithFlag(8, FieldMode.Read | FieldMode.Write, name: "DBUS_CNT_OVF_INT_CLR") // The bit is used to clear interrupt by dbus counter overflow. + }, + {(long)Registers.CACHE_WRAP_AROUND_CTRL, new DoubleWordRegister(this) + .WithFlag(0, FieldMode.Read | FieldMode.Write, name: "CACHE_FLASH_WRAP_AROUND") // The bit is used to enable wrap around mode when read data from flash. + .WithFlag(1, FieldMode.Read | FieldMode.Write, name: "CACHE_SRAM_RD_WRAP_AROUND") // The bit is used to enable wrap around mode when read data from spiram. + + // .WithValueField(0, 2, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => 0, name: "SW_STALL_APPCPU_C0") // {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU + // .WithValueField(2, 2, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => 0, name: "SW_STALL_PROCPU_C0") // {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU + // .WithFlag(4, FieldMode.Read | FieldMode.Write, name: "SW_APPCPU_RST") // APP CPU SW reset + // .WithFlag(5, FieldMode.Read | FieldMode.Write, name: "SW_PROCPU_RST") // PRO CPU SW reset + // .WithFlag(6, FieldMode.Read | FieldMode.Write, name: "BB_I2C_FORCE_PD") // BB_I2C force power down + // .WithFlag(7, FieldMode.Read | FieldMode.Write, name: "BB_I2C_FORCE_PU") // BB_I2C force power up + // .WithFlag(8, FieldMode.Read | FieldMode.Write, name: "BBPLL_I2C_FORCE_PD") // BB_PLL _I2C force power down + // .WithFlag(9, FieldMode.Read | FieldMode.Write, name: "BBPLL_I2C_FORCE_PU") // BB_PLL_I2C force power up + // .WithFlag(10, FieldMode.Read | FieldMode.Write, name: "BBPLL_FORCE_PD") // BB_PLL force power down + // .WithFlag(11, FieldMode.Read | FieldMode.Write, name: "BBPLL_FORCE_PU") // BB_PLL force power up + // .WithFlag(12, FieldMode.Read | FieldMode.Write, name: "XTL_FORCE_PD") // crystall force power down + // .WithFlag(13, FieldMode.Read | FieldMode.Write, name: "XTL_FORCE_PU") // crystall force power up + // .WithValueField(14, 4, FieldMode.Read | FieldMode.Write, name: "XTL_EN_WAIT") // wait bias_sleep and current source wakeup + // .WithFlag(23, FieldMode.Read | FieldMode.Write, name: "XTL_FORCE_ISO") // No public + // .WithFlag(24, FieldMode.Read | FieldMode.Write, name: "PLL_FORCE_ISO") // No public + // .WithFlag(25, FieldMode.Read | FieldMode.Write, name: "ANALOG_FORCE_ISO") // No public + // .WithFlag(26, FieldMode.Read | FieldMode.Write, name: "XTL_FORCE_NOISO") // No public + // .WithFlag(27, FieldMode.Read | FieldMode.Write, name: "PLL_FORCE_NOISO") // No public + // .WithFlag(28, FieldMode.Read | FieldMode.Write, name: "ANALOG_FORCE_NOISO") // No public + // .WithFlag(29, FieldMode.Read | FieldMode.Write, name: "DG_WRAP_FORCE_RST") // digital wrap force reset in deep sleep + // .WithFlag(30, FieldMode.Read | FieldMode.Write, name: "DG_WRAP_FORCE_NORST") // digital core force no reset in deep sleep + // .WithFlag(31, FieldMode.Write, name: "SW_SYS_RST") // SW system reset + }, + {(long)Registers.CACHE_MMU_OWNER, new DoubleWordRegister(this) + .WithValueField(7, 2, FieldMode.Read | FieldMode.Write, name: "CACHE_MMU_OWNER") // The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, bit2: dma, bit3: reserved. + }, + {(long)Registers.DCACHE_FREEZE, new DoubleWordRegister(this) + .WithFlag(0, FieldMode.Read | FieldMode.Write, name: "ENA") // The bit is used to enable dcache freeze mode + .WithFlag(1, FieldMode.Read | FieldMode.Write, name: "MODE") // The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss + .WithFlag(2, FieldMode.Read, valueProviderCallback: (_) => true, name: "DONE") // The bit is used to indicate dcache freeze success + }, + {(long)Registers.ICACHE_FREEZE, new DoubleWordRegister(this) + .WithFlag(0, FieldMode.Read | FieldMode.Write, name: "ENA") // The bit is used to enable icache freeze mode + .WithFlag(1, FieldMode.Read | FieldMode.Write, name: "MODE") // The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss + .WithFlag(2, FieldMode.Read, valueProviderCallback: (_) => true, name: "DONE") // The bit is used to indicate icache freeze success + }, + }; + + registers = new DoubleWordRegisterCollection(this, registersMap); + } + + public uint ReadDoubleWord(long offset) + { + return registers.Read(offset); + } + + public byte ReadByte(long offset) + { + if (offset % 4 != 0) + { + // in the current configuration, only the lowest byte + // contains a meaningful data + return 0; + } + return (byte)ReadDoubleWord(offset); + } + + public void Reset() + { + // base.Reset(); + registers.Reset(); + + // UpdateInterrupts(); + } + + public void WriteDoubleWord(long offset, uint value) + { + registers.Write(offset, value); + } + + public void WriteByte(long offset, byte value) + { + if (offset % 4 != 0) + { + // in the current configuration, only the lowest byte + // contains a meaningful data + return; + } + + WriteDoubleWord(offset, value); + } + + public long Size => 0x17C; + private readonly DoubleWordRegisterCollection registers; + + private enum Registers : long + { + DCACHE_CTRL = 0x00, + DCACHE_CTRL1 = 0x04, + DCACHE_SYNC_CTRL = 0x28, + DCACHE_SYNC_ADDR = 0x2C, + DCACHE_SYNC_SIZE = 0x30, + DCACHE_PRELOAD_CTRL = 0x40, + DCACHE_AUTOLOAD_CTRL = 0x4C, + CACHE_ILG_INT_CLR = 0xE0, + CACHE_WRAP_AROUND_CTRL = 0x128, + CACHE_MMU_OWNER = 0x148, + DCACHE_FREEZE = 0x150, + ICACHE_FREEZE = 0x154, + } + } +} diff --git a/peripherals/ESP32S3_GPIO.cs b/peripherals/ESP32S3_GPIO.cs new file mode 100644 index 0000000..f76774c --- /dev/null +++ b/peripherals/ESP32S3_GPIO.cs @@ -0,0 +1,269 @@ +// +// Copyright (c) 2010-2021 Antmicro +// +// This file is licensed under the MIT License. +// Full license text is available in 'licenses/MIT.txt'. +// +using System.Collections.Generic; +using Antmicro.Renode.Core; +using Antmicro.Renode.Utilities; +using Antmicro.Renode.Peripherals.Bus; +using Antmicro.Renode.Core.Structure.Registers; +using Antmicro.Renode.Logging; + +namespace Antmicro.Renode.Peripherals.GPIOPort +{ + public class ESP32S3_GPIO : BaseGPIOPort, IDoubleWordPeripheral, IKnownSize + { + public ESP32S3_GPIO(Machine machine) : base(machine, NumberOfPins) + { + locker = new object(); + IRQ = new GPIO(); + registers = new DoubleWordRegisterCollection(this, BuildRegisterMap()); + data = new bool[NumberOfPins]; + directionOutNotIn = new bool[NumberOfPins]; + interruptEnabled = new bool[NumberOfPins]; + interruptRequest = new bool[NumberOfPins]; + edgeSelect = new bool[NumberOfPins]; + interruptConfig = new InterruptConfig[NumberOfPins]; + } + + public override void Reset() + { + lock(locker) + { + base.Reset(); + IRQ.Unset(); + registers.Reset(); + for(var i = 0; i < NumberOfPins; ++i) + { + data[i] = false; + directionOutNotIn[i] = false; + interruptEnabled[i] = false; + interruptRequest[i] = false; + edgeSelect[i] = false; + interruptConfig[i] = InterruptConfig.Low; + } + } + } + + public uint ReadDoubleWord(long offset) + { + lock(locker) + { + return registers.Read(offset); + } + } + + public void WriteDoubleWord(long offset, uint value) + { + lock(locker) + { + registers.Write(offset, value); + } + } + + public override void OnGPIO(int number, bool value) + { + // if(!CheckPinNumber(number)) + // { + // return; + // } + + // if(directionOutNotIn[number]) + // { + // this.Log(LogLevel.Warning, "gpio {0} is set to output, signal ignored.", number); + // return; + // } + + // lock(locker) + // { + // var previousState = State[number]; + // base.OnGPIO(number, value); + + // UpdateSingleInterruptRequest(number, value, previousState != value); + // UpdateIRQ(); + // } + } + + public long Size => 0x634; + + public GPIO IRQ { get; } + + private Dictionary BuildRegisterMap() + { + var registersDictionary = new Dictionary + { + {(long)Registers.STRAP, new DoubleWordRegister(this) + .WithFlag(2, FieldMode.Read, valueProviderCallback: (_) => !EnableBootMessages, name: "GPIO46") // GND = enable boot messages + .WithFlag(3, FieldMode.Read, valueProviderCallback: (_) => !EnterBootloader, name: "GPIO0") // GND = enter bootloader + .WithFlag(4, FieldMode.Read, valueProviderCallback: (_) => false, name: "GPIO45") // GND = VDD_SPI @ 3.3V + .WithFlag(5, FieldMode.Read, valueProviderCallback: (_) => false, name: "GPIO3") // GND = JTAG from pins, not USB + }, + // {(long)Registers.Data, new DoubleWordRegister(this) + // .WithFlags(0, NumberOfPins, name: "GR / GPIO data register", + // writeCallback: (id, _, val) => { data[id] = val; }, + // valueProviderCallback: (id, _) => + // { + // return (directionOutNotIn[id]) + // ? data[id] + // : State[id]; + // }) + // .WithWriteCallback((_, __) => UpdateConnections()) + // }, + // {(long)Registers.Direction, new DoubleWordRegister(this) + // .WithFlags(0, NumberOfPins, name: "GDIR / GPIO direction register", + // writeCallback: (id, _, val) => { directionOutNotIn[id] = val; }, + // valueProviderCallback: (id, _) => directionOutNotIn[id]) + // .WithWriteCallback((_, __) => UpdateConnections()) + // }, + // {(long)Registers.PadStatus, new DoubleWordRegister(this) + // .WithFlags(0, NumberOfPins, FieldMode.Read, name: "PSR / GPIO pad status register", + // valueProviderCallback: (id, _) => State[id]) + // }, + // {(long)Registers.Mask, new DoubleWordRegister(this) + // .WithFlags(0, NumberOfPins, name: "IMR / GPIO interrupt mask register", + // writeCallback: (id, _, val) => { interruptEnabled[id] = val; }, + // valueProviderCallback: (id, _) => interruptEnabled[id]) + // .WithWriteCallback((_, __) => UpdateIRQ()) + // }, + // {(long)Registers.Status, new DoubleWordRegister(this) + // .WithFlags(0, NumberOfPins, FieldMode.Read | FieldMode.WriteOneToClear, name: "ISR / GPIO interrupt status register", + // writeCallback: (id, _, val) => + // { + // if(val) + // { + // interruptRequest[id] = false; + // } + // }, + // valueProviderCallback: (id, _) => interruptRequest[id]) + // .WithWriteCallback((_, __) => UpdateIRQ()) + // }, + // {(long)Registers.EdgeSelect, new DoubleWordRegister(this) + // .WithFlags(0, NumberOfPins, name: "EDGE_SEL / GPIO edge select register", + // writeCallback: (id, _, val) => { edgeSelect[id] = val; }, + // valueProviderCallback: (id, _) => edgeSelect[id]) + // }, + // {(long)Registers.DataSet, new DoubleWordRegister(this) + // .WithFlags(0, NumberOfPins, FieldMode.Write, name: "DR_SET / GPIO data register SET", + // writeCallback: (id, _, __) => { data[id] = true; }) + // .WithWriteCallback((_, __) => UpdateConnections()) + // }, + // {(long)Registers.DataClear, new DoubleWordRegister(this) + // .WithFlags(0, NumberOfPins, FieldMode.Write, name: "DR_CLEAR / GPIO data register CLEAR", + // writeCallback: (id, _, __) => { data[id] = false; }) + // .WithWriteCallback((_, __) => UpdateConnections()) + // }, + // {(long)Registers.DataToggle, new DoubleWordRegister(this) + // .WithFlags(0, NumberOfPins, FieldMode.Write, name: "DR_TOGGLE / GPIO data register TOGGLE", + // writeCallback: (id, _, __) => { data[id] ^= true; }) + // .WithWriteCallback((_, __) => UpdateConnections()) + // }, + }; + + // var config1 = new DoubleWordRegister(this); + // var config2 = new DoubleWordRegister(this); + // var half = NumberOfPins / 2; + // for(var i = 0; i < half; ++i) + // { + // var j = i; + // config1.WithEnumField(j * 2, 2, + // name: $"ICR{j} / Interrupt configuration {j}", + // writeCallback: (_, val) => { interruptConfig[j] = val; }, + // valueProviderCallback: _ => interruptConfig[j]); + // config2.WithEnumField(j * 2, 2, + // name: $"ICR{half + j} / Interrupt configuration {half + j}", + // writeCallback: (_, val) => { interruptConfig[half + j] = val; }, + // valueProviderCallback: _ => interruptConfig[half + j]); + // } + // config1.WithWriteCallback((_, __) => UpdateAllInterruptRequests()); + // config2.WithWriteCallback((_, __) => UpdateAllInterruptRequests()); + // registersDictionary.Add((long)Registers.Config1, config1); + // registersDictionary.Add((long)Registers.Config2, config2); + return registersDictionary; + } + + private void UpdateIRQ() + { + var flag = false; + for(var i = 0; i < NumberOfPins; ++i) + { + flag |= interruptEnabled[i] && interruptRequest[i]; + } + IRQ.Set(flag); + } + + private void UpdateConnections() + { + for(var i = 0; i < NumberOfPins; ++i) + { + Connections[i].Set(directionOutNotIn[i] && data[i]); + } + UpdateIRQ(); + } + + private void UpdateAllInterruptRequests() + { + for(var i = 0; i < NumberOfPins; ++i) + { + UpdateSingleInterruptRequest(i, State[i]); + } + UpdateIRQ(); + } + + private void UpdateSingleInterruptRequest(int i, bool currentState, bool stateChanged = false) + { + if(edgeSelect[i]) + { + interruptRequest[i] |= stateChanged; + } + else + { + switch(interruptConfig[i]) + { + case InterruptConfig.Low: + interruptRequest[i] |= !currentState; + break; + case InterruptConfig.High: + interruptRequest[i] |= currentState; + break; + case InterruptConfig.Rising: + interruptRequest[i] |= stateChanged && currentState; + break; + case InterruptConfig.Falling: + interruptRequest[i] |= stateChanged && !currentState; + break; + default: + this.Log(LogLevel.Error, "Invalid state (interruptConfig[{0}]: 0x{1:X}).", i, interruptConfig[i]); + break; + } + } + } + + private readonly DoubleWordRegisterCollection registers; + private readonly object locker; + private readonly bool[] data; + private readonly bool[] directionOutNotIn; + private readonly bool[] interruptEnabled; + private readonly bool[] interruptRequest; + private readonly bool[] edgeSelect; + private readonly InterruptConfig[] interruptConfig; + public bool EnableBootMessages = true; + public bool EnterBootloader = false; + + private const int NumberOfPins = 54; + + private enum InterruptConfig + { + Low = 0b00, + High = 0b01, + Rising = 0b10, + Falling = 0b11, + } + + private enum Registers : long + { + STRAP = 0x38, + } + } +} diff --git a/peripherals/ESP32S3_RTC_CNTL.cs b/peripherals/ESP32S3_RTC_CNTL.cs new file mode 100644 index 0000000..acc6428 --- /dev/null +++ b/peripherals/ESP32S3_RTC_CNTL.cs @@ -0,0 +1,194 @@ +// +// Copyright (c) 2010-2023 Antmicro +// Copyright (c) 2011-2015 Realtime Embedded +// +// This file is licensed under the MIT License. +// Full license text is available in 'licenses/MIT.txt'. +// +using System; +using Antmicro.Renode.Peripherals.Bus; +using Antmicro.Renode.Core; +using Antmicro.Renode.Peripherals; +using Antmicro.Renode.Utilities; +using Antmicro.Renode.Logging; +using System.Collections.Generic; +using Antmicro.Renode.Core.Structure.Registers; + +namespace Antmicro.Renode.Peripherals.Miscellaneous +{ + public class ESP32S3_RTC_CNTL : IBytePeripheral, IDoubleWordPeripheral, IKnownSize + { + public ESP32S3_RTC_CNTL(Machine machine) + { + var registersMap = new Dictionary + { + {(long)Registers.OPTIONS0, new DoubleWordRegister(this) + .WithValueField(0, 2, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => 0, name: "SW_STALL_APPCPU_C0") // {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU + .WithValueField(2, 2, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => 0, name: "SW_STALL_PROCPU_C0") // {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU + .WithFlag(4, FieldMode.Read | FieldMode.Write, name: "SW_APPCPU_RST") // APP CPU SW reset + .WithFlag(5, FieldMode.Read | FieldMode.Write, name: "SW_PROCPU_RST") // PRO CPU SW reset + .WithFlag(6, FieldMode.Read | FieldMode.Write, name: "BB_I2C_FORCE_PD") // BB_I2C force power down + .WithFlag(7, FieldMode.Read | FieldMode.Write, name: "BB_I2C_FORCE_PU") // BB_I2C force power up + .WithFlag(8, FieldMode.Read | FieldMode.Write, name: "BBPLL_I2C_FORCE_PD") // BB_PLL _I2C force power down + .WithFlag(9, FieldMode.Read | FieldMode.Write, name: "BBPLL_I2C_FORCE_PU") // BB_PLL_I2C force power up + .WithFlag(10, FieldMode.Read | FieldMode.Write, name: "BBPLL_FORCE_PD") // BB_PLL force power down + .WithFlag(11, FieldMode.Read | FieldMode.Write, name: "BBPLL_FORCE_PU") // BB_PLL force power up + .WithFlag(12, FieldMode.Read | FieldMode.Write, name: "XTL_FORCE_PD") // crystall force power down + .WithFlag(13, FieldMode.Read | FieldMode.Write, name: "XTL_FORCE_PU") // crystall force power up + .WithValueField(14, 4, FieldMode.Read | FieldMode.Write, name: "XTL_EN_WAIT") // wait bias_sleep and current source wakeup + .WithFlag(23, FieldMode.Read | FieldMode.Write, name: "XTL_FORCE_ISO") // No public + .WithFlag(24, FieldMode.Read | FieldMode.Write, name: "PLL_FORCE_ISO") // No public + .WithFlag(25, FieldMode.Read | FieldMode.Write, name: "ANALOG_FORCE_ISO") // No public + .WithFlag(26, FieldMode.Read | FieldMode.Write, name: "XTL_FORCE_NOISO") // No public + .WithFlag(27, FieldMode.Read | FieldMode.Write, name: "PLL_FORCE_NOISO") // No public + .WithFlag(28, FieldMode.Read | FieldMode.Write, name: "ANALOG_FORCE_NOISO") // No public + .WithFlag(29, FieldMode.Read | FieldMode.Write, name: "DG_WRAP_FORCE_RST") // digital wrap force reset in deep sleep + .WithFlag(30, FieldMode.Read | FieldMode.Write, name: "DG_WRAP_FORCE_NORST") // digital core force no reset in deep sleep + .WithFlag(31, FieldMode.Write, name: "SW_SYS_RST") // SW system reset + }, + {(long)Registers.RESET_STATE, new DoubleWordRegister(this) + .WithValueField(0, 6, FieldMode.Read, valueProviderCallback: (_) => (ulong)ResetReason.POWERON, name: "RESET_CAUSE_PROCPU") + .WithValueField(6, 6, FieldMode.Read, valueProviderCallback: (_) => 1, name: "RESET_CAUSE_APPCPU") + .WithFlag(12, FieldMode.Read | FieldMode.Write, name: "APPCPU_STAT_VECTOR_SEL") + .WithFlag(13, FieldMode.Read | FieldMode.Write, name: "PROCPU_STAT_VECTOR_SEL") + .WithFlag(14, FieldMode.Read, valueProviderCallback: (_) => true, name: "RESET_FLAG_PROCPU") + .WithFlag(15, FieldMode.Read, valueProviderCallback: (_) => true, name: "RESET_FLAG_APPCPU") + .WithFlag(16, FieldMode.Write, name: "RESET_FLAG_PROCPU_CLR") + .WithFlag(17, FieldMode.Write, name: "RESET_FLAG_APPCPU_CLR") + .WithFlag(18, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => true, name: "PROCPU_OCD_HALT_ON_RESET") + .WithFlag(19, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => true, name: "RESET_FLAG_APPCPU") + .WithFlag(20, FieldMode.Read, valueProviderCallback: (_) => true, name: "RESET_FLAG_JTAG_PROCPU") + .WithFlag(21, FieldMode.Read, valueProviderCallback: (_) => true, name: "RESET_FLAG_JTAG_APPCPU") + .WithFlag(22, FieldMode.Write, name: "RESET_FLAG_JTAG_PROCPU_CLR") + .WithFlag(23, FieldMode.Write, name: "RESET_FLAG_JTAG_APPCPU_CLR") + .WithFlag(24, FieldMode.Read | FieldMode.Write, name: "APP_DRESET_MASK") + .WithFlag(25, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => true, name: "PRO_DRESET_MASK") + }, + {(long)Registers.PWC, new DoubleWordRegister(this) + .WithValueField(0, 32) + }, + {(long)Registers.DIG_ISO, new DoubleWordRegister(this) + .WithValueField(0, 32) + }, + {(long)Registers.SWD_CONF, new DoubleWordRegister(this) + .WithValueField(0, 32) + }, + {(long)Registers.STORE4, new DoubleWordRegister(this) + .WithValueField(0, 32, name: "SCRATCH4") + }, + {(long)Registers.DIG_PAD_HOLD, new DoubleWordRegister(this) + .WithValueField(0, 32) + }, + // {(long)Registers.STATUS, new DoubleWordRegister(this) + // .WithValueField(0, 10, FieldMode.Read, name: "RXFIFO_CNT") + // .WithFlag(13, FieldMode.Read, name: "UART_DSRN") + // .WithFlag(14, FieldMode.Read, valueProviderCallback: (_) => true, name: "UART_CTSN") + // .WithFlag(15, FieldMode.Read, valueProviderCallback: (_) => true, name: "UART_RXD") + // .WithValueField(16, 10, FieldMode.Read, name: "TXFIFO_CNT") + // .WithFlag(29, FieldMode.Read, valueProviderCallback: (_) => true, name: "UART_DTRN") + // .WithFlag(30, FieldMode.Read, valueProviderCallback: (_) => true, name: "UART_RTSN") + // .WithFlag(31, FieldMode.Read, valueProviderCallback: (_) => true, name: "UART_TXD") + // }, + // {(long)Registers.TxFull, new DoubleWordRegister(this) + // .WithFlag(0, FieldMode.Read) //tx is never full + // }, + // {(long)Registers.RxEmpty, new DoubleWordRegister(this) + // .WithFlag(0, FieldMode.Read, valueProviderCallback: _ => Count == 0) + // }, + // {(long)Registers.EventPending, new DoubleWordRegister(this) + // // `txEventPending` implements `WriteOneToClear` semantics to avoid fake warnings + // // `txEventPending` is generated on the falling edge of TxFull; in our case it means never + // .WithFlag(0, FieldMode.Read | FieldMode.WriteOneToClear, valueProviderCallback: _ => false, name: "txEventPending") + // .WithFlag(1, out rxEventPending, FieldMode.Read | FieldMode.WriteOneToClear, name: "rxEventPending") + // .WithWriteCallback((_, __) => UpdateInterrupts()) + // }, + // {(long)Registers.EventEnable, new DoubleWordRegister(this) + // .WithFlag(0, name: "txEventEnabled") + // .WithFlag(1, out rxEventEnabled) + // .WithWriteCallback((_, __) => UpdateInterrupts()) + // }, + }; + + registers = new DoubleWordRegisterCollection(this, registersMap); + } + + public uint ReadDoubleWord(long offset) + { + return registers.Read(offset); + } + + public byte ReadByte(long offset) + { + if (offset % 4 != 0) + { + // in the current configuration, only the lowest byte + // contains a meaningful data + return 0; + } + return (byte)ReadDoubleWord(offset); + } + + public void Reset() + { + // base.Reset(); + registers.Reset(); + + // UpdateInterrupts(); + } + + public void WriteDoubleWord(long offset, uint value) + { + registers.Write(offset, value); + } + + public void WriteByte(long offset, byte value) + { + if (offset % 4 != 0) + { + // in the current configuration, only the lowest byte + // contains a meaningful data + return; + } + + WriteDoubleWord(offset, value); + } + + public long Size => 0x15C; + private readonly DoubleWordRegisterCollection registers; + + private enum Registers : long + { + OPTIONS0 = 0x00, // RTC common configure register + RESET_STATE = 0x38, // get reset state + PWC = 0x88, // configure rtc power + DIG_ISO = 0x94, // congigure digital power isolation + SWD_CONF = 0xB4, // congfigure super watch dog + STORE4 = 0xC0, // reserved register + DIG_PAD_HOLD = 0xDC, // configure digtal pad hold + } + + private enum ResetReason : long + { + POWERON = 0x01, + JTAG = 0x02, + RTC_SW_SYS_RST = 0x03, + DSLEEP = 0x05, + TG0WDT_SYS_RST = 0x07, + TG1WDT_SYS_RST = 0x08, + RTCWDT_SYS_RST = 0x09, + INTRUSION_RST = 0x0A, + TG0WDT_CPU_RST = 0x0B, + RTC_SW_CPU_RST = 0x0C, + RTCWDT_CPU_RST = 0x0D, + BROWNOUT_RST = 0x0F, + RTCWDT_RTC_RST = 0x10, + TG01DT_CPU_RST = 0x11, + SUPER_WDT_RST = 0x12, + GLITCH_RTC_RST = 0x13, + EFUSE_RST = 0x14, + USB_UART_CHIP_RESET = 0x15, + USB_JTAG_CHIP_RESET = 0x16, + POWER_GLITCH_RESET = 0x17, + } + } +} diff --git a/peripherals/ESP32_SPIController.cs b/peripherals/ESP32_SPIController.cs new file mode 100644 index 0000000..70a424e --- /dev/null +++ b/peripherals/ESP32_SPIController.cs @@ -0,0 +1,435 @@ +using System.Linq; +using System.Collections.Generic; +using Antmicro.Renode.Core; +using Antmicro.Renode.Core.Structure; +using Antmicro.Renode.Core.Structure.Registers; +using Antmicro.Renode.Logging; +using Antmicro.Renode.Peripherals.Bus; +using Antmicro.Renode.Peripherals.Memory; +using Antmicro.Renode.Peripherals.MTD; + +namespace Antmicro.Renode.Peripherals.SPI +{ + public class ESP32_SPIController : NullRegistrationPointPeripheralContainer, IDoubleWordPeripheral, IProvidesRegisterCollection, IKnownSize + { + public GPIO IRQ { get; private set; } + public DoubleWordRegisterCollection RegistersCollection { get; } + public long Size => 0x1000; // 0xb4 + private readonly Machine machine; + + public ESP32_SPIController(Machine machine) : base(machine) + { + this.machine = machine; + + IRQ = new GPIO(); + + RegistersCollection = new DoubleWordRegisterCollection(this); + DefineRegisters(); + Reset(); + } + + private void DefineRegisters() + { + // SPI1 memory command register + Registers.CMD.Define(this, 0x0) + .WithFlag(17, FieldMode.Read | FieldMode.Write, name: "FLASH_PE") // In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with SPI_MEM_USR bit. The bit will be cleared once the operation done.1: enable 0: disable. + .WithFlag(18, FieldMode.Read | FieldMode.Write, name: "USR") // User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + .WithFlag(19, FieldMode.Read | FieldMode.Write, name: "FLASH_HPM") // Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. + .WithFlag(20, FieldMode.Read | FieldMode.Write, name: "FLASH_RES") // This bit combined with SPI_MEM_RESANDRES bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. + .WithFlag(21, FieldMode.Read | FieldMode.Write, name: "FLASH_DP") // Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + .WithFlag(22, FieldMode.Read | FieldMode.Write, name: "FLASH_CE") // Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + .WithFlag(23, FieldMode.Read | FieldMode.Write, name: "FLASH_BE") // Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + .WithFlag(24, FieldMode.Read | FieldMode.Write, name: "FLASH_SE") // Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + .WithFlag(25, FieldMode.Read | FieldMode.Write, name: "FLASH_PP") // Page program enable(1 byte ~64 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. + .WithFlag(26, FieldMode.Read | FieldMode.Write, name: "FLASH_WRSR") // Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + .WithFlag(27, FieldMode.Read | FieldMode.Write, name: "FLASH_RDSR") // Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + .WithFlag(28, FieldMode.Read | FieldMode.Write, name: "FLASH_RDID") // Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + .WithFlag(29, FieldMode.Read | FieldMode.Write, name: "FLASH_WRDI") // Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + .WithFlag(30, FieldMode.Read | FieldMode.Write, name: "FLASH_WREN") // Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + .WithFlag(31, FieldMode.Read | FieldMode.Write, name: "FLASH_READ") // Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + ; + + // SPI1 address register + Registers.ADDR.Define(this, 0x0) + .WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "USR_ADDR_VALUE") // In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer. + ; + + // SPI1 control register + Registers.CTRL.Define(this, 0x2ca000) + .WithFlag(3, FieldMode.Read | FieldMode.Write, name: "FDUMMY_OUT") // In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller. + .WithFlag(4, FieldMode.Read | FieldMode.Write, name: "FDOUT_OCT") // Set this bit to enable 8-bit-mode(8-bm) in DOUT phase. + .WithFlag(5, FieldMode.Read | FieldMode.Write, name: "FDIN_OCT") // Set this bit to enable 8-bit-mode(8-bm) in DIN phase. + .WithFlag(6, FieldMode.Read | FieldMode.Write, name: "FADDR_OCT") // Set this bit to enable 8-bit-mode(8-bm) in ADDR phase. + .WithFlag(7, FieldMode.Read | FieldMode.Write, name: "FCMD_DUAL") // Set this bit to enable 2-bit-mode(2-bm) in CMD phase. + .WithFlag(8, FieldMode.Read | FieldMode.Write, name: "FCMD_QUAD") // Set this bit to enable 4-bit-mode(4-bm) in CMD phase. + .WithFlag(9, FieldMode.Read | FieldMode.Write, name: "FCMD_OCT") // Set this bit to enable 8-bit-mode(8-bm) in CMD phase. + .WithFlag(10, FieldMode.Read | FieldMode.Write, name: "FCS_CRC_EN") // For SPI1, initialize crc32 module before writing encrypted data to flash. Active low. + .WithFlag(11, FieldMode.Read | FieldMode.Write, name: "TX_CRC_EN") // For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + .WithFlag(13, FieldMode.Read | FieldMode.Write, name: "FASTRD_MODE") // This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set. + .WithFlag(14, FieldMode.Read | FieldMode.Write, name: "FREAD_DUAL") // In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable. + .WithFlag(15, FieldMode.Read | FieldMode.Write, name: "RESANDRES") // The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. + .WithFlag(18, FieldMode.Read | FieldMode.Write, name: "Q_POL") // The bit is used to set MISO line polarity, 1: high 0, low + .WithFlag(19, FieldMode.Read | FieldMode.Write, name: "D_POL") // The bit is used to set MOSI line polarity, 1: high 0, low + .WithFlag(20, FieldMode.Read | FieldMode.Write, name: "FREAD_QUAD") // In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. + .WithFlag(21, FieldMode.Read | FieldMode.Write, name: "WP") // Write protect signal output when SPI is idle. 1: output high, 0: output low. + .WithFlag(22, FieldMode.Read | FieldMode.Write, name: "WRSR_2B") // Two bytes data will be written to status register when it is set. 1: enable 0: disable. + .WithFlag(23, FieldMode.Read | FieldMode.Write, name: "FREAD_DIO") // In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable. + .WithFlag(24, FieldMode.Read | FieldMode.Write, name: "FREAD_QIO") // In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. + ; + + // SPI1 control1 register + Registers.CTRL1.Define(this, 0xffc) + .WithValueField(0, 2, FieldMode.Read | FieldMode.Write, name: "CLK_MODE") // SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on. + .WithValueField(2, 10, FieldMode.Read | FieldMode.Write, name: "CS_HOLD_DLY_RES") // After RES/DP/HPM/PES/PER command is sent, SPI1 may waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or * 256) SPI_CLK cycles. + ; + + // SPI1 control2 register + Registers.CTRL2.Define(this, 0x0) + .WithFlag(31, FieldMode.Read | FieldMode.Write, name: "SYNC_RESET") // The FSM will be reset. + ; + + // SPI_CLK clock division register when SPI1 accesses to flash or Ext_RAM. + Registers.CLOCK.Define(this, 0x30103) + .WithValueField(0, 8, FieldMode.Read | FieldMode.Write, name: "CLKCNT_L") // It must equal to the value of SPI_MEM_CLKCNT_N. + .WithValueField(8, 8, FieldMode.Read | FieldMode.Write, name: "CLKCNT_H") // It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1). + .WithValueField(16, 8, FieldMode.Read | FieldMode.Write, name: "CLKCNT_N") // When SPI1 accesses to flash or Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLKCNT_N+1) + .WithFlag(31, FieldMode.Read | FieldMode.Write, name: "CLK_EQU_SYSCLK") // When SPI1 access to flash or Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK. + ; + + // SPI1 user register. + Registers.USER.Define(this, 0x80000000) + .WithFlag(9, FieldMode.Read | FieldMode.Write, name: "CK_OUT_EDGE") // This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK. + .WithFlag(12, FieldMode.Read | FieldMode.Write, name: "FWRITE_DUAL") // Set this bit to enable 2-bm in DOUT phase in SPI1 write operation. + .WithFlag(13, FieldMode.Read | FieldMode.Write, name: "FWRITE_QUAD") // Set this bit to enable 4-bm in DOUT phase in SPI1 write operation. + .WithFlag(14, FieldMode.Read | FieldMode.Write, name: "FWRITE_DIO") // Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 write operation. + .WithFlag(15, FieldMode.Read | FieldMode.Write, name: "FWRITE_QIO") // Set this bit to enable 4-bit-mode(4-bm) in ADDR and DOUT phase in SPI1 write operation. + .WithFlag(24, FieldMode.Read | FieldMode.Write, name: "USR_MISO_HIGHPART") // DIN phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable. + .WithFlag(25, FieldMode.Read | FieldMode.Write, name: "USR_MOSI_HIGHPART") // DOUT phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable. + .WithFlag(26, FieldMode.Read | FieldMode.Write, name: "USR_DUMMY_IDLE") // SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable. + .WithFlag(27, FieldMode.Read | FieldMode.Write, name: "USR_MOSI") // Set this bit to enable the DOUT phase of an write-data operation. + .WithFlag(28, FieldMode.Read | FieldMode.Write, name: "USR_MISO") // Set this bit to enable enable the DIN phase of a read-data operation. + .WithFlag(29, FieldMode.Read | FieldMode.Write, name: "USR_DUMMY") // Set this bit to enable enable the DUMMY phase of an operation. + .WithFlag(30, FieldMode.Read | FieldMode.Write, name: "USR_ADDR") // Set this bit to enable enable the ADDR phase of an operation. + .WithFlag(31, FieldMode.Read | FieldMode.Write, name: "USR_COMMAND") // Set this bit to enable enable the CMD phase of an operation. + ; + + // SPI1 user1 register. + Registers.USER1.Define(this, 0x5c000007) + .WithValueField(0, 6, FieldMode.Read | FieldMode.Write, name: "USR_DUMMY_CYCLELEN") // The SPI_CLK cycle length minus 1 of DUMMY phase. + .WithValueField(26, 6, FieldMode.Read | FieldMode.Write, name: "USR_ADDR_BITLEN") // The length in bits of ADDR phase. The register value shall be (bit_num-1). + ; + + // SPI1 user2 register. + Registers.USER2.Define(this, 0x70000000) + .WithValueField(0, 16, FieldMode.Read | FieldMode.Write, name: "USR_COMMAND_VALUE") // The value of user defined(USR) command. + .WithValueField(28, 4, FieldMode.Read | FieldMode.Write, name: "USR_COMMAND_BITLEN") // The length in bits of CMD phase. The register value shall be (bit_num-1) + ; + + // SPI1 write-data bit length register. + Registers.MOSI_DLEN.Define(this, 0x0) + .WithValueField(0, 10, FieldMode.Read | FieldMode.Write, name: "USR_MOSI_DBITLEN") // The length in bits of DOUT phase. The register value shall be (bit_num-1). + ; + + // SPI1 read-data bit length register. + Registers.MISO_DLEN.Define(this, 0x0) + .WithValueField(0, 10, FieldMode.Read | FieldMode.Write, name: "USR_MISO_DBITLEN") // The length in bits of DIN phase. The register value shall be (bit_num-1). + ; + + // SPI1 read control register. + Registers.RD_STATUS.Define(this, 0x0) + .WithValueField(0, 16, FieldMode.Read | FieldMode.Write, name: "STATUS") // The value is stored when set SPI_MEM_FLASH_RDSR bit and SPI_MEM_FLASH_RES bit. + .WithValueField(16, 8, FieldMode.Read | FieldMode.Write, name: "WB_MODE") // Mode bits in the flash fast read mode it is combined with SPI_MEM_FASTRD_MODE bit. + ; + + // SPI1 extended address register. + Registers.EXT_ADDR.Define(this, 0x0) + .WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "EXT_ADDR") // The register are the higher 32bits in the 64 bits address mode. + ; + + // SPI1 misc register. + Registers.MISC.Define(this, 0x2) + .WithFlag(0, FieldMode.Read | FieldMode.Write, name: "CS0_DIS") // Set this bit to raise high SPI_CS pin, which means that the SPI device(flash) connected to SPI_CS is in low level when SPI1 transfer starts. + .WithFlag(1, FieldMode.Read | FieldMode.Write, name: "CS1_DIS") // Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM) connected to SPI_CS1 is in low level when SPI1 transfer starts. + .WithFlag(9, FieldMode.Read | FieldMode.Write, name: "CK_IDLE_EDGE") // 1: SPI_CLK line is high when MSPI is idle. 0: SPI_CLK line is low when MSPI is idle. + .WithFlag(10, FieldMode.Read | FieldMode.Write, name: "CS_KEEP_ACTIVE") // SPI_CS line keep low when the bit is set. + .WithFlag(11, FieldMode.Read | FieldMode.Write, name: "AUTO_PER") // Set this bit to enable auto PER function. Hardware will sent out PER command if PES command is sent. + ; + + // SPI1 CRC data register. + Registers.TX_CRC.Define(this, 0xffffffff) + .WithValueField(0, 32, FieldMode.Read, name: "DATA") // For SPI1, the value of crc32. + ; + + // SPI1 bit mode control register. + Registers.CACHE_FCTRL.Define(this, 0x0) + .WithFlag(1, FieldMode.Read | FieldMode.Write, name: "CACHE_USR_CMD_4BYTE") // Set this bit to enable SPI1 transfer with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31. + .WithFlag(3, FieldMode.Read | FieldMode.Write, name: "FDIN_DUAL") // When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DIN phase. + .WithFlag(4, FieldMode.Read | FieldMode.Write, name: "FDOUT_DUAL") // When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DOUT phase. + .WithFlag(5, FieldMode.Read | FieldMode.Write, name: "FADDR_DUAL") // When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in ADDR phase. + .WithFlag(6, FieldMode.Read | FieldMode.Write, name: "FDIN_QUAD") // When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DIN phase. + .WithFlag(7, FieldMode.Read | FieldMode.Write, name: "FDOUT_QUAD") // When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DOUT phase. + .WithFlag(8, FieldMode.Read | FieldMode.Write, name: "FADDR_QUAD") // When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in ADDR phase. + ; + + // SPI1 state machine(FSM) status register. + Registers.FSM.Define(this, 0x0) + .WithValueField(0, 3, FieldMode.Read, name: "ST") // The status of SPI1 state machine. 0: idle state(IDLE), 1: preparation state(PREP), 2: send command state(CMD), 3: send address state(ADDR), 4: red data state(DIN), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE). + ; + + // SPI1 memory data buffer0 + Registers.W0.Define(this, 0x0) + .WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF0") // data buffer + ; + + // SPI1 memory data buffer1 + Registers.W1.Define(this, 0x0) + .WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF1") // data buffer + ; + + // SPI1 memory data buffer2 + Registers.W2.Define(this, 0x0) + .WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF2") // data buffer + ; + + // SPI1 memory data buffer3 + Registers.W3.Define(this, 0x0) + .WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF3") // data buffer + ; + + // SPI1 memory data buffer4 + Registers.W4.Define(this, 0x0) + .WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF4") // data buffer + ; + + // SPI1 memory data buffer5 + Registers.W5.Define(this, 0x0) + .WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF5") // data buffer + ; + + // SPI1 memory data buffer6 + Registers.W6.Define(this, 0x0) + .WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF6") // data buffer + ; + + // SPI1 memory data buffer7 + Registers.W7.Define(this, 0x0) + .WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF7") // data buffer + ; + + // SPI1 memory data buffer8 + Registers.W8.Define(this, 0x0) + .WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF8") // data buffer + ; + + // SPI1 memory data buffer9 + Registers.W9.Define(this, 0x0) + .WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF9") // data buffer + ; + + // SPI1 memory data buffer10 + Registers.W10.Define(this, 0x0) + .WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF10") // data buffer + ; + + // SPI1 memory data buffer11 + Registers.W11.Define(this, 0x0) + .WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF11") // data buffer + ; + + // SPI1 memory data buffer12 + Registers.W12.Define(this, 0x0) + .WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF12") // data buffer + ; + + // SPI1 memory data buffer13 + Registers.W13.Define(this, 0x0) + .WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF13") // data buffer + ; + + // SPI1 memory data buffer14 + Registers.W14.Define(this, 0x0) + .WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF14") // data buffer + ; + + // SPI1 memory data buffer15 + Registers.W15.Define(this, 0x0) + .WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF15") // data buffer + ; + + // SPI1 wait idle control register + Registers.FLASH_WAITI_CTRL.Define(this, 0x14) + .WithFlag(0, FieldMode.Read | FieldMode.Write, name: "WAITI_EN") // Set this bit to enable auto-waiting flash idle operation when PP/SE/BE/CE/WRSR/PES command is sent. + .WithFlag(1, FieldMode.Read | FieldMode.Write, name: "WAITI_DUMMY") // Set this bit to enable DUMMY phase in auto wait flash idle transfer(RDSR). + .WithValueField(2, 8, FieldMode.Read | FieldMode.Write, name: "WAITI_CMD") // The command value of auto wait flash idle transfer(RDSR). + .WithValueField(10, 6, FieldMode.Read | FieldMode.Write, name: "WAITI_DUMMY_CYCLELEN") // The dummy cycle length when wait flash idle(RDSR). + ; + + // SPI1 flash suspend control register + Registers.FLASH_SUS_CMD.Define(this, 0x0) + .WithFlag(0, FieldMode.Read | FieldMode.Write, name: "FLASH_PER") // program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + .WithFlag(1, FieldMode.Read | FieldMode.Write, name: "FLASH_PES") // program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + .WithFlag(2, FieldMode.Read | FieldMode.Write, name: "FLASH_PER_WAIT_EN") // Set this bit to add delay time after program erase resume(PER) is sent. + .WithFlag(3, FieldMode.Read | FieldMode.Write, name: "FLASH_PES_WAIT_EN") // Set this bit to add delay time after program erase suspend(PES) command is sent. + .WithFlag(4, FieldMode.Read | FieldMode.Write, name: "PES_PER_EN") // Set this bit to enable PES transfer trigger PES transfer option. + .WithFlag(5, FieldMode.Read | FieldMode.Write, name: "PESR_IDLE_EN") // 1: Separate PER flash wait idle and PES flash wait idle. 0: Not separate. + ; + + // SPI1 flash suspend command register + Registers.FLASH_SUS_CTRL.Define(this, 0xeaf4) + .WithFlag(0, FieldMode.Read | FieldMode.Write, name: "FLASH_PES_EN") // Set this bit to enable auto-suspend function. + .WithValueField(1, 8, FieldMode.Read | FieldMode.Write, name: "FLASH_PER_COMMAND") // Program/Erase resume command value. + .WithValueField(9, 8, FieldMode.Read | FieldMode.Write, name: "FLASH_PES_COMMAND") // Program/Erase suspend command value. + ; + + // SPI1 flash suspend status register + Registers.SUS_STATUS.Define(this, 0x0) + .WithFlag(0, FieldMode.Read | FieldMode.Write, name: "FLASH_SUS") // The status of flash suspend. This bit is set when PES command is sent, and cleared when PER is sent. Only used in SPI1. + .WithFlag(2, FieldMode.Read | FieldMode.Write, name: "FLASH_HPM_DLY_256") // 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent. + .WithFlag(3, FieldMode.Read | FieldMode.Write, name: "FLASH_RES_DLY_256") // 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent. + .WithFlag(4, FieldMode.Read | FieldMode.Write, name: "FLASH_DP_DLY_256") // 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent. + .WithFlag(5, FieldMode.Read | FieldMode.Write, name: "FLASH_PER_DLY_256") // Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent. + .WithFlag(6, FieldMode.Read | FieldMode.Write, name: "FLASH_PES_DLY_256") // Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent. + ; + + // SPI1 timing compensation register when accesses to flash or Ext_RAM. + Registers.TIMING_CALI.Define(this, 0x0) + .WithFlag(1, FieldMode.Read | FieldMode.Write, name: "TIMING_CALI") // Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations. + .WithValueField(2, 3, FieldMode.Read | FieldMode.Write, name: "EXTRA_DUMMY_CYCLELEN") // Extra SPI_CLK cycles added in DUMMY phase for timing compensation. Active when SPI_MEM_TIMING_CALI bit is set. + ; + + // SPI1 DDR control register + Registers.DDR.Define(this, 0x20) + .WithFlag(0, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_DDR_EN") // 1: in DDR mode, 0: in SDR mode. + .WithFlag(1, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_VAR_DUMMY") // Set the bit to enable variable dummy cycle in DDRmode. + .WithFlag(2, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_DDR_RDAT_SWP") // Set the bit to reorder RX data of the word in DDR mode. + .WithFlag(3, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_DDR_WDAT_SWP") // Set the bit to reorder TX data of the word in DDR mode. + .WithFlag(4, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_DDR_CMD_DIS") // the bit is used to disable dual edge in command phase when DDR mode. + .WithValueField(5, 7, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_OUTMINBYTELEN") // It is the minimum output data length in the panda device. + .WithValueField(14, 7, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_USR_DDR_DQS_THD") // The delay number of data strobe which from memory based on SPI_CLK. + .WithFlag(21, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_DDR_DQS_LOOP") // 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module + .WithFlag(22, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_DDR_DQS_LOOP_MODE") // When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active. + .WithFlag(24, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_CLK_DIFF_EN") // Set this bit to enable the differential SPI_CLK#. + .WithFlag(25, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_HYPERBUS_MODE") // Set this bit to enable the SPI HyperBus mode. + .WithFlag(26, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_DQS_CA_IN") // Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + .WithFlag(27, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_HYPERBUS_DUMMY_2X") // Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. + .WithFlag(28, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_CLK_DIFF_INV") // Set this bit to invert SPI_DIFF when accesses to flash. . + .WithFlag(29, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_OCTA_RAM_ADDR") // Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + .WithFlag(30, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_HYPERBUS_CA") // Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + ; + + // SPI1 clk_gate register + Registers.CLOCK_GATE.Define(this, 0x1) + .WithFlag(0, FieldMode.Read | FieldMode.Write, name: "CLK_EN") // Register clock gate enable signal. 1: Enable. 0: Disable. + ; + + // SPI1 interrupt enable register + Registers.INT_ENA.Define(this, 0x0) + .WithFlag(0, FieldMode.Read | FieldMode.Write, name: "PER_END_INT_ENA") // The enable bit for SPI_MEM_PER_END_INT interrupt. + .WithFlag(1, FieldMode.Read | FieldMode.Write, name: "PES_END_INT_ENA") // The enable bit for SPI_MEM_PES_END_INT interrupt. + .WithFlag(2, FieldMode.Read | FieldMode.Write, name: "TOTAL_TRANS_END_INT_ENA") // The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + .WithFlag(3, FieldMode.Read | FieldMode.Write, name: "BROWN_OUT_INT_ENA") // The enable bit for SPI_MEM_BROWN_OUT_INT interrupt. + ; + + // SPI1 interrupt clear register + Registers.INT_CLR.Define(this, 0x0) + .WithFlag(0, FieldMode.Write, name: "PER_END_INT_CLR") // The clear bit for SPI_MEM_PER_END_INT interrupt. + .WithFlag(1, FieldMode.Write, name: "PES_END_INT_CLR") // The clear bit for SPI_MEM_PES_END_INT interrupt. + .WithFlag(2, FieldMode.Write, name: "TOTAL_TRANS_END_INT_CLR") // The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + .WithFlag(3, FieldMode.Write, name: "BROWN_OUT_INT_CLR") // The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + ; + + // SPI1 interrupt raw register + Registers.INT_RAW.Define(this, 0x0) + .WithFlag(0, FieldMode.Read | FieldMode.Write, name: "PER_END_INT_RAW") // The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others. + .WithFlag(1, FieldMode.Read | FieldMode.Write, name: "PES_END_INT_RAW") // The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others. + .WithFlag(2, FieldMode.Read | FieldMode.Write, name: "TOTAL_TRANS_END_INT_RAW") // The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 transfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success. 0: Others. + .WithFlag(3, FieldMode.Read | FieldMode.Write, name: "BROWN_OUT_INT_RAW") // The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others. + ; + + // SPI1 interrupt status register + Registers.INT_ST.Define(this, 0x0) + .WithFlag(0, FieldMode.Read, name: "PER_END_INT_ST") // The status bit for SPI_MEM_PER_END_INT interrupt. + .WithFlag(1, FieldMode.Read, name: "PES_END_INT_ST") // The status bit for SPI_MEM_PES_END_INT interrupt. + .WithFlag(2, FieldMode.Read, name: "TOTAL_TRANS_END_INT_ST") // The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + .WithFlag(3, FieldMode.Read, name: "BROWN_OUT_INT_ST") // The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + ; + + // SPI0 version control register + Registers.DATE.Define(this, 0x2101040) + .WithValueField(0, 28, FieldMode.Read | FieldMode.Write, name: "DATE") // SPI register version. + ; + + } + + public override void Reset() + { + RegistersCollection.Reset(); + UpdateInterrupts(); + } + + public uint ReadDoubleWord(long offset) + { + return RegistersCollection.Read(offset); + } + + public void WriteDoubleWord(long offset, uint value) + { + RegistersCollection.Write(offset, value); + } + private void UpdateInterrupts() + { + var status = false; + this.Log(LogLevel.Noisy, "Setting IRQ to {0}", status); + IRQ.Set(status); + } + + private enum Registers + { + CMD = 0x0, + ADDR = 0x4, + CTRL = 0x8, + CTRL1 = 0xc, + CTRL2 = 0x10, + CLOCK = 0x14, + USER = 0x18, + USER1 = 0x1c, + USER2 = 0x20, + MOSI_DLEN = 0x24, + MISO_DLEN = 0x28, + RD_STATUS = 0x2c, + EXT_ADDR = 0x30, + MISC = 0x34, + TX_CRC = 0x38, + CACHE_FCTRL = 0x3c, + FSM = 0x54, + W0 = 0x58, + W1 = 0x5c, + W2 = 0x60, + W3 = 0x64, + W4 = 0x68, + W5 = 0x6c, + W6 = 0x70, + W7 = 0x74, + W8 = 0x78, + W9 = 0x7c, + W10 = 0x80, + W11 = 0x84, + W12 = 0x88, + W13 = 0x8c, + W14 = 0x90, + W15 = 0x94, + FLASH_WAITI_CTRL = 0x98, + FLASH_SUS_CMD = 0x9c, + FLASH_SUS_CTRL = 0xa0, + SUS_STATUS = 0xa4, + TIMING_CALI = 0xa8, + DDR = 0xe0, + CLOCK_GATE = 0xe8, + INT_ENA = 0xf0, + INT_CLR = 0xf4, + INT_RAW = 0xf8, + INT_ST = 0xfc, + DATE = 0x3fc, + } + } +} diff --git a/peripherals/ESP32_UART.cs b/peripherals/ESP32_UART.cs new file mode 100644 index 0000000..ef47cec --- /dev/null +++ b/peripherals/ESP32_UART.cs @@ -0,0 +1,214 @@ +// +// Copyright (c) 2010-2018 Antmicro +// +// This file is licensed under the MIT License. +// Full license text is available in 'licenses/MIT.txt'. +// +using System.Collections.Generic; +using Antmicro.Renode.Peripherals.Bus; +using Antmicro.Renode.Core.Structure.Registers; +using Antmicro.Renode.Core; +using Antmicro.Renode.Logging; + +namespace Antmicro.Renode.Peripherals.UART +{ + public class ESP32_UART : UARTBase, IDoubleWordPeripheral, IBytePeripheral, IKnownSize + { + public ESP32_UART(Machine machine) : base(machine) + { + IRQ = new GPIO(); + var registersMap = new Dictionary + { + {(long)Registers.FIFO, new DoubleWordRegister(this) + .WithValueField(0, 8, writeCallback: (_, value) => this.TransmitCharacter((byte)value), + valueProviderCallback: _ => { + if(!TryGetCharacter(out var character)) + { + this.Log(LogLevel.Warning, "Trying to read from an empty FIFO."); + } + return character; + }) + }, + {(long)Registers.INT_ENA, new DoubleWordRegister(this) + .WithFlag(0, FieldMode.Write, name: "UART_RXFIFO_FULL_INT_ENA") + }, + {(long)Registers.INT_CLR, new DoubleWordRegister(this) + .WithValueField(0, 32, FieldMode.Write) // Temporary hack + }, + {(long)Registers.RX_FILT, new DoubleWordRegister(this) + .WithValueField(0, 8, FieldMode.Read | FieldMode.Write, name: "GLITCH_FILT") // when input pulse width is lower than this value, the pulse is ignored. + .WithFlag(8, FieldMode.Read | FieldMode.Write, name: "GLITCH_FILT_EN") // Set this bit to enable Rx signal filter. + }, + {(long)Registers.STATUS, new DoubleWordRegister(this) + .WithValueField(0, 10, FieldMode.Read, name: "RXFIFO_CNT") + .WithFlag(13, FieldMode.Read, name: "UART_DSRN") + .WithFlag(14, FieldMode.Read, valueProviderCallback: (_) => true, name: "UART_CTSN") + .WithFlag(15, FieldMode.Read, valueProviderCallback: (_) => true, name: "UART_RXD") + .WithValueField(16, 10, FieldMode.Read, name: "TXFIFO_CNT") + .WithFlag(29, FieldMode.Read, valueProviderCallback: (_) => true, name: "UART_DTRN") + .WithFlag(30, FieldMode.Read, valueProviderCallback: (_) => true, name: "UART_RTSN") + .WithFlag(31, FieldMode.Read, valueProviderCallback: (_) => true, name: "UART_TXD") + }, + {(long)Registers.CONF0, new DoubleWordRegister(this) + .WithFlag(0, FieldMode.Write, name: "UART_PARITY") + .WithFlag(1, FieldMode.Write, name: "UART_PARITY_EN") + .WithValueField(2, 2, FieldMode.Read, name: "UART_BIT_NUM") + .WithValueField(4, 2, FieldMode.Read, name: "UART_STOPBIT_NUM") + .WithFlag(17, FieldMode.Write, name: "UART_RXFIFO_RST") + .WithFlag(18, FieldMode.Write, name: "UART_TXFIFO_RST") + .WithFlag(26, FieldMode.Write, name: "UART_ERR_WR_MASK") + .WithFlag(27, FieldMode.Write, name: "UART_AUTOBAUD_EN") + }, + {(long)Registers.CONF1, new DoubleWordRegister(this) + .WithValueField(0, 10, FieldMode.Read | FieldMode.Write, name: "RXFIFO_FULL_THRHD") // It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. + .WithValueField(10, 10, FieldMode.Read | FieldMode.Write, name: "TXFIFO_EMPTY_THRHD") // It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. + .WithFlag(20, FieldMode.Read | FieldMode.Write, name: "DIS_RX_DAT_OVF") // Disable UART Rx data overflow detect. + .WithFlag(21, FieldMode.Read | FieldMode.Write, name: "RX_TOUT_FLOW_DIS") // Set this bit to stop accumulating idle_cnt when hardware flow control works. + .WithFlag(22, FieldMode.Read | FieldMode.Write, name: "RX_FLOW_EN") // This is the flow enable bit for UART receiver. + .WithFlag(23, FieldMode.Read | FieldMode.Write, name: "RX_TOUT_EN") // This is the enble bit for uart receiver's timeout function. + }, + {(long)Registers.RXD_CNT, new DoubleWordRegister(this) + .WithValueField(0, 10, FieldMode.Read, name: "RXD_EDGE_CNT") // This register stores the count of rxd edge change. It is used in baud rate-detect process. + }, + {(long)Registers.CLKDIV, new DoubleWordRegister(this) + .WithValueField(0, 12, FieldMode.Read | FieldMode.Write, name: "CLKDIV") // Clock divider configuration + .WithValueField(20, 4, FieldMode.Read | FieldMode.Write, name: "FRAG") // The decimal part of the frequency divider factor. + }, + {(long)Registers.CLK_CONF, new DoubleWordRegister(this) + .WithValueField(0, 6, FieldMode.Read | FieldMode.Write, name: "SCLK_DIV_B") // The denominator of the frequency divider factor. + .WithValueField(6, 6, FieldMode.Read | FieldMode.Write, name: "SCLK_DIV_A") // The numerator of the frequency divider factor. + .WithValueField(12, 8, FieldMode.Read | FieldMode.Write, name: "SCLK_DIV_NUM") // The integral part of the frequency divider factor. + .WithValueField(20, 2, FieldMode.Read | FieldMode.Write, name: "SCLK_SEL") // UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL. + .WithFlag(22, FieldMode.Read | FieldMode.Write, name: "SCLK_EN") // Set this bit to enable UART Tx/Rx clock. + .WithFlag(23, FieldMode.Read | FieldMode.Write, name: "RST_CORE") // Write 1 then write 0 to this bit, reset UART Tx/Rx. + .WithFlag(24, FieldMode.Read | FieldMode.Write, name: "TX_SCLK_EN") // Set this bit to enable UART Tx clock. + .WithFlag(25, FieldMode.Read | FieldMode.Write, name: "RX_SCLK_EN") // Set this bit to enable UART Rx clock. + .WithFlag(26, FieldMode.Read | FieldMode.Write, name: "TX_RST_CORE") // Write 1 then write 0 to this bit, reset UART Tx. + .WithFlag(27, FieldMode.Read | FieldMode.Write, name: "RX_RST_CORE") // Write 1 then write 0 to this bit, reset UART Rx. + }, + }; + + registers = new DoubleWordRegisterCollection(this, registersMap); + } + + public uint ReadDoubleWord(long offset) + { + return registers.Read(offset); + } + + public byte ReadByte(long offset) + { + if (offset % 4 != 0) + { + // in the current configuration, only the lowest byte + // contains a meaningful data + return 0; + } + return (byte)ReadDoubleWord(offset); + } + + public override void Reset() + { + base.Reset(); + registers.Reset(); + + UpdateInterrupts(); + } + + public void WriteDoubleWord(long offset, uint value) + { + registers.Write(offset, value); + } + + public void WriteByte(long offset, byte value) + { + if (offset % 4 != 0) + { + // in the current configuration, only the lowest byte + // contains a meaningful data + return; + } + + WriteDoubleWord(offset, value); + } + + public long Size => 0x100; + + public GPIO IRQ { get; private set; } + + public override Bits StopBits => Bits.One; + + public override Parity ParityBit => Parity.None; + + public override uint BaudRate => 115200; + + protected override void CharWritten() + { + UpdateInterrupts(); + } + + protected override void QueueEmptied() + { + UpdateInterrupts(); + } + + private void UpdateInterrupts() + { + IRQ.Set(false); + } + + private IFlagRegisterField rxEventEnabled; + private IFlagRegisterField rxEventPending; + private readonly DoubleWordRegisterCollection registers; + + private enum Registers : long + { + // FIFO Configuration + FIFO = 0x00, + MEM_CONF = 0x60, + + // UART interrupt register + INT_RAW = 0x04, + INT_ST = 0x08, + INT_ENA = 0x0c, + INT_CLR = 0x10, + + // Configuration register + CLKDIV = 0x14, + RX_FILT = 0x18, + CONF0 = 0x20, + CONF1 = 0x24, + FLOW_CONF = 0x34, + SLEEP_CONF = 0x38, + SWFC_CONF0 = 0x3c, + SWFC_CONF1 = 0x40, + TXBRK_CONF = 0x44, + IDLE_CONF = 0x48, + RS485_CONF = 0x4c, + CLK_CONF = 0x78, + + // Status register + STATUS = 0x1c, + MEM_TX_STATUS = 0x64, + MEM_RX_STATUS = 0x68, + FSM_STATUS = 0x6c, + + // Autobaud register + LOWPULSE = 0x28, + HIGHPULSE = 0x2c, + RXD_CNT = 0x30, + POSPULSE = 0x70, + NEGPULSE = 0x74, + + // Escape sequence selection configuration + AT_CMD_PRECNT = 0x50, + AT_CMD_POSTCNT = 0x54, + AT_CMD_GAPTOUT = 0x58, + AT_CMD_CHAR = 0x5c, + + // Version + DATE = 0x7c, + ID = 0x80, + } + } +} diff --git a/svd-to-renode.py b/svd-to-renode.py new file mode 100644 index 0000000..1de2926 --- /dev/null +++ b/svd-to-renode.py @@ -0,0 +1,171 @@ +#!/usr/bin/env python3 +import xml.etree.ElementTree as ET + + +class SVDExtractor: + def __init__(self, filename): + self.tree = ET.parse(filename) + self.root = self.tree.getroot() + self.peripherals = self.root.find("peripherals") + + def extract( + self, + peripheral_to_print, + namespace, + generated_peripheral_name, + imports=None, + extra_subclasses=None, + ): + for peripheral in self.peripherals.iter("peripheral"): + peripheral_name = peripheral.find("name").text + if peripheral_name != peripheral_to_print: + continue + + register_list = dict() + + peripheral_size = int(peripheral.find("addressBlock").find("size").text, 0) + registers = peripheral.find("registers") + + if imports is not None: + for i in imports: + print(f"using {i};") + print() + + print(f"namespace {namespace}") + print("{") + print(f" public class {generated_peripheral_name} : ", end="") + if extra_subclasses is not None: + for esc in extra_subclasses: + print(f"{esc}, ", end="") + print( + "IDoubleWordPeripheral, IProvidesRegisterCollection, IKnownSize" + ) + print(" {") + + print(" public GPIO IRQ { get; private set; }") + print( + " public DoubleWordRegisterCollection RegistersCollection { get; }" + ) + print(f" public long Size => 0x1000; // {hex(peripheral_size)}") + print(" private readonly Machine machine;") + print() + + print( + f" public {generated_peripheral_name}(Machine machine) : base(machine)" + ) + print(" {") + print(" this.machine = machine;") + print() + print(" IRQ = new GPIO();") + print() + print( + " RegistersCollection = new DoubleWordRegisterCollection(this);" + ) + print(" DefineRegisters();") + print(" Reset();") + print(" }") + print() + + print(" private void DefineRegisters()") + print(" {") + + for register in registers.iter("register"): + register_name = register.find("name").text + register_description = register.find("description").text + register_offset = int(register.find("addressOffset").text, 0) + register_default = 0 + register_reset_value_field = register.find("resetValue") + if register_reset_value_field is not None: + register_default = int(register_reset_value_field.text, 0) + register_list[register_offset] = register_name + + if "\n" in register_description: + raise Exception("Register description contains a newline") + print(f" // {register_description}") + print(f" Registers.{register_name}.Define(this, {hex(register_default)})") + for field in register.find("fields").iter("field"): + field_offset = int(field.find("bitOffset").text, 0) + field_width = int(field.find("bitWidth").text, 0) + field_name = field.find("name").text + field_description = field.find("description").text + field_access = field.find("access").text + + field_access_mask = "" + if field_access == "read-write": + field_access_mask = "FieldMode.Read | FieldMode.Write, " + elif field_access == "read-only": + field_access_mask = "FieldMode.Read, " + elif field_access == "write-only": + field_access_mask = "FieldMode.Write, " + else: + raise Exception( + f"Unrecognized field access type: {field_access}" + ) + + if "\n" in field_description: + raise Exception("Field description contains a newline") + + if field_width == 1: + print( + f' .WithFlag({field_offset}, {field_access_mask}name: "{field_name}") // {field_description}' + ) + else: + print( + f' .WithValueField({field_offset}, {field_width}, {field_access_mask}name: "{field_name}") // {field_description}' + ) + print(" ;") + print() + print(" }") + print() + + print(" public override void Reset()") + print(" {") + print(" RegistersCollection.Reset();") + print(" UpdateInterrupts();") + print(" }") + print() + print(" public uint ReadDoubleWord(long offset)") + print(" {") + print(" return RegistersCollection.Read(offset);") + print(" }") + print() + print(" public void WriteDoubleWord(long offset, uint value)") + print(" {") + print(" RegistersCollection.Write(offset, value);") + print(" }") + + print(" private void UpdateInterrupts()") + print(" {") + print(" var status = false;") + print(" this.Log(LogLevel.Noisy, \"Setting IRQ to {0}\", status);") + print(" IRQ.Set(status);") + print(" }") + print() + print(" private enum Registers") + print(" {") + for offset, name in register_list.items(): + print(f" {name} = {hex(offset)},") + print(" }") + print(" }") + print("}") + + +if __name__ == "__main__": + extractor = SVDExtractor("esp32s3.svd") + extractor.extract( + "SPI1", + "Antmicro.Renode.Peripherals.SPI", + "ESP32_SPIController", + imports=[ + "System.Linq", + "System.Collections.Generic", + "Antmicro.Renode.Core", + "Antmicro.Renode.Core.Structure", + "Antmicro.Renode.Core.Structure.Registers", + "Antmicro.Renode.Logging", + "Antmicro.Renode.Peripherals.Bus", + "Antmicro.Renode.Peripherals.Memory", + "Antmicro.Renode.Peripherals.MTD", + ], + extra_subclasses=["NullRegistrationPointPeripheralContainer"], + )