Paying it Forward: Documenting Your Hardware Project

Approaches to documenting a hardware description language using lxsocdoc

Sean Cross - https://xobs.io/ - @xobs

Introduction

About Me

Undocumented Hardware = Bad

(But so easy to do!)

Talk Outline

  1. How to write HDL Code
  2. Rationale behind lxsocdoc
  3. Examples of lxsocdoc
  4. Benefits of this approach

Motivation

// Hardware definitions of the SoC. Also is the main repo of
// documentation for the programmer-centric view
// of the hardware.
/* Start of memory range for the UART peripheral */
#define UART_OFFSET     0x10000000
/* Offset of the data register for the debug UART. A write
   here will send the data out of the UART. A write when a
   send is going on will halt the processor until the send is
   completed. A read will receive any byte that was received
   by the UART since the last read, or 0xFFFFFFFF when none
   was. There is no receive buffer, so it's possible to miss
   data if you don't poll frequently enough.
   The debug UART is always configured as 8N1. */
#define UART_DATA_REG   0x00

mach_defines.h, Hackaday 2019 Con Badge

About LiteX and lxsocdoc

LiteX Primitives

class GPIOOut(Module, AutoCSR):
    def __init__(self, signal):
        self._out = CSRStorage(len(signal))
        self.comb += signal.eq(self._out.storage)

SPI Bitbang Module

self.bitbang = CSRStorage(4)
If(self.bitbang.storage[3],
    dq.oe.eq(0)
).Else(
    dq.oe.eq(1)
),
# CPOL=0/CPHA=0 or CPOL=1/CPHA=1 only.
If(self.bitbang.storage[1],
    self.miso.status.eq(dq.i[1])
),
dq.o.eq(
    Cat(self.bitbang.storage[0], Replicate(1, spi_width-1))
)

Aside: Python Docstrings

New Register Definition

self.bitbang = CSRStorage(4, fields=[
    CSRField("mosi", description="Output value for MOSI..."
    CSRField("clk", description="Output value for SPI CLK..."
    CSRField("cs_n", description="Output value for SPI C..."
    CSRField("dir", description="Sets the dir...", values=[
        ("0", "OUT", "SPI pins are all output"),
        ("1", "IN", "SPI pins are all input"),
    ])
], description="""Bitbang controls for SPI output.  Only
	standard 1x SPI is supported, and as a result all
	four wires are ganged together.  This means that it
	is only possible to perform half-duplex operations,
	using this SPI core.""")

Refactored SPI Bitbang

If(self.bitbang.fields.dir,
    dq.oe.eq(0)
).Else(
    dq.oe.eq(1)
),
# CPOL=0/CPHA=0 or CPOL=1/CPHA=1 only.
If(self.bitbang.fields.clk,
    self.miso.status.eq(dq.i[1])
),
dq.o.eq(
    Cat(self.bitbang.fields.mosi, Replicate(1, spi_width-1))
)

Generating a Manual

Undocumented Fields

Interrupts

More Documentation: ModuleDoc

Protocol Documentation

SVD: Documentation for Machines

SVD2Rust: Generating Safe Accessors

Renode: Fancy Register Logging

Benefits of Higher Level Languages

Documentation helps you

Documentation helps others

Thank you

Questions