index: add slide with rm length

Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross 2020-01-12 16:16:08 +10:00
parent 0b55614d31
commit 2d450116d7
3 changed files with 11 additions and 1 deletions

Binary file not shown.

Before

Width:  |  Height:  |  Size: 383 KiB

After

Width:  |  Height:  |  Size: 164 KiB

BIN
img/rm-page-numbers.png Normal file

Binary file not shown.

After

Width:  |  Height:  |  Size: 25 KiB

View File

@ -205,7 +205,7 @@
The debug UART is always configured as 8N1. */
#define UART_DATA_REG 0x00</code></pre>
<p><tt>mach_defines.h</tt>, Hackaday 2019 Con Badge</p>
<aside class="notes">
<aside class="notes">
Verilog and VHDL are kind of the C or assembly of the FPGA world. They're universal,
but somewhat unwieldy to use. You need to manually set up your address decoders,
and documentation is very free-form. Common approaches today involve comments in
@ -214,6 +214,16 @@
</aside>
</section>
<section>
<h2>Lots of Documentation</h2>
<img data-src="img/rm-page-numbers.png">
<aside class="notes">
This documentation is very extensive. The start of Chapter 1 is on page 197, with all
previous pages being the Table of Contents. It's almost 6000 pages. It's very
extensive, because it's a very complicated chip.
</aside>
</section>
<section>
<h2>About LiteX</h2>
<ul>