theme: add lca2020 theme
Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
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6f8dcb1827
commit
0737480489
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css/theme/lca2020.css
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422
css/theme/lca2020.css
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/**
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* Black theme for reveal.js. This is the opposite of the 'white' theme.
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*
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* By Hakim El Hattab, http://hakim.se
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*/
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@import url(../../lib/font/space-mono/space-mono.css);
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section.has-light-background,
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section.has-light-background h1,
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section.has-light-background h2,
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section.has-light-background h3,
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section.has-light-background h4,
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section.has-light-background h5,
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section.has-light-background h6 {
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color: #222;
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}
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/*********************************************
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* GLOBAL STYLES
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*********************************************/
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body {
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background: #387A3B;
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background-color: #387A3B;
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}
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.reveal .footer {
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position: absolute;
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bottom: 1em;
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right: 2em;
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text-align: right;
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font-size: 0.5em;
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width: 100%;
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height: 96px;
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background-image: url("lca2019-logo.svg");
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background-repeat: no-repeat;
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display: flex;
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justify-content: flex-end;
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align-items: flex-end;
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z-index: 1;
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}
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.reveal .footer .url {
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position: absolute;
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padding-bottom: 30px;
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}
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.reveal .footer .theme {
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padding-right: 80px;
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}
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.reveal .footer .hashtag {
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padding-right: 80px;
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}
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@media only screen and (max-width:800px) {
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.reveal .footer .url {
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display: none;
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}
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}
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@media only screen and (max-width:550px) {
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.reveal .footer {
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background-image: none;
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}
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}
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@media only screen and (max-width:750px) {
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.reveal .footer .twitter {
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display: none;
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}
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}
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@media only screen and (max-width:1050px) {
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.reveal .footer .theme {
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display: none;
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}
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}
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@media only screen and (max-width:1300px) {
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.reveal .footer .hashtag {
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display: none;
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}
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}
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.reveal {
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font-family: "Space Mono", Helvetica, sans-serif;
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font-size: 42px;
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font-weight: normal;
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color: #fff;
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}
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::selection {
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color: #fff;
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background: #bee4fd;
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text-shadow: none;
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}
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::-moz-selection {
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color: #fff;
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background: #bee4fd;
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text-shadow: none;
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}
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.reveal .slides section,
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.reveal .slides section>section {
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line-height: 1.3;
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font-weight: inherit;
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}
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/*********************************************
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* HEADERS
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*********************************************/
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.reveal h1,
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.reveal h2,
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.reveal h3,
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.reveal h4,
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.reveal h5,
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.reveal h6 {
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margin: 0 0 20px 0;
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color: #fff;
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font-family: "Space Mono", Helvetica, sans-serif;
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font-weight: 600;
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line-height: 1.2;
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letter-spacing: normal;
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text-transform: uppercase;
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text-shadow: none;
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word-wrap: break-word;
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}
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.reveal h1 {
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font-size: 2.5em;
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}
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.reveal h2 {
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font-size: 1.6em;
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}
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.reveal h3 {
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font-size: 1.3em;
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}
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.reveal h4 {
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font-size: 1em;
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}
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.reveal h1 {
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text-shadow: none;
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}
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/*********************************************
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* OTHER
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*********************************************/
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.reveal p {
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margin: 20px 0;
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line-height: 1.3;
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}
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/* Ensure certain elements are never larger than the slide itself */
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.reveal img,
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.reveal video,
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.reveal iframe {
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max-width: 95%;
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max-height: 95%;
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}
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.reveal strong,
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.reveal b {
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font-weight: bold;
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}
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.reveal em {
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font-style: italic;
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}
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.reveal ol,
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.reveal dl,
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.reveal ul {
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display: inline-block;
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text-align: left;
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margin: 0 0 0 1em;
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}
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.reveal ol {
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list-style-type: decimal;
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}
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.reveal ul {
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list-style-type: disc;
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}
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.reveal ul ul {
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list-style-type: square;
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}
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.reveal ul ul ul {
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list-style-type: circle;
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}
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.reveal ul ul,
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.reveal ul ol,
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.reveal ol ol,
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.reveal ol ul {
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display: block;
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margin-left: 40px;
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}
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.reveal dt {
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font-weight: bold;
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}
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.reveal dd {
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margin-left: 40px;
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}
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.reveal blockquote {
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display: block;
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position: relative;
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width: 70%;
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margin: 20px auto;
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padding: 5px;
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font-style: italic;
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background: rgba(255, 255, 255, 0.05);
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box-shadow: 0px 0px 2px rgba(0, 0, 0, 0.2);
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}
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.reveal blockquote p:first-child,
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.reveal blockquote p:last-child {
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display: inline-block;
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}
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.reveal q {
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font-style: italic;
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}
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.reveal pre {
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display: block;
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position: relative;
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width: 90%;
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margin: 20px auto;
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text-align: left;
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font-size: 0.55em;
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font-family: monospace;
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line-height: 1.2em;
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word-wrap: break-word;
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box-shadow: 0px 0px 6px rgba(0, 0, 0, 0.3);
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}
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.reveal code {
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font-family: monospace;
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text-transform: none;
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}
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.reveal pre code {
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display: block;
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padding: 5px;
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overflow: auto;
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max-height: 400px;
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word-wrap: normal;
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}
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.reveal table {
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margin: auto;
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border-collapse: collapse;
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border-spacing: 0;
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}
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.reveal table th {
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font-weight: bold;
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}
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.reveal table th,
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.reveal table td {
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text-align: left;
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padding: 0.2em 0.5em 0.2em 0.5em;
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border-bottom: 1px solid;
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}
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.reveal table th[align="center"],
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.reveal table td[align="center"] {
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text-align: center;
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}
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.reveal table th[align="right"],
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.reveal table td[align="right"] {
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text-align: right;
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}
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.reveal table tbody tr:last-child th,
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.reveal table tbody tr:last-child td {
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border-bottom: none;
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}
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.reveal sup {
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vertical-align: super;
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font-size: smaller;
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}
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.reveal sub {
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vertical-align: sub;
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font-size: smaller;
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}
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.reveal small {
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display: inline-block;
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font-size: 0.6em;
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line-height: 1.2em;
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vertical-align: top;
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}
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.reveal small * {
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vertical-align: top;
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}
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/*********************************************
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* LINKS
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*********************************************/
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.reveal a {
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color: #42affa;
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text-decoration: none;
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-webkit-transition: color .15s ease;
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-moz-transition: color .15s ease;
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transition: color .15s ease;
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}
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.reveal a:hover {
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color: #8dcffc;
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text-shadow: none;
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border: none;
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}
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.reveal .roll span:after {
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color: #fff;
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background: #068de9;
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}
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/*********************************************
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* IMAGES
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*********************************************/
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.reveal section img {
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margin: 15px 0px;
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background: rgba(255, 255, 255, 0.12);
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border: 4px solid #fff;
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box-shadow: 0 0 10px rgba(0, 0, 0, 0.15);
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}
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.reveal section img.plain {
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border: 0;
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box-shadow: none;
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}
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.reveal a img {
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-webkit-transition: all .15s linear;
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-moz-transition: all .15s linear;
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transition: all .15s linear;
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}
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.reveal a:hover img {
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background: rgba(255, 255, 255, 0.2);
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border-color: #42affa;
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box-shadow: 0 0 20px rgba(0, 0, 0, 0.55);
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}
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/*********************************************
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* VIDEOS
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*********************************************/
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.reveal section video {
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margin: 15px 0px;
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background: rgba(255, 255, 255, 0.12);
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border: 4px solid #fff;
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box-shadow: 0 0 10px rgba(0, 0, 0, 0.15);
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}
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.reveal section video.plain {
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border: 0;
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box-shadow: none;
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}
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.reveal a video {
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-webkit-transition: all .15s linear;
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-moz-transition: all .15s linear;
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transition: all .15s linear;
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}
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/*********************************************
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* NAVIGATION CONTROLS
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*********************************************/
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.reveal .controls {
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color: #42affa;
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}
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/*********************************************
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* PROGRESS BAR
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*********************************************/
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.reveal .progress {
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background: rgba(0, 0, 0, 0.2);
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color: #42affa;
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}
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.reveal .progress span {
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-webkit-transition: width 800ms cubic-bezier(0.26, 0.86, 0.44, 0.985);
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-moz-transition: width 800ms cubic-bezier(0.26, 0.86, 0.44, 0.985);
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transition: width 800ms cubic-bezier(0.26, 0.86, 0.44, 0.985);
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}
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/*********************************************
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* PRINT BACKGROUND
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*********************************************/
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@media print {
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.backgrounds {
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background-color: #222;
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}
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}
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303
index.html
303
index.html
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<meta name="viewport" content="width=device-width, initial-scale=1.0, maximum-scale=1.0, user-scalable=no">
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<meta name="viewport" content="width=device-width, initial-scale=1.0, maximum-scale=1.0, user-scalable=no">
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<link rel="stylesheet" href="css/reveal.css">
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<link rel="stylesheet" href="css/reveal.css">
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<link rel="stylesheet" href="css/theme/lca2019.css" id="theme">
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<link rel="stylesheet" href="css/theme/lca2020.css" id="theme">
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<!-- Theme used for syntax highlighting of code -->
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<!-- Theme used for syntax highlighting of code -->
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<link rel="stylesheet" href="lib/css/zenburn.css">
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<link rel="stylesheet" href="lib/css/zenburn.css">
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@ -92,152 +92,205 @@
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<small>Sean Cross - <a href="https://xobs.io/">https://xobs.io/</a> - @xobs</small>
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<small>Sean Cross - <a href="https://xobs.io/">https://xobs.io/</a> - @xobs</small>
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</p>
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</p>
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</section>
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</section>
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<section>
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<section>
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<h1>Hardware is different</h1>
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<aside class="notes">
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<ol>
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This is the Open ISA miniconf, which today tends to mean FPGAs. This means that
|
||||||
<li>Massively Parallel</li>
|
hardware and software are both extensible, and developers will be able to extend
|
||||||
</ol>
|
the hardware in addition to making modifications to your software package.
|
||||||
|
</aside>
|
||||||
</section>
|
</section>
|
||||||
This is the Open ISA miniconf, which today tends to mean FPGAs. This means that
|
|
||||||
hardware and software are both extensible, and developers will be able to extend
|
|
||||||
the hardware in addition to making modifications to your software package.
|
|
||||||
|
|
||||||
Undocumented hardware is bad. There are all sorts of quirks, and even if you have
|
<section>
|
||||||
the source code, it can be very difficult to read. I'm the primary developer for
|
<aside class="notes">
|
||||||
the Fomu project, and this talk will cover some of the issues I've run into with
|
Undocumented hardware is bad. There are all sorts of quirks, and even if you have
|
||||||
respect to documentation. It is most directly related to the LiteX and Migen
|
the source code, it can be very difficult to read. I'm the primary developer for
|
||||||
projects, but the concepts will carry over into any other Hardware Description
|
the Fomu project, and this talk will cover some of the issues I've run into with
|
||||||
Language you may use.
|
respect to documentation. It is most directly related to the LiteX and Migen
|
||||||
|
projects, but the concepts will carry over into any other Hardware Description
|
||||||
|
Language you may use.
|
||||||
|
</aside>
|
||||||
|
</section>
|
||||||
|
|
||||||
I'll briefly cover various methods of writing HDL code, then cover the rationale
|
<section>
|
||||||
behind the approach we take with lxsocdoc, then give an example of how to use
|
<aside class="notes">
|
||||||
lxsocdoc and how you might apply it to your language. Finally, I'll cover the
|
I'll briefly cover various methods of writing HDL code, then cover the rationale
|
||||||
implications of having documented hardware and how this will help you pay it forward.
|
behind the approach we take with lxsocdoc, then give an example of how to use
|
||||||
|
lxsocdoc and how you might apply it to your language. Finally, I'll cover the
|
||||||
|
implications of having documented hardware and how this will help you pay it forward.
|
||||||
|
</aside>
|
||||||
|
</section>
|
||||||
|
|
||||||
Verilog and VHDL are kind of the C or assembly of the FPGA world. They're universal,
|
<section>
|
||||||
but somewhat unwieldy to use. You need to manually set up your address decoders,
|
<aside class="notes">
|
||||||
and documentation is very free-form. Common approaches today involve comments in
|
Verilog and VHDL are kind of the C or assembly of the FPGA world. They're universal,
|
||||||
the HDL and/or C header files. This works, but we can do better. We just need to
|
but somewhat unwieldy to use. You need to manually set up your address decoders,
|
||||||
describe the hardware better.
|
and documentation is very free-form. Common approaches today involve comments in
|
||||||
```//Hardware definitions of the SoC. Also is the main repo of documentation for the
|
the HDL and/or C header files. This works, but we can do better. We just need to
|
||||||
//programmer-centric view of the hardware.```
|
describe the hardware better.
|
||||||
|
```//Hardware definitions of the SoC. Also is the main repo of documentation for the
|
||||||
|
//programmer-centric view of the hardware.```
|
||||||
|
</aside>
|
||||||
|
</section>
|
||||||
|
|
||||||
Fomu uses LiteX, which is related to Migen. This is a hardware description language
|
<section>
|
||||||
written in Python. You write Python code and run the program, and it generates
|
<aside class="notes">
|
||||||
a design file -- either Verilog code, or a Yosys netlist. There are many other
|
Fomu uses LiteX, which is related to Migen. This is a hardware description language
|
||||||
alternatives such as SpinalHDL or Chisel. By writing in Python as opposed to
|
written in Python. You write Python code and run the program, and it generates
|
||||||
direct Verilog, we get a lot of nice primitives. The examples from this talk
|
a design file -- either Verilog code, or a Yosys netlist. There are many other
|
||||||
are taken from lxsocdoc and LiteX, but most higher-level hardware description
|
alternatives such as SpinalHDL or Chisel. By writing in Python as opposed to
|
||||||
languages can take similar approaches to documentation.
|
direct Verilog, we get a lot of nice primitives. The examples from this talk
|
||||||
|
are taken from lxsocdoc and LiteX, but most higher-level hardware description
|
||||||
|
languages can take similar approaches to documentation.
|
||||||
|
</aside>
|
||||||
|
</section>
|
||||||
|
|
||||||
In LiteX, two of the primitives used to expose hardware registers to the CPU softcore
|
<section>
|
||||||
are CSRStorage and CSRStatus. Instead of manually wiring up a crossbar and decoding
|
<aside class="notes">
|
||||||
the addresses ourselves, we just need to write `self.regname = CSRStatus(8)`,
|
In LiteX, two of the primitives used to expose hardware registers to the CPU softcore
|
||||||
and the build system will wire up 8 bits of read-only memory to the target CPU.
|
are CSRStorage and CSRStatus. Instead of manually wiring up a crossbar and decoding
|
||||||
Similarly, `self.othername = CSRStorage(8)` will give 8-bits of write-only memory.
|
the addresses ourselves, we just need to write `self.regname = CSRStatus(8)`,
|
||||||
|
and the build system will wire up 8 bits of read-only memory to the target CPU.
|
||||||
|
Similarly, `self.othername = CSRStorage(8)` will give 8-bits of write-only memory.
|
||||||
|
</aside>
|
||||||
|
</section>
|
||||||
|
|
||||||
This works well, but exposes a new problem: Documentation. As an example, I was
|
<section>
|
||||||
working with the SPI Flash block in litex, and wanted to know how the bitbang
|
<h4>SPI Bitbang Module</h4>
|
||||||
driver worked. There wasn't any documentation except the source, which looked
|
<pre><code class="python" data-trim>self.bitbang = CSRStorage(4)
|
||||||
like this:
|
If(self.bitbang.storage[3],
|
||||||
|
dq.oe.eq(0)
|
||||||
|
).Else(
|
||||||
|
dq.oe.eq(1)
|
||||||
|
),
|
||||||
|
If(self.bitbang.storage[1], # CPOL=0/CPHA=0 or CPOL=1/CPHA=1 only.
|
||||||
|
self.miso.status.eq(dq.i[1])
|
||||||
|
),
|
||||||
|
dq.o.eq(Cat(self.bitbang.storage[0], Replicate(1, spi_width-1)))</code></pre>
|
||||||
|
<aside class="notes">
|
||||||
|
This works well, but exposes a new problem: Documentation. As an example, I was
|
||||||
|
working with the SPI Flash block in litex, and wanted to know how the bitbang
|
||||||
|
driver worked. There wasn't any documentation except the source, which looked
|
||||||
|
like this.
|
||||||
|
|
||||||
self.bitbang = CSRStorage(4)
|
You can kind of understand it, but it does take a lot of mental power to
|
||||||
If(self.bitbang.storage[3],
|
work through it. I started by creating aliases for the various elements
|
||||||
dq.oe.eq(0)
|
in the storage array, but then I thought: There has to be a better way!
|
||||||
).Else(
|
</aside>
|
||||||
dq.oe.eq(1)
|
</section>
|
||||||
),
|
|
||||||
If(self.bitbang.storage[1], # CPOL=0/CPHA=0 or CPOL=1/CPHA=1 only.
|
|
||||||
self.miso.status.eq(dq.i[1])
|
|
||||||
),
|
|
||||||
dq.o.eq(Cat(self.bitbang.storage[0], Replicate(1, spi_width-1)))
|
|
||||||
|
|
||||||
You can kind of understand it, but it does take a lot of mental power to
|
<section>
|
||||||
work through it. I started by creating aliases for the various elements
|
<aside class="notes">
|
||||||
in the storage array, but then I thought: There has to be a better way!
|
As an aside, Python has something called Pydoc and Docstrings. These are
|
||||||
|
comments that go at the top of functions and classes that let you describe
|
||||||
|
what a Python object is and how to use it. This is almost what we want,
|
||||||
|
except once the final SoC is generated we don't really care so much about
|
||||||
|
things like constructor arguments or method properties. Documentation for
|
||||||
|
the end user is different from documentation for the module developer.
|
||||||
|
</aside>
|
||||||
|
</section>
|
||||||
|
|
||||||
As an aside, Python has something called Pydoc and Docstrings. These are
|
<section>
|
||||||
comments that go at the top of functions and classes that let you describe
|
<aside class="notes">
|
||||||
what a Python object is and how to use it. This is almost what we want,
|
This is when I hit upon the idea of `lxsocdoc`. The basic idea is that
|
||||||
except once the final SoC is generated we don't really care so much about
|
Python is really good at introspecting Python, so let's add a little bit
|
||||||
things like constructor arguments or method properties. Documentation for
|
more information to the CSR objects to make our life easier. And so, after
|
||||||
the end user is different from documentation for the module developer.
|
working with the LiteX creator Florent, we refactored the bitbang
|
||||||
|
definition to this:
|
||||||
|
|
||||||
This is when I hit upon the idea of `lxsocdoc`. The basic idea is that
|
self.bitbang = CSRStorage(4, fields=[
|
||||||
Python is really good at introspecting Python, so let's add a little bit
|
CSRField("mosi", description="Output value for MOSI pin, valid whenever ``dir`` is ``0``."),
|
||||||
more information to the CSR objects to make our life easier. And so, after
|
CSRField("clk", description="Output value for SPI CLK pin."),
|
||||||
working with the LiteX creator Florent, we refactored the bitbang
|
CSRField("cs_n", description="Output value for SPI CSn pin."),
|
||||||
definition to this:
|
CSRField("dir", description="Sets the direction for *ALL* SPI data pins except CLK and CSn.", values=[
|
||||||
|
("0", "OUT", "SPI pins are all output"),
|
||||||
|
("1", "IN", "SPI pins are all input"),
|
||||||
|
])
|
||||||
|
], description="""
|
||||||
|
Bitbang controls for SPI output. Only standard 1x SPI is supported, and as
|
||||||
|
a result all four wires are ganged together. This means that it is only possible
|
||||||
|
to perform half-duplex operations, using this SPI core.
|
||||||
|
""")
|
||||||
|
</aside>
|
||||||
|
</section>
|
||||||
|
|
||||||
self.bitbang = CSRStorage(4, fields=[
|
<section>
|
||||||
CSRField("mosi", description="Output value for MOSI pin, valid whenever ``dir`` is ``0``."),
|
<aside class="notes">
|
||||||
CSRField("clk", description="Output value for SPI CLK pin."),
|
Now the actual bitbang logic looks like:
|
||||||
CSRField("cs_n", description="Output value for SPI CSn pin."),
|
|
||||||
CSRField("dir", description="Sets the direction for *ALL* SPI data pins except CLK and CSn.", values=[
|
|
||||||
("0", "OUT", "SPI pins are all output"),
|
|
||||||
("1", "IN", "SPI pins are all input"),
|
|
||||||
])
|
|
||||||
], description="""
|
|
||||||
Bitbang controls for SPI output. Only standard 1x SPI is supported, and as
|
|
||||||
a result all four wires are ganged together. This means that it is only possible
|
|
||||||
to perform half-duplex operations, using this SPI core.
|
|
||||||
""")
|
|
||||||
|
|
||||||
Now the actual bitbang logic looks like:
|
If(self.bitbang.fields.dir,
|
||||||
|
dq.oe.eq(0)
|
||||||
|
).Else(
|
||||||
|
dq.oe.eq(1)
|
||||||
|
),
|
||||||
|
If(self.bitbang.fields.clk, # CPOL=0/CPHA=0 or CPOL=1/CPHA=1 only.
|
||||||
|
self.miso.status.eq(dq.i[1])
|
||||||
|
),
|
||||||
|
dq.o.eq(Cat(self.bitbang.fields.mosi, Replicate(1, spi_width-1)))
|
||||||
|
|
||||||
If(self.bitbang.fields.dir,
|
This is a little bit easier to understand -- no longer are we looking at indices
|
||||||
dq.oe.eq(0)
|
in an array to determine what field does what. Instead we get actual named fields.
|
||||||
).Else(
|
But because Python can introspect Python very easily, this is just the beginning.
|
||||||
dq.oe.eq(1)
|
</aside>
|
||||||
),
|
</section>
|
||||||
If(self.bitbang.fields.clk, # CPOL=0/CPHA=0 or CPOL=1/CPHA=1 only.
|
|
||||||
self.miso.status.eq(dq.i[1])
|
|
||||||
),
|
|
||||||
dq.o.eq(Cat(self.bitbang.fields.mosi, Replicate(1, spi_width-1)))
|
|
||||||
|
|
||||||
This is a little bit easier to understand -- no longer are we looking at indices
|
<section>
|
||||||
in an array to determine what field does what. Instead we get actual named fields.
|
<aside class="notes">
|
||||||
But because Python can introspect Python very easily, this is just the beginning.
|
After the design is elaborated and the output file is generated, we can iterate
|
||||||
|
through the resulting tree and pick out any CSR objects and using any additional
|
||||||
|
information. We can actually generate a full reference manual, just like one you
|
||||||
|
would receive from a SoC Vendor.
|
||||||
|
|
||||||
After the design is elaborated and the output file is generated, we can iterate
|
For example, this is what the start of the Fomu SPI Flash documentation looks like:
|
||||||
through the resulting tree and pick out any CSR objects and using any additional
|
[Register Listing for LXSPI]
|
||||||
information. We can actually generate a full reference manual, just like one you
|
|
||||||
would receive from a SoC Vendor.
|
|
||||||
|
|
||||||
For example, this is what the start of the Fomu SPI Flash documentation looks like:
|
This is already pretty useful. You can hand this file to someone and show them
|
||||||
[Register Listing for LXSPI]
|
how your design works. But the title of this talk is called "Paying it Forward",
|
||||||
|
and I can tell you from experience that having such a reference manual for yourself
|
||||||
|
while developing software for your own hardware is still invaluable. Hardware
|
||||||
|
designs are complex things, and not having to decode bitfield offsets in your
|
||||||
|
head or constantly referring to various sections of code to see how it's implemented
|
||||||
|
saves valuable time.
|
||||||
|
</aside>
|
||||||
|
</section>
|
||||||
|
|
||||||
This is already pretty useful. You can hand this file to someone and show them
|
<section>
|
||||||
how your design works. But the title of this talk is called "Paying it Forward",
|
<aside class="notes">
|
||||||
and I can tell you from experience that having such a reference manual for yourself
|
So now we have register documentation. Can we do better? Of course we can.
|
||||||
while developing software for your own hardware is still invaluable. Hardware
|
SoC reference manuals are more than just register definitions. They also include
|
||||||
designs are complex things, and not having to decode bitfield offsets in your
|
background information on protocols, as well as more elaboration on how the block
|
||||||
head or constantly referring to various sections of code to see how it's implemented
|
works. We can take a cue from CSRs themselves, and add module documentation
|
||||||
saves valuable time.
|
in a similar fashion.
|
||||||
|
</aside>
|
||||||
|
</section>
|
||||||
|
---ModuleDoc---
|
||||||
|
|
||||||
So now we have register documentation. Can we do better? Of course we can.
|
<section>
|
||||||
SoC reference manuals are more than just register definitions. They also include
|
<aside class="notes">
|
||||||
background information on protocols, as well as more elaboration on how the block
|
Having documentation for humans is great, but we can go one step further and
|
||||||
works. We can take a cue from CSRs themselves, and add module documentation
|
make documentation for computers. SVD is an XML format defined by ARM that
|
||||||
in a similar fashion.
|
defines various aspects about a chip, including memory layout, interrupt map,
|
||||||
|
and register sets. SVD includes information such as default values and field
|
||||||
|
bits, all information we have thanks to the introspectability of Python.
|
||||||
|
</aside>
|
||||||
|
</section>
|
||||||
|
|
||||||
---ModuleDoc---
|
<section>
|
||||||
|
<aside class="notes">
|
||||||
Having documentation for humans is great, but we can go one step further and
|
In addition to generating a reference manual for humans, we can generate an SVD
|
||||||
make documentation for computers. SVD is an XML format defined by ARM that
|
file that's usable in a wide variety of areas. For example, we can turn an SVD
|
||||||
defines various aspects about a chip, including memory layout, interrupt map,
|
file into a Rust Peripheral Access Crate (PAC) using `SVD2Rust`, giving us an
|
||||||
and register sets. SVD includes information such as default values and field
|
easy way to safely access all peripherals on a device.
|
||||||
bits, all information we have thanks to the introspectability of Python.
|
</aside>
|
||||||
|
</section>
|
||||||
In addition to generating a reference manual for humans, we can generate an SVD
|
|
||||||
file that's usable in a wide variety of areas. For example, we can turn an SVD
|
|
||||||
file into a Rust Peripheral Access Crate (PAC) using `SVD2Rust`, giving us an
|
|
||||||
easy way to safely access all peripherals on a device.
|
|
||||||
|
|
||||||
We can also import this SVD file into an emulator such as Renode, which will
|
|
||||||
print out fields and flags that get accessed, giving us greater visibility into
|
|
||||||
what a program is doing.
|
|
||||||
|
|
||||||
|
<section>
|
||||||
|
<aside class="notes">
|
||||||
|
We can also import this SVD file into an emulator such as Renode, which will
|
||||||
|
print out fields and flags that get accessed, giving us greater visibility into
|
||||||
|
what a program is doing.
|
||||||
|
</aside>
|
||||||
|
</section>
|
||||||
lxsocdoc
|
lxsocdoc
|
||||||
intro to litex/migen
|
intro to litex/migen
|
||||||
concept of mixins
|
concept of mixins
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user