142 lines
5.3 KiB
Rust
142 lines
5.3 KiB
Rust
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// /* Transfer Command bits */
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// /* All byte based commands consist of:
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// * - Command byte
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// * - Length lsb
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// * - Length msb
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// *
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// * If data out is enabled the data follows after the above command bytes,
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// * otherwise no additional data is needed.
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// * - Data * n
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// *
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// * All bit based commands consist of:
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// * - Command byte
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// * - Length
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// *
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// * If data out is enabled a byte containing bitst to transfer follows.
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// * Otherwise no additional data is needed. Only up to 8 bits can be transferred
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// * per transaction when in bit mode.
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// */
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// /* b 0000 0000
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// * |||| |||`- Data out negative enable. Update DO on negative clock edge.
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// * |||| ||`-- Bit count enable. When reset count represents bytes.
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// * |||| |`--- Data in negative enable. Latch DI on negative clock edge.
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// * |||| `---- LSB enable. When set clock data out LSB first.
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// * ||||
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// * |||`------ Data out enable
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// * ||`------- Data in enable
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// * |`-------- TMS mode enable
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// * `--------- Special command mode enable. See mpsse_cmd enum.
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// */
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// pub enum CommandBits {
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// #define MC_DATA_TMS (0x40) /* When set use TMS mode */
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// #define MC_DATA_IN (0x20) /* When set read data (Data IN) */
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// #define MC_DATA_OUT (0x10) /* When set write data (Data OUT) */
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// #define MC_DATA_LSB (0x08) /* When set input/output data LSB first. */
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// #define MC_DATA_ICN (0x04) /* When set receive data on negative clock edge */
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// #define MC_DATA_BITS (0x02) /* When set count bits not bytes */
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// #define MC_DATA_OCN (0x01) /* When set update data on negative clock edge */
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// }
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/* MPSSE engine command definitions */
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#[allow(non_camel_case_types)]
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pub enum Command {
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// Mode commands
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/// Set Data bits LowByte
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MC_SETB_LOW,
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/// Read Data bits LowByte
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MC_READB_LOW,
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/// Set Data bits HighByte
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MC_SETB_HIGH,
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/// Read data bits HighByte
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MC_READB_HIGH,
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/// Enable loopback
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MC_LOOPBACK_EN,
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/// Disable loopback
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MC_LOOPBACK_DIS,
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/// Set clock divisor
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MC_SET_CLK_DIV,
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/// Flush buffer fifos to the PC.
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MC_FLUSH,
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/// Wait on GPIOL1 to go high.
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MC_WAIT_H,
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/// Wait on GPIOL1 to go low.
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MC_WAIT_L,
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/// Disable /5 div, enables 60MHz master clock
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MC_TCK_X5,
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/// Enable /5 div, backward compat to FT2232D
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MC_TCK_D5,
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/// Enable 3 phase clk, DDR I2C
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MC_EN_3PH_CLK,
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/// Disable 3 phase clk
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MC_DIS_3PH_CLK,
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/// Clock every bit, used for JTAG
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MC_CLK_N,
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/// Clock every byte, used for JTAG
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MC_CLK_N8,
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/// Clock until GPIOL1 goes high
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MC_CLK_TO_H,
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/// Clock until GPIOL1 goes low
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MC_CLK_TO_L,
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/// Enable adaptive clocking
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MC_EN_ADPT_CLK,
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/// Disable adaptive clocking
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MC_DIS_ADPT_CLK,
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/// Clock until GPIOL1 goes high, count bytes
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MC_CLK8_TO_H,
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/// Clock until GPIOL1 goes low, count bytes
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MC_CLK8_TO_L,
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/// Set IO to only drive on 0 and tristate on 1
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MC_TRI,
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/// CPU mode commands
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/// CPUMode read short address
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MC_CPU_RS,
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/// CPUMode read extended address
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MC_CPU_RE,
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/// CPUMode write short address
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MC_CPU_WS,
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/// CPUMode write extended address
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MC_CPU_WE,
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}
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impl Command {
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pub fn to_u8(&self) -> u8{
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use Command::*;
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match *self {
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/* Mode commands */
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MC_SETB_LOW => 0x80, /* Set Data bits LowByte */
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MC_READB_LOW => 0x81, /* Read Data bits LowByte */
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MC_SETB_HIGH => 0x82, /* Set Data bits HighByte */
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MC_READB_HIGH => 0x83, /* Read data bits HighByte */
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MC_LOOPBACK_EN => 0x84, /* Enable loopback */
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MC_LOOPBACK_DIS => 0x85, /* Disable loopback */
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MC_SET_CLK_DIV => 0x86, /* Set clock divisor */
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MC_FLUSH => 0x87, /* Flush buffer fifos to the PC. */
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MC_WAIT_H => 0x88, /* Wait on GPIOL1 to go high. */
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MC_WAIT_L => 0x89, /* Wait on GPIOL1 to go low. */
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MC_TCK_X5 => 0x8A, /* Disable /5 div, enables 60MHz master clock */
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MC_TCK_D5 => 0x8B, /* Enable /5 div, backward compat to FT2232D */
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MC_EN_3PH_CLK => 0x8C, /* Enable 3 phase clk, DDR I2C */
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MC_DIS_3PH_CLK => 0x8D, /* Disable 3 phase clk */
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MC_CLK_N => 0x8E, /* Clock every bit, used for JTAG */
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MC_CLK_N8 => 0x8F, /* Clock every byte, used for JTAG */
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MC_CLK_TO_H => 0x94, /* Clock until GPIOL1 goes high */
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MC_CLK_TO_L => 0x95, /* Clock until GPIOL1 goes low */
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MC_EN_ADPT_CLK => 0x96, /* Enable adaptive clocking */
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MC_DIS_ADPT_CLK => 0x97, /* Disable adaptive clocking */
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MC_CLK8_TO_H => 0x9C, /* Clock until GPIOL1 goes high, count bytes */
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MC_CLK8_TO_L => 0x9D, /* Clock until GPIOL1 goes low, count bytes */
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MC_TRI => 0x9E, /* Set IO to only drive on 0 and tristate on 1 */
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/* CPU mode commands */
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MC_CPU_RS => 0x90, /* CPUMode read short address */
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MC_CPU_RE => 0x91, /* CPUMode read extended address */
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MC_CPU_WS => 0x92, /* CPUMode write short address */
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MC_CPU_WE => 0x93, /* CPUMode write extended address */
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}
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}
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}
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