753 lines
15 KiB
C
753 lines
15 KiB
C
#include <stdint.h>
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#include <stdio.h>
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#include <fcntl.h>
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#include <unistd.h>
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <string.h>
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#include "rpi.h"
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#define S_MOSI 10
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#define S_MISO 9
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#define S_CLK 11
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#define S_CE0 8
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#define S_HOLD 25
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#define S_WP 24
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#define S_D0 S_MOSI
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#define S_D1 S_MISO
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#define S_D2 S_WP
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#define S_D3 S_HOLD
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#define F_RESET 27
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#define F_DONE 17
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enum spi_state {
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SS_UNCONFIGURED = 0,
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SS_SINGLE,
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SS_DUAL_RX,
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SS_DUAL_TX,
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SS_QUAD_RX,
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SS_QUAD_TX,
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SS_HARDWARE,
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};
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enum spi_type {
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ST_UNCONFIGURED,
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ST_SINGLE,
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ST_DUAL,
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ST_QUAD,
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ST_QPI,
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};
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struct bb_spi {
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enum spi_state state;
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enum spi_type type;
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int qpi;
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struct {
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int clk;
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int d0;
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int d1;
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int d2;
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int d3;
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int wp;
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int hold;
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int cs;
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int miso;
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int mosi;
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} pins;
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};
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static void spi_set_state(struct bb_spi *spi, enum spi_state state) {
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if (spi->state == state)
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return;
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switch (state) {
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case SS_SINGLE:
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gpioSetMode(spi->pins.clk, PI_OUTPUT); // CLK
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gpioSetMode(spi->pins.cs, PI_OUTPUT); // CE0#
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gpioSetMode(spi->pins.mosi, PI_OUTPUT); // MOSI
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gpioSetMode(spi->pins.miso, PI_INPUT); // MISO
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gpioSetMode(spi->pins.hold, PI_OUTPUT);
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gpioSetMode(spi->pins.wp, PI_OUTPUT);
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break;
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case SS_DUAL_RX:
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gpioSetMode(spi->pins.clk, PI_OUTPUT); // CLK
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gpioSetMode(spi->pins.cs, PI_OUTPUT); // CE0#
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gpioSetMode(spi->pins.mosi, PI_INPUT); // MOSI
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gpioSetMode(spi->pins.miso, PI_INPUT); // MISO
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gpioSetMode(spi->pins.hold, PI_OUTPUT);
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gpioSetMode(spi->pins.wp, PI_OUTPUT);
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break;
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case SS_DUAL_TX:
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gpioSetMode(spi->pins.clk, PI_OUTPUT); // CLK
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gpioSetMode(spi->pins.cs, PI_OUTPUT); // CE0#
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gpioSetMode(spi->pins.mosi, PI_OUTPUT); // MOSI
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gpioSetMode(spi->pins.miso, PI_OUTPUT); // MISO
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gpioSetMode(spi->pins.hold, PI_OUTPUT);
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gpioSetMode(spi->pins.wp, PI_OUTPUT);
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break;
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case SS_QUAD_RX:
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gpioSetMode(spi->pins.clk, PI_OUTPUT); // CLK
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gpioSetMode(spi->pins.cs, PI_OUTPUT); // CE0#
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gpioSetMode(spi->pins.mosi, PI_INPUT); // MOSI
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gpioSetMode(spi->pins.miso, PI_INPUT); // MISO
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gpioSetMode(spi->pins.hold, PI_INPUT);
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gpioSetMode(spi->pins.wp, PI_INPUT);
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break;
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case SS_QUAD_TX:
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gpioSetMode(spi->pins.clk, PI_OUTPUT); // CLK
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gpioSetMode(spi->pins.cs, PI_OUTPUT); // CE0#
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gpioSetMode(spi->pins.mosi, PI_OUTPUT); // MOSI
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gpioSetMode(spi->pins.miso, PI_OUTPUT); // MISO
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gpioSetMode(spi->pins.hold, PI_OUTPUT);
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gpioSetMode(spi->pins.wp, PI_OUTPUT);
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break;
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case SS_HARDWARE:
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gpioSetMode(spi->pins.clk, PI_ALT0); // CLK
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gpioSetMode(spi->pins.cs, PI_ALT0); // CE0#
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gpioSetMode(spi->pins.mosi, PI_ALT0); // MOSI
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gpioSetMode(spi->pins.miso, PI_ALT0); // MISO
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gpioSetMode(spi->pins.hold, PI_OUTPUT);
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gpioSetMode(spi->pins.wp, PI_OUTPUT);
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break;
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default:
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fprintf(stderr, "Unrecognized spi state\n");
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return;
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}
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spi->state = state;
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}
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static void spi_pause(void) {
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// usleep(1);
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return;
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}
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static void spiBegin(struct bb_spi *spi) {
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spi_set_state(spi, SS_SINGLE);
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gpioWrite(spi->pins.cs, 0);
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}
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static void spiEnd(struct bb_spi *spi) {
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(void)spi;
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gpioWrite(spi->pins.cs, 1);
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}
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static uint8_t spiXfer(struct bb_spi *spi, uint8_t out) {
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int bit;
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uint8_t in = 0;
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for (bit = 7; bit >= 0; bit--) {
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if (out & (1 << bit)) {
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gpioWrite(spi->pins.mosi, 1);
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}
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else {
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gpioWrite(spi->pins.mosi, 0);
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}
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gpioWrite(spi->pins.clk, 1);
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spi_pause();
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in |= ((!!gpioRead(spi->pins.miso)) << bit);
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gpioWrite(spi->pins.clk, 0);
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spi_pause();
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}
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return in;
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}
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static void spiSingleTx(struct bb_spi *spi, uint8_t out) {
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spi_set_state(spi, SS_SINGLE);
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spiXfer(spi, out);
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}
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static uint8_t spiSingleRx(struct bb_spi *spi) {
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spi_set_state(spi, SS_SINGLE);
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return spiXfer(spi, 0xff);
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}
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static void spiDualTx(struct bb_spi *spi, uint8_t out) {
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int bit;
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spi_set_state(spi, SS_DUAL_TX);
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for (bit = 7; bit >= 0; bit -= 2) {
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if (out & (1 << (bit - 1))) {
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gpioWrite(spi->pins.d0, 1);
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}
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else {
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gpioWrite(spi->pins.d0, 0);
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}
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if (out & (1 << (bit - 0))) {
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gpioWrite(spi->pins.d1, 1);
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}
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else {
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gpioWrite(spi->pins.d1, 0);
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}
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gpioWrite(spi->pins.clk, 1);
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spi_pause();
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gpioWrite(spi->pins.clk, 0);
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spi_pause();
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}
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}
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static void spiQuadTx(struct bb_spi *spi, uint8_t out) {
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int bit;
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spi_set_state(spi, SS_QUAD_TX);
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for (bit = 7; bit >= 0; bit -= 4) {
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if (out & (1 << (bit - 3))) {
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gpioWrite(spi->pins.d0, 1);
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}
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else {
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gpioWrite(spi->pins.d0, 0);
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}
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if (out & (1 << (bit - 2))) {
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gpioWrite(spi->pins.d1, 1);
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}
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else {
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gpioWrite(spi->pins.d1, 0);
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}
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if (out & (1 << (bit - 1))) {
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gpioWrite(spi->pins.d2, 1);
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}
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else {
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gpioWrite(spi->pins.d2, 0);
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}
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if (out & (1 << (bit - 0))) {
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gpioWrite(spi->pins.d3, 1);
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}
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else {
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gpioWrite(spi->pins.d3, 0);
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}
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gpioWrite(spi->pins.clk, 1);
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spi_pause();
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gpioWrite(spi->pins.clk, 0);
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spi_pause();
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}
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}
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void spiCommand(struct bb_spi *spi, uint8_t cmd) {
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if (spi->qpi)
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spiQuadTx(spi, cmd);
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else
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spiSingleTx(spi, cmd);
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}
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static uint8_t spiDualRx(struct bb_spi *spi) {
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int bit;
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uint8_t in = 0;
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spi_set_state(spi, SS_QUAD_RX);
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for (bit = 7; bit >= 0; bit -= 2) {
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gpioWrite(spi->pins.clk, 1);
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spi_pause();
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in |= ((!!gpioRead(spi->pins.d0)) << (bit - 1));
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in |= ((!!gpioRead(spi->pins.d1)) << (bit - 0));
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gpioWrite(spi->pins.clk, 0);
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spi_pause();
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}
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return in;
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}
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static uint8_t spiQuadRx(struct bb_spi *spi) {
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int bit;
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uint8_t in = 0;
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spi_set_state(spi, SS_QUAD_RX);
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for (bit = 7; bit >= 0; bit -= 4) {
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gpioWrite(spi->pins.clk, 1);
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spi_pause();
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in |= ((!!gpioRead(spi->pins.d0)) << (bit - 3));
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in |= ((!!gpioRead(spi->pins.d1)) << (bit - 2));
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in |= ((!!gpioRead(spi->pins.d2)) << (bit - 1));
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in |= ((!!gpioRead(spi->pins.d3)) << (bit - 0));
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gpioWrite(spi->pins.clk, 0);
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spi_pause();
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}
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return in;
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}
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int spiTx(struct bb_spi *spi, uint8_t word) {
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switch (spi->type) {
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case ST_SINGLE:
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spiSingleTx(spi, word);
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break;
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case ST_DUAL:
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spiDualTx(spi, word);
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break;
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case ST_QUAD:
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case ST_QPI:
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spiQuadTx(spi, word);
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break;
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default:
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return -1;
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}
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return 0;
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}
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uint8_t spiRx(struct bb_spi *spi) {
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switch (spi->type) {
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case ST_SINGLE:
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return spiSingleRx(spi);
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case ST_DUAL:
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return spiDualRx(spi);
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case ST_QUAD:
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case ST_QPI:
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return spiQuadRx(spi);
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default:
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return 0xff;
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}
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}
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uint8_t spiReadSr(struct bb_spi *spi, int sr) {
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uint8_t val = 0xff;
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switch (sr) {
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case 1:
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spiBegin(spi);
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spiCommand(spi, 0x05);
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val = spiRx(spi);
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spiEnd(spi);
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break;
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case 2:
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spiBegin(spi);
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spiCommand(spi, 0x35);
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val = spiRx(spi);
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spiEnd(spi);
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break;
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case 3:
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spiBegin(spi);
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spiCommand(spi, 0x15);
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val = spiRx(spi);
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spiEnd(spi);
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break;
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default:
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fprintf(stderr, "unrecognized status register: %d\n", sr);
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break;
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}
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return val;
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}
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void spiWriteSr(struct bb_spi *spi, int sr, uint8_t val) {
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switch (sr) {
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case 1:
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spiBegin(spi);
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spiCommand(spi, 0x50);
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spiEnd(spi);
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spiBegin(spi);
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spiCommand(spi, 0x01);
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spiCommand(spi, val);
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spiEnd(spi);
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break;
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case 2:
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spiBegin(spi);
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spiCommand(spi, 0x50);
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spiEnd(spi);
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spiBegin(spi);
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spiCommand(spi, 0x31);
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spiCommand(spi, val);
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spiEnd(spi);
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break;
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case 3:
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spiBegin(spi);
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spiCommand(spi, 0x50);
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spiEnd(spi);
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spiBegin(spi);
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spiCommand(spi, 0x11);
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spiCommand(spi, val);
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spiEnd(spi);
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break;
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default:
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fprintf(stderr, "unrecognized status register: %d\n", sr);
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break;
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}
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}
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int spiSetType(struct bb_spi *spi, enum spi_type type) {
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if (spi->type == type)
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return 0;
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switch (type) {
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case ST_SINGLE:
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if (spi->type == ST_QPI) {
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spiBegin(spi);
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spiCommand(spi, 0xff); // Exit QPI Mode
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spiEnd(spi);
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spi->qpi = 0;
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}
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spi->type = type;
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spi_set_state(spi, SS_SINGLE);
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break;
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case ST_DUAL:
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if (spi->type == ST_QPI) {
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spiBegin(spi);
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spiCommand(spi, 0xff); // Exit QPI Mode
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spiEnd(spi);
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spi->qpi = 0;
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}
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spi->type = type;
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spi_set_state(spi, SS_DUAL_TX);
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break;
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case ST_QUAD:
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if (spi->type == ST_QPI) {
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spiBegin(spi);
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spiCommand(spi, 0xff); // Exit QPI Mode
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spiEnd(spi);
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spi->qpi = 0;
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}
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// Enable QE bit
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spiWriteSr(spi, 2, spiReadSr(spi, 2) | (1 << 1));
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spi->type = type;
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spi_set_state(spi, SS_QUAD_TX);
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break;
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case ST_QPI:
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// Enable QE bit
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spiWriteSr(spi, 2, spiReadSr(spi, 2) | (1 << 1));
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spiBegin(spi);
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spiCommand(spi, 0x38); // Enter QPI Mode
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spiEnd(spi);
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spi->qpi = 1;
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spi->type = type;
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spi_set_state(spi, SS_QUAD_TX);
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break;
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default:
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fprintf(stderr, "Unrecognized SPI type: %d\n", type);
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return 1;
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}
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return 0;
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}
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int spiRead(struct bb_spi *spi, uint32_t addr, uint8_t *data, unsigned int count) {
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unsigned int i;
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spiBegin(spi);
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switch (spi->type) {
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case ST_SINGLE:
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case ST_QPI:
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spiCommand(spi, 0x0b);
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break;
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case ST_DUAL:
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spiCommand(spi, 0x3b);
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break;
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case ST_QUAD:
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spiCommand(spi, 0x6b);
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break;
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default:
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fprintf(stderr, "unrecognized spi mode\n");
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spiEnd(spi);
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return 1;
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}
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spiCommand(spi, addr >> 16);
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spiCommand(spi, addr >> 8);
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spiCommand(spi, addr >> 0);
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spiCommand(spi, 0x00);
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for (i = 0; i < count; i++)
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data[i] = spiRx(spi);
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spiEnd(spi);
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return 0;
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}
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int spi_wait_for_not_busy(struct bb_spi *spi) {
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uint8_t sr1;
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sr1 = spiReadSr(spi, 1);
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do {
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sr1 = spiReadSr(spi, 1);
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} while (sr1 & (1 << 0));
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return 0;
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}
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int spiWrite(struct bb_spi *spi, uint32_t addr, const uint8_t *data, unsigned int count) {
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unsigned int i;
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if (addr & 0xff) {
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fprintf(stderr, "Error: Target address is not page-aligned to 256 bytes\n");
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return 1;
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}
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// Erase all applicable blocks
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uint32_t erase_addr;
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for (erase_addr = 0; erase_addr < count; erase_addr += 32768) {
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spiBegin(spi);
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spiCommand(spi, 0x06);
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spiEnd(spi);
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spiBegin(spi);
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spiCommand(spi, 0x52);
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spiCommand(spi, erase_addr >> 16);
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spiCommand(spi, erase_addr >> 8);
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spiCommand(spi, erase_addr >> 0);
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spiEnd(spi);
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spi_wait_for_not_busy(spi);
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}
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uint8_t write_cmd;
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switch (spi->type) {
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case ST_DUAL:
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fprintf(stderr, "dual writes are broken -- need to temporarily set SINGLE mode\n");
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return 1;
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case ST_SINGLE:
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case ST_QPI:
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write_cmd = 0x02;
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break;
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case ST_QUAD:
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write_cmd = 0x32;
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break;
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default:
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fprintf(stderr, "unrecognized spi mode\n");
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return 1;
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}
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while (count) {
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spiBegin(spi);
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spiCommand(spi, 0x06);
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spiEnd(spi);
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spiBegin(spi);
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spiCommand(spi, write_cmd);
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spiCommand(spi, addr >> 16);
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spiCommand(spi, addr >> 8);
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spiCommand(spi, addr >> 0);
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for (i = 0; (i < count) && (i < 256); i++)
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spiTx(spi, *data++);
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spiEnd(spi);
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count -= i;
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addr += i;
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spi_wait_for_not_busy(spi);
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}
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return 0;
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}
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uint8_t spiReset(struct bb_spi *spi) {
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// XXX You should check the "Ready" bit before doing this!
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spiSetType(spi, ST_SINGLE);
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spiBegin(spi);
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spiSingleTx(spi, 0x66); // "Enable Reset" command
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spiEnd(spi);
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spiBegin(spi);
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spiSingleTx(spi, 0x99); // "Reset Device" command
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spiEnd(spi);
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usleep(30);
|
|
return 0;
|
|
}
|
|
|
|
void fpgaSlaveMode(struct bb_spi *spi) {
|
|
|
|
// Set the CS pin to a GPIO, which will let us control it
|
|
gpioSetMode(spi->pins.cs, PI_OUTPUT);
|
|
|
|
// Set CS to 0, which will put the FPGA into slave mode
|
|
gpioWrite(spi->pins.cs, 0);
|
|
|
|
usleep(10000); // XXX figure out correct sleep length here
|
|
|
|
// Bring the FPGA out of reset
|
|
gpioWrite(F_RESET, 1);
|
|
|
|
usleep(1200); // 13.2.SPI Slave Configuration Process
|
|
}
|
|
|
|
int spiInit(struct bb_spi *spi) {
|
|
spi->state = SS_UNCONFIGURED;
|
|
spi->type = ST_UNCONFIGURED;
|
|
spi->qpi = 0;
|
|
|
|
// Reset the SPI flash, which will return it to SPI mode even
|
|
// if it's in QPI mode.
|
|
spiReset(spi);
|
|
|
|
spiSetType(spi, ST_SINGLE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
static inline int isprint(int c)
|
|
{
|
|
return c > 32 && c < 127;
|
|
}
|
|
|
|
int print_hex_offset(FILE *stream,
|
|
const void *block, int count, int offset, uint32_t start)
|
|
{
|
|
|
|
int byte;
|
|
const uint8_t *b = block;
|
|
|
|
count += offset;
|
|
b -= offset;
|
|
for ( ; offset < count; offset += 16) {
|
|
fprintf(stream, "%08x", start + offset);
|
|
|
|
for (byte = 0; byte < 16; byte++) {
|
|
if (byte == 8)
|
|
fprintf(stream, " ");
|
|
fprintf(stream, " ");
|
|
if (offset + byte < count)
|
|
fprintf(stream, "%02x", b[offset + byte] & 0xff);
|
|
else
|
|
fprintf(stream, " ");
|
|
}
|
|
|
|
fprintf(stream, " |");
|
|
for (byte = 0; byte < 16 && byte + offset < count; byte++)
|
|
fprintf(stream, "%c", isprint(b[offset + byte]) ? b[offset + byte] : '.');
|
|
fprintf(stream, "|\r\n");
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int print_hex(const void *block, int count, uint32_t start)
|
|
{
|
|
FILE *stream = stdout;
|
|
return print_hex_offset(stream, block, count, 0, start);
|
|
}
|
|
|
|
int main(int argc, char *argv[])
|
|
{
|
|
int result;
|
|
struct bb_spi spi;
|
|
|
|
if (gpioInitialise() < 0) {
|
|
fprintf(stderr, "Unable to initialize GPIO\n");
|
|
return 1;
|
|
}
|
|
|
|
/* The dance to put the FPGA into programming mode:
|
|
* 1) Put it into reset (set C_RESET to 0)
|
|
* 2) Drive CS to 0
|
|
* 3) Bring it out of reset
|
|
* 4) Let CS go back to 1
|
|
* 5) Set HOLD/ on the SPI flash by setting pin 25 to 0
|
|
* To program the FPGA
|
|
*/
|
|
|
|
spi.pins.clk = S_CLK;
|
|
spi.pins.d0 = S_D0;
|
|
spi.pins.d1 = S_D1;
|
|
spi.pins.d2 = S_D2;
|
|
spi.pins.d3 = S_D3;
|
|
spi.pins.miso = S_MISO;
|
|
spi.pins.mosi = S_MOSI;
|
|
spi.pins.hold = S_HOLD;
|
|
spi.pins.wp = S_WP;
|
|
spi.pins.cs = S_CE0;
|
|
|
|
// Have the SPI flash pay attention to us
|
|
gpioWrite(spi.pins.hold, 1);
|
|
|
|
// Disable WP
|
|
gpioWrite(spi.pins.wp, 1);
|
|
|
|
// Put the FPGA into reset
|
|
gpioSetMode(F_RESET, PI_OUTPUT);
|
|
gpioWrite(F_RESET, 0);
|
|
|
|
// Also monitor the C_DONE pin
|
|
gpioSetMode(F_DONE, PI_INPUT);
|
|
|
|
// Restart the FPGA in slave mode
|
|
//fpgaSlaveMode();
|
|
|
|
result = gpioRead(F_DONE);
|
|
fprintf(stderr, "Reset before running: %d\n", result);
|
|
|
|
spiInit(&spi);
|
|
|
|
spiSetType(&spi, ST_QPI);
|
|
|
|
// Assert CS
|
|
spiBegin(&spi);
|
|
|
|
int i;
|
|
fprintf(stderr, "Write:");
|
|
spiCommand(&spi, 0x90);
|
|
spiTx(&spi, 0x00); // A23-16
|
|
spiTx(&spi, 0x00); // A15-8
|
|
spiRx(&spi); // Dummy0
|
|
spiRx(&spi); // Dummy1
|
|
fprintf(stderr, "\nRead:");
|
|
for (i=0; i<16; i++) {
|
|
fprintf(stderr, " 0x%02x", spiRx(&spi));
|
|
}
|
|
fprintf(stderr, "\n");
|
|
spiEnd(&spi);
|
|
|
|
|
|
uint8_t data[383316];
|
|
{
|
|
memset(data, 0xaa, sizeof(data));
|
|
int fd = open("/tmp/image-gateware+bios+micropython.bin", O_RDONLY);
|
|
if (read(fd, data, sizeof(data)) != sizeof(data)) {
|
|
perror("uanble to read");
|
|
return 1;
|
|
}
|
|
spiWrite(&spi, 0, data, sizeof(data));
|
|
}
|
|
|
|
{
|
|
uint8_t page0[256];
|
|
spiRead(&spi, 0, page0, sizeof(page0));
|
|
print_hex(page0, sizeof(page0), 0);
|
|
}
|
|
{
|
|
uint8_t check_data[sizeof(data)];
|
|
spiRead(&spi, 0, check_data, sizeof(check_data));
|
|
size_t j;
|
|
for (j=0; j<sizeof(check_data); j++) {
|
|
if (data[j] != check_data[j]) {
|
|
fprintf(stderr, "check data %d different: %02x vs %02x\n", j, check_data[j], data[j]);
|
|
}
|
|
}
|
|
}
|
|
|
|
result = gpioRead(F_DONE);
|
|
fprintf(stderr, "Programming result: %d\n", result);
|
|
|
|
// Deassert CS
|
|
gpioWrite(spi.pins.cs, 1);
|
|
|
|
// Deassert hold, if set
|
|
gpioWrite(spi.pins.hold, 1);
|
|
|
|
// Return the SPI pins to SPI mode, so we can talk to
|
|
// the FPGA normally
|
|
spiSetType(&spi, ST_SINGLE);
|
|
spiInit(&spi);
|
|
spi_set_state(&spi, SS_HARDWARE);
|
|
|
|
return 0;
|
|
}
|