608 lines
12 KiB
C
608 lines
12 KiB
C
#include <stdint.h>
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#include <stdio.h>
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#include <fcntl.h>
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#include <unistd.h>
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <string.h>
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#include <stdlib.h>
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#include "rpi.h"
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#include "spi.h"
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struct ff_spi {
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enum spi_state state;
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enum spi_type type;
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enum spi_type desired_type;
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struct {
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int clk;
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int d0;
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int d1;
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int d2;
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int d3;
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int wp;
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int hold;
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int cs;
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int miso;
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int mosi;
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} pins;
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};
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static void spi_set_state(struct ff_spi *spi, enum spi_state state) {
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if (spi->state == state)
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return;
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switch (state) {
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case SS_SINGLE:
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gpioSetMode(spi->pins.clk, PI_OUTPUT); // CLK
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gpioSetMode(spi->pins.cs, PI_OUTPUT); // CE0#
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gpioSetMode(spi->pins.mosi, PI_OUTPUT); // MOSI
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gpioSetMode(spi->pins.miso, PI_INPUT); // MISO
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gpioSetMode(spi->pins.hold, PI_OUTPUT);
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gpioSetMode(spi->pins.wp, PI_OUTPUT);
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break;
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case SS_DUAL_RX:
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gpioSetMode(spi->pins.clk, PI_OUTPUT); // CLK
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gpioSetMode(spi->pins.cs, PI_OUTPUT); // CE0#
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gpioSetMode(spi->pins.mosi, PI_INPUT); // MOSI
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gpioSetMode(spi->pins.miso, PI_INPUT); // MISO
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gpioSetMode(spi->pins.hold, PI_OUTPUT);
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gpioSetMode(spi->pins.wp, PI_OUTPUT);
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break;
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case SS_DUAL_TX:
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gpioSetMode(spi->pins.clk, PI_OUTPUT); // CLK
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gpioSetMode(spi->pins.cs, PI_OUTPUT); // CE0#
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gpioSetMode(spi->pins.mosi, PI_OUTPUT); // MOSI
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gpioSetMode(spi->pins.miso, PI_OUTPUT); // MISO
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gpioSetMode(spi->pins.hold, PI_OUTPUT);
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gpioSetMode(spi->pins.wp, PI_OUTPUT);
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break;
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case SS_QUAD_RX:
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gpioSetMode(spi->pins.clk, PI_OUTPUT); // CLK
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gpioSetMode(spi->pins.cs, PI_OUTPUT); // CE0#
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gpioSetMode(spi->pins.mosi, PI_INPUT); // MOSI
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gpioSetMode(spi->pins.miso, PI_INPUT); // MISO
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gpioSetMode(spi->pins.hold, PI_INPUT);
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gpioSetMode(spi->pins.wp, PI_INPUT);
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break;
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case SS_QUAD_TX:
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gpioSetMode(spi->pins.clk, PI_OUTPUT); // CLK
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gpioSetMode(spi->pins.cs, PI_OUTPUT); // CE0#
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gpioSetMode(spi->pins.mosi, PI_OUTPUT); // MOSI
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gpioSetMode(spi->pins.miso, PI_OUTPUT); // MISO
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gpioSetMode(spi->pins.hold, PI_OUTPUT);
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gpioSetMode(spi->pins.wp, PI_OUTPUT);
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break;
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case SS_HARDWARE:
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gpioSetMode(spi->pins.clk, PI_ALT0); // CLK
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gpioSetMode(spi->pins.cs, PI_ALT0); // CE0#
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gpioSetMode(spi->pins.mosi, PI_ALT0); // MOSI
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gpioSetMode(spi->pins.miso, PI_ALT0); // MISO
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gpioSetMode(spi->pins.hold, PI_OUTPUT);
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gpioSetMode(spi->pins.wp, PI_OUTPUT);
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break;
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default:
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fprintf(stderr, "Unrecognized spi state\n");
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return;
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}
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spi->state = state;
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}
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void spiPause(struct ff_spi *spi) {
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(void)spi;
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// usleep(1);
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return;
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}
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void spiBegin(struct ff_spi *spi) {
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spi_set_state(spi, SS_SINGLE);
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gpioWrite(spi->pins.cs, 0);
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}
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void spiEnd(struct ff_spi *spi) {
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(void)spi;
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gpioWrite(spi->pins.cs, 1);
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}
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static uint8_t spiXfer(struct ff_spi *spi, uint8_t out) {
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int bit;
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uint8_t in = 0;
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for (bit = 7; bit >= 0; bit--) {
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if (out & (1 << bit)) {
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gpioWrite(spi->pins.mosi, 1);
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}
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else {
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gpioWrite(spi->pins.mosi, 0);
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}
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gpioWrite(spi->pins.clk, 1);
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spiPause(spi);
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in |= ((!!gpioRead(spi->pins.miso)) << bit);
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gpioWrite(spi->pins.clk, 0);
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spiPause(spi);
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}
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return in;
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}
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static void spiSingleTx(struct ff_spi *spi, uint8_t out) {
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spi_set_state(spi, SS_SINGLE);
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spiXfer(spi, out);
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}
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static uint8_t spiSingleRx(struct ff_spi *spi) {
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spi_set_state(spi, SS_SINGLE);
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return spiXfer(spi, 0xff);
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}
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static void spiDualTx(struct ff_spi *spi, uint8_t out) {
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int bit;
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spi_set_state(spi, SS_DUAL_TX);
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for (bit = 7; bit >= 0; bit -= 2) {
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if (out & (1 << (bit - 1))) {
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gpioWrite(spi->pins.d0, 1);
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}
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else {
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gpioWrite(spi->pins.d0, 0);
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}
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if (out & (1 << (bit - 0))) {
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gpioWrite(spi->pins.d1, 1);
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}
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else {
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gpioWrite(spi->pins.d1, 0);
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}
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gpioWrite(spi->pins.clk, 1);
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spiPause(spi);
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gpioWrite(spi->pins.clk, 0);
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spiPause(spi);
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}
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}
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static void spiQuadTx(struct ff_spi *spi, uint8_t out) {
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int bit;
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spi_set_state(spi, SS_QUAD_TX);
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for (bit = 7; bit >= 0; bit -= 4) {
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if (out & (1 << (bit - 3))) {
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gpioWrite(spi->pins.d0, 1);
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}
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else {
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gpioWrite(spi->pins.d0, 0);
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}
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if (out & (1 << (bit - 2))) {
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gpioWrite(spi->pins.d1, 1);
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}
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else {
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gpioWrite(spi->pins.d1, 0);
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}
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if (out & (1 << (bit - 1))) {
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gpioWrite(spi->pins.d2, 1);
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}
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else {
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gpioWrite(spi->pins.d2, 0);
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}
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if (out & (1 << (bit - 0))) {
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gpioWrite(spi->pins.d3, 1);
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}
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else {
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gpioWrite(spi->pins.d3, 0);
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}
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gpioWrite(spi->pins.clk, 1);
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spiPause(spi);
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gpioWrite(spi->pins.clk, 0);
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spiPause(spi);
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}
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}
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void spiCommand(struct ff_spi *spi, uint8_t cmd) {
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if (spi->type == ST_QPI)
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spiQuadTx(spi, cmd);
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else
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spiSingleTx(spi, cmd);
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}
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static uint8_t spiDualRx(struct ff_spi *spi) {
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int bit;
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uint8_t in = 0;
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spi_set_state(spi, SS_QUAD_RX);
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for (bit = 7; bit >= 0; bit -= 2) {
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gpioWrite(spi->pins.clk, 1);
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spiPause(spi);
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in |= ((!!gpioRead(spi->pins.d0)) << (bit - 1));
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in |= ((!!gpioRead(spi->pins.d1)) << (bit - 0));
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gpioWrite(spi->pins.clk, 0);
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spiPause(spi);
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}
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return in;
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}
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static uint8_t spiQuadRx(struct ff_spi *spi) {
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int bit;
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uint8_t in = 0;
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spi_set_state(spi, SS_QUAD_RX);
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for (bit = 7; bit >= 0; bit -= 4) {
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gpioWrite(spi->pins.clk, 1);
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spiPause(spi);
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in |= ((!!gpioRead(spi->pins.d0)) << (bit - 3));
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in |= ((!!gpioRead(spi->pins.d1)) << (bit - 2));
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in |= ((!!gpioRead(spi->pins.d2)) << (bit - 1));
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in |= ((!!gpioRead(spi->pins.d3)) << (bit - 0));
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gpioWrite(spi->pins.clk, 0);
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spiPause(spi);
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}
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return in;
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}
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int spiTx(struct ff_spi *spi, uint8_t word) {
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switch (spi->type) {
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case ST_SINGLE:
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spiSingleTx(spi, word);
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break;
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case ST_DUAL:
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spiDualTx(spi, word);
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break;
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case ST_QUAD:
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case ST_QPI:
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spiQuadTx(spi, word);
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break;
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default:
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return -1;
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}
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return 0;
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}
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uint8_t spiRx(struct ff_spi *spi) {
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switch (spi->type) {
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case ST_SINGLE:
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return spiSingleRx(spi);
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case ST_DUAL:
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return spiDualRx(spi);
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case ST_QUAD:
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case ST_QPI:
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return spiQuadRx(spi);
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default:
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return 0xff;
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}
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}
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uint8_t spiReadSr(struct ff_spi *spi, int sr) {
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uint8_t val = 0xff;
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switch (sr) {
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case 1:
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spiBegin(spi);
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spiCommand(spi, 0x05);
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val = spiRx(spi);
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spiEnd(spi);
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break;
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case 2:
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spiBegin(spi);
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spiCommand(spi, 0x35);
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val = spiRx(spi);
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spiEnd(spi);
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break;
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case 3:
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spiBegin(spi);
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spiCommand(spi, 0x15);
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val = spiRx(spi);
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spiEnd(spi);
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break;
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default:
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fprintf(stderr, "unrecognized status register: %d\n", sr);
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break;
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}
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return val;
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}
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void spiWriteSr(struct ff_spi *spi, int sr, uint8_t val) {
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switch (sr) {
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case 1:
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spiBegin(spi);
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spiCommand(spi, 0x50);
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spiEnd(spi);
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spiBegin(spi);
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spiCommand(spi, 0x01);
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spiCommand(spi, val);
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spiEnd(spi);
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break;
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case 2:
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spiBegin(spi);
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spiCommand(spi, 0x50);
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spiEnd(spi);
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spiBegin(spi);
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spiCommand(spi, 0x31);
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spiCommand(spi, val);
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spiEnd(spi);
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break;
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case 3:
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spiBegin(spi);
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spiCommand(spi, 0x50);
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spiEnd(spi);
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spiBegin(spi);
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spiCommand(spi, 0x11);
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spiCommand(spi, val);
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spiEnd(spi);
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break;
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default:
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fprintf(stderr, "unrecognized status register: %d\n", sr);
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break;
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}
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}
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int spiSetType(struct ff_spi *spi, enum spi_type type) {
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if (spi->type == type)
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return 0;
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switch (type) {
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case ST_SINGLE:
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if (spi->type == ST_QPI) {
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spiBegin(spi);
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spiCommand(spi, 0xff); // Exit QPI Mode
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spiEnd(spi);
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}
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spi->type = type;
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spi_set_state(spi, SS_SINGLE);
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break;
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case ST_DUAL:
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if (spi->type == ST_QPI) {
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spiBegin(spi);
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spiCommand(spi, 0xff); // Exit QPI Mode
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spiEnd(spi);
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}
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spi->type = type;
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spi_set_state(spi, SS_DUAL_TX);
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break;
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case ST_QUAD:
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if (spi->type == ST_QPI) {
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spiBegin(spi);
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spiCommand(spi, 0xff); // Exit QPI Mode
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spiEnd(spi);
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}
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// Enable QE bit
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spiWriteSr(spi, 2, spiReadSr(spi, 2) | (1 << 1));
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spi->type = type;
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spi_set_state(spi, SS_QUAD_TX);
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break;
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case ST_QPI:
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// Enable QE bit
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spiWriteSr(spi, 2, spiReadSr(spi, 2) | (1 << 1));
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spiBegin(spi);
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spiCommand(spi, 0x38); // Enter QPI Mode
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spiEnd(spi);
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spi->type = type;
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spi_set_state(spi, SS_QUAD_TX);
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break;
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default:
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fprintf(stderr, "Unrecognized SPI type: %d\n", type);
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return 1;
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}
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return 0;
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}
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int spiRead(struct ff_spi *spi, uint32_t addr, uint8_t *data, unsigned int count) {
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unsigned int i;
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spiBegin(spi);
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switch (spi->type) {
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case ST_SINGLE:
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case ST_QPI:
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spiCommand(spi, 0x0b);
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break;
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case ST_DUAL:
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spiCommand(spi, 0x3b);
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break;
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case ST_QUAD:
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spiCommand(spi, 0x6b);
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break;
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default:
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fprintf(stderr, "unrecognized spi mode\n");
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spiEnd(spi);
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return 1;
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}
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spiCommand(spi, addr >> 16);
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spiCommand(spi, addr >> 8);
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spiCommand(spi, addr >> 0);
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spiCommand(spi, 0x00);
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for (i = 0; i < count; i++)
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data[i] = spiRx(spi);
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spiEnd(spi);
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return 0;
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}
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static int spi_wait_for_not_busy(struct ff_spi *spi) {
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uint8_t sr1;
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sr1 = spiReadSr(spi, 1);
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do {
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sr1 = spiReadSr(spi, 1);
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} while (sr1 & (1 << 0));
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return 0;
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}
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void spiSwapTxRx(struct ff_spi *spi) {
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int tmp = spi->pins.mosi;
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spi->pins.mosi = spi->pins.miso;
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spi->pins.miso = tmp;
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spiSetType(spi, ST_SINGLE);
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spi->state = SS_UNCONFIGURED;
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spi_set_state(spi, SS_SINGLE);
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}
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int spiWrite(struct ff_spi *spi, uint32_t addr, const uint8_t *data, unsigned int count) {
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unsigned int i;
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if (addr & 0xff) {
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fprintf(stderr, "Error: Target address is not page-aligned to 256 bytes\n");
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return 1;
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}
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// Erase all applicable blocks
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uint32_t erase_addr;
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for (erase_addr = 0; erase_addr < count; erase_addr += 32768) {
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spiBegin(spi);
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spiCommand(spi, 0x06);
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spiEnd(spi);
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spiBegin(spi);
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spiCommand(spi, 0x52);
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spiCommand(spi, erase_addr >> 16);
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spiCommand(spi, erase_addr >> 8);
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spiCommand(spi, erase_addr >> 0);
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spiEnd(spi);
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spi_wait_for_not_busy(spi);
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}
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uint8_t write_cmd;
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switch (spi->type) {
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case ST_DUAL:
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fprintf(stderr, "dual writes are broken -- need to temporarily set SINGLE mode\n");
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return 1;
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case ST_SINGLE:
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case ST_QPI:
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write_cmd = 0x02;
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break;
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case ST_QUAD:
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write_cmd = 0x32;
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break;
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default:
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fprintf(stderr, "unrecognized spi mode\n");
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return 1;
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}
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while (count) {
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spiBegin(spi);
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spiCommand(spi, 0x06);
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spiEnd(spi);
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spiBegin(spi);
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spiCommand(spi, write_cmd);
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spiCommand(spi, addr >> 16);
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spiCommand(spi, addr >> 8);
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spiCommand(spi, addr >> 0);
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for (i = 0; (i < count) && (i < 256); i++)
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spiTx(spi, *data++);
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spiEnd(spi);
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count -= i;
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addr += i;
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spi_wait_for_not_busy(spi);
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}
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return 0;
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}
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uint8_t spiReset(struct ff_spi *spi) {
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// XXX You should check the "Ready" bit before doing this!
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// Shift to QPI mode, then back to Single mode, to ensure
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// we're actually in Single mode.
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spiSetType(spi, ST_QPI);
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spiSetType(spi, ST_SINGLE);
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spiBegin(spi);
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spiCommand(spi, 0x66); // "Enable Reset" command
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spiEnd(spi);
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spiBegin(spi);
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spiCommand(spi, 0x99); // "Reset Device" command
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spiEnd(spi);
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usleep(30);
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return 0;
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}
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int spiInit(struct ff_spi *spi) {
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spi->state = SS_UNCONFIGURED;
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spi->type = ST_UNCONFIGURED;
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// Reset the SPI flash, which will return it to SPI mode even
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// if it's in QPI mode.
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spiReset(spi);
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spiSetType(spi, ST_SINGLE);
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// Have the SPI flash pay attention to us
|
|
gpioWrite(spi->pins.hold, 1);
|
|
// Disable WP
|
|
gpioWrite(spi->pins.wp, 1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct ff_spi *spiAlloc(void) {
|
|
struct ff_spi *spi = (struct ff_spi *)malloc(sizeof(struct ff_spi));
|
|
memset(spi, 0, sizeof(*spi));
|
|
return spi;
|
|
}
|
|
|
|
void spiSetPin(struct ff_spi *spi, enum spi_pin pin, int val) {
|
|
switch (pin) {
|
|
case SP_MOSI: spi->pins.mosi = val; break;
|
|
case SP_MISO: spi->pins.miso = val; break;
|
|
case SP_HOLD: spi->pins.hold = val; break;
|
|
case SP_WP: spi->pins.wp = val; break;
|
|
case SP_CS: spi->pins.cs = val; break;
|
|
case SP_CLK: spi->pins.clk = val; break;
|
|
case SP_D0: spi->pins.d0 = val; break;
|
|
case SP_D1: spi->pins.d1 = val; break;
|
|
case SP_D2: spi->pins.d2 = val; break;
|
|
case SP_D3: spi->pins.d3 = val; break;
|
|
default: fprintf(stderr, "unrecognized pin: %d\n", pin); break;
|
|
}
|
|
}
|
|
|
|
void spiHold(struct ff_spi *spi) {
|
|
spiBegin(spi);
|
|
spiCommand(spi, 0xb9);
|
|
spiEnd(spi);
|
|
}
|
|
void spiUnhold(struct ff_spi *spi) {
|
|
spiBegin(spi);
|
|
spiCommand(spi, 0xab);
|
|
spiEnd(spi);
|
|
}
|
|
|
|
void spiFree(struct ff_spi **spi) {
|
|
if (!spi)
|
|
return;
|
|
if (!*spi)
|
|
return;
|
|
|
|
spi_set_state(*spi, SS_HARDWARE);
|
|
free(*spi);
|
|
*spi = NULL;
|
|
}
|