#include #include #include #include #include #include #include #include #include #include #include #include static volatile uint32_t piModel = 1; static volatile uint32_t piPeriphBase = 0x20000000; static volatile uint32_t piBusAddr = 0x40000000; #define SYST_BASE (piPeriphBase + 0x003000) #define DMA_BASE (piPeriphBase + 0x007000) #define CLK_BASE (piPeriphBase + 0x101000) #define GPIO_BASE (piPeriphBase + 0x200000) #define UART0_BASE (piPeriphBase + 0x201000) #define PCM_BASE (piPeriphBase + 0x203000) #define SPI0_BASE (piPeriphBase + 0x204000) #define I2C0_BASE (piPeriphBase + 0x205000) #define PWM_BASE (piPeriphBase + 0x20C000) #define BSCS_BASE (piPeriphBase + 0x214000) #define UART1_BASE (piPeriphBase + 0x215000) #define I2C1_BASE (piPeriphBase + 0x804000) #define I2C2_BASE (piPeriphBase + 0x805000) #define DMA15_BASE (piPeriphBase + 0xE05000) #define DMA_LEN 0x1000 /* allow access to all channels */ #define CLK_LEN 0xA8 #define GPIO_LEN 0xB4 #define SYST_LEN 0x1C #define PCM_LEN 0x24 #define PWM_LEN 0x28 #define I2C_LEN 0x1C #define GPSET0 7 #define GPSET1 8 #define GPCLR0 10 #define GPCLR1 11 #define GPLEV0 13 #define GPLEV1 14 #define GPPUD 37 #define GPPUDCLK0 38 #define GPPUDCLK1 39 #define SYST_CS 0 #define SYST_CLO 1 #define SYST_CHI 2 #define CLK_PASSWD (0x5A<<24) #define CLK_CTL_MASH(x)((x)<<9) #define CLK_CTL_BUSY (1 <<7) #define CLK_CTL_KILL (1 <<5) #define CLK_CTL_ENAB (1 <<4) #define CLK_CTL_SRC(x) ((x)<<0) #define CLK_SRCS 4 #define CLK_CTL_SRC_OSC 1 /* 19.2 MHz */ #define CLK_CTL_SRC_PLLC 5 /* 1000 MHz */ #define CLK_CTL_SRC_PLLD 6 /* 500 MHz */ #define CLK_CTL_SRC_HDMI 7 /* 216 MHz */ #define CLK_DIV_DIVI(x) ((x)<<12) #define CLK_DIV_DIVF(x) ((x)<< 0) #define CLK_GP0_CTL 28 #define CLK_GP0_DIV 29 #define CLK_GP1_CTL 30 #define CLK_GP1_DIV 31 #define CLK_GP2_CTL 32 #define CLK_GP2_DIV 33 #define CLK_PCM_CTL 38 #define CLK_PCM_DIV 39 #define CLK_PWM_CTL 40 #define CLK_PWM_DIV 41 static volatile uint32_t *gpioReg = MAP_FAILED; static volatile uint32_t *systReg = MAP_FAILED; static volatile uint32_t *clkReg = MAP_FAILED; #define PI_BANK (gpio>>5) #define PI_BIT (1<<(gpio&0x1F)) /* gpio modes. */ #define PI_INPUT 0 #define PI_OUTPUT 1 #define PI_ALT0 4 #define PI_ALT1 5 #define PI_ALT2 6 #define PI_ALT3 7 #define PI_ALT4 3 #define PI_ALT5 2 void gpioSetMode(unsigned gpio, unsigned mode) { int reg, shift; reg = gpio/10; shift = (gpio%10) * 3; gpioReg[reg] = (gpioReg[reg] & ~(7<> shift) & 7; } /* Values for pull-ups/downs off, pull-down and pull-up. */ #define PI_PUD_OFF 0 #define PI_PUD_DOWN 1 #define PI_PUD_UP 2 void gpioSetPullUpDown(unsigned gpio, unsigned pud) { *(gpioReg + GPPUD) = pud; usleep(20); *(gpioReg + GPPUDCLK0 + PI_BANK) = PI_BIT; usleep(20); *(gpioReg + GPPUD) = 0; *(gpioReg + GPPUDCLK0 + PI_BANK) = 0; } int gpioRead(unsigned gpio) { if ((*(gpioReg + GPLEV0 + PI_BANK) & PI_BIT) != 0) return 1; else return 0; } void gpioWrite(unsigned gpio, unsigned level) { if (level == 0) *(gpioReg + GPCLR0 + PI_BANK) = PI_BIT; else *(gpioReg + GPSET0 + PI_BANK) = PI_BIT; } void gpioTrigger(unsigned gpio, unsigned pulseLen, unsigned level) { if (level == 0) *(gpioReg + GPCLR0 + PI_BANK) = PI_BIT; else *(gpioReg + GPSET0 + PI_BANK) = PI_BIT; usleep(pulseLen); if (level != 0) *(gpioReg + GPCLR0 + PI_BANK) = PI_BIT; else *(gpioReg + GPSET0 + PI_BANK) = PI_BIT; } /* Bit (1<