3579 lines
143 KiB
Verilog
3579 lines
143 KiB
Verilog
// Generator : SpinalHDL v1.3.3 git head : 8b8cd335eecbea3b5f1f970f218a982dbdb12d99
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// Date : 26/04/2019, 01:10:02
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// Component : VexRiscv
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`define Src1CtrlEnum_defaultEncoding_type [1:0]
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`define Src1CtrlEnum_defaultEncoding_RS 2'b00
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`define Src1CtrlEnum_defaultEncoding_IMU 2'b01
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`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10
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`define Src1CtrlEnum_defaultEncoding_URS1 2'b11
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`define EnvCtrlEnum_defaultEncoding_type [1:0]
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`define EnvCtrlEnum_defaultEncoding_NONE 2'b00
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`define EnvCtrlEnum_defaultEncoding_XRET 2'b01
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`define EnvCtrlEnum_defaultEncoding_ECALL 2'b10
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`define EnvCtrlEnum_defaultEncoding_EBREAK 2'b11
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`define AluCtrlEnum_defaultEncoding_type [1:0]
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`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00
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`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01
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`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10
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`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0]
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`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00
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`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01
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`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10
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`define BranchCtrlEnum_defaultEncoding_type [1:0]
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`define BranchCtrlEnum_defaultEncoding_INC 2'b00
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`define BranchCtrlEnum_defaultEncoding_B 2'b01
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`define BranchCtrlEnum_defaultEncoding_JAL 2'b10
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`define BranchCtrlEnum_defaultEncoding_JALR 2'b11
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`define ShiftCtrlEnum_defaultEncoding_type [1:0]
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`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00
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`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01
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`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10
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`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11
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`define Src2CtrlEnum_defaultEncoding_type [1:0]
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`define Src2CtrlEnum_defaultEncoding_RS 2'b00
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`define Src2CtrlEnum_defaultEncoding_IMI 2'b01
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`define Src2CtrlEnum_defaultEncoding_IMS 2'b10
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`define Src2CtrlEnum_defaultEncoding_PC 2'b11
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module InstructionCache (
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input io_flush,
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input io_cpu_prefetch_isValid,
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output reg io_cpu_prefetch_haltIt,
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input [31:0] io_cpu_prefetch_pc,
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input io_cpu_fetch_isValid,
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input io_cpu_fetch_isStuck,
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input io_cpu_fetch_isRemoved,
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input [31:0] io_cpu_fetch_pc,
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output [31:0] io_cpu_fetch_data,
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input io_cpu_fetch_dataBypassValid,
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input [31:0] io_cpu_fetch_dataBypass,
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output io_cpu_fetch_mmuBus_cmd_isValid,
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output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress,
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output io_cpu_fetch_mmuBus_cmd_bypassTranslation,
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input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress,
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input io_cpu_fetch_mmuBus_rsp_isIoAccess,
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input io_cpu_fetch_mmuBus_rsp_allowRead,
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input io_cpu_fetch_mmuBus_rsp_allowWrite,
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input io_cpu_fetch_mmuBus_rsp_allowExecute,
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input io_cpu_fetch_mmuBus_rsp_exception,
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input io_cpu_fetch_mmuBus_rsp_refilling,
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output io_cpu_fetch_mmuBus_end,
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input io_cpu_fetch_mmuBus_busy,
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output [31:0] io_cpu_fetch_physicalAddress,
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output io_cpu_fetch_cacheMiss,
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output io_cpu_fetch_error,
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output io_cpu_fetch_mmuRefilling,
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output io_cpu_fetch_mmuException,
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input io_cpu_fetch_isUser,
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output io_cpu_fetch_haltIt,
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input io_cpu_decode_isValid,
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input io_cpu_decode_isStuck,
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input [31:0] io_cpu_decode_pc,
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output [31:0] io_cpu_decode_physicalAddress,
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output [31:0] io_cpu_decode_data,
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input io_cpu_fill_valid,
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input [31:0] io_cpu_fill_payload,
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output io_mem_cmd_valid,
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input io_mem_cmd_ready,
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output [31:0] io_mem_cmd_payload_address,
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output [2:0] io_mem_cmd_payload_size,
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input io_mem_rsp_valid,
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input [31:0] io_mem_rsp_payload_data,
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input io_mem_rsp_payload_error,
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input clk,
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input reset);
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reg [22:0] _zz_10_;
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reg [31:0] _zz_11_;
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wire _zz_12_;
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wire _zz_13_;
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wire [0:0] _zz_14_;
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wire [0:0] _zz_15_;
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wire [22:0] _zz_16_;
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reg _zz_1_;
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reg _zz_2_;
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reg lineLoader_fire;
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reg lineLoader_valid;
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reg [31:0] lineLoader_address;
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reg lineLoader_hadError;
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reg lineLoader_flushPending;
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reg [6:0] lineLoader_flushCounter;
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reg _zz_3_;
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reg lineLoader_cmdSent;
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reg lineLoader_wayToAllocate_willIncrement;
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wire lineLoader_wayToAllocate_willClear;
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wire lineLoader_wayToAllocate_willOverflowIfInc;
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wire lineLoader_wayToAllocate_willOverflow;
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reg [2:0] lineLoader_wordIndex;
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wire lineLoader_write_tag_0_valid;
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wire [5:0] lineLoader_write_tag_0_payload_address;
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wire lineLoader_write_tag_0_payload_data_valid;
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wire lineLoader_write_tag_0_payload_data_error;
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wire [20:0] lineLoader_write_tag_0_payload_data_address;
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wire lineLoader_write_data_0_valid;
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wire [8:0] lineLoader_write_data_0_payload_address;
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wire [31:0] lineLoader_write_data_0_payload_data;
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wire _zz_4_;
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wire [5:0] _zz_5_;
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wire _zz_6_;
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wire fetchStage_read_waysValues_0_tag_valid;
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wire fetchStage_read_waysValues_0_tag_error;
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wire [20:0] fetchStage_read_waysValues_0_tag_address;
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wire [22:0] _zz_7_;
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wire [8:0] _zz_8_;
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wire _zz_9_;
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wire [31:0] fetchStage_read_waysValues_0_data;
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wire fetchStage_hit_hits_0;
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wire fetchStage_hit_valid;
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wire fetchStage_hit_error;
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wire [31:0] fetchStage_hit_data;
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wire [31:0] fetchStage_hit_word;
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reg [22:0] ways_0_tags [0:63];
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reg [31:0] ways_0_datas [0:511];
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assign _zz_12_ = (! lineLoader_flushCounter[6]);
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assign _zz_13_ = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid)));
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assign _zz_14_ = _zz_7_[0 : 0];
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assign _zz_15_ = _zz_7_[1 : 1];
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assign _zz_16_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}};
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always @ (posedge clk) begin
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if(_zz_2_) begin
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ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_16_;
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end
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end
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always @ (posedge clk) begin
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if(_zz_6_) begin
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_zz_10_ <= ways_0_tags[_zz_5_];
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end
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end
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always @ (posedge clk) begin
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if(_zz_1_) begin
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ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data;
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end
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end
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always @ (posedge clk) begin
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if(_zz_9_) begin
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_zz_11_ <= ways_0_datas[_zz_8_];
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end
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end
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always @ (*) begin
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_zz_1_ = 1'b0;
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if(lineLoader_write_data_0_valid)begin
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_zz_1_ = 1'b1;
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end
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end
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always @ (*) begin
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_zz_2_ = 1'b0;
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if(lineLoader_write_tag_0_valid)begin
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_zz_2_ = 1'b1;
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end
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end
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assign io_cpu_fetch_haltIt = io_cpu_fetch_mmuBus_busy;
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always @ (*) begin
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lineLoader_fire = 1'b0;
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if(io_mem_rsp_valid)begin
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if((lineLoader_wordIndex == (3'b111)))begin
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lineLoader_fire = 1'b1;
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end
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end
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end
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always @ (*) begin
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io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending);
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if(_zz_12_)begin
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io_cpu_prefetch_haltIt = 1'b1;
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end
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if((! _zz_3_))begin
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io_cpu_prefetch_haltIt = 1'b1;
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end
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if(io_flush)begin
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io_cpu_prefetch_haltIt = 1'b1;
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end
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end
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assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent));
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assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)};
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assign io_mem_cmd_payload_size = (3'b101);
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always @ (*) begin
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lineLoader_wayToAllocate_willIncrement = 1'b0;
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if(lineLoader_fire)begin
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lineLoader_wayToAllocate_willIncrement = 1'b1;
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end
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end
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assign lineLoader_wayToAllocate_willClear = 1'b0;
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assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1;
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assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement);
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assign _zz_4_ = 1'b1;
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assign lineLoader_write_tag_0_valid = ((_zz_4_ && lineLoader_fire) || (! lineLoader_flushCounter[6]));
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assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]);
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assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6];
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assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error);
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assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11];
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assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_4_);
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assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex};
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assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data;
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assign _zz_5_ = io_cpu_prefetch_pc[10 : 5];
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assign _zz_6_ = (! io_cpu_fetch_isStuck);
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assign _zz_7_ = _zz_10_;
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assign fetchStage_read_waysValues_0_tag_valid = _zz_14_[0];
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assign fetchStage_read_waysValues_0_tag_error = _zz_15_[0];
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assign fetchStage_read_waysValues_0_tag_address = _zz_7_[22 : 2];
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assign _zz_8_ = io_cpu_prefetch_pc[10 : 2];
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assign _zz_9_ = (! io_cpu_fetch_isStuck);
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assign fetchStage_read_waysValues_0_data = _zz_11_;
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assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuBus_rsp_physicalAddress[31 : 11]));
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assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != (1'b0));
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assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error;
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assign fetchStage_hit_data = fetchStage_read_waysValues_0_data;
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assign fetchStage_hit_word = fetchStage_hit_data[31 : 0];
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assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_hit_word);
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assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid;
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assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc;
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assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0;
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assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved);
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assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress;
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assign io_cpu_fetch_cacheMiss = (! fetchStage_hit_valid);
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assign io_cpu_fetch_error = fetchStage_hit_error;
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assign io_cpu_fetch_mmuRefilling = io_cpu_fetch_mmuBus_rsp_refilling;
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assign io_cpu_fetch_mmuException = ((! io_cpu_fetch_mmuBus_rsp_refilling) && (io_cpu_fetch_mmuBus_rsp_exception || (! io_cpu_fetch_mmuBus_rsp_allowExecute)));
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always @ (posedge clk) begin
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if(reset) begin
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lineLoader_valid <= 1'b0;
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lineLoader_hadError <= 1'b0;
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lineLoader_flushPending <= 1'b1;
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lineLoader_cmdSent <= 1'b0;
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lineLoader_wordIndex <= (3'b000);
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end else begin
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if(lineLoader_fire)begin
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lineLoader_valid <= 1'b0;
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end
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if(lineLoader_fire)begin
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lineLoader_hadError <= 1'b0;
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end
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if(io_cpu_fill_valid)begin
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lineLoader_valid <= 1'b1;
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end
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if(io_flush)begin
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lineLoader_flushPending <= 1'b1;
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end
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if(_zz_13_)begin
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lineLoader_flushPending <= 1'b0;
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end
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if((io_mem_cmd_valid && io_mem_cmd_ready))begin
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lineLoader_cmdSent <= 1'b1;
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end
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if(lineLoader_fire)begin
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lineLoader_cmdSent <= 1'b0;
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end
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if(io_mem_rsp_valid)begin
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lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001));
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if(io_mem_rsp_payload_error)begin
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lineLoader_hadError <= 1'b1;
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end
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end
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end
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end
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always @ (posedge clk) begin
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if(io_cpu_fill_valid)begin
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lineLoader_address <= io_cpu_fill_payload;
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end
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if(_zz_12_)begin
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lineLoader_flushCounter <= (lineLoader_flushCounter + (7'b0000001));
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end
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_zz_3_ <= lineLoader_flushCounter[6];
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if(_zz_13_)begin
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lineLoader_flushCounter <= (7'b0000000);
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end
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end
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endmodule
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module VexRiscv (
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input [31:0] externalResetVector,
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input timerInterrupt,
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input softwareInterrupt,
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input [31:0] externalInterruptArray,
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input debug_bus_cmd_valid,
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output reg debug_bus_cmd_ready,
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input debug_bus_cmd_payload_wr,
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input [7:0] debug_bus_cmd_payload_address,
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input [31:0] debug_bus_cmd_payload_data,
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output reg [31:0] debug_bus_rsp_data,
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output debug_resetOut,
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output reg iBusWishbone_CYC,
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output reg iBusWishbone_STB,
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input iBusWishbone_ACK,
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output iBusWishbone_WE,
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output [29:0] iBusWishbone_ADR,
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input [31:0] iBusWishbone_DAT_MISO,
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output [31:0] iBusWishbone_DAT_MOSI,
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output [3:0] iBusWishbone_SEL,
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input iBusWishbone_ERR,
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output [1:0] iBusWishbone_BTE,
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output [2:0] iBusWishbone_CTI,
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output dBusWishbone_CYC,
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output dBusWishbone_STB,
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input dBusWishbone_ACK,
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output dBusWishbone_WE,
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output [29:0] dBusWishbone_ADR,
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input [31:0] dBusWishbone_DAT_MISO,
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output [31:0] dBusWishbone_DAT_MOSI,
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output reg [3:0] dBusWishbone_SEL,
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input dBusWishbone_ERR,
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output [1:0] dBusWishbone_BTE,
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output [2:0] dBusWishbone_CTI,
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input clk,
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input reset,
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input debugReset);
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wire _zz_136_;
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wire _zz_137_;
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wire _zz_138_;
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wire _zz_139_;
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wire _zz_140_;
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wire [31:0] _zz_141_;
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wire _zz_142_;
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wire _zz_143_;
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wire _zz_144_;
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wire _zz_145_;
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wire _zz_146_;
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wire _zz_147_;
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wire _zz_148_;
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wire _zz_149_;
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wire _zz_150_;
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wire _zz_151_;
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wire [31:0] _zz_152_;
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reg _zz_153_;
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reg [31:0] _zz_154_;
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reg [31:0] _zz_155_;
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reg [31:0] _zz_156_;
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reg [3:0] _zz_157_;
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reg [31:0] _zz_158_;
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wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt;
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wire IBusCachedPlugin_cache_io_cpu_fetch_error;
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wire IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling;
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wire IBusCachedPlugin_cache_io_cpu_fetch_mmuException;
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wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data;
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wire IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss;
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wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress;
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wire IBusCachedPlugin_cache_io_cpu_fetch_haltIt;
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wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid;
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wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress;
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wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation;
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wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end;
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wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data;
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wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress;
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wire IBusCachedPlugin_cache_io_mem_cmd_valid;
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wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address;
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wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size;
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wire _zz_159_;
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wire _zz_160_;
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wire _zz_161_;
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wire _zz_162_;
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wire _zz_163_;
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wire _zz_164_;
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wire [1:0] _zz_165_;
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wire _zz_166_;
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wire _zz_167_;
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wire _zz_168_;
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wire _zz_169_;
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wire [5:0] _zz_170_;
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wire _zz_171_;
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wire _zz_172_;
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wire [1:0] _zz_173_;
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wire _zz_174_;
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wire [2:0] _zz_175_;
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wire [2:0] _zz_176_;
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wire [31:0] _zz_177_;
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wire [2:0] _zz_178_;
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wire [0:0] _zz_179_;
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wire [0:0] _zz_180_;
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wire [0:0] _zz_181_;
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wire [0:0] _zz_182_;
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wire [0:0] _zz_183_;
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wire [0:0] _zz_184_;
|
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wire [0:0] _zz_185_;
|
|
wire [0:0] _zz_186_;
|
|
wire [0:0] _zz_187_;
|
|
wire [0:0] _zz_188_;
|
|
wire [2:0] _zz_189_;
|
|
wire [4:0] _zz_190_;
|
|
wire [11:0] _zz_191_;
|
|
wire [11:0] _zz_192_;
|
|
wire [31:0] _zz_193_;
|
|
wire [31:0] _zz_194_;
|
|
wire [31:0] _zz_195_;
|
|
wire [31:0] _zz_196_;
|
|
wire [31:0] _zz_197_;
|
|
wire [31:0] _zz_198_;
|
|
wire [31:0] _zz_199_;
|
|
wire [31:0] _zz_200_;
|
|
wire [32:0] _zz_201_;
|
|
wire [19:0] _zz_202_;
|
|
wire [11:0] _zz_203_;
|
|
wire [11:0] _zz_204_;
|
|
wire [1:0] _zz_205_;
|
|
wire [1:0] _zz_206_;
|
|
wire [2:0] _zz_207_;
|
|
wire [0:0] _zz_208_;
|
|
wire [0:0] _zz_209_;
|
|
wire [0:0] _zz_210_;
|
|
wire [0:0] _zz_211_;
|
|
wire [30:0] _zz_212_;
|
|
wire [30:0] _zz_213_;
|
|
wire [30:0] _zz_214_;
|
|
wire [30:0] _zz_215_;
|
|
wire [0:0] _zz_216_;
|
|
wire [0:0] _zz_217_;
|
|
wire [0:0] _zz_218_;
|
|
wire [0:0] _zz_219_;
|
|
wire [0:0] _zz_220_;
|
|
wire [0:0] _zz_221_;
|
|
wire [26:0] _zz_222_;
|
|
wire [6:0] _zz_223_;
|
|
wire [1:0] _zz_224_;
|
|
wire [31:0] _zz_225_;
|
|
wire [31:0] _zz_226_;
|
|
wire [31:0] _zz_227_;
|
|
wire [1:0] _zz_228_;
|
|
wire [1:0] _zz_229_;
|
|
wire _zz_230_;
|
|
wire [0:0] _zz_231_;
|
|
wire [20:0] _zz_232_;
|
|
wire [31:0] _zz_233_;
|
|
wire [31:0] _zz_234_;
|
|
wire [31:0] _zz_235_;
|
|
wire [31:0] _zz_236_;
|
|
wire _zz_237_;
|
|
wire _zz_238_;
|
|
wire [1:0] _zz_239_;
|
|
wire [1:0] _zz_240_;
|
|
wire _zz_241_;
|
|
wire [0:0] _zz_242_;
|
|
wire [16:0] _zz_243_;
|
|
wire [31:0] _zz_244_;
|
|
wire [31:0] _zz_245_;
|
|
wire [31:0] _zz_246_;
|
|
wire [31:0] _zz_247_;
|
|
wire _zz_248_;
|
|
wire _zz_249_;
|
|
wire [0:0] _zz_250_;
|
|
wire [0:0] _zz_251_;
|
|
wire _zz_252_;
|
|
wire [0:0] _zz_253_;
|
|
wire [13:0] _zz_254_;
|
|
wire [31:0] _zz_255_;
|
|
wire _zz_256_;
|
|
wire _zz_257_;
|
|
wire [0:0] _zz_258_;
|
|
wire [0:0] _zz_259_;
|
|
wire _zz_260_;
|
|
wire [0:0] _zz_261_;
|
|
wire [10:0] _zz_262_;
|
|
wire [31:0] _zz_263_;
|
|
wire _zz_264_;
|
|
wire [0:0] _zz_265_;
|
|
wire [0:0] _zz_266_;
|
|
wire [0:0] _zz_267_;
|
|
wire [4:0] _zz_268_;
|
|
wire [1:0] _zz_269_;
|
|
wire [1:0] _zz_270_;
|
|
wire _zz_271_;
|
|
wire [0:0] _zz_272_;
|
|
wire [6:0] _zz_273_;
|
|
wire [31:0] _zz_274_;
|
|
wire [31:0] _zz_275_;
|
|
wire [31:0] _zz_276_;
|
|
wire [31:0] _zz_277_;
|
|
wire _zz_278_;
|
|
wire [0:0] _zz_279_;
|
|
wire [1:0] _zz_280_;
|
|
wire [31:0] _zz_281_;
|
|
wire [31:0] _zz_282_;
|
|
wire _zz_283_;
|
|
wire _zz_284_;
|
|
wire [1:0] _zz_285_;
|
|
wire [1:0] _zz_286_;
|
|
wire _zz_287_;
|
|
wire [0:0] _zz_288_;
|
|
wire [3:0] _zz_289_;
|
|
wire [31:0] _zz_290_;
|
|
wire [31:0] _zz_291_;
|
|
wire [31:0] _zz_292_;
|
|
wire [31:0] _zz_293_;
|
|
wire [31:0] _zz_294_;
|
|
wire [31:0] _zz_295_;
|
|
wire [31:0] _zz_296_;
|
|
wire [31:0] _zz_297_;
|
|
wire _zz_298_;
|
|
wire _zz_299_;
|
|
wire _zz_300_;
|
|
wire [1:0] _zz_301_;
|
|
wire [1:0] _zz_302_;
|
|
wire _zz_303_;
|
|
wire [0:0] _zz_304_;
|
|
wire [0:0] _zz_305_;
|
|
wire [31:0] _zz_306_;
|
|
wire [31:0] _zz_307_;
|
|
wire [31:0] _zz_308_;
|
|
wire [31:0] _zz_309_;
|
|
wire _zz_310_;
|
|
wire _zz_311_;
|
|
wire _zz_312_;
|
|
wire [0:0] _zz_313_;
|
|
wire [2:0] _zz_314_;
|
|
wire [31:0] _zz_315_;
|
|
wire [31:0] _zz_316_;
|
|
wire [31:0] _zz_317_;
|
|
wire _zz_318_;
|
|
wire [0:0] _zz_319_;
|
|
wire [12:0] _zz_320_;
|
|
wire [31:0] _zz_321_;
|
|
wire [31:0] _zz_322_;
|
|
wire [31:0] _zz_323_;
|
|
wire _zz_324_;
|
|
wire [0:0] _zz_325_;
|
|
wire [6:0] _zz_326_;
|
|
wire [31:0] _zz_327_;
|
|
wire [31:0] _zz_328_;
|
|
wire [31:0] _zz_329_;
|
|
wire _zz_330_;
|
|
wire [0:0] _zz_331_;
|
|
wire [0:0] _zz_332_;
|
|
wire decode_SRC_LESS_UNSIGNED;
|
|
wire decode_DO_EBREAK;
|
|
wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL;
|
|
wire `Src1CtrlEnum_defaultEncoding_type _zz_1_;
|
|
wire `Src1CtrlEnum_defaultEncoding_type _zz_2_;
|
|
wire `Src1CtrlEnum_defaultEncoding_type _zz_3_;
|
|
wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL;
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_4_;
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_5_;
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_6_;
|
|
wire decode_MEMORY_ENABLE;
|
|
wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL;
|
|
wire `AluCtrlEnum_defaultEncoding_type _zz_7_;
|
|
wire `AluCtrlEnum_defaultEncoding_type _zz_8_;
|
|
wire `AluCtrlEnum_defaultEncoding_type _zz_9_;
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL;
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_10_;
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_11_;
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_12_;
|
|
wire decode_IS_CSR;
|
|
wire execute_REGFILE_WRITE_VALID;
|
|
wire decode_SRC2_FORCE_ZERO;
|
|
wire decode_CSR_WRITE_OPCODE;
|
|
wire decode_CSR_READ_OPCODE;
|
|
wire decode_MEMORY_STORE;
|
|
wire [31:0] execute_FORMAL_PC_NEXT;
|
|
wire [31:0] decode_FORMAL_PC_NEXT;
|
|
wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL;
|
|
wire `BranchCtrlEnum_defaultEncoding_type _zz_13_;
|
|
wire `BranchCtrlEnum_defaultEncoding_type _zz_14_;
|
|
wire `BranchCtrlEnum_defaultEncoding_type _zz_15_;
|
|
wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL;
|
|
wire `ShiftCtrlEnum_defaultEncoding_type _zz_16_;
|
|
wire `ShiftCtrlEnum_defaultEncoding_type _zz_17_;
|
|
wire `ShiftCtrlEnum_defaultEncoding_type _zz_18_;
|
|
wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL;
|
|
wire `Src2CtrlEnum_defaultEncoding_type _zz_19_;
|
|
wire `Src2CtrlEnum_defaultEncoding_type _zz_20_;
|
|
wire `Src2CtrlEnum_defaultEncoding_type _zz_21_;
|
|
wire execute_DO_EBREAK;
|
|
wire decode_IS_EBREAK;
|
|
wire _zz_22_;
|
|
wire execute_CSR_READ_OPCODE;
|
|
wire execute_CSR_WRITE_OPCODE;
|
|
wire execute_IS_CSR;
|
|
wire _zz_23_;
|
|
wire _zz_24_;
|
|
wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL;
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_25_;
|
|
wire [31:0] execute_BRANCH_CALC;
|
|
wire execute_BRANCH_DO;
|
|
wire [31:0] _zz_26_;
|
|
wire [31:0] execute_RS1;
|
|
wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL;
|
|
wire `BranchCtrlEnum_defaultEncoding_type _zz_27_;
|
|
wire _zz_28_;
|
|
wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL;
|
|
wire `ShiftCtrlEnum_defaultEncoding_type _zz_29_;
|
|
wire _zz_30_;
|
|
wire [31:0] _zz_31_;
|
|
wire [31:0] _zz_32_;
|
|
wire execute_SRC_LESS_UNSIGNED;
|
|
wire execute_SRC2_FORCE_ZERO;
|
|
wire execute_SRC_USE_SUB_LESS;
|
|
wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL;
|
|
wire `Src2CtrlEnum_defaultEncoding_type _zz_33_;
|
|
wire [31:0] _zz_34_;
|
|
wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL;
|
|
wire `Src1CtrlEnum_defaultEncoding_type _zz_35_;
|
|
wire [31:0] _zz_36_;
|
|
wire decode_SRC_USE_SUB_LESS;
|
|
wire decode_SRC_ADD_ZERO;
|
|
wire _zz_37_;
|
|
wire [31:0] execute_SRC_ADD_SUB;
|
|
wire execute_SRC_LESS;
|
|
wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL;
|
|
wire `AluCtrlEnum_defaultEncoding_type _zz_38_;
|
|
wire [31:0] _zz_39_;
|
|
wire [31:0] execute_SRC2;
|
|
wire [31:0] execute_SRC1;
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL;
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_40_;
|
|
reg _zz_41_;
|
|
wire [31:0] _zz_42_;
|
|
wire [31:0] _zz_43_;
|
|
reg decode_REGFILE_WRITE_VALID;
|
|
wire decode_LEGAL_INSTRUCTION;
|
|
wire decode_INSTRUCTION_READY;
|
|
wire _zz_44_;
|
|
wire _zz_45_;
|
|
wire _zz_46_;
|
|
wire `Src2CtrlEnum_defaultEncoding_type _zz_47_;
|
|
wire _zz_48_;
|
|
wire `BranchCtrlEnum_defaultEncoding_type _zz_49_;
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_50_;
|
|
wire _zz_51_;
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_52_;
|
|
wire _zz_53_;
|
|
wire _zz_54_;
|
|
wire `Src1CtrlEnum_defaultEncoding_type _zz_55_;
|
|
wire `ShiftCtrlEnum_defaultEncoding_type _zz_56_;
|
|
wire `AluCtrlEnum_defaultEncoding_type _zz_57_;
|
|
wire _zz_58_;
|
|
wire _zz_59_;
|
|
wire _zz_60_;
|
|
reg [31:0] decode_INSTRUCTION;
|
|
reg [31:0] _zz_61_;
|
|
wire [1:0] execute_MEMORY_ADDRESS_LOW;
|
|
wire [31:0] execute_MEMORY_READ_DATA;
|
|
wire [31:0] execute_REGFILE_WRITE_DATA;
|
|
wire [31:0] _zz_62_;
|
|
wire [31:0] execute_SRC_ADD;
|
|
wire [1:0] _zz_63_;
|
|
wire [31:0] execute_RS2;
|
|
wire execute_MEMORY_STORE;
|
|
wire execute_MEMORY_ENABLE;
|
|
wire execute_ALIGNEMENT_FAULT;
|
|
wire _zz_64_;
|
|
wire decode_FLUSH_ALL;
|
|
reg IBusCachedPlugin_rsp_issueDetected;
|
|
reg _zz_65_;
|
|
reg _zz_66_;
|
|
reg _zz_67_;
|
|
reg [31:0] _zz_68_;
|
|
wire [31:0] decode_PC;
|
|
wire [31:0] _zz_69_;
|
|
wire [31:0] _zz_70_;
|
|
wire [31:0] _zz_71_;
|
|
wire [31:0] execute_PC;
|
|
wire [31:0] execute_INSTRUCTION;
|
|
reg decode_arbitration_haltItself;
|
|
reg decode_arbitration_haltByOther;
|
|
reg decode_arbitration_removeIt;
|
|
reg decode_arbitration_flushAll;
|
|
reg decode_arbitration_isValid;
|
|
wire decode_arbitration_isStuck;
|
|
wire decode_arbitration_isStuckByOthers;
|
|
wire decode_arbitration_isFlushed;
|
|
wire decode_arbitration_isMoving;
|
|
wire decode_arbitration_isFiring;
|
|
reg execute_arbitration_haltItself;
|
|
reg execute_arbitration_haltByOther;
|
|
reg execute_arbitration_removeIt;
|
|
reg execute_arbitration_flushAll;
|
|
reg execute_arbitration_isValid;
|
|
wire execute_arbitration_isStuck;
|
|
wire execute_arbitration_isStuckByOthers;
|
|
wire execute_arbitration_isFlushed;
|
|
wire execute_arbitration_isMoving;
|
|
wire execute_arbitration_isFiring;
|
|
wire [31:0] lastStageInstruction /* verilator public */ ;
|
|
wire [31:0] lastStagePc /* verilator public */ ;
|
|
wire lastStageIsValid /* verilator public */ ;
|
|
wire lastStageIsFiring /* verilator public */ ;
|
|
reg IBusCachedPlugin_fetcherHalt;
|
|
reg IBusCachedPlugin_fetcherflushIt;
|
|
reg IBusCachedPlugin_incomingInstruction;
|
|
wire IBusCachedPlugin_pcValids_0;
|
|
wire IBusCachedPlugin_pcValids_1;
|
|
wire IBusCachedPlugin_redoBranch_valid;
|
|
wire [31:0] IBusCachedPlugin_redoBranch_payload;
|
|
reg IBusCachedPlugin_decodeExceptionPort_valid;
|
|
reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code;
|
|
wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr;
|
|
reg DBusSimplePlugin_memoryExceptionPort_valid;
|
|
reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code;
|
|
wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr;
|
|
wire decodeExceptionPort_valid;
|
|
wire [3:0] decodeExceptionPort_payload_code;
|
|
wire [31:0] decodeExceptionPort_payload_badAddr;
|
|
wire BranchPlugin_jumpInterface_valid;
|
|
wire [31:0] BranchPlugin_jumpInterface_payload;
|
|
reg BranchPlugin_branchExceptionPort_valid;
|
|
wire [3:0] BranchPlugin_branchExceptionPort_payload_code;
|
|
wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr;
|
|
reg CsrPlugin_jumpInterface_valid;
|
|
reg [31:0] CsrPlugin_jumpInterface_payload;
|
|
wire CsrPlugin_exceptionPendings_0;
|
|
wire CsrPlugin_exceptionPendings_1;
|
|
wire externalInterrupt;
|
|
wire contextSwitching;
|
|
reg [1:0] CsrPlugin_privilege;
|
|
reg CsrPlugin_forceMachineWire;
|
|
reg CsrPlugin_selfException_valid;
|
|
reg [3:0] CsrPlugin_selfException_payload_code;
|
|
wire [31:0] CsrPlugin_selfException_payload_badAddr;
|
|
reg CsrPlugin_allowInterrupts;
|
|
reg CsrPlugin_allowException;
|
|
reg IBusCachedPlugin_injectionPort_valid;
|
|
reg IBusCachedPlugin_injectionPort_ready;
|
|
wire [31:0] IBusCachedPlugin_injectionPort_payload;
|
|
wire IBusCachedPlugin_jump_pcLoad_valid;
|
|
wire [31:0] IBusCachedPlugin_jump_pcLoad_payload;
|
|
wire [2:0] _zz_72_;
|
|
wire [2:0] _zz_73_;
|
|
wire _zz_74_;
|
|
wire _zz_75_;
|
|
wire IBusCachedPlugin_fetchPc_preOutput_valid;
|
|
wire IBusCachedPlugin_fetchPc_preOutput_ready;
|
|
wire [31:0] IBusCachedPlugin_fetchPc_preOutput_payload;
|
|
wire _zz_76_;
|
|
wire IBusCachedPlugin_fetchPc_output_valid;
|
|
wire IBusCachedPlugin_fetchPc_output_ready;
|
|
wire [31:0] IBusCachedPlugin_fetchPc_output_payload;
|
|
reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ;
|
|
reg IBusCachedPlugin_fetchPc_inc;
|
|
reg IBusCachedPlugin_fetchPc_propagatePc;
|
|
reg [31:0] IBusCachedPlugin_fetchPc_pc;
|
|
reg IBusCachedPlugin_fetchPc_samplePcNext;
|
|
reg _zz_77_;
|
|
wire IBusCachedPlugin_iBusRsp_stages_0_input_valid;
|
|
wire IBusCachedPlugin_iBusRsp_stages_0_input_ready;
|
|
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload;
|
|
wire IBusCachedPlugin_iBusRsp_stages_0_output_valid;
|
|
wire IBusCachedPlugin_iBusRsp_stages_0_output_ready;
|
|
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload;
|
|
reg IBusCachedPlugin_iBusRsp_stages_0_halt;
|
|
wire IBusCachedPlugin_iBusRsp_stages_0_inputSample;
|
|
wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid;
|
|
wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready;
|
|
wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload;
|
|
wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid;
|
|
wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready;
|
|
wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload;
|
|
reg IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt;
|
|
wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample;
|
|
wire _zz_78_;
|
|
wire _zz_79_;
|
|
wire _zz_80_;
|
|
wire _zz_81_;
|
|
reg _zz_82_;
|
|
reg IBusCachedPlugin_iBusRsp_readyForError;
|
|
wire IBusCachedPlugin_iBusRsp_decodeInput_valid;
|
|
wire IBusCachedPlugin_iBusRsp_decodeInput_ready;
|
|
wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_pc;
|
|
wire IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_error;
|
|
wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst;
|
|
wire IBusCachedPlugin_iBusRsp_decodeInput_payload_isRvc;
|
|
reg IBusCachedPlugin_injector_nextPcCalc_valids_0;
|
|
reg IBusCachedPlugin_injector_nextPcCalc_valids_1;
|
|
reg IBusCachedPlugin_injector_decodeRemoved;
|
|
wire iBus_cmd_valid;
|
|
wire iBus_cmd_ready;
|
|
reg [31:0] iBus_cmd_payload_address;
|
|
wire [2:0] iBus_cmd_payload_size;
|
|
wire iBus_rsp_valid;
|
|
wire [31:0] iBus_rsp_payload_data;
|
|
wire iBus_rsp_payload_error;
|
|
wire IBusCachedPlugin_s0_tightlyCoupledHit;
|
|
reg IBusCachedPlugin_s1_tightlyCoupledHit;
|
|
wire IBusCachedPlugin_rsp_iBusRspOutputHalt;
|
|
reg IBusCachedPlugin_rsp_redoFetch;
|
|
wire dBus_cmd_valid;
|
|
wire dBus_cmd_ready;
|
|
wire dBus_cmd_payload_wr;
|
|
wire [31:0] dBus_cmd_payload_address;
|
|
wire [31:0] dBus_cmd_payload_data;
|
|
wire [1:0] dBus_cmd_payload_size;
|
|
wire dBus_rsp_ready;
|
|
wire dBus_rsp_error;
|
|
wire [31:0] dBus_rsp_data;
|
|
reg _zz_83_;
|
|
reg execute_DBusSimplePlugin_skipCmd;
|
|
reg [31:0] _zz_84_;
|
|
reg [3:0] _zz_85_;
|
|
wire [3:0] execute_DBusSimplePlugin_formalMask;
|
|
reg [31:0] execute_DBusSimplePlugin_rspShifted;
|
|
wire _zz_86_;
|
|
reg [31:0] _zz_87_;
|
|
wire _zz_88_;
|
|
reg [31:0] _zz_89_;
|
|
reg [31:0] execute_DBusSimplePlugin_rspFormated;
|
|
wire [27:0] _zz_90_;
|
|
wire _zz_91_;
|
|
wire _zz_92_;
|
|
wire _zz_93_;
|
|
wire _zz_94_;
|
|
wire _zz_95_;
|
|
wire `AluCtrlEnum_defaultEncoding_type _zz_96_;
|
|
wire `ShiftCtrlEnum_defaultEncoding_type _zz_97_;
|
|
wire `Src1CtrlEnum_defaultEncoding_type _zz_98_;
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_99_;
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_100_;
|
|
wire `BranchCtrlEnum_defaultEncoding_type _zz_101_;
|
|
wire `Src2CtrlEnum_defaultEncoding_type _zz_102_;
|
|
wire [4:0] execute_RegFilePlugin_regFileReadAddress1;
|
|
wire [4:0] execute_RegFilePlugin_regFileReadAddress2;
|
|
wire _zz_103_;
|
|
wire [31:0] execute_RegFilePlugin_rs1Data;
|
|
wire [31:0] execute_RegFilePlugin_rs2Data;
|
|
wire lastStageRegFileWrite_valid /* verilator public */ ;
|
|
wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ;
|
|
wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ;
|
|
reg [31:0] execute_IntAluPlugin_bitwise;
|
|
reg [31:0] _zz_104_;
|
|
reg [31:0] _zz_105_;
|
|
wire _zz_106_;
|
|
reg [19:0] _zz_107_;
|
|
wire _zz_108_;
|
|
reg [19:0] _zz_109_;
|
|
reg [31:0] _zz_110_;
|
|
reg [31:0] execute_SrcPlugin_addSub;
|
|
wire execute_SrcPlugin_less;
|
|
reg execute_LightShifterPlugin_isActive;
|
|
wire execute_LightShifterPlugin_isShift;
|
|
reg [4:0] execute_LightShifterPlugin_amplitudeReg;
|
|
wire [4:0] execute_LightShifterPlugin_amplitude;
|
|
reg [31:0] execute_LightShifterPlugin_shiftReg;
|
|
wire [31:0] execute_LightShifterPlugin_shiftInput;
|
|
wire execute_LightShifterPlugin_done;
|
|
reg [31:0] _zz_111_;
|
|
wire execute_BranchPlugin_eq;
|
|
wire [2:0] _zz_112_;
|
|
reg _zz_113_;
|
|
reg _zz_114_;
|
|
wire [31:0] execute_BranchPlugin_branch_src1;
|
|
wire _zz_115_;
|
|
reg [10:0] _zz_116_;
|
|
wire _zz_117_;
|
|
reg [19:0] _zz_118_;
|
|
wire _zz_119_;
|
|
reg [18:0] _zz_120_;
|
|
reg [31:0] _zz_121_;
|
|
wire [31:0] execute_BranchPlugin_branch_src2;
|
|
wire [31:0] execute_BranchPlugin_branchAdder;
|
|
wire [1:0] CsrPlugin_misa_base;
|
|
wire [25:0] CsrPlugin_misa_extensions;
|
|
reg [1:0] CsrPlugin_mtvec_mode;
|
|
reg [29:0] CsrPlugin_mtvec_base;
|
|
reg [31:0] CsrPlugin_mepc;
|
|
reg CsrPlugin_mstatus_MIE;
|
|
reg CsrPlugin_mstatus_MPIE;
|
|
reg [1:0] CsrPlugin_mstatus_MPP;
|
|
reg CsrPlugin_mip_MEIP;
|
|
reg CsrPlugin_mip_MTIP;
|
|
reg CsrPlugin_mip_MSIP;
|
|
reg CsrPlugin_mie_MEIE;
|
|
reg CsrPlugin_mie_MTIE;
|
|
reg CsrPlugin_mie_MSIE;
|
|
reg [31:0] CsrPlugin_mscratch;
|
|
reg CsrPlugin_mcause_interrupt;
|
|
reg [3:0] CsrPlugin_mcause_exceptionCode;
|
|
reg [31:0] CsrPlugin_mtval;
|
|
reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000;
|
|
reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000;
|
|
reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
|
|
reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
|
|
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
|
|
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
|
|
reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code;
|
|
reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
|
|
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped;
|
|
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
|
|
wire [1:0] _zz_122_;
|
|
wire _zz_123_;
|
|
wire [2:0] _zz_124_;
|
|
wire [2:0] _zz_125_;
|
|
wire _zz_126_;
|
|
wire _zz_127_;
|
|
wire [1:0] _zz_128_;
|
|
reg CsrPlugin_interrupt;
|
|
reg [3:0] CsrPlugin_interruptCode /* verilator public */ ;
|
|
reg [1:0] CsrPlugin_interruptTargetPrivilege;
|
|
wire CsrPlugin_exception;
|
|
wire CsrPlugin_lastStageWasWfi;
|
|
reg CsrPlugin_pipelineLiberator_done;
|
|
wire CsrPlugin_interruptJump /* verilator public */ ;
|
|
reg CsrPlugin_hadException;
|
|
reg [1:0] CsrPlugin_targetPrivilege;
|
|
reg [3:0] CsrPlugin_trapCause;
|
|
reg [1:0] CsrPlugin_xtvec_mode;
|
|
reg [29:0] CsrPlugin_xtvec_base;
|
|
wire execute_CsrPlugin_inWfi /* verilator public */ ;
|
|
wire execute_CsrPlugin_blockedBySideEffects;
|
|
reg execute_CsrPlugin_illegalAccess;
|
|
reg execute_CsrPlugin_illegalInstruction;
|
|
reg [31:0] execute_CsrPlugin_readData;
|
|
wire execute_CsrPlugin_writeInstruction;
|
|
wire execute_CsrPlugin_readInstruction;
|
|
wire execute_CsrPlugin_writeEnable;
|
|
wire execute_CsrPlugin_readEnable;
|
|
wire [31:0] execute_CsrPlugin_readToWriteData;
|
|
reg [31:0] execute_CsrPlugin_writeData;
|
|
wire [11:0] execute_CsrPlugin_csrAddress;
|
|
reg [31:0] _zz_129_;
|
|
reg [31:0] externalInterruptArray_regNext;
|
|
wire [31:0] _zz_130_;
|
|
reg DebugPlugin_firstCycle;
|
|
reg DebugPlugin_secondCycle;
|
|
reg DebugPlugin_resetIt;
|
|
reg DebugPlugin_haltIt;
|
|
reg DebugPlugin_stepIt;
|
|
reg DebugPlugin_isPipBusy;
|
|
reg DebugPlugin_godmode;
|
|
reg DebugPlugin_haltedByBreak;
|
|
reg DebugPlugin_hardwareBreakpoints_0_valid;
|
|
reg [30:0] DebugPlugin_hardwareBreakpoints_0_pc;
|
|
reg DebugPlugin_hardwareBreakpoints_1_valid;
|
|
reg [30:0] DebugPlugin_hardwareBreakpoints_1_pc;
|
|
reg DebugPlugin_hardwareBreakpoints_2_valid;
|
|
reg [30:0] DebugPlugin_hardwareBreakpoints_2_pc;
|
|
reg DebugPlugin_hardwareBreakpoints_3_valid;
|
|
reg [30:0] DebugPlugin_hardwareBreakpoints_3_pc;
|
|
reg [31:0] DebugPlugin_busReadDataReg;
|
|
reg _zz_131_;
|
|
reg DebugPlugin_resetIt_regNext;
|
|
reg decode_to_execute_SRC_USE_SUB_LESS;
|
|
reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL;
|
|
reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL;
|
|
reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL;
|
|
reg [31:0] decode_to_execute_FORMAL_PC_NEXT;
|
|
reg decode_to_execute_MEMORY_STORE;
|
|
reg decode_to_execute_CSR_READ_OPCODE;
|
|
reg decode_to_execute_CSR_WRITE_OPCODE;
|
|
reg decode_to_execute_SRC2_FORCE_ZERO;
|
|
reg decode_to_execute_REGFILE_WRITE_VALID;
|
|
reg [31:0] decode_to_execute_INSTRUCTION;
|
|
reg decode_to_execute_IS_CSR;
|
|
reg [31:0] decode_to_execute_PC;
|
|
reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL;
|
|
reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL;
|
|
reg decode_to_execute_MEMORY_ENABLE;
|
|
reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL;
|
|
reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL;
|
|
reg decode_to_execute_DO_EBREAK;
|
|
reg decode_to_execute_SRC_LESS_UNSIGNED;
|
|
reg [2:0] _zz_132_;
|
|
reg [31:0] IBusCachedPlugin_injectionPort_payload_regNext;
|
|
reg [2:0] _zz_133_;
|
|
reg _zz_134_;
|
|
reg [31:0] iBusWishbone_DAT_MISO_regNext;
|
|
wire dBus_cmd_halfPipe_valid;
|
|
wire dBus_cmd_halfPipe_ready;
|
|
wire dBus_cmd_halfPipe_payload_wr;
|
|
wire [31:0] dBus_cmd_halfPipe_payload_address;
|
|
wire [31:0] dBus_cmd_halfPipe_payload_data;
|
|
wire [1:0] dBus_cmd_halfPipe_payload_size;
|
|
reg dBus_cmd_halfPipe_regs_valid;
|
|
reg dBus_cmd_halfPipe_regs_ready;
|
|
reg dBus_cmd_halfPipe_regs_payload_wr;
|
|
reg [31:0] dBus_cmd_halfPipe_regs_payload_address;
|
|
reg [31:0] dBus_cmd_halfPipe_regs_payload_data;
|
|
reg [1:0] dBus_cmd_halfPipe_regs_payload_size;
|
|
reg [3:0] _zz_135_;
|
|
`ifndef SYNTHESIS
|
|
reg [95:0] decode_SRC1_CTRL_string;
|
|
reg [95:0] _zz_1__string;
|
|
reg [95:0] _zz_2__string;
|
|
reg [95:0] _zz_3__string;
|
|
reg [47:0] decode_ENV_CTRL_string;
|
|
reg [47:0] _zz_4__string;
|
|
reg [47:0] _zz_5__string;
|
|
reg [47:0] _zz_6__string;
|
|
reg [63:0] decode_ALU_CTRL_string;
|
|
reg [63:0] _zz_7__string;
|
|
reg [63:0] _zz_8__string;
|
|
reg [63:0] _zz_9__string;
|
|
reg [39:0] decode_ALU_BITWISE_CTRL_string;
|
|
reg [39:0] _zz_10__string;
|
|
reg [39:0] _zz_11__string;
|
|
reg [39:0] _zz_12__string;
|
|
reg [31:0] decode_BRANCH_CTRL_string;
|
|
reg [31:0] _zz_13__string;
|
|
reg [31:0] _zz_14__string;
|
|
reg [31:0] _zz_15__string;
|
|
reg [71:0] decode_SHIFT_CTRL_string;
|
|
reg [71:0] _zz_16__string;
|
|
reg [71:0] _zz_17__string;
|
|
reg [71:0] _zz_18__string;
|
|
reg [23:0] decode_SRC2_CTRL_string;
|
|
reg [23:0] _zz_19__string;
|
|
reg [23:0] _zz_20__string;
|
|
reg [23:0] _zz_21__string;
|
|
reg [47:0] execute_ENV_CTRL_string;
|
|
reg [47:0] _zz_25__string;
|
|
reg [31:0] execute_BRANCH_CTRL_string;
|
|
reg [31:0] _zz_27__string;
|
|
reg [71:0] execute_SHIFT_CTRL_string;
|
|
reg [71:0] _zz_29__string;
|
|
reg [23:0] execute_SRC2_CTRL_string;
|
|
reg [23:0] _zz_33__string;
|
|
reg [95:0] execute_SRC1_CTRL_string;
|
|
reg [95:0] _zz_35__string;
|
|
reg [63:0] execute_ALU_CTRL_string;
|
|
reg [63:0] _zz_38__string;
|
|
reg [39:0] execute_ALU_BITWISE_CTRL_string;
|
|
reg [39:0] _zz_40__string;
|
|
reg [23:0] _zz_47__string;
|
|
reg [31:0] _zz_49__string;
|
|
reg [47:0] _zz_50__string;
|
|
reg [39:0] _zz_52__string;
|
|
reg [95:0] _zz_55__string;
|
|
reg [71:0] _zz_56__string;
|
|
reg [63:0] _zz_57__string;
|
|
reg [63:0] _zz_96__string;
|
|
reg [71:0] _zz_97__string;
|
|
reg [95:0] _zz_98__string;
|
|
reg [39:0] _zz_99__string;
|
|
reg [47:0] _zz_100__string;
|
|
reg [31:0] _zz_101__string;
|
|
reg [23:0] _zz_102__string;
|
|
reg [23:0] decode_to_execute_SRC2_CTRL_string;
|
|
reg [71:0] decode_to_execute_SHIFT_CTRL_string;
|
|
reg [31:0] decode_to_execute_BRANCH_CTRL_string;
|
|
reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string;
|
|
reg [63:0] decode_to_execute_ALU_CTRL_string;
|
|
reg [47:0] decode_to_execute_ENV_CTRL_string;
|
|
reg [95:0] decode_to_execute_SRC1_CTRL_string;
|
|
`endif
|
|
|
|
reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ;
|
|
assign _zz_159_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000)));
|
|
assign _zz_160_ = (! execute_arbitration_isStuckByOthers);
|
|
assign _zz_161_ = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != (2'b00));
|
|
assign _zz_162_ = ({CsrPlugin_selfException_valid,{BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}} != (3'b000));
|
|
assign _zz_163_ = (CsrPlugin_hadException || CsrPlugin_interruptJump);
|
|
assign _zz_164_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET));
|
|
assign _zz_165_ = execute_INSTRUCTION[29 : 28];
|
|
assign _zz_166_ = (execute_arbitration_isValid && execute_DO_EBREAK);
|
|
assign _zz_167_ = (1'b0 == 1'b0);
|
|
assign _zz_168_ = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction);
|
|
assign _zz_169_ = (IBusCachedPlugin_fetchPc_preOutput_valid && IBusCachedPlugin_fetchPc_preOutput_ready);
|
|
assign _zz_170_ = debug_bus_cmd_payload_address[7 : 2];
|
|
assign _zz_171_ = (iBus_cmd_valid || (_zz_133_ != (3'b000)));
|
|
assign _zz_172_ = (! dBus_cmd_halfPipe_regs_valid);
|
|
assign _zz_173_ = execute_INSTRUCTION[13 : 12];
|
|
assign _zz_174_ = execute_INSTRUCTION[13];
|
|
assign _zz_175_ = (_zz_72_ - (3'b001));
|
|
assign _zz_176_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)};
|
|
assign _zz_177_ = {29'd0, _zz_176_};
|
|
assign _zz_178_ = (execute_MEMORY_STORE ? (3'b110) : (3'b100));
|
|
assign _zz_179_ = _zz_90_[1 : 1];
|
|
assign _zz_180_ = _zz_90_[3 : 3];
|
|
assign _zz_181_ = _zz_90_[10 : 10];
|
|
assign _zz_182_ = _zz_90_[11 : 11];
|
|
assign _zz_183_ = _zz_90_[14 : 14];
|
|
assign _zz_184_ = _zz_90_[19 : 19];
|
|
assign _zz_185_ = _zz_90_[23 : 23];
|
|
assign _zz_186_ = _zz_90_[25 : 25];
|
|
assign _zz_187_ = _zz_90_[27 : 27];
|
|
assign _zz_188_ = execute_SRC_LESS;
|
|
assign _zz_189_ = (3'b100);
|
|
assign _zz_190_ = execute_INSTRUCTION[19 : 15];
|
|
assign _zz_191_ = execute_INSTRUCTION[31 : 20];
|
|
assign _zz_192_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]};
|
|
assign _zz_193_ = ($signed(_zz_194_) + $signed(_zz_197_));
|
|
assign _zz_194_ = ($signed(_zz_195_) + $signed(_zz_196_));
|
|
assign _zz_195_ = execute_SRC1;
|
|
assign _zz_196_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2);
|
|
assign _zz_197_ = (execute_SRC_USE_SUB_LESS ? _zz_198_ : _zz_199_);
|
|
assign _zz_198_ = (32'b00000000000000000000000000000001);
|
|
assign _zz_199_ = (32'b00000000000000000000000000000000);
|
|
assign _zz_200_ = (_zz_201_ >>> 1);
|
|
assign _zz_201_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput};
|
|
assign _zz_202_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
|
|
assign _zz_203_ = execute_INSTRUCTION[31 : 20];
|
|
assign _zz_204_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
|
|
assign _zz_205_ = (_zz_122_ & (~ _zz_206_));
|
|
assign _zz_206_ = (_zz_122_ - (2'b01));
|
|
assign _zz_207_ = (_zz_124_ - (3'b001));
|
|
assign _zz_208_ = debug_bus_cmd_payload_data[0 : 0];
|
|
assign _zz_209_ = debug_bus_cmd_payload_data[0 : 0];
|
|
assign _zz_210_ = debug_bus_cmd_payload_data[0 : 0];
|
|
assign _zz_211_ = debug_bus_cmd_payload_data[0 : 0];
|
|
assign _zz_212_ = (decode_PC >>> 1);
|
|
assign _zz_213_ = (decode_PC >>> 1);
|
|
assign _zz_214_ = (decode_PC >>> 1);
|
|
assign _zz_215_ = (decode_PC >>> 1);
|
|
assign _zz_216_ = execute_CsrPlugin_writeData[7 : 7];
|
|
assign _zz_217_ = execute_CsrPlugin_writeData[3 : 3];
|
|
assign _zz_218_ = execute_CsrPlugin_writeData[3 : 3];
|
|
assign _zz_219_ = execute_CsrPlugin_writeData[11 : 11];
|
|
assign _zz_220_ = execute_CsrPlugin_writeData[7 : 7];
|
|
assign _zz_221_ = execute_CsrPlugin_writeData[3 : 3];
|
|
assign _zz_222_ = (iBus_cmd_payload_address >>> 5);
|
|
assign _zz_223_ = ({3'd0,_zz_135_} <<< dBus_cmd_halfPipe_payload_address[1 : 0]);
|
|
assign _zz_224_ = {_zz_75_,_zz_74_};
|
|
assign _zz_225_ = (32'b00000000000000000000000000010000);
|
|
assign _zz_226_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000));
|
|
assign _zz_227_ = (32'b00000000000000000000000000000000);
|
|
assign _zz_228_ = {((decode_INSTRUCTION & _zz_233_) == (32'b00000000000000000001000001010000)),((decode_INSTRUCTION & _zz_234_) == (32'b00000000000000000010000001010000))};
|
|
assign _zz_229_ = (2'b00);
|
|
assign _zz_230_ = ({_zz_95_,(_zz_235_ == _zz_236_)} != (2'b00));
|
|
assign _zz_231_ = ({_zz_95_,_zz_237_} != (2'b00));
|
|
assign _zz_232_ = {(_zz_238_ != (1'b0)),{(_zz_239_ != _zz_240_),{_zz_241_,{_zz_242_,_zz_243_}}}};
|
|
assign _zz_233_ = (32'b00000000000000000001000001010000);
|
|
assign _zz_234_ = (32'b00000000000000000010000001010000);
|
|
assign _zz_235_ = (decode_INSTRUCTION & (32'b00000000000000000000000001110000));
|
|
assign _zz_236_ = (32'b00000000000000000000000000100000);
|
|
assign _zz_237_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000000000));
|
|
assign _zz_238_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000000)) == (32'b00000000000000000000000000000000));
|
|
assign _zz_239_ = {(_zz_244_ == _zz_245_),(_zz_246_ == _zz_247_)};
|
|
assign _zz_240_ = (2'b00);
|
|
assign _zz_241_ = ({_zz_93_,_zz_248_} != (2'b00));
|
|
assign _zz_242_ = (_zz_249_ != (1'b0));
|
|
assign _zz_243_ = {(_zz_250_ != _zz_251_),{_zz_252_,{_zz_253_,_zz_254_}}};
|
|
assign _zz_244_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100));
|
|
assign _zz_245_ = (32'b00000000000000000000000000100100);
|
|
assign _zz_246_ = (decode_INSTRUCTION & (32'b00000000000000000011000001010100));
|
|
assign _zz_247_ = (32'b00000000000000000001000000010000);
|
|
assign _zz_248_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000011100)) == (32'b00000000000000000000000000000100));
|
|
assign _zz_249_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000001000000));
|
|
assign _zz_250_ = ((decode_INSTRUCTION & _zz_255_) == (32'b00000000000000000000000001010000));
|
|
assign _zz_251_ = (1'b0);
|
|
assign _zz_252_ = ({_zz_94_,_zz_256_} != (2'b00));
|
|
assign _zz_253_ = (_zz_257_ != (1'b0));
|
|
assign _zz_254_ = {(_zz_258_ != _zz_259_),{_zz_260_,{_zz_261_,_zz_262_}}};
|
|
assign _zz_255_ = (32'b00010000000000000011000001010000);
|
|
assign _zz_256_ = ((decode_INSTRUCTION & (32'b00010000010000000011000001010000)) == (32'b00010000000000000000000001010000));
|
|
assign _zz_257_ = ((decode_INSTRUCTION & (32'b00000000000000000001000001001000)) == (32'b00000000000000000001000000001000));
|
|
assign _zz_258_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000000000)) == (32'b00000000000000000001000000000000));
|
|
assign _zz_259_ = (1'b0);
|
|
assign _zz_260_ = (((decode_INSTRUCTION & _zz_263_) == (32'b00000000000000000010000000000000)) != (1'b0));
|
|
assign _zz_261_ = ({_zz_264_,{_zz_265_,_zz_266_}} != (3'b000));
|
|
assign _zz_262_ = {({_zz_267_,_zz_268_} != (6'b000000)),{(_zz_269_ != _zz_270_),{_zz_271_,{_zz_272_,_zz_273_}}}};
|
|
assign _zz_263_ = (32'b00000000000000000011000000000000);
|
|
assign _zz_264_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000001000000));
|
|
assign _zz_265_ = ((decode_INSTRUCTION & _zz_274_) == (32'b00000000000000000010000000010000));
|
|
assign _zz_266_ = ((decode_INSTRUCTION & _zz_275_) == (32'b01000000000000000000000000110000));
|
|
assign _zz_267_ = _zz_93_;
|
|
assign _zz_268_ = {(_zz_276_ == _zz_277_),{_zz_278_,{_zz_279_,_zz_280_}}};
|
|
assign _zz_269_ = {(_zz_281_ == _zz_282_),_zz_91_};
|
|
assign _zz_270_ = (2'b00);
|
|
assign _zz_271_ = ({_zz_283_,_zz_91_} != (2'b00));
|
|
assign _zz_272_ = (_zz_284_ != (1'b0));
|
|
assign _zz_273_ = {(_zz_285_ != _zz_286_),{_zz_287_,{_zz_288_,_zz_289_}}};
|
|
assign _zz_274_ = (32'b00000000000000000010000000010100);
|
|
assign _zz_275_ = (32'b01000000000000000100000000110100);
|
|
assign _zz_276_ = (decode_INSTRUCTION & (32'b00000000000000000001000000010000));
|
|
assign _zz_277_ = (32'b00000000000000000001000000010000);
|
|
assign _zz_278_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000010000));
|
|
assign _zz_279_ = _zz_92_;
|
|
assign _zz_280_ = {(_zz_290_ == _zz_291_),(_zz_292_ == _zz_293_)};
|
|
assign _zz_281_ = (decode_INSTRUCTION & (32'b00000000000000000000000000010100));
|
|
assign _zz_282_ = (32'b00000000000000000000000000000100);
|
|
assign _zz_283_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000000000100));
|
|
assign _zz_284_ = ((decode_INSTRUCTION & (32'b00000000000000000111000001010100)) == (32'b00000000000000000101000000010000));
|
|
assign _zz_285_ = {(_zz_294_ == _zz_295_),(_zz_296_ == _zz_297_)};
|
|
assign _zz_286_ = (2'b00);
|
|
assign _zz_287_ = ({_zz_298_,_zz_299_} != (2'b00));
|
|
assign _zz_288_ = (_zz_300_ != (1'b0));
|
|
assign _zz_289_ = {(_zz_301_ != _zz_302_),{_zz_303_,{_zz_304_,_zz_305_}}};
|
|
assign _zz_290_ = (decode_INSTRUCTION & (32'b00000000000000000000000000001100));
|
|
assign _zz_291_ = (32'b00000000000000000000000000000100);
|
|
assign _zz_292_ = (decode_INSTRUCTION & (32'b00000000000000000000000000101000));
|
|
assign _zz_293_ = (32'b00000000000000000000000000000000);
|
|
assign _zz_294_ = (decode_INSTRUCTION & (32'b01000000000000000011000001010100));
|
|
assign _zz_295_ = (32'b01000000000000000001000000010000);
|
|
assign _zz_296_ = (decode_INSTRUCTION & (32'b00000000000000000111000001010100));
|
|
assign _zz_297_ = (32'b00000000000000000001000000010000);
|
|
assign _zz_298_ = ((decode_INSTRUCTION & (32'b00000000000000000110000000010100)) == (32'b00000000000000000110000000010000));
|
|
assign _zz_299_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000010100)) == (32'b00000000000000000100000000010000));
|
|
assign _zz_300_ = ((decode_INSTRUCTION & (32'b00000000000000000110000000010100)) == (32'b00000000000000000010000000010000));
|
|
assign _zz_301_ = {(_zz_306_ == _zz_307_),(_zz_308_ == _zz_309_)};
|
|
assign _zz_302_ = (2'b00);
|
|
assign _zz_303_ = ({_zz_310_,_zz_311_} != (2'b00));
|
|
assign _zz_304_ = (_zz_312_ != (1'b0));
|
|
assign _zz_305_ = ({_zz_313_,_zz_314_} != (4'b0000));
|
|
assign _zz_306_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010000));
|
|
assign _zz_307_ = (32'b00000000000000000010000000000000);
|
|
assign _zz_308_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000000));
|
|
assign _zz_309_ = (32'b00000000000000000001000000000000);
|
|
assign _zz_310_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000110100)) == (32'b00000000000000000000000000100000));
|
|
assign _zz_311_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100000));
|
|
assign _zz_312_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000100000));
|
|
assign _zz_313_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000000000000));
|
|
assign _zz_314_ = {((decode_INSTRUCTION & (32'b00000000000000000000000000011000)) == (32'b00000000000000000000000000000000)),{((decode_INSTRUCTION & (32'b00000000000000000110000000000100)) == (32'b00000000000000000010000000000000)),((decode_INSTRUCTION & (32'b00000000000000000101000000000100)) == (32'b00000000000000000001000000000000))}};
|
|
assign _zz_315_ = (32'b00000000000000000001000001111111);
|
|
assign _zz_316_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111));
|
|
assign _zz_317_ = (32'b00000000000000000010000001110011);
|
|
assign _zz_318_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011));
|
|
assign _zz_319_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011));
|
|
assign _zz_320_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_321_) == (32'b00000000000000000000000000000011)),{(_zz_322_ == _zz_323_),{_zz_324_,{_zz_325_,_zz_326_}}}}}};
|
|
assign _zz_321_ = (32'b00000000000000000101000001011111);
|
|
assign _zz_322_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011));
|
|
assign _zz_323_ = (32'b00000000000000000000000001100011);
|
|
assign _zz_324_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111));
|
|
assign _zz_325_ = ((decode_INSTRUCTION & (32'b11111110000000000000000001111111)) == (32'b00000000000000000000000000110011));
|
|
assign _zz_326_ = {((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & (32'b11111100000000000011000001111111)) == (32'b00000000000000000001000000010011)),{((decode_INSTRUCTION & _zz_327_) == (32'b00000000000000000101000000110011)),{(_zz_328_ == _zz_329_),{_zz_330_,{_zz_331_,_zz_332_}}}}}};
|
|
assign _zz_327_ = (32'b10111110000000000111000001111111);
|
|
assign _zz_328_ = (decode_INSTRUCTION & (32'b10111110000000000111000001111111));
|
|
assign _zz_329_ = (32'b00000000000000000000000000110011);
|
|
assign _zz_330_ = ((decode_INSTRUCTION & (32'b11011111111111111111111111111111)) == (32'b00010000001000000000000001110011));
|
|
assign _zz_331_ = ((decode_INSTRUCTION & (32'b11111111111011111111111111111111)) == (32'b00000000000000000000000001110011));
|
|
assign _zz_332_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00010000010100000000000001110011));
|
|
initial begin
|
|
$readmemb("2-stage-2048-cache-debug.v_toplevel_RegFilePlugin_regFile.bin",RegFilePlugin_regFile);
|
|
end
|
|
always @ (posedge clk) begin
|
|
if(_zz_41_) begin
|
|
RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data;
|
|
end
|
|
end
|
|
|
|
always @ (posedge clk) begin
|
|
if(_zz_103_) begin
|
|
_zz_154_ <= RegFilePlugin_regFile[execute_RegFilePlugin_regFileReadAddress1];
|
|
end
|
|
end
|
|
|
|
always @ (posedge clk) begin
|
|
if(_zz_103_) begin
|
|
_zz_155_ <= RegFilePlugin_regFile[execute_RegFilePlugin_regFileReadAddress2];
|
|
end
|
|
end
|
|
|
|
InstructionCache IBusCachedPlugin_cache (
|
|
.io_flush(_zz_136_),
|
|
.io_cpu_prefetch_isValid(_zz_137_),
|
|
.io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt),
|
|
.io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_0_input_payload),
|
|
.io_cpu_fetch_isValid(_zz_138_),
|
|
.io_cpu_fetch_isStuck(_zz_139_),
|
|
.io_cpu_fetch_isRemoved(_zz_140_),
|
|
.io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload),
|
|
.io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data),
|
|
.io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit),
|
|
.io_cpu_fetch_dataBypass(_zz_141_),
|
|
.io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid),
|
|
.io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress),
|
|
.io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation),
|
|
.io_cpu_fetch_mmuBus_rsp_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress),
|
|
.io_cpu_fetch_mmuBus_rsp_isIoAccess(_zz_142_),
|
|
.io_cpu_fetch_mmuBus_rsp_allowRead(_zz_143_),
|
|
.io_cpu_fetch_mmuBus_rsp_allowWrite(_zz_144_),
|
|
.io_cpu_fetch_mmuBus_rsp_allowExecute(_zz_145_),
|
|
.io_cpu_fetch_mmuBus_rsp_exception(_zz_146_),
|
|
.io_cpu_fetch_mmuBus_rsp_refilling(_zz_147_),
|
|
.io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end),
|
|
.io_cpu_fetch_mmuBus_busy(_zz_148_),
|
|
.io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress),
|
|
.io_cpu_fetch_cacheMiss(IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss),
|
|
.io_cpu_fetch_error(IBusCachedPlugin_cache_io_cpu_fetch_error),
|
|
.io_cpu_fetch_mmuRefilling(IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling),
|
|
.io_cpu_fetch_mmuException(IBusCachedPlugin_cache_io_cpu_fetch_mmuException),
|
|
.io_cpu_fetch_isUser(_zz_149_),
|
|
.io_cpu_fetch_haltIt(IBusCachedPlugin_cache_io_cpu_fetch_haltIt),
|
|
.io_cpu_decode_isValid(_zz_150_),
|
|
.io_cpu_decode_isStuck(_zz_151_),
|
|
.io_cpu_decode_pc(_zz_152_),
|
|
.io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress),
|
|
.io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data),
|
|
.io_cpu_fill_valid(_zz_153_),
|
|
.io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress),
|
|
.io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid),
|
|
.io_mem_cmd_ready(iBus_cmd_ready),
|
|
.io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address),
|
|
.io_mem_cmd_payload_size(IBusCachedPlugin_cache_io_mem_cmd_payload_size),
|
|
.io_mem_rsp_valid(iBus_rsp_valid),
|
|
.io_mem_rsp_payload_data(iBus_rsp_payload_data),
|
|
.io_mem_rsp_payload_error(iBus_rsp_payload_error),
|
|
.clk(clk),
|
|
.reset(reset)
|
|
);
|
|
always @(*) begin
|
|
case(_zz_224_)
|
|
2'b00 : begin
|
|
_zz_156_ = BranchPlugin_jumpInterface_payload;
|
|
end
|
|
2'b01 : begin
|
|
_zz_156_ = CsrPlugin_jumpInterface_payload;
|
|
end
|
|
default : begin
|
|
_zz_156_ = IBusCachedPlugin_redoBranch_payload;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always @(*) begin
|
|
case(_zz_128_)
|
|
2'b00 : begin
|
|
_zz_157_ = DBusSimplePlugin_memoryExceptionPort_payload_code;
|
|
_zz_158_ = DBusSimplePlugin_memoryExceptionPort_payload_badAddr;
|
|
end
|
|
2'b01 : begin
|
|
_zz_157_ = BranchPlugin_branchExceptionPort_payload_code;
|
|
_zz_158_ = BranchPlugin_branchExceptionPort_payload_badAddr;
|
|
end
|
|
default : begin
|
|
_zz_157_ = CsrPlugin_selfException_payload_code;
|
|
_zz_158_ = CsrPlugin_selfException_payload_badAddr;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
`ifndef SYNTHESIS
|
|
always @(*) begin
|
|
case(decode_SRC1_CTRL)
|
|
`Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS ";
|
|
`Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU ";
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT";
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 ";
|
|
default : decode_SRC1_CTRL_string = "????????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_1_)
|
|
`Src1CtrlEnum_defaultEncoding_RS : _zz_1__string = "RS ";
|
|
`Src1CtrlEnum_defaultEncoding_IMU : _zz_1__string = "IMU ";
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_1__string = "PC_INCREMENT";
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_1__string = "URS1 ";
|
|
default : _zz_1__string = "????????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_2_)
|
|
`Src1CtrlEnum_defaultEncoding_RS : _zz_2__string = "RS ";
|
|
`Src1CtrlEnum_defaultEncoding_IMU : _zz_2__string = "IMU ";
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_2__string = "PC_INCREMENT";
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_2__string = "URS1 ";
|
|
default : _zz_2__string = "????????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_3_)
|
|
`Src1CtrlEnum_defaultEncoding_RS : _zz_3__string = "RS ";
|
|
`Src1CtrlEnum_defaultEncoding_IMU : _zz_3__string = "IMU ";
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_3__string = "PC_INCREMENT";
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_3__string = "URS1 ";
|
|
default : _zz_3__string = "????????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(decode_ENV_CTRL)
|
|
`EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE ";
|
|
`EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET ";
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL ";
|
|
`EnvCtrlEnum_defaultEncoding_EBREAK : decode_ENV_CTRL_string = "EBREAK";
|
|
default : decode_ENV_CTRL_string = "??????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_4_)
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_4__string = "NONE ";
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_4__string = "XRET ";
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_4__string = "ECALL ";
|
|
`EnvCtrlEnum_defaultEncoding_EBREAK : _zz_4__string = "EBREAK";
|
|
default : _zz_4__string = "??????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_5_)
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_5__string = "NONE ";
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_5__string = "XRET ";
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_5__string = "ECALL ";
|
|
`EnvCtrlEnum_defaultEncoding_EBREAK : _zz_5__string = "EBREAK";
|
|
default : _zz_5__string = "??????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_6_)
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_6__string = "NONE ";
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_6__string = "XRET ";
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_6__string = "ECALL ";
|
|
`EnvCtrlEnum_defaultEncoding_EBREAK : _zz_6__string = "EBREAK";
|
|
default : _zz_6__string = "??????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(decode_ALU_CTRL)
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB ";
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU";
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE ";
|
|
default : decode_ALU_CTRL_string = "????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_7_)
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_7__string = "ADD_SUB ";
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_7__string = "SLT_SLTU";
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_7__string = "BITWISE ";
|
|
default : _zz_7__string = "????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_8_)
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_8__string = "ADD_SUB ";
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_8__string = "SLT_SLTU";
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_8__string = "BITWISE ";
|
|
default : _zz_8__string = "????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_9_)
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_9__string = "ADD_SUB ";
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_9__string = "SLT_SLTU";
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_9__string = "BITWISE ";
|
|
default : _zz_9__string = "????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(decode_ALU_BITWISE_CTRL)
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 ";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1";
|
|
default : decode_ALU_BITWISE_CTRL_string = "?????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_10_)
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_10__string = "XOR_1";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_10__string = "OR_1 ";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_10__string = "AND_1";
|
|
default : _zz_10__string = "?????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_11_)
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_11__string = "XOR_1";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_11__string = "OR_1 ";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_11__string = "AND_1";
|
|
default : _zz_11__string = "?????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_12_)
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_12__string = "XOR_1";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_12__string = "OR_1 ";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_12__string = "AND_1";
|
|
default : _zz_12__string = "?????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(decode_BRANCH_CTRL)
|
|
`BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC ";
|
|
`BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B ";
|
|
`BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL ";
|
|
`BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR";
|
|
default : decode_BRANCH_CTRL_string = "????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_13_)
|
|
`BranchCtrlEnum_defaultEncoding_INC : _zz_13__string = "INC ";
|
|
`BranchCtrlEnum_defaultEncoding_B : _zz_13__string = "B ";
|
|
`BranchCtrlEnum_defaultEncoding_JAL : _zz_13__string = "JAL ";
|
|
`BranchCtrlEnum_defaultEncoding_JALR : _zz_13__string = "JALR";
|
|
default : _zz_13__string = "????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_14_)
|
|
`BranchCtrlEnum_defaultEncoding_INC : _zz_14__string = "INC ";
|
|
`BranchCtrlEnum_defaultEncoding_B : _zz_14__string = "B ";
|
|
`BranchCtrlEnum_defaultEncoding_JAL : _zz_14__string = "JAL ";
|
|
`BranchCtrlEnum_defaultEncoding_JALR : _zz_14__string = "JALR";
|
|
default : _zz_14__string = "????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_15_)
|
|
`BranchCtrlEnum_defaultEncoding_INC : _zz_15__string = "INC ";
|
|
`BranchCtrlEnum_defaultEncoding_B : _zz_15__string = "B ";
|
|
`BranchCtrlEnum_defaultEncoding_JAL : _zz_15__string = "JAL ";
|
|
`BranchCtrlEnum_defaultEncoding_JALR : _zz_15__string = "JALR";
|
|
default : _zz_15__string = "????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(decode_SHIFT_CTRL)
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1";
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 ";
|
|
default : decode_SHIFT_CTRL_string = "?????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_16_)
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_16__string = "DISABLE_1";
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_16__string = "SLL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_16__string = "SRL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_16__string = "SRA_1 ";
|
|
default : _zz_16__string = "?????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_17_)
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_17__string = "DISABLE_1";
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_17__string = "SLL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_17__string = "SRL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_17__string = "SRA_1 ";
|
|
default : _zz_17__string = "?????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_18_)
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_18__string = "DISABLE_1";
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_18__string = "SLL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_18__string = "SRL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_18__string = "SRA_1 ";
|
|
default : _zz_18__string = "?????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(decode_SRC2_CTRL)
|
|
`Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS ";
|
|
`Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI";
|
|
`Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS";
|
|
`Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC ";
|
|
default : decode_SRC2_CTRL_string = "???";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_19_)
|
|
`Src2CtrlEnum_defaultEncoding_RS : _zz_19__string = "RS ";
|
|
`Src2CtrlEnum_defaultEncoding_IMI : _zz_19__string = "IMI";
|
|
`Src2CtrlEnum_defaultEncoding_IMS : _zz_19__string = "IMS";
|
|
`Src2CtrlEnum_defaultEncoding_PC : _zz_19__string = "PC ";
|
|
default : _zz_19__string = "???";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_20_)
|
|
`Src2CtrlEnum_defaultEncoding_RS : _zz_20__string = "RS ";
|
|
`Src2CtrlEnum_defaultEncoding_IMI : _zz_20__string = "IMI";
|
|
`Src2CtrlEnum_defaultEncoding_IMS : _zz_20__string = "IMS";
|
|
`Src2CtrlEnum_defaultEncoding_PC : _zz_20__string = "PC ";
|
|
default : _zz_20__string = "???";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_21_)
|
|
`Src2CtrlEnum_defaultEncoding_RS : _zz_21__string = "RS ";
|
|
`Src2CtrlEnum_defaultEncoding_IMI : _zz_21__string = "IMI";
|
|
`Src2CtrlEnum_defaultEncoding_IMS : _zz_21__string = "IMS";
|
|
`Src2CtrlEnum_defaultEncoding_PC : _zz_21__string = "PC ";
|
|
default : _zz_21__string = "???";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(execute_ENV_CTRL)
|
|
`EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE ";
|
|
`EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET ";
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL ";
|
|
`EnvCtrlEnum_defaultEncoding_EBREAK : execute_ENV_CTRL_string = "EBREAK";
|
|
default : execute_ENV_CTRL_string = "??????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_25_)
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_25__string = "NONE ";
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_25__string = "XRET ";
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_25__string = "ECALL ";
|
|
`EnvCtrlEnum_defaultEncoding_EBREAK : _zz_25__string = "EBREAK";
|
|
default : _zz_25__string = "??????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(execute_BRANCH_CTRL)
|
|
`BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC ";
|
|
`BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B ";
|
|
`BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL ";
|
|
`BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR";
|
|
default : execute_BRANCH_CTRL_string = "????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_27_)
|
|
`BranchCtrlEnum_defaultEncoding_INC : _zz_27__string = "INC ";
|
|
`BranchCtrlEnum_defaultEncoding_B : _zz_27__string = "B ";
|
|
`BranchCtrlEnum_defaultEncoding_JAL : _zz_27__string = "JAL ";
|
|
`BranchCtrlEnum_defaultEncoding_JALR : _zz_27__string = "JALR";
|
|
default : _zz_27__string = "????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(execute_SHIFT_CTRL)
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1";
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 ";
|
|
default : execute_SHIFT_CTRL_string = "?????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_29_)
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_29__string = "DISABLE_1";
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_29__string = "SLL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_29__string = "SRL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_29__string = "SRA_1 ";
|
|
default : _zz_29__string = "?????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(execute_SRC2_CTRL)
|
|
`Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS ";
|
|
`Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI";
|
|
`Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS";
|
|
`Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC ";
|
|
default : execute_SRC2_CTRL_string = "???";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_33_)
|
|
`Src2CtrlEnum_defaultEncoding_RS : _zz_33__string = "RS ";
|
|
`Src2CtrlEnum_defaultEncoding_IMI : _zz_33__string = "IMI";
|
|
`Src2CtrlEnum_defaultEncoding_IMS : _zz_33__string = "IMS";
|
|
`Src2CtrlEnum_defaultEncoding_PC : _zz_33__string = "PC ";
|
|
default : _zz_33__string = "???";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(execute_SRC1_CTRL)
|
|
`Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS ";
|
|
`Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU ";
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT";
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 ";
|
|
default : execute_SRC1_CTRL_string = "????????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_35_)
|
|
`Src1CtrlEnum_defaultEncoding_RS : _zz_35__string = "RS ";
|
|
`Src1CtrlEnum_defaultEncoding_IMU : _zz_35__string = "IMU ";
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_35__string = "PC_INCREMENT";
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_35__string = "URS1 ";
|
|
default : _zz_35__string = "????????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(execute_ALU_CTRL)
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB ";
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU";
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE ";
|
|
default : execute_ALU_CTRL_string = "????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_38_)
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_38__string = "ADD_SUB ";
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_38__string = "SLT_SLTU";
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_38__string = "BITWISE ";
|
|
default : _zz_38__string = "????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(execute_ALU_BITWISE_CTRL)
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 ";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1";
|
|
default : execute_ALU_BITWISE_CTRL_string = "?????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_40_)
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_40__string = "XOR_1";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_40__string = "OR_1 ";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_40__string = "AND_1";
|
|
default : _zz_40__string = "?????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_47_)
|
|
`Src2CtrlEnum_defaultEncoding_RS : _zz_47__string = "RS ";
|
|
`Src2CtrlEnum_defaultEncoding_IMI : _zz_47__string = "IMI";
|
|
`Src2CtrlEnum_defaultEncoding_IMS : _zz_47__string = "IMS";
|
|
`Src2CtrlEnum_defaultEncoding_PC : _zz_47__string = "PC ";
|
|
default : _zz_47__string = "???";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_49_)
|
|
`BranchCtrlEnum_defaultEncoding_INC : _zz_49__string = "INC ";
|
|
`BranchCtrlEnum_defaultEncoding_B : _zz_49__string = "B ";
|
|
`BranchCtrlEnum_defaultEncoding_JAL : _zz_49__string = "JAL ";
|
|
`BranchCtrlEnum_defaultEncoding_JALR : _zz_49__string = "JALR";
|
|
default : _zz_49__string = "????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_50_)
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_50__string = "NONE ";
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_50__string = "XRET ";
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_50__string = "ECALL ";
|
|
`EnvCtrlEnum_defaultEncoding_EBREAK : _zz_50__string = "EBREAK";
|
|
default : _zz_50__string = "??????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_52_)
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_52__string = "XOR_1";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_52__string = "OR_1 ";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_52__string = "AND_1";
|
|
default : _zz_52__string = "?????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_55_)
|
|
`Src1CtrlEnum_defaultEncoding_RS : _zz_55__string = "RS ";
|
|
`Src1CtrlEnum_defaultEncoding_IMU : _zz_55__string = "IMU ";
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_55__string = "PC_INCREMENT";
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_55__string = "URS1 ";
|
|
default : _zz_55__string = "????????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_56_)
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_56__string = "DISABLE_1";
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_56__string = "SLL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_56__string = "SRL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_56__string = "SRA_1 ";
|
|
default : _zz_56__string = "?????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_57_)
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_57__string = "ADD_SUB ";
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_57__string = "SLT_SLTU";
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_57__string = "BITWISE ";
|
|
default : _zz_57__string = "????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_96_)
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_96__string = "ADD_SUB ";
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_96__string = "SLT_SLTU";
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_96__string = "BITWISE ";
|
|
default : _zz_96__string = "????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_97_)
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_97__string = "DISABLE_1";
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_97__string = "SLL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_97__string = "SRL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_97__string = "SRA_1 ";
|
|
default : _zz_97__string = "?????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_98_)
|
|
`Src1CtrlEnum_defaultEncoding_RS : _zz_98__string = "RS ";
|
|
`Src1CtrlEnum_defaultEncoding_IMU : _zz_98__string = "IMU ";
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_98__string = "PC_INCREMENT";
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_98__string = "URS1 ";
|
|
default : _zz_98__string = "????????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_99_)
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_99__string = "XOR_1";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_99__string = "OR_1 ";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_99__string = "AND_1";
|
|
default : _zz_99__string = "?????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_100_)
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_100__string = "NONE ";
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_100__string = "XRET ";
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_100__string = "ECALL ";
|
|
`EnvCtrlEnum_defaultEncoding_EBREAK : _zz_100__string = "EBREAK";
|
|
default : _zz_100__string = "??????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_101_)
|
|
`BranchCtrlEnum_defaultEncoding_INC : _zz_101__string = "INC ";
|
|
`BranchCtrlEnum_defaultEncoding_B : _zz_101__string = "B ";
|
|
`BranchCtrlEnum_defaultEncoding_JAL : _zz_101__string = "JAL ";
|
|
`BranchCtrlEnum_defaultEncoding_JALR : _zz_101__string = "JALR";
|
|
default : _zz_101__string = "????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_102_)
|
|
`Src2CtrlEnum_defaultEncoding_RS : _zz_102__string = "RS ";
|
|
`Src2CtrlEnum_defaultEncoding_IMI : _zz_102__string = "IMI";
|
|
`Src2CtrlEnum_defaultEncoding_IMS : _zz_102__string = "IMS";
|
|
`Src2CtrlEnum_defaultEncoding_PC : _zz_102__string = "PC ";
|
|
default : _zz_102__string = "???";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(decode_to_execute_SRC2_CTRL)
|
|
`Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS ";
|
|
`Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI";
|
|
`Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS";
|
|
`Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC ";
|
|
default : decode_to_execute_SRC2_CTRL_string = "???";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(decode_to_execute_SHIFT_CTRL)
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
|
|
default : decode_to_execute_SHIFT_CTRL_string = "?????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(decode_to_execute_BRANCH_CTRL)
|
|
`BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC ";
|
|
`BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B ";
|
|
`BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL ";
|
|
`BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR";
|
|
default : decode_to_execute_BRANCH_CTRL_string = "????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(decode_to_execute_ALU_BITWISE_CTRL)
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
|
|
default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(decode_to_execute_ALU_CTRL)
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE ";
|
|
default : decode_to_execute_ALU_CTRL_string = "????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(decode_to_execute_ENV_CTRL)
|
|
`EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE ";
|
|
`EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET ";
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL ";
|
|
`EnvCtrlEnum_defaultEncoding_EBREAK : decode_to_execute_ENV_CTRL_string = "EBREAK";
|
|
default : decode_to_execute_ENV_CTRL_string = "??????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(decode_to_execute_SRC1_CTRL)
|
|
`Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS ";
|
|
`Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU ";
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 ";
|
|
default : decode_to_execute_SRC1_CTRL_string = "????????????";
|
|
endcase
|
|
end
|
|
`endif
|
|
|
|
assign decode_SRC_LESS_UNSIGNED = _zz_58_;
|
|
assign decode_DO_EBREAK = _zz_22_;
|
|
assign decode_SRC1_CTRL = _zz_1_;
|
|
assign _zz_2_ = _zz_3_;
|
|
assign decode_ENV_CTRL = _zz_4_;
|
|
assign _zz_5_ = _zz_6_;
|
|
assign decode_MEMORY_ENABLE = _zz_45_;
|
|
assign decode_ALU_CTRL = _zz_7_;
|
|
assign _zz_8_ = _zz_9_;
|
|
assign decode_ALU_BITWISE_CTRL = _zz_10_;
|
|
assign _zz_11_ = _zz_12_;
|
|
assign decode_IS_CSR = _zz_46_;
|
|
assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID;
|
|
assign decode_SRC2_FORCE_ZERO = _zz_37_;
|
|
assign decode_CSR_WRITE_OPCODE = _zz_24_;
|
|
assign decode_CSR_READ_OPCODE = _zz_23_;
|
|
assign decode_MEMORY_STORE = _zz_59_;
|
|
assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT;
|
|
assign decode_FORMAL_PC_NEXT = _zz_69_;
|
|
assign decode_BRANCH_CTRL = _zz_13_;
|
|
assign _zz_14_ = _zz_15_;
|
|
assign decode_SHIFT_CTRL = _zz_16_;
|
|
assign _zz_17_ = _zz_18_;
|
|
assign decode_SRC2_CTRL = _zz_19_;
|
|
assign _zz_20_ = _zz_21_;
|
|
assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK;
|
|
assign decode_IS_EBREAK = _zz_44_;
|
|
assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE;
|
|
assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE;
|
|
assign execute_IS_CSR = decode_to_execute_IS_CSR;
|
|
assign execute_ENV_CTRL = _zz_25_;
|
|
assign execute_BRANCH_CALC = _zz_26_;
|
|
assign execute_BRANCH_DO = _zz_28_;
|
|
assign execute_RS1 = _zz_43_;
|
|
assign execute_BRANCH_CTRL = _zz_27_;
|
|
assign execute_SHIFT_CTRL = _zz_29_;
|
|
assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED;
|
|
assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO;
|
|
assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS;
|
|
assign execute_SRC2_CTRL = _zz_33_;
|
|
assign execute_SRC1_CTRL = _zz_35_;
|
|
assign decode_SRC_USE_SUB_LESS = _zz_53_;
|
|
assign decode_SRC_ADD_ZERO = _zz_48_;
|
|
assign execute_SRC_ADD_SUB = _zz_32_;
|
|
assign execute_SRC_LESS = _zz_30_;
|
|
assign execute_ALU_CTRL = _zz_38_;
|
|
assign execute_SRC2 = _zz_34_;
|
|
assign execute_SRC1 = _zz_36_;
|
|
assign execute_ALU_BITWISE_CTRL = _zz_40_;
|
|
always @ (*) begin
|
|
_zz_41_ = 1'b0;
|
|
if(lastStageRegFileWrite_valid)begin
|
|
_zz_41_ = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
decode_REGFILE_WRITE_VALID = _zz_54_;
|
|
if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin
|
|
decode_REGFILE_WRITE_VALID = 1'b0;
|
|
end
|
|
end
|
|
|
|
assign decode_LEGAL_INSTRUCTION = _zz_60_;
|
|
assign decode_INSTRUCTION_READY = 1'b1;
|
|
always @ (*) begin
|
|
decode_INSTRUCTION = _zz_70_;
|
|
if((_zz_132_ != (3'b000)))begin
|
|
decode_INSTRUCTION = IBusCachedPlugin_injectionPort_payload_regNext;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
_zz_61_ = execute_REGFILE_WRITE_DATA;
|
|
execute_arbitration_haltItself = 1'b0;
|
|
if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_83_)))begin
|
|
execute_arbitration_haltItself = 1'b1;
|
|
end
|
|
if((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_MEMORY_STORE)) && ((! dBus_rsp_ready) || (! _zz_83_))))begin
|
|
execute_arbitration_haltItself = 1'b1;
|
|
end
|
|
if((execute_arbitration_isValid && execute_MEMORY_ENABLE))begin
|
|
_zz_61_ = execute_DBusSimplePlugin_rspFormated;
|
|
end
|
|
if(_zz_159_)begin
|
|
_zz_61_ = _zz_111_;
|
|
if(_zz_160_)begin
|
|
if(! execute_LightShifterPlugin_done) begin
|
|
execute_arbitration_haltItself = 1'b1;
|
|
end
|
|
end
|
|
end
|
|
if((execute_arbitration_isValid && execute_IS_CSR))begin
|
|
_zz_61_ = execute_CsrPlugin_readData;
|
|
if(execute_CsrPlugin_blockedBySideEffects)begin
|
|
execute_arbitration_haltItself = 1'b1;
|
|
end
|
|
end
|
|
end
|
|
|
|
assign execute_MEMORY_ADDRESS_LOW = _zz_63_;
|
|
assign execute_MEMORY_READ_DATA = _zz_62_;
|
|
assign execute_REGFILE_WRITE_DATA = _zz_39_;
|
|
assign execute_SRC_ADD = _zz_31_;
|
|
assign execute_RS2 = _zz_42_;
|
|
assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE;
|
|
assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE;
|
|
assign execute_ALIGNEMENT_FAULT = _zz_64_;
|
|
assign decode_FLUSH_ALL = _zz_51_;
|
|
always @ (*) begin
|
|
IBusCachedPlugin_rsp_issueDetected = _zz_65_;
|
|
_zz_66_ = _zz_67_;
|
|
IBusCachedPlugin_decodeExceptionPort_valid = 1'b0;
|
|
IBusCachedPlugin_decodeExceptionPort_payload_code = (4'bxxxx);
|
|
if(((_zz_138_ && IBusCachedPlugin_cache_io_cpu_fetch_mmuException) && (! _zz_67_)))begin
|
|
_zz_66_ = 1'b1;
|
|
IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
|
|
IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1100);
|
|
end
|
|
if(((_zz_138_ && IBusCachedPlugin_cache_io_cpu_fetch_error) && (! _zz_65_)))begin
|
|
IBusCachedPlugin_rsp_issueDetected = 1'b1;
|
|
IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
|
|
IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b0001);
|
|
end
|
|
if(IBusCachedPlugin_fetcherHalt)begin
|
|
IBusCachedPlugin_decodeExceptionPort_valid = 1'b0;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
_zz_65_ = _zz_66_;
|
|
_zz_67_ = 1'b0;
|
|
IBusCachedPlugin_rsp_redoFetch = 1'b0;
|
|
_zz_153_ = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling));
|
|
if(((_zz_138_ && IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling) && (! 1'b0)))begin
|
|
_zz_67_ = 1'b1;
|
|
IBusCachedPlugin_rsp_redoFetch = 1'b1;
|
|
end
|
|
if(((_zz_138_ && IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss) && (! _zz_66_)))begin
|
|
_zz_65_ = 1'b1;
|
|
_zz_153_ = 1'b1;
|
|
IBusCachedPlugin_rsp_redoFetch = 1'b1;
|
|
end
|
|
if((! IBusCachedPlugin_iBusRsp_readyForError))begin
|
|
IBusCachedPlugin_rsp_redoFetch = 1'b0;
|
|
end
|
|
if((! IBusCachedPlugin_iBusRsp_readyForError))begin
|
|
_zz_153_ = 1'b0;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
_zz_68_ = decode_FORMAL_PC_NEXT;
|
|
if(IBusCachedPlugin_redoBranch_valid)begin
|
|
_zz_68_ = IBusCachedPlugin_redoBranch_payload;
|
|
end
|
|
end
|
|
|
|
assign decode_PC = _zz_71_;
|
|
assign execute_PC = decode_to_execute_PC;
|
|
assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION;
|
|
always @ (*) begin
|
|
decode_arbitration_haltItself = 1'b0;
|
|
decode_arbitration_isValid = (IBusCachedPlugin_iBusRsp_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved));
|
|
IBusCachedPlugin_injectionPort_ready = 1'b0;
|
|
case(_zz_132_)
|
|
3'b000 : begin
|
|
end
|
|
3'b001 : begin
|
|
end
|
|
3'b010 : begin
|
|
decode_arbitration_isValid = 1'b1;
|
|
decode_arbitration_haltItself = 1'b1;
|
|
end
|
|
3'b011 : begin
|
|
decode_arbitration_isValid = 1'b1;
|
|
end
|
|
3'b100 : begin
|
|
IBusCachedPlugin_injectionPort_ready = 1'b1;
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always @ (*) begin
|
|
decode_arbitration_haltByOther = 1'b0;
|
|
if(CsrPlugin_interrupt)begin
|
|
decode_arbitration_haltByOther = decode_arbitration_isValid;
|
|
end
|
|
if(((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)) != (1'b0)))begin
|
|
decode_arbitration_haltByOther = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
decode_arbitration_removeIt = 1'b0;
|
|
if(_zz_161_)begin
|
|
decode_arbitration_removeIt = 1'b1;
|
|
end
|
|
if(decode_arbitration_isFlushed)begin
|
|
decode_arbitration_removeIt = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
decode_arbitration_flushAll = 1'b0;
|
|
execute_arbitration_haltByOther = 1'b0;
|
|
execute_arbitration_removeIt = 1'b0;
|
|
IBusCachedPlugin_fetcherHalt = 1'b0;
|
|
IBusCachedPlugin_fetcherflushIt = 1'b0;
|
|
CsrPlugin_jumpInterface_valid = 1'b0;
|
|
CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
|
|
if(BranchPlugin_jumpInterface_valid)begin
|
|
decode_arbitration_flushAll = 1'b1;
|
|
end
|
|
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
|
|
if(_zz_162_)begin
|
|
decode_arbitration_flushAll = 1'b1;
|
|
execute_arbitration_removeIt = 1'b1;
|
|
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1;
|
|
end
|
|
if(execute_arbitration_isFlushed)begin
|
|
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0;
|
|
end
|
|
if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode} != (2'b00)))begin
|
|
IBusCachedPlugin_fetcherHalt = 1'b1;
|
|
end
|
|
if(_zz_163_)begin
|
|
IBusCachedPlugin_fetcherHalt = 1'b1;
|
|
CsrPlugin_jumpInterface_valid = 1'b1;
|
|
CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)};
|
|
decode_arbitration_flushAll = 1'b1;
|
|
end
|
|
if(_zz_164_)begin
|
|
IBusCachedPlugin_fetcherHalt = 1'b1;
|
|
CsrPlugin_jumpInterface_valid = 1'b1;
|
|
decode_arbitration_flushAll = 1'b1;
|
|
case(_zz_165_)
|
|
2'b11 : begin
|
|
CsrPlugin_jumpInterface_payload = CsrPlugin_mepc;
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
end
|
|
if(_zz_166_)begin
|
|
execute_arbitration_haltByOther = 1'b1;
|
|
if(_zz_167_)begin
|
|
IBusCachedPlugin_fetcherflushIt = 1'b1;
|
|
IBusCachedPlugin_fetcherHalt = 1'b1;
|
|
end
|
|
end
|
|
if(DebugPlugin_haltIt)begin
|
|
IBusCachedPlugin_fetcherHalt = 1'b1;
|
|
end
|
|
if(_zz_168_)begin
|
|
IBusCachedPlugin_fetcherHalt = 1'b1;
|
|
end
|
|
if(execute_arbitration_isFlushed)begin
|
|
execute_arbitration_removeIt = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
execute_arbitration_flushAll = 1'b0;
|
|
if(_zz_166_)begin
|
|
if(_zz_167_)begin
|
|
execute_arbitration_flushAll = 1'b1;
|
|
end
|
|
end
|
|
end
|
|
|
|
assign lastStageInstruction = execute_INSTRUCTION;
|
|
assign lastStagePc = execute_PC;
|
|
assign lastStageIsValid = execute_arbitration_isValid;
|
|
assign lastStageIsFiring = execute_arbitration_isFiring;
|
|
always @ (*) begin
|
|
IBusCachedPlugin_incomingInstruction = 1'b0;
|
|
if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid)begin
|
|
IBusCachedPlugin_incomingInstruction = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
CsrPlugin_forceMachineWire = 1'b0;
|
|
CsrPlugin_allowException = 1'b1;
|
|
if(DebugPlugin_godmode)begin
|
|
CsrPlugin_allowException = 1'b0;
|
|
CsrPlugin_forceMachineWire = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
CsrPlugin_allowInterrupts = 1'b1;
|
|
if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin
|
|
CsrPlugin_allowInterrupts = 1'b0;
|
|
end
|
|
end
|
|
|
|
assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,IBusCachedPlugin_redoBranch_valid}} != (3'b000));
|
|
assign _zz_72_ = {IBusCachedPlugin_redoBranch_valid,{CsrPlugin_jumpInterface_valid,BranchPlugin_jumpInterface_valid}};
|
|
assign _zz_73_ = (_zz_72_ & (~ _zz_175_));
|
|
assign _zz_74_ = _zz_73_[1];
|
|
assign _zz_75_ = _zz_73_[2];
|
|
assign IBusCachedPlugin_jump_pcLoad_payload = _zz_156_;
|
|
assign _zz_76_ = (! IBusCachedPlugin_fetcherHalt);
|
|
assign IBusCachedPlugin_fetchPc_output_valid = (IBusCachedPlugin_fetchPc_preOutput_valid && _zz_76_);
|
|
assign IBusCachedPlugin_fetchPc_preOutput_ready = (IBusCachedPlugin_fetchPc_output_ready && _zz_76_);
|
|
assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_preOutput_payload;
|
|
always @ (*) begin
|
|
IBusCachedPlugin_fetchPc_propagatePc = 1'b0;
|
|
if((IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready))begin
|
|
IBusCachedPlugin_fetchPc_propagatePc = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_177_);
|
|
IBusCachedPlugin_fetchPc_samplePcNext = 1'b0;
|
|
if(IBusCachedPlugin_fetchPc_propagatePc)begin
|
|
IBusCachedPlugin_fetchPc_samplePcNext = 1'b1;
|
|
end
|
|
if(IBusCachedPlugin_jump_pcLoad_valid)begin
|
|
IBusCachedPlugin_fetchPc_samplePcNext = 1'b1;
|
|
IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload;
|
|
end
|
|
if(_zz_169_)begin
|
|
IBusCachedPlugin_fetchPc_samplePcNext = 1'b1;
|
|
end
|
|
IBusCachedPlugin_fetchPc_pc[0] = 1'b0;
|
|
IBusCachedPlugin_fetchPc_pc[1] = 1'b0;
|
|
end
|
|
|
|
assign IBusCachedPlugin_fetchPc_preOutput_valid = _zz_77_;
|
|
assign IBusCachedPlugin_fetchPc_preOutput_payload = IBusCachedPlugin_fetchPc_pc;
|
|
assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid;
|
|
assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready;
|
|
assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload;
|
|
assign IBusCachedPlugin_iBusRsp_stages_0_inputSample = 1'b1;
|
|
always @ (*) begin
|
|
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0;
|
|
if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin
|
|
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1;
|
|
end
|
|
end
|
|
|
|
assign _zz_78_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt);
|
|
assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_78_);
|
|
assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_78_);
|
|
assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload;
|
|
always @ (*) begin
|
|
IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0;
|
|
if(IBusCachedPlugin_cache_io_cpu_fetch_haltIt)begin
|
|
IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1;
|
|
end
|
|
if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin
|
|
IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1;
|
|
end
|
|
end
|
|
|
|
assign _zz_79_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt);
|
|
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_79_);
|
|
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_79_);
|
|
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload;
|
|
assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_80_;
|
|
assign _zz_80_ = ((1'b0 && (! _zz_81_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready);
|
|
assign _zz_81_ = _zz_82_;
|
|
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_81_;
|
|
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = IBusCachedPlugin_fetchPc_pcReg;
|
|
always @ (*) begin
|
|
IBusCachedPlugin_iBusRsp_readyForError = 1'b1;
|
|
if((! IBusCachedPlugin_pcValids_0))begin
|
|
IBusCachedPlugin_iBusRsp_readyForError = 1'b0;
|
|
end
|
|
end
|
|
|
|
assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_0;
|
|
assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_1;
|
|
assign IBusCachedPlugin_iBusRsp_decodeInput_ready = (! decode_arbitration_isStuck);
|
|
assign _zz_71_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_pc;
|
|
assign _zz_70_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst;
|
|
assign _zz_69_ = (decode_PC + (32'b00000000000000000000000000000100));
|
|
assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid;
|
|
always @ (*) begin
|
|
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
|
|
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
|
|
end
|
|
|
|
assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size;
|
|
assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0;
|
|
assign _zz_137_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit));
|
|
assign _zz_140_ = (IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt);
|
|
assign _zz_141_ = (32'b00000000000000000000000000000000);
|
|
assign _zz_138_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit));
|
|
assign _zz_139_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready);
|
|
assign _zz_149_ = (CsrPlugin_privilege == (2'b00));
|
|
assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0;
|
|
assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload[31 : 2],(2'b00)};
|
|
assign IBusCachedPlugin_redoBranch_valid = IBusCachedPlugin_rsp_redoFetch;
|
|
assign IBusCachedPlugin_redoBranch_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload;
|
|
assign IBusCachedPlugin_iBusRsp_decodeInput_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid;
|
|
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_decodeInput_ready;
|
|
assign IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_fetch_data;
|
|
assign IBusCachedPlugin_iBusRsp_decodeInput_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload;
|
|
assign _zz_145_ = 1'b1;
|
|
assign _zz_143_ = 1'b1;
|
|
assign _zz_144_ = 1'b1;
|
|
assign _zz_142_ = 1'b0;
|
|
assign _zz_146_ = 1'b0;
|
|
assign _zz_147_ = 1'b0;
|
|
assign _zz_148_ = 1'b0;
|
|
assign _zz_136_ = (decode_arbitration_isValid && decode_FLUSH_ALL);
|
|
assign _zz_64_ = (((dBus_cmd_payload_size == (2'b10)) && (dBus_cmd_payload_address[1 : 0] != (2'b00))) || ((dBus_cmd_payload_size == (2'b01)) && (dBus_cmd_payload_address[0 : 0] != (1'b0))));
|
|
always @ (*) begin
|
|
execute_DBusSimplePlugin_skipCmd = 1'b0;
|
|
if(execute_ALIGNEMENT_FAULT)begin
|
|
execute_DBusSimplePlugin_skipCmd = 1'b1;
|
|
end
|
|
end
|
|
|
|
assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_83_));
|
|
assign dBus_cmd_payload_wr = execute_MEMORY_STORE;
|
|
assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12];
|
|
always @ (*) begin
|
|
case(dBus_cmd_payload_size)
|
|
2'b00 : begin
|
|
_zz_84_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]};
|
|
end
|
|
2'b01 : begin
|
|
_zz_84_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]};
|
|
end
|
|
default : begin
|
|
_zz_84_ = execute_RS2[31 : 0];
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign dBus_cmd_payload_data = _zz_84_;
|
|
assign _zz_63_ = dBus_cmd_payload_address[1 : 0];
|
|
always @ (*) begin
|
|
case(dBus_cmd_payload_size)
|
|
2'b00 : begin
|
|
_zz_85_ = (4'b0001);
|
|
end
|
|
2'b01 : begin
|
|
_zz_85_ = (4'b0011);
|
|
end
|
|
default : begin
|
|
_zz_85_ = (4'b1111);
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign execute_DBusSimplePlugin_formalMask = (_zz_85_ <<< dBus_cmd_payload_address[1 : 0]);
|
|
assign dBus_cmd_payload_address = execute_SRC_ADD;
|
|
assign _zz_62_ = dBus_rsp_data;
|
|
always @ (*) begin
|
|
DBusSimplePlugin_memoryExceptionPort_valid = 1'b0;
|
|
DBusSimplePlugin_memoryExceptionPort_payload_code = (4'bxxxx);
|
|
if(execute_ALIGNEMENT_FAULT)begin
|
|
DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_178_};
|
|
DBusSimplePlugin_memoryExceptionPort_valid = 1'b1;
|
|
end
|
|
if((! ((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (1'b0 || (! execute_arbitration_isStuckByOthers)))))begin
|
|
DBusSimplePlugin_memoryExceptionPort_valid = 1'b0;
|
|
end
|
|
end
|
|
|
|
assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = execute_REGFILE_WRITE_DATA;
|
|
always @ (*) begin
|
|
execute_DBusSimplePlugin_rspShifted = execute_MEMORY_READ_DATA;
|
|
case(execute_MEMORY_ADDRESS_LOW)
|
|
2'b01 : begin
|
|
execute_DBusSimplePlugin_rspShifted[7 : 0] = execute_MEMORY_READ_DATA[15 : 8];
|
|
end
|
|
2'b10 : begin
|
|
execute_DBusSimplePlugin_rspShifted[15 : 0] = execute_MEMORY_READ_DATA[31 : 16];
|
|
end
|
|
2'b11 : begin
|
|
execute_DBusSimplePlugin_rspShifted[7 : 0] = execute_MEMORY_READ_DATA[31 : 24];
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign _zz_86_ = (execute_DBusSimplePlugin_rspShifted[7] && (! execute_INSTRUCTION[14]));
|
|
always @ (*) begin
|
|
_zz_87_[31] = _zz_86_;
|
|
_zz_87_[30] = _zz_86_;
|
|
_zz_87_[29] = _zz_86_;
|
|
_zz_87_[28] = _zz_86_;
|
|
_zz_87_[27] = _zz_86_;
|
|
_zz_87_[26] = _zz_86_;
|
|
_zz_87_[25] = _zz_86_;
|
|
_zz_87_[24] = _zz_86_;
|
|
_zz_87_[23] = _zz_86_;
|
|
_zz_87_[22] = _zz_86_;
|
|
_zz_87_[21] = _zz_86_;
|
|
_zz_87_[20] = _zz_86_;
|
|
_zz_87_[19] = _zz_86_;
|
|
_zz_87_[18] = _zz_86_;
|
|
_zz_87_[17] = _zz_86_;
|
|
_zz_87_[16] = _zz_86_;
|
|
_zz_87_[15] = _zz_86_;
|
|
_zz_87_[14] = _zz_86_;
|
|
_zz_87_[13] = _zz_86_;
|
|
_zz_87_[12] = _zz_86_;
|
|
_zz_87_[11] = _zz_86_;
|
|
_zz_87_[10] = _zz_86_;
|
|
_zz_87_[9] = _zz_86_;
|
|
_zz_87_[8] = _zz_86_;
|
|
_zz_87_[7 : 0] = execute_DBusSimplePlugin_rspShifted[7 : 0];
|
|
end
|
|
|
|
assign _zz_88_ = (execute_DBusSimplePlugin_rspShifted[15] && (! execute_INSTRUCTION[14]));
|
|
always @ (*) begin
|
|
_zz_89_[31] = _zz_88_;
|
|
_zz_89_[30] = _zz_88_;
|
|
_zz_89_[29] = _zz_88_;
|
|
_zz_89_[28] = _zz_88_;
|
|
_zz_89_[27] = _zz_88_;
|
|
_zz_89_[26] = _zz_88_;
|
|
_zz_89_[25] = _zz_88_;
|
|
_zz_89_[24] = _zz_88_;
|
|
_zz_89_[23] = _zz_88_;
|
|
_zz_89_[22] = _zz_88_;
|
|
_zz_89_[21] = _zz_88_;
|
|
_zz_89_[20] = _zz_88_;
|
|
_zz_89_[19] = _zz_88_;
|
|
_zz_89_[18] = _zz_88_;
|
|
_zz_89_[17] = _zz_88_;
|
|
_zz_89_[16] = _zz_88_;
|
|
_zz_89_[15 : 0] = execute_DBusSimplePlugin_rspShifted[15 : 0];
|
|
end
|
|
|
|
always @ (*) begin
|
|
case(_zz_173_)
|
|
2'b00 : begin
|
|
execute_DBusSimplePlugin_rspFormated = _zz_87_;
|
|
end
|
|
2'b01 : begin
|
|
execute_DBusSimplePlugin_rspFormated = _zz_89_;
|
|
end
|
|
default : begin
|
|
execute_DBusSimplePlugin_rspFormated = execute_DBusSimplePlugin_rspShifted;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign _zz_91_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000));
|
|
assign _zz_92_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000010000));
|
|
assign _zz_93_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000));
|
|
assign _zz_94_ = ((decode_INSTRUCTION & (32'b00010000000100000011000001010000)) == (32'b00000000000100000000000001010000));
|
|
assign _zz_95_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100));
|
|
assign _zz_90_ = {(_zz_94_ != (1'b0)),{(((decode_INSTRUCTION & _zz_225_) == (32'b00000000000000000000000000010000)) != (1'b0)),{((_zz_226_ == _zz_227_) != (1'b0)),{(_zz_92_ != (1'b0)),{(_zz_228_ != _zz_229_),{_zz_230_,{_zz_231_,_zz_232_}}}}}}};
|
|
assign _zz_60_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_315_) == (32'b00000000000000000001000001110011)),{(_zz_316_ == _zz_317_),{_zz_318_,{_zz_319_,_zz_320_}}}}}}} != (20'b00000000000000000000));
|
|
assign _zz_59_ = _zz_179_[0];
|
|
assign _zz_58_ = _zz_180_[0];
|
|
assign _zz_96_ = _zz_90_[5 : 4];
|
|
assign _zz_57_ = _zz_96_;
|
|
assign _zz_97_ = _zz_90_[7 : 6];
|
|
assign _zz_56_ = _zz_97_;
|
|
assign _zz_98_ = _zz_90_[9 : 8];
|
|
assign _zz_55_ = _zz_98_;
|
|
assign _zz_54_ = _zz_181_[0];
|
|
assign _zz_53_ = _zz_182_[0];
|
|
assign _zz_99_ = _zz_90_[13 : 12];
|
|
assign _zz_52_ = _zz_99_;
|
|
assign _zz_51_ = _zz_183_[0];
|
|
assign _zz_100_ = _zz_90_[16 : 15];
|
|
assign _zz_50_ = _zz_100_;
|
|
assign _zz_101_ = _zz_90_[18 : 17];
|
|
assign _zz_49_ = _zz_101_;
|
|
assign _zz_48_ = _zz_184_[0];
|
|
assign _zz_102_ = _zz_90_[22 : 21];
|
|
assign _zz_47_ = _zz_102_;
|
|
assign _zz_46_ = _zz_185_[0];
|
|
assign _zz_45_ = _zz_186_[0];
|
|
assign _zz_44_ = _zz_187_[0];
|
|
assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION));
|
|
assign decodeExceptionPort_payload_code = (4'b0010);
|
|
assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION;
|
|
assign execute_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION[19 : 15];
|
|
assign execute_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION[24 : 20];
|
|
assign _zz_103_ = (! execute_arbitration_isStuck);
|
|
assign execute_RegFilePlugin_rs1Data = _zz_154_;
|
|
assign execute_RegFilePlugin_rs2Data = _zz_155_;
|
|
assign _zz_43_ = execute_RegFilePlugin_rs1Data;
|
|
assign _zz_42_ = execute_RegFilePlugin_rs2Data;
|
|
assign lastStageRegFileWrite_valid = (execute_REGFILE_WRITE_VALID && execute_arbitration_isFiring);
|
|
assign lastStageRegFileWrite_payload_address = execute_INSTRUCTION[11 : 7];
|
|
assign lastStageRegFileWrite_payload_data = _zz_61_;
|
|
always @ (*) begin
|
|
case(execute_ALU_BITWISE_CTRL)
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin
|
|
execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2);
|
|
end
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin
|
|
execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2);
|
|
end
|
|
default : begin
|
|
execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2);
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always @ (*) begin
|
|
case(execute_ALU_CTRL)
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : begin
|
|
_zz_104_ = execute_IntAluPlugin_bitwise;
|
|
end
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : begin
|
|
_zz_104_ = {31'd0, _zz_188_};
|
|
end
|
|
default : begin
|
|
_zz_104_ = execute_SRC_ADD_SUB;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign _zz_39_ = _zz_104_;
|
|
assign _zz_37_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS));
|
|
always @ (*) begin
|
|
case(execute_SRC1_CTRL)
|
|
`Src1CtrlEnum_defaultEncoding_RS : begin
|
|
_zz_105_ = execute_RS1;
|
|
end
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin
|
|
_zz_105_ = {29'd0, _zz_189_};
|
|
end
|
|
`Src1CtrlEnum_defaultEncoding_IMU : begin
|
|
_zz_105_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)};
|
|
end
|
|
default : begin
|
|
_zz_105_ = {27'd0, _zz_190_};
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign _zz_36_ = _zz_105_;
|
|
assign _zz_106_ = _zz_191_[11];
|
|
always @ (*) begin
|
|
_zz_107_[19] = _zz_106_;
|
|
_zz_107_[18] = _zz_106_;
|
|
_zz_107_[17] = _zz_106_;
|
|
_zz_107_[16] = _zz_106_;
|
|
_zz_107_[15] = _zz_106_;
|
|
_zz_107_[14] = _zz_106_;
|
|
_zz_107_[13] = _zz_106_;
|
|
_zz_107_[12] = _zz_106_;
|
|
_zz_107_[11] = _zz_106_;
|
|
_zz_107_[10] = _zz_106_;
|
|
_zz_107_[9] = _zz_106_;
|
|
_zz_107_[8] = _zz_106_;
|
|
_zz_107_[7] = _zz_106_;
|
|
_zz_107_[6] = _zz_106_;
|
|
_zz_107_[5] = _zz_106_;
|
|
_zz_107_[4] = _zz_106_;
|
|
_zz_107_[3] = _zz_106_;
|
|
_zz_107_[2] = _zz_106_;
|
|
_zz_107_[1] = _zz_106_;
|
|
_zz_107_[0] = _zz_106_;
|
|
end
|
|
|
|
assign _zz_108_ = _zz_192_[11];
|
|
always @ (*) begin
|
|
_zz_109_[19] = _zz_108_;
|
|
_zz_109_[18] = _zz_108_;
|
|
_zz_109_[17] = _zz_108_;
|
|
_zz_109_[16] = _zz_108_;
|
|
_zz_109_[15] = _zz_108_;
|
|
_zz_109_[14] = _zz_108_;
|
|
_zz_109_[13] = _zz_108_;
|
|
_zz_109_[12] = _zz_108_;
|
|
_zz_109_[11] = _zz_108_;
|
|
_zz_109_[10] = _zz_108_;
|
|
_zz_109_[9] = _zz_108_;
|
|
_zz_109_[8] = _zz_108_;
|
|
_zz_109_[7] = _zz_108_;
|
|
_zz_109_[6] = _zz_108_;
|
|
_zz_109_[5] = _zz_108_;
|
|
_zz_109_[4] = _zz_108_;
|
|
_zz_109_[3] = _zz_108_;
|
|
_zz_109_[2] = _zz_108_;
|
|
_zz_109_[1] = _zz_108_;
|
|
_zz_109_[0] = _zz_108_;
|
|
end
|
|
|
|
always @ (*) begin
|
|
case(execute_SRC2_CTRL)
|
|
`Src2CtrlEnum_defaultEncoding_RS : begin
|
|
_zz_110_ = execute_RS2;
|
|
end
|
|
`Src2CtrlEnum_defaultEncoding_IMI : begin
|
|
_zz_110_ = {_zz_107_,execute_INSTRUCTION[31 : 20]};
|
|
end
|
|
`Src2CtrlEnum_defaultEncoding_IMS : begin
|
|
_zz_110_ = {_zz_109_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}};
|
|
end
|
|
default : begin
|
|
_zz_110_ = execute_PC;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign _zz_34_ = _zz_110_;
|
|
always @ (*) begin
|
|
execute_SrcPlugin_addSub = _zz_193_;
|
|
if(execute_SRC2_FORCE_ZERO)begin
|
|
execute_SrcPlugin_addSub = execute_SRC1;
|
|
end
|
|
end
|
|
|
|
assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31]));
|
|
assign _zz_32_ = execute_SrcPlugin_addSub;
|
|
assign _zz_31_ = execute_SrcPlugin_addSub;
|
|
assign _zz_30_ = execute_SrcPlugin_less;
|
|
assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1);
|
|
assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]);
|
|
assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_shiftReg : execute_SRC1);
|
|
assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == (4'b0000));
|
|
always @ (*) begin
|
|
case(execute_SHIFT_CTRL)
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : begin
|
|
_zz_111_ = (execute_LightShifterPlugin_shiftInput <<< 1);
|
|
end
|
|
default : begin
|
|
_zz_111_ = _zz_200_;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2);
|
|
assign _zz_112_ = execute_INSTRUCTION[14 : 12];
|
|
always @ (*) begin
|
|
if((_zz_112_ == (3'b000))) begin
|
|
_zz_113_ = execute_BranchPlugin_eq;
|
|
end else if((_zz_112_ == (3'b001))) begin
|
|
_zz_113_ = (! execute_BranchPlugin_eq);
|
|
end else if((((_zz_112_ & (3'b101)) == (3'b101)))) begin
|
|
_zz_113_ = (! execute_SRC_LESS);
|
|
end else begin
|
|
_zz_113_ = execute_SRC_LESS;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
case(execute_BRANCH_CTRL)
|
|
`BranchCtrlEnum_defaultEncoding_INC : begin
|
|
_zz_114_ = 1'b0;
|
|
end
|
|
`BranchCtrlEnum_defaultEncoding_JAL : begin
|
|
_zz_114_ = 1'b1;
|
|
end
|
|
`BranchCtrlEnum_defaultEncoding_JALR : begin
|
|
_zz_114_ = 1'b1;
|
|
end
|
|
default : begin
|
|
_zz_114_ = _zz_113_;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign _zz_28_ = _zz_114_;
|
|
assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC);
|
|
assign _zz_115_ = _zz_202_[19];
|
|
always @ (*) begin
|
|
_zz_116_[10] = _zz_115_;
|
|
_zz_116_[9] = _zz_115_;
|
|
_zz_116_[8] = _zz_115_;
|
|
_zz_116_[7] = _zz_115_;
|
|
_zz_116_[6] = _zz_115_;
|
|
_zz_116_[5] = _zz_115_;
|
|
_zz_116_[4] = _zz_115_;
|
|
_zz_116_[3] = _zz_115_;
|
|
_zz_116_[2] = _zz_115_;
|
|
_zz_116_[1] = _zz_115_;
|
|
_zz_116_[0] = _zz_115_;
|
|
end
|
|
|
|
assign _zz_117_ = _zz_203_[11];
|
|
always @ (*) begin
|
|
_zz_118_[19] = _zz_117_;
|
|
_zz_118_[18] = _zz_117_;
|
|
_zz_118_[17] = _zz_117_;
|
|
_zz_118_[16] = _zz_117_;
|
|
_zz_118_[15] = _zz_117_;
|
|
_zz_118_[14] = _zz_117_;
|
|
_zz_118_[13] = _zz_117_;
|
|
_zz_118_[12] = _zz_117_;
|
|
_zz_118_[11] = _zz_117_;
|
|
_zz_118_[10] = _zz_117_;
|
|
_zz_118_[9] = _zz_117_;
|
|
_zz_118_[8] = _zz_117_;
|
|
_zz_118_[7] = _zz_117_;
|
|
_zz_118_[6] = _zz_117_;
|
|
_zz_118_[5] = _zz_117_;
|
|
_zz_118_[4] = _zz_117_;
|
|
_zz_118_[3] = _zz_117_;
|
|
_zz_118_[2] = _zz_117_;
|
|
_zz_118_[1] = _zz_117_;
|
|
_zz_118_[0] = _zz_117_;
|
|
end
|
|
|
|
assign _zz_119_ = _zz_204_[11];
|
|
always @ (*) begin
|
|
_zz_120_[18] = _zz_119_;
|
|
_zz_120_[17] = _zz_119_;
|
|
_zz_120_[16] = _zz_119_;
|
|
_zz_120_[15] = _zz_119_;
|
|
_zz_120_[14] = _zz_119_;
|
|
_zz_120_[13] = _zz_119_;
|
|
_zz_120_[12] = _zz_119_;
|
|
_zz_120_[11] = _zz_119_;
|
|
_zz_120_[10] = _zz_119_;
|
|
_zz_120_[9] = _zz_119_;
|
|
_zz_120_[8] = _zz_119_;
|
|
_zz_120_[7] = _zz_119_;
|
|
_zz_120_[6] = _zz_119_;
|
|
_zz_120_[5] = _zz_119_;
|
|
_zz_120_[4] = _zz_119_;
|
|
_zz_120_[3] = _zz_119_;
|
|
_zz_120_[2] = _zz_119_;
|
|
_zz_120_[1] = _zz_119_;
|
|
_zz_120_[0] = _zz_119_;
|
|
end
|
|
|
|
always @ (*) begin
|
|
case(execute_BRANCH_CTRL)
|
|
`BranchCtrlEnum_defaultEncoding_JAL : begin
|
|
_zz_121_ = {{_zz_116_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0};
|
|
end
|
|
`BranchCtrlEnum_defaultEncoding_JALR : begin
|
|
_zz_121_ = {_zz_118_,execute_INSTRUCTION[31 : 20]};
|
|
end
|
|
default : begin
|
|
_zz_121_ = {{_zz_120_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0};
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign execute_BranchPlugin_branch_src2 = _zz_121_;
|
|
assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2);
|
|
assign _zz_26_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)};
|
|
assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && (! execute_arbitration_isStuckByOthers)) && execute_BRANCH_DO);
|
|
assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC;
|
|
always @ (*) begin
|
|
BranchPlugin_branchExceptionPort_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]);
|
|
if(1'b0)begin
|
|
BranchPlugin_branchExceptionPort_valid = 1'b0;
|
|
end
|
|
end
|
|
|
|
assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000);
|
|
assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload;
|
|
always @ (*) begin
|
|
CsrPlugin_privilege = (2'b11);
|
|
if(CsrPlugin_forceMachineWire)begin
|
|
CsrPlugin_privilege = (2'b11);
|
|
end
|
|
end
|
|
|
|
assign CsrPlugin_misa_base = (2'b01);
|
|
assign CsrPlugin_misa_extensions = (26'b00000000000000000000000000);
|
|
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11);
|
|
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege);
|
|
assign _zz_122_ = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid};
|
|
assign _zz_123_ = _zz_205_[0];
|
|
assign _zz_124_ = {CsrPlugin_selfException_valid,{BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}};
|
|
assign _zz_125_ = (_zz_124_ & (~ _zz_207_));
|
|
assign _zz_126_ = _zz_125_[1];
|
|
assign _zz_127_ = _zz_125_[2];
|
|
assign _zz_128_ = {_zz_127_,_zz_126_};
|
|
always @ (*) begin
|
|
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
|
|
if(_zz_161_)begin
|
|
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1;
|
|
end
|
|
if(decode_arbitration_isFlushed)begin
|
|
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0;
|
|
end
|
|
end
|
|
|
|
assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
|
|
assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
|
|
always @ (*) begin
|
|
CsrPlugin_interrupt = 1'b0;
|
|
CsrPlugin_interruptCode = (4'bxxxx);
|
|
CsrPlugin_interruptTargetPrivilege = (2'bxx);
|
|
if((CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11))))begin
|
|
if((((CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE) && 1'b1) && (! 1'b0)))begin
|
|
CsrPlugin_interrupt = 1'b1;
|
|
CsrPlugin_interruptCode = (4'b0111);
|
|
CsrPlugin_interruptTargetPrivilege = (2'b11);
|
|
end
|
|
if((((CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE) && 1'b1) && (! 1'b0)))begin
|
|
CsrPlugin_interrupt = 1'b1;
|
|
CsrPlugin_interruptCode = (4'b0011);
|
|
CsrPlugin_interruptTargetPrivilege = (2'b11);
|
|
end
|
|
if((((CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE) && 1'b1) && (! 1'b0)))begin
|
|
CsrPlugin_interrupt = 1'b1;
|
|
CsrPlugin_interruptCode = (4'b1011);
|
|
CsrPlugin_interruptTargetPrivilege = (2'b11);
|
|
end
|
|
end
|
|
if((! CsrPlugin_allowInterrupts))begin
|
|
CsrPlugin_interrupt = 1'b0;
|
|
end
|
|
end
|
|
|
|
assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && CsrPlugin_allowException);
|
|
assign CsrPlugin_lastStageWasWfi = 1'b0;
|
|
always @ (*) begin
|
|
CsrPlugin_pipelineLiberator_done = ((! (execute_arbitration_isValid != (1'b0))) && IBusCachedPlugin_pcValids_1);
|
|
if((CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute != (1'b0)))begin
|
|
CsrPlugin_pipelineLiberator_done = 1'b0;
|
|
end
|
|
if(CsrPlugin_hadException)begin
|
|
CsrPlugin_pipelineLiberator_done = 1'b0;
|
|
end
|
|
end
|
|
|
|
assign CsrPlugin_interruptJump = (CsrPlugin_interrupt && CsrPlugin_pipelineLiberator_done);
|
|
always @ (*) begin
|
|
CsrPlugin_targetPrivilege = CsrPlugin_interruptTargetPrivilege;
|
|
if(CsrPlugin_hadException)begin
|
|
CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
CsrPlugin_trapCause = CsrPlugin_interruptCode;
|
|
if(CsrPlugin_hadException)begin
|
|
CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
CsrPlugin_xtvec_mode = (2'bxx);
|
|
CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
|
|
case(CsrPlugin_targetPrivilege)
|
|
2'b11 : begin
|
|
CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode;
|
|
CsrPlugin_xtvec_base = CsrPlugin_mtvec_base;
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign contextSwitching = CsrPlugin_jumpInterface_valid;
|
|
assign _zz_24_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000)))));
|
|
assign _zz_23_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000));
|
|
assign execute_CsrPlugin_inWfi = 1'b0;
|
|
assign execute_CsrPlugin_blockedBySideEffects = 1'b0;
|
|
always @ (*) begin
|
|
execute_CsrPlugin_illegalAccess = 1'b1;
|
|
execute_CsrPlugin_readData = (32'b00000000000000000000000000000000);
|
|
case(execute_CsrPlugin_csrAddress)
|
|
12'b101111000000 : begin
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
|
execute_CsrPlugin_readData[31 : 0] = _zz_129_;
|
|
end
|
|
12'b001100000000 : begin
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
|
execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP;
|
|
execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE;
|
|
execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE;
|
|
end
|
|
12'b001101000001 : begin
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
|
execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc;
|
|
end
|
|
12'b001100000101 : begin
|
|
if(execute_CSR_WRITE_OPCODE)begin
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
|
end
|
|
end
|
|
12'b001101000100 : begin
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
|
execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP;
|
|
execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP;
|
|
execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP;
|
|
end
|
|
12'b001101000011 : begin
|
|
if(execute_CSR_READ_OPCODE)begin
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
|
end
|
|
execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval;
|
|
end
|
|
12'b111111000000 : begin
|
|
if(execute_CSR_READ_OPCODE)begin
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
|
end
|
|
execute_CsrPlugin_readData[31 : 0] = _zz_130_;
|
|
end
|
|
12'b001101000000 : begin
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
|
execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mscratch;
|
|
end
|
|
12'b001100000100 : begin
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
|
execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE;
|
|
execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE;
|
|
execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE;
|
|
end
|
|
12'b001101000010 : begin
|
|
if(execute_CSR_READ_OPCODE)begin
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
|
end
|
|
execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt;
|
|
execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode;
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin
|
|
execute_CsrPlugin_illegalAccess = 1'b1;
|
|
end
|
|
if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
execute_CsrPlugin_illegalInstruction = 1'b0;
|
|
if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin
|
|
if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin
|
|
execute_CsrPlugin_illegalInstruction = 1'b1;
|
|
end
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
CsrPlugin_selfException_valid = 1'b0;
|
|
CsrPlugin_selfException_payload_code = (4'bxxxx);
|
|
if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)))begin
|
|
CsrPlugin_selfException_valid = 1'b1;
|
|
case(CsrPlugin_privilege)
|
|
2'b00 : begin
|
|
CsrPlugin_selfException_payload_code = (4'b1000);
|
|
end
|
|
default : begin
|
|
CsrPlugin_selfException_payload_code = (4'b1011);
|
|
end
|
|
endcase
|
|
end
|
|
if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_EBREAK)))begin
|
|
CsrPlugin_selfException_valid = 1'b1;
|
|
CsrPlugin_selfException_payload_code = (4'b0011);
|
|
end
|
|
end
|
|
|
|
assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION;
|
|
assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE);
|
|
assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE);
|
|
assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers));
|
|
assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers));
|
|
assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData;
|
|
always @ (*) begin
|
|
case(_zz_174_)
|
|
1'b0 : begin
|
|
execute_CsrPlugin_writeData = execute_SRC1;
|
|
end
|
|
default : begin
|
|
execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1));
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20];
|
|
assign _zz_130_ = (_zz_129_ & externalInterruptArray_regNext);
|
|
assign externalInterrupt = (_zz_130_ != (32'b00000000000000000000000000000000));
|
|
always @ (*) begin
|
|
debug_bus_cmd_ready = 1'b1;
|
|
IBusCachedPlugin_injectionPort_valid = 1'b0;
|
|
if(debug_bus_cmd_valid)begin
|
|
case(_zz_170_)
|
|
6'b000000 : begin
|
|
end
|
|
6'b000001 : begin
|
|
if(debug_bus_cmd_payload_wr)begin
|
|
IBusCachedPlugin_injectionPort_valid = 1'b1;
|
|
debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready;
|
|
end
|
|
end
|
|
6'b010000 : begin
|
|
end
|
|
6'b010001 : begin
|
|
end
|
|
6'b010010 : begin
|
|
end
|
|
6'b010011 : begin
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
debug_bus_rsp_data = DebugPlugin_busReadDataReg;
|
|
if((! _zz_131_))begin
|
|
debug_bus_rsp_data[0] = DebugPlugin_resetIt;
|
|
debug_bus_rsp_data[1] = DebugPlugin_haltIt;
|
|
debug_bus_rsp_data[2] = DebugPlugin_isPipBusy;
|
|
debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak;
|
|
debug_bus_rsp_data[4] = DebugPlugin_stepIt;
|
|
end
|
|
end
|
|
|
|
assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data;
|
|
assign _zz_22_ = ((! DebugPlugin_haltIt) && (decode_IS_EBREAK || ((((1'b0 || (DebugPlugin_hardwareBreakpoints_0_valid && (DebugPlugin_hardwareBreakpoints_0_pc == _zz_212_))) || (DebugPlugin_hardwareBreakpoints_1_valid && (DebugPlugin_hardwareBreakpoints_1_pc == _zz_213_))) || (DebugPlugin_hardwareBreakpoints_2_valid && (DebugPlugin_hardwareBreakpoints_2_pc == _zz_214_))) || (DebugPlugin_hardwareBreakpoints_3_valid && (DebugPlugin_hardwareBreakpoints_3_pc == _zz_215_)))));
|
|
assign debug_resetOut = DebugPlugin_resetIt_regNext;
|
|
assign _zz_21_ = decode_SRC2_CTRL;
|
|
assign _zz_19_ = _zz_47_;
|
|
assign _zz_33_ = decode_to_execute_SRC2_CTRL;
|
|
assign _zz_18_ = decode_SHIFT_CTRL;
|
|
assign _zz_16_ = _zz_56_;
|
|
assign _zz_29_ = decode_to_execute_SHIFT_CTRL;
|
|
assign _zz_15_ = decode_BRANCH_CTRL;
|
|
assign _zz_13_ = _zz_49_;
|
|
assign _zz_27_ = decode_to_execute_BRANCH_CTRL;
|
|
assign _zz_12_ = decode_ALU_BITWISE_CTRL;
|
|
assign _zz_10_ = _zz_52_;
|
|
assign _zz_40_ = decode_to_execute_ALU_BITWISE_CTRL;
|
|
assign _zz_9_ = decode_ALU_CTRL;
|
|
assign _zz_7_ = _zz_57_;
|
|
assign _zz_38_ = decode_to_execute_ALU_CTRL;
|
|
assign _zz_6_ = decode_ENV_CTRL;
|
|
assign _zz_4_ = _zz_50_;
|
|
assign _zz_25_ = decode_to_execute_ENV_CTRL;
|
|
assign _zz_3_ = decode_SRC1_CTRL;
|
|
assign _zz_1_ = _zz_55_;
|
|
assign _zz_35_ = decode_to_execute_SRC1_CTRL;
|
|
assign decode_arbitration_isFlushed = ({execute_arbitration_flushAll,decode_arbitration_flushAll} != (2'b00));
|
|
assign execute_arbitration_isFlushed = (execute_arbitration_flushAll != (1'b0));
|
|
assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (1'b0 || execute_arbitration_isStuck));
|
|
assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers);
|
|
assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
|
|
assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt));
|
|
assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || 1'b0);
|
|
assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers);
|
|
assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
|
|
assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt));
|
|
assign iBusWishbone_ADR = {_zz_222_,_zz_133_};
|
|
assign iBusWishbone_CTI = ((_zz_133_ == (3'b111)) ? (3'b111) : (3'b010));
|
|
assign iBusWishbone_BTE = (2'b00);
|
|
assign iBusWishbone_SEL = (4'b1111);
|
|
assign iBusWishbone_WE = 1'b0;
|
|
assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
|
|
always @ (*) begin
|
|
iBusWishbone_CYC = 1'b0;
|
|
iBusWishbone_STB = 1'b0;
|
|
if(_zz_171_)begin
|
|
iBusWishbone_CYC = 1'b1;
|
|
iBusWishbone_STB = 1'b1;
|
|
end
|
|
end
|
|
|
|
assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK);
|
|
assign iBus_rsp_valid = _zz_134_;
|
|
assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext;
|
|
assign iBus_rsp_payload_error = 1'b0;
|
|
assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid;
|
|
assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr;
|
|
assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address;
|
|
assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data;
|
|
assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size;
|
|
assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready;
|
|
assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2);
|
|
assign dBusWishbone_CTI = (3'b000);
|
|
assign dBusWishbone_BTE = (2'b00);
|
|
always @ (*) begin
|
|
case(dBus_cmd_halfPipe_payload_size)
|
|
2'b00 : begin
|
|
_zz_135_ = (4'b0001);
|
|
end
|
|
2'b01 : begin
|
|
_zz_135_ = (4'b0011);
|
|
end
|
|
default : begin
|
|
_zz_135_ = (4'b1111);
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always @ (*) begin
|
|
dBusWishbone_SEL = _zz_223_[3:0];
|
|
if((! dBus_cmd_halfPipe_payload_wr))begin
|
|
dBusWishbone_SEL = (4'b1111);
|
|
end
|
|
end
|
|
|
|
assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr;
|
|
assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data;
|
|
assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK);
|
|
assign dBusWishbone_CYC = dBus_cmd_halfPipe_valid;
|
|
assign dBusWishbone_STB = dBus_cmd_halfPipe_valid;
|
|
assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK);
|
|
assign dBus_rsp_data = dBusWishbone_DAT_MISO;
|
|
assign dBus_rsp_error = 1'b0;
|
|
always @ (posedge clk) begin
|
|
if(reset) begin
|
|
IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;
|
|
IBusCachedPlugin_fetchPc_inc <= 1'b0;
|
|
_zz_77_ <= 1'b0;
|
|
_zz_82_ <= 1'b0;
|
|
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
|
|
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
|
|
IBusCachedPlugin_injector_decodeRemoved <= 1'b0;
|
|
_zz_83_ <= 1'b0;
|
|
execute_LightShifterPlugin_isActive <= 1'b0;
|
|
CsrPlugin_mstatus_MIE <= 1'b0;
|
|
CsrPlugin_mstatus_MPIE <= 1'b0;
|
|
CsrPlugin_mstatus_MPP <= (2'b11);
|
|
CsrPlugin_mie_MEIE <= 1'b0;
|
|
CsrPlugin_mie_MTIE <= 1'b0;
|
|
CsrPlugin_mie_MSIE <= 1'b0;
|
|
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
|
|
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0;
|
|
CsrPlugin_hadException <= 1'b0;
|
|
_zz_129_ <= (32'b00000000000000000000000000000000);
|
|
execute_arbitration_isValid <= 1'b0;
|
|
_zz_132_ <= (3'b000);
|
|
_zz_133_ <= (3'b000);
|
|
_zz_134_ <= 1'b0;
|
|
dBus_cmd_halfPipe_regs_valid <= 1'b0;
|
|
dBus_cmd_halfPipe_regs_ready <= 1'b1;
|
|
end else begin
|
|
if(IBusCachedPlugin_fetchPc_propagatePc)begin
|
|
IBusCachedPlugin_fetchPc_inc <= 1'b0;
|
|
end
|
|
if(IBusCachedPlugin_jump_pcLoad_valid)begin
|
|
IBusCachedPlugin_fetchPc_inc <= 1'b0;
|
|
end
|
|
if(_zz_169_)begin
|
|
IBusCachedPlugin_fetchPc_inc <= 1'b1;
|
|
end
|
|
if(IBusCachedPlugin_fetchPc_samplePcNext)begin
|
|
IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc;
|
|
end
|
|
_zz_77_ <= 1'b1;
|
|
if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin
|
|
_zz_82_ <= 1'b0;
|
|
end
|
|
if(_zz_80_)begin
|
|
_zz_82_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid;
|
|
end
|
|
if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin
|
|
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
|
|
end
|
|
if((! (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)))begin
|
|
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1;
|
|
end
|
|
if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin
|
|
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0;
|
|
end
|
|
if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin
|
|
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
|
|
end
|
|
if(decode_arbitration_removeIt)begin
|
|
IBusCachedPlugin_injector_decodeRemoved <= 1'b1;
|
|
end
|
|
if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin
|
|
IBusCachedPlugin_injector_decodeRemoved <= 1'b0;
|
|
end
|
|
if((dBus_cmd_valid && dBus_cmd_ready))begin
|
|
_zz_83_ <= 1'b1;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
_zz_83_ <= 1'b0;
|
|
end
|
|
if(_zz_159_)begin
|
|
if(_zz_160_)begin
|
|
execute_LightShifterPlugin_isActive <= 1'b1;
|
|
if(execute_LightShifterPlugin_done)begin
|
|
execute_LightShifterPlugin_isActive <= 1'b0;
|
|
end
|
|
end
|
|
end
|
|
if(execute_arbitration_removeIt)begin
|
|
execute_LightShifterPlugin_isActive <= 1'b0;
|
|
end
|
|
if((! decode_arbitration_isStuck))begin
|
|
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
|
|
end else begin
|
|
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck));
|
|
end else begin
|
|
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0;
|
|
end
|
|
CsrPlugin_hadException <= CsrPlugin_exception;
|
|
if(_zz_163_)begin
|
|
case(CsrPlugin_targetPrivilege)
|
|
2'b11 : begin
|
|
CsrPlugin_mstatus_MIE <= 1'b0;
|
|
CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE;
|
|
CsrPlugin_mstatus_MPP <= CsrPlugin_privilege;
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
end
|
|
if(_zz_164_)begin
|
|
case(_zz_165_)
|
|
2'b11 : begin
|
|
CsrPlugin_mstatus_MPP <= (2'b00);
|
|
CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE;
|
|
CsrPlugin_mstatus_MPIE <= 1'b1;
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
end
|
|
if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin
|
|
execute_arbitration_isValid <= 1'b0;
|
|
end
|
|
if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin
|
|
execute_arbitration_isValid <= decode_arbitration_isValid;
|
|
end
|
|
case(_zz_132_)
|
|
3'b000 : begin
|
|
if(IBusCachedPlugin_injectionPort_valid)begin
|
|
_zz_132_ <= (3'b001);
|
|
end
|
|
end
|
|
3'b001 : begin
|
|
_zz_132_ <= (3'b010);
|
|
end
|
|
3'b010 : begin
|
|
_zz_132_ <= (3'b011);
|
|
end
|
|
3'b011 : begin
|
|
if((! decode_arbitration_isStuck))begin
|
|
_zz_132_ <= (3'b100);
|
|
end
|
|
end
|
|
3'b100 : begin
|
|
_zz_132_ <= (3'b000);
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
case(execute_CsrPlugin_csrAddress)
|
|
12'b101111000000 : begin
|
|
if(execute_CsrPlugin_writeEnable)begin
|
|
_zz_129_ <= execute_CsrPlugin_writeData[31 : 0];
|
|
end
|
|
end
|
|
12'b001100000000 : begin
|
|
if(execute_CsrPlugin_writeEnable)begin
|
|
CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11];
|
|
CsrPlugin_mstatus_MPIE <= _zz_216_[0];
|
|
CsrPlugin_mstatus_MIE <= _zz_217_[0];
|
|
end
|
|
end
|
|
12'b001101000001 : begin
|
|
end
|
|
12'b001100000101 : begin
|
|
end
|
|
12'b001101000100 : begin
|
|
end
|
|
12'b001101000011 : begin
|
|
end
|
|
12'b111111000000 : begin
|
|
end
|
|
12'b001101000000 : begin
|
|
end
|
|
12'b001100000100 : begin
|
|
if(execute_CsrPlugin_writeEnable)begin
|
|
CsrPlugin_mie_MEIE <= _zz_219_[0];
|
|
CsrPlugin_mie_MTIE <= _zz_220_[0];
|
|
CsrPlugin_mie_MSIE <= _zz_221_[0];
|
|
end
|
|
end
|
|
12'b001101000010 : begin
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
if(_zz_171_)begin
|
|
if(iBusWishbone_ACK)begin
|
|
_zz_133_ <= (_zz_133_ + (3'b001));
|
|
end
|
|
end
|
|
_zz_134_ <= (iBusWishbone_CYC && iBusWishbone_ACK);
|
|
if(_zz_172_)begin
|
|
dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid;
|
|
dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid);
|
|
end else begin
|
|
dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready);
|
|
dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready;
|
|
end
|
|
end
|
|
end
|
|
|
|
always @ (posedge clk) begin
|
|
if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin
|
|
IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit;
|
|
end
|
|
if((! execute_arbitration_isStuckByOthers))begin
|
|
execute_LightShifterPlugin_shiftReg <= _zz_61_;
|
|
end
|
|
if(_zz_159_)begin
|
|
if(_zz_160_)begin
|
|
execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - (5'b00001));
|
|
end
|
|
end
|
|
CsrPlugin_mip_MEIP <= externalInterrupt;
|
|
CsrPlugin_mip_MTIP <= timerInterrupt;
|
|
CsrPlugin_mip_MSIP <= softwareInterrupt;
|
|
CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001));
|
|
if(execute_arbitration_isFiring)begin
|
|
CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001));
|
|
end
|
|
if(_zz_161_)begin
|
|
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_123_ ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code);
|
|
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_123_ ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr);
|
|
end
|
|
if(_zz_162_)begin
|
|
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= _zz_157_;
|
|
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= _zz_158_;
|
|
end
|
|
if(_zz_163_)begin
|
|
case(CsrPlugin_targetPrivilege)
|
|
2'b11 : begin
|
|
CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException);
|
|
CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause;
|
|
CsrPlugin_mepc <= execute_PC;
|
|
if(CsrPlugin_hadException)begin
|
|
CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
|
|
end
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
end
|
|
externalInterruptArray_regNext <= externalInterruptArray;
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_SRC2_CTRL <= _zz_20_;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_SHIFT_CTRL <= _zz_17_;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_BRANCH_CTRL <= _zz_14_;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_FORMAL_PC_NEXT <= _zz_68_;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_INSTRUCTION <= decode_INSTRUCTION;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_IS_CSR <= decode_IS_CSR;
|
|
end
|
|
if(((! execute_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_execute)))begin
|
|
decode_to_execute_PC <= decode_PC;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_ALU_BITWISE_CTRL <= _zz_11_;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_ALU_CTRL <= _zz_8_;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_ENV_CTRL <= _zz_5_;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_SRC1_CTRL <= _zz_2_;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_DO_EBREAK <= decode_DO_EBREAK;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED;
|
|
end
|
|
case(execute_CsrPlugin_csrAddress)
|
|
12'b101111000000 : begin
|
|
end
|
|
12'b001100000000 : begin
|
|
end
|
|
12'b001101000001 : begin
|
|
if(execute_CsrPlugin_writeEnable)begin
|
|
CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0];
|
|
end
|
|
end
|
|
12'b001100000101 : begin
|
|
if(execute_CsrPlugin_writeEnable)begin
|
|
CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2];
|
|
CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0];
|
|
end
|
|
end
|
|
12'b001101000100 : begin
|
|
if(execute_CsrPlugin_writeEnable)begin
|
|
CsrPlugin_mip_MSIP <= _zz_218_[0];
|
|
end
|
|
end
|
|
12'b001101000011 : begin
|
|
end
|
|
12'b111111000000 : begin
|
|
end
|
|
12'b001101000000 : begin
|
|
if(execute_CsrPlugin_writeEnable)begin
|
|
CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0];
|
|
end
|
|
end
|
|
12'b001100000100 : begin
|
|
end
|
|
12'b001101000010 : begin
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO;
|
|
if(_zz_172_)begin
|
|
dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr;
|
|
dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address;
|
|
dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data;
|
|
dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size;
|
|
end
|
|
end
|
|
|
|
always @ (posedge clk) begin
|
|
DebugPlugin_firstCycle <= 1'b0;
|
|
if(debug_bus_cmd_ready)begin
|
|
DebugPlugin_firstCycle <= 1'b1;
|
|
end
|
|
DebugPlugin_secondCycle <= DebugPlugin_firstCycle;
|
|
DebugPlugin_isPipBusy <= (({execute_arbitration_isValid,decode_arbitration_isValid} != (2'b00)) || IBusCachedPlugin_incomingInstruction);
|
|
if(execute_arbitration_isValid)begin
|
|
DebugPlugin_busReadDataReg <= _zz_61_;
|
|
end
|
|
_zz_131_ <= debug_bus_cmd_payload_address[2];
|
|
if(debug_bus_cmd_valid)begin
|
|
case(_zz_170_)
|
|
6'b000000 : begin
|
|
end
|
|
6'b000001 : begin
|
|
end
|
|
6'b010000 : begin
|
|
if(debug_bus_cmd_payload_wr)begin
|
|
DebugPlugin_hardwareBreakpoints_0_pc <= debug_bus_cmd_payload_data[31 : 1];
|
|
end
|
|
end
|
|
6'b010001 : begin
|
|
if(debug_bus_cmd_payload_wr)begin
|
|
DebugPlugin_hardwareBreakpoints_1_pc <= debug_bus_cmd_payload_data[31 : 1];
|
|
end
|
|
end
|
|
6'b010010 : begin
|
|
if(debug_bus_cmd_payload_wr)begin
|
|
DebugPlugin_hardwareBreakpoints_2_pc <= debug_bus_cmd_payload_data[31 : 1];
|
|
end
|
|
end
|
|
6'b010011 : begin
|
|
if(debug_bus_cmd_payload_wr)begin
|
|
DebugPlugin_hardwareBreakpoints_3_pc <= debug_bus_cmd_payload_data[31 : 1];
|
|
end
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
end
|
|
if(_zz_166_)begin
|
|
DebugPlugin_busReadDataReg <= execute_PC;
|
|
end
|
|
DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt;
|
|
end
|
|
|
|
always @ (posedge clk) begin
|
|
if(debugReset) begin
|
|
DebugPlugin_resetIt <= 1'b0;
|
|
DebugPlugin_haltIt <= 1'b0;
|
|
DebugPlugin_stepIt <= 1'b0;
|
|
DebugPlugin_godmode <= 1'b0;
|
|
DebugPlugin_haltedByBreak <= 1'b0;
|
|
DebugPlugin_hardwareBreakpoints_0_valid <= 1'b0;
|
|
DebugPlugin_hardwareBreakpoints_1_valid <= 1'b0;
|
|
DebugPlugin_hardwareBreakpoints_2_valid <= 1'b0;
|
|
DebugPlugin_hardwareBreakpoints_3_valid <= 1'b0;
|
|
end else begin
|
|
if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin
|
|
DebugPlugin_godmode <= 1'b1;
|
|
end
|
|
if(debug_bus_cmd_valid)begin
|
|
case(_zz_170_)
|
|
6'b000000 : begin
|
|
if(debug_bus_cmd_payload_wr)begin
|
|
DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4];
|
|
if(debug_bus_cmd_payload_data[16])begin
|
|
DebugPlugin_resetIt <= 1'b1;
|
|
end
|
|
if(debug_bus_cmd_payload_data[24])begin
|
|
DebugPlugin_resetIt <= 1'b0;
|
|
end
|
|
if(debug_bus_cmd_payload_data[17])begin
|
|
DebugPlugin_haltIt <= 1'b1;
|
|
end
|
|
if(debug_bus_cmd_payload_data[25])begin
|
|
DebugPlugin_haltIt <= 1'b0;
|
|
end
|
|
if(debug_bus_cmd_payload_data[25])begin
|
|
DebugPlugin_haltedByBreak <= 1'b0;
|
|
end
|
|
if(debug_bus_cmd_payload_data[25])begin
|
|
DebugPlugin_godmode <= 1'b0;
|
|
end
|
|
end
|
|
end
|
|
6'b000001 : begin
|
|
end
|
|
6'b010000 : begin
|
|
if(debug_bus_cmd_payload_wr)begin
|
|
DebugPlugin_hardwareBreakpoints_0_valid <= _zz_208_[0];
|
|
end
|
|
end
|
|
6'b010001 : begin
|
|
if(debug_bus_cmd_payload_wr)begin
|
|
DebugPlugin_hardwareBreakpoints_1_valid <= _zz_209_[0];
|
|
end
|
|
end
|
|
6'b010010 : begin
|
|
if(debug_bus_cmd_payload_wr)begin
|
|
DebugPlugin_hardwareBreakpoints_2_valid <= _zz_210_[0];
|
|
end
|
|
end
|
|
6'b010011 : begin
|
|
if(debug_bus_cmd_payload_wr)begin
|
|
DebugPlugin_hardwareBreakpoints_3_valid <= _zz_211_[0];
|
|
end
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
end
|
|
if(_zz_166_)begin
|
|
if(_zz_167_)begin
|
|
DebugPlugin_haltIt <= 1'b1;
|
|
DebugPlugin_haltedByBreak <= 1'b1;
|
|
end
|
|
end
|
|
if(_zz_168_)begin
|
|
if(decode_arbitration_isValid)begin
|
|
DebugPlugin_haltIt <= 1'b1;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
|
|
always @ (posedge clk) begin
|
|
IBusCachedPlugin_injectionPort_payload_regNext <= IBusCachedPlugin_injectionPort_payload;
|
|
end
|
|
|
|
endmodule
|
|
|