823 lines
15 KiB
C
823 lines
15 KiB
C
#include <stdint.h>
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#include <stdio.h>
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#include <fcntl.h>
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#include <unistd.h>
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <string.h>
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#include <stdlib.h>
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#include <time.h>
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#include <fomu/csr.h>
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#include "spi.h"
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#define fprintf(...) do {} while(0)
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static uint8_t do_mirror;
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static uint8_t oe_mirror;
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#define PI_OUTPUT 1
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#define PI_INPUT 0
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#define PI_ALT0 PI_INPUT
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static void gpioSetMode(int pin, int mode) {
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if (mode)
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oe_mirror |= 1 << pin;
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else
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oe_mirror &= ~(1 << pin);
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picorvspi_cfg2_write(oe_mirror);
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}
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static void gpioWrite(int pin, int val) {
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if (val)
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do_mirror |= 1 << pin;
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else
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do_mirror &= ~(1 << pin);
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picorvspi_cfg1_write(do_mirror);
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}
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static int gpioRead(int pin) {
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return !!(picorvspi_stat1_read() & (1 << pin));
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}
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enum ff_spi_quirks {
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// There is no separate "Write SR 2" command. Instead,
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// you must write SR2 after writing SR1
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SQ_SR2_FROM_SR1 = (1 << 0),
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// Don't issue a "Write Enable" command prior to writing
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// a status register
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SQ_SKIP_SR_WEL = (1 << 1),
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// Security registers are shifted up by 4 bits
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SQ_SECURITY_NYBBLE_SHIFT = (1 << 2),
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};
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struct ff_spi {
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enum spi_state state;
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enum spi_type type;
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enum spi_type desired_type;
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struct spi_id id;
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enum ff_spi_quirks quirks;
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int size_override;
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struct {
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union {
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int mosi;
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int d0;
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};
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union {
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int miso;
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int d1;
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};
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union {
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int wp;
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int d2;
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};
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union {
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int hold;
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int d3;
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};
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int clk;
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int cs;
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} pins;
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};
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static struct ff_spi spi;
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static void spi_get_id(void);
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static void spi_set_state(enum spi_state state) {
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if (spi.state == state)
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return;
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switch (state) {
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case SS_SINGLE:
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gpioSetMode(spi.pins.clk, PI_OUTPUT); // CLK
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gpioSetMode(spi.pins.cs, PI_OUTPUT); // CE0#
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gpioSetMode(spi.pins.mosi, PI_OUTPUT); // MOSI
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gpioSetMode(spi.pins.miso, PI_INPUT); // MISO
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gpioSetMode(spi.pins.hold, PI_OUTPUT);
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gpioSetMode(spi.pins.wp, PI_OUTPUT);
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break;
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case SS_QUAD_RX:
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gpioSetMode(spi.pins.clk, PI_OUTPUT); // CLK
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gpioSetMode(spi.pins.cs, PI_OUTPUT); // CE0#
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gpioSetMode(spi.pins.mosi, PI_INPUT); // MOSI
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gpioSetMode(spi.pins.miso, PI_INPUT); // MISO
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gpioSetMode(spi.pins.hold, PI_INPUT);
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gpioSetMode(spi.pins.wp, PI_INPUT);
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break;
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case SS_QUAD_TX:
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gpioSetMode(spi.pins.clk, PI_OUTPUT); // CLK
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gpioSetMode(spi.pins.cs, PI_OUTPUT); // CE0#
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gpioSetMode(spi.pins.mosi, PI_OUTPUT); // MOSI
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gpioSetMode(spi.pins.miso, PI_OUTPUT); // MISO
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gpioSetMode(spi.pins.hold, PI_OUTPUT);
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gpioSetMode(spi.pins.wp, PI_OUTPUT);
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break;
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case SS_HARDWARE:
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gpioSetMode(spi.pins.clk, PI_ALT0); // CLK
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gpioSetMode(spi.pins.cs, PI_ALT0); // CE0#
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gpioSetMode(spi.pins.mosi, PI_ALT0); // MOSI
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gpioSetMode(spi.pins.miso, PI_ALT0); // MISO
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gpioSetMode(spi.pins.hold, PI_OUTPUT);
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gpioSetMode(spi.pins.wp, PI_OUTPUT);
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break;
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default:
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fprintf(stderr, "Unrecognized spi state\n");
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return;
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}
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spi.state = state;
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}
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void spiPause(void) {
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// usleep(1);
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return;
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}
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void spiBegin(void) {
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spi_set_state(SS_SINGLE);
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if ((spi.type == ST_SINGLE)) {
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gpioWrite(spi.pins.wp, 1);
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gpioWrite(spi.pins.hold, 1);
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}
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gpioWrite(spi.pins.cs, 0);
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}
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void spiEnd(void) {
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(void)spi;
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gpioWrite(spi.pins.cs, 1);
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}
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static uint8_t spiXfer(uint8_t out) {
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int bit;
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uint8_t in = 0;
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for (bit = 7; bit >= 0; bit--) {
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if (out & (1 << bit)) {
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gpioWrite(spi.pins.mosi, 1);
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}
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else {
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gpioWrite(spi.pins.mosi, 0);
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}
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gpioWrite(spi.pins.clk, 1);
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spiPause();
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in |= ((!!gpioRead(spi.pins.miso)) << bit);
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gpioWrite(spi.pins.clk, 0);
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spiPause();
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}
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return in;
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}
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static void spiSingleTx(uint8_t out) {
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spi_set_state(SS_SINGLE);
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spiXfer(out);
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}
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static uint8_t spiSingleRx(void) {
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spi_set_state(SS_SINGLE);
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return spiXfer(0xff);
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}
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static void spiQuadTx(uint8_t out) {
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int bit;
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spi_set_state(SS_QUAD_TX);
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for (bit = 7; bit >= 0; bit -= 4) {
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if (out & (1 << (bit - 3))) {
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gpioWrite(spi.pins.d0, 1);
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}
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else {
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gpioWrite(spi.pins.d0, 0);
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}
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if (out & (1 << (bit - 2))) {
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gpioWrite(spi.pins.d1, 1);
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}
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else {
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gpioWrite(spi.pins.d1, 0);
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}
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if (out & (1 << (bit - 1))) {
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gpioWrite(spi.pins.d2, 1);
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}
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else {
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gpioWrite(spi.pins.d2, 0);
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}
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if (out & (1 << (bit - 0))) {
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gpioWrite(spi.pins.d3, 1);
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}
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else {
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gpioWrite(spi.pins.d3, 0);
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}
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gpioWrite(spi.pins.clk, 1);
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spiPause();
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gpioWrite(spi.pins.clk, 0);
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spiPause();
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}
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}
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static uint8_t spiQuadRx(void) {
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int bit;
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uint8_t in = 0;
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spi_set_state(SS_QUAD_RX);
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for (bit = 7; bit >= 0; bit -= 4) {
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gpioWrite(spi.pins.clk, 1);
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spiPause();
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in |= ((!!gpioRead(spi.pins.d0)) << (bit - 3));
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in |= ((!!gpioRead(spi.pins.d1)) << (bit - 2));
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in |= ((!!gpioRead(spi.pins.d2)) << (bit - 1));
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in |= ((!!gpioRead(spi.pins.d3)) << (bit - 0));
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gpioWrite(spi.pins.clk, 0);
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spiPause();
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}
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return in;
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}
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int spiTx(uint8_t word) {
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switch (spi.type) {
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case ST_SINGLE:
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spiSingleTx(word);
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break;
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case ST_QUAD:
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case ST_QPI:
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spiQuadTx(word);
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break;
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default:
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return -1;
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}
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return 0;
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}
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uint8_t spiRx(void) {
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switch (spi.type) {
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case ST_SINGLE:
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return spiSingleRx();
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case ST_QUAD:
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case ST_QPI:
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return spiQuadRx();
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default:
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return 0xff;
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}
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}
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void spiCommand(uint8_t cmd) {
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if (spi.type == ST_QPI)
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spiQuadTx(cmd);
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else
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spiSingleTx(cmd);
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}
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uint8_t spiCommandRx(void) {
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if (spi.type == ST_QPI)
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return spiQuadRx();
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else
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return spiSingleRx();
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}
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uint8_t spiReadStatus(uint8_t sr) {
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uint8_t val = 0xff;
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(void)sr;
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switch (sr) {
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case 1:
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case 2:
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spiBegin();
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spiCommand(0x05);
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val = spiCommandRx();
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if (sr == 2)
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val = spiCommandRx();
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spiEnd();
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break;
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case 3:
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spiBegin();
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spiCommand(0x15);
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val = spiCommandRx();
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spiEnd();
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break;
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default:
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fprintf(stderr, "unrecognized status register: %d\n", sr);
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break;
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}
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return val;
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}
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void spiWriteSecurity(uint8_t sr, uint8_t security[256]) {
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if (spi.quirks & SQ_SECURITY_NYBBLE_SHIFT)
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sr <<= 4;
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spiBegin();
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spiCommand(0x06);
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spiEnd();
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// erase the register
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spiBegin();
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spiCommand(0x44);
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spiCommand(0x00); // A23-16
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spiCommand(sr); // A15-8
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spiCommand(0x00); // A0-7
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spiEnd();
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spi_get_id();
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sleep(1);
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// write enable
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spiBegin();
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spiCommand(0x06);
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spiEnd();
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spiBegin();
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spiCommand(0x42);
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spiCommand(0x00); // A23-16
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spiCommand(sr); // A15-8
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spiCommand(0x00); // A0-7
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int i;
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for (i = 0; i < 256; i++)
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spiCommand(security[i]);
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spiEnd();
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spi_get_id();
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}
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void spiReadSecurity(uint8_t sr, uint8_t security[256]) {
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if (spi.quirks & SQ_SECURITY_NYBBLE_SHIFT)
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sr <<= 4;
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spiBegin();
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spiCommand(0x48); // Read security registers
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spiCommand(0x00); // A23-16
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spiCommand(sr); // A15-8
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spiCommand(0x00); // A0-7
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int i;
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for (i = 0; i < 256; i++)
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security[i] = spiCommandRx();
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spiEnd();
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}
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void spiWriteStatus(uint8_t sr, uint8_t val) {
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switch (sr) {
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case 1:
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if (!(spi.quirks & SQ_SKIP_SR_WEL)) {
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spiBegin();
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spiCommand(0x06);
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spiEnd();
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}
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spiBegin();
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spiCommand(0x50);
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spiEnd();
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spiBegin();
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spiCommand(0x01);
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spiCommand(val);
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spiEnd();
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break;
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case 2: {
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uint8_t sr1 = 0x00;
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if (spi.quirks & SQ_SR2_FROM_SR1)
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sr1 = spiReadStatus(1);
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if (!(spi.quirks & SQ_SKIP_SR_WEL)) {
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spiBegin();
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spiCommand(0x06);
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spiEnd();
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}
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spiBegin();
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spiCommand(0x50);
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spiEnd();
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spiBegin();
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if (spi.quirks & SQ_SR2_FROM_SR1) {
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spiCommand(0x01);
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spiCommand(sr1);
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spiCommand(val);
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}
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else {
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spiCommand(0x31);
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spiCommand(val);
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}
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spiEnd();
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break;
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}
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case 3:
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if (!(spi.quirks & SQ_SKIP_SR_WEL)) {
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spiBegin();
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spiCommand(0x06);
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spiEnd();
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}
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spiBegin();
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spiCommand(0x50);
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spiEnd();
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spiBegin();
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spiCommand(0x11);
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spiCommand(val);
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spiEnd();
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break;
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default:
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fprintf(stderr, "unrecognized status register: %d\n", sr);
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break;
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}
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}
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struct spi_id spiId(void) {
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return spi.id;
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}
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#if 0
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static void spi_decode_id(void) {
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spi.id.bytes = -1; // unknown
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spi.id.manufacturer = "Unknown";
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spi.id.model = "Unknown";
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spi.id.capacity = "Unknown";
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if (spi.id.manufacturer_id == 0xef) {
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spi.id.manufacturer = "Winbond";
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if ((spi.id.memory_type == 0x70)
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&& (spi.id.memory_size == 0x18)) {
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spi.id.model = "W25Q128JV";
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spi.id.capacity = "128 Mbit";
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spi.id.bytes = 16 * 1024 * 1024;
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}
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}
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if (spi.id.manufacturer_id == 0x1f) {
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spi.id.manufacturer = "Adesto";
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if ((spi.id.memory_type == 0x86)
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&& (spi.id.memory_size == 0x01)) {
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spi.id.model = "AT25SF161";
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spi.id.capacity = "16 Mbit";
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spi.id.bytes = 1 * 1024 * 1024;
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}
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}
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return;
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}
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#endif
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static void spi_get_id(void) {
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spiBegin();
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spiCommand(0x90); // Read manufacturer ID
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spiCommand(0x00); // Dummy byte 1
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spiCommand(0x00); // Dummy byte 2
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spiCommand(0x00); // Dummy byte 3
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spi.id.manufacturer_id = spiCommandRx();
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spi.id.device_id = spiCommandRx();
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spiEnd();
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spiBegin();
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spiCommand(0x9f); // Read device id
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spi.id._manufacturer_id = spiCommandRx();
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spi.id.memory_type = spiCommandRx();
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spi.id.memory_size = spiCommandRx();
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spiEnd();
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spiBegin();
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spiCommand(0xab); // Read electronic signature
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spiCommand(0x00); // Dummy byte 1
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spiCommand(0x00); // Dummy byte 2
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spiCommand(0x00); // Dummy byte 3
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spi.id.signature = spiCommandRx();
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spiEnd();
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spiBegin();
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spiCommand(0x4b); // Read unique ID
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spiCommand(0x00); // Dummy byte 1
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spiCommand(0x00); // Dummy byte 2
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spiCommand(0x00); // Dummy byte 3
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spiCommand(0x00); // Dummy byte 4
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spi.id.serial[0] = spiCommandRx();
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spi.id.serial[1] = spiCommandRx();
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spi.id.serial[2] = spiCommandRx();
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spi.id.serial[3] = spiCommandRx();
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spiEnd();
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// spi_decode_id();
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return;
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}
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#if 0
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void spiOverrideSize(uint32_t size) {
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spi.size_override = size;
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// If size is 0, re-read the capacity
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if (!size)
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spi_decode_id();
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else
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spi.id.bytes = size;
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}
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#endif
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int spiSetType(enum spi_type type) {
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if (spi.type == type)
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return 0;
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switch (type) {
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case ST_SINGLE:
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if (spi.type == ST_QPI) {
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spiBegin();
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spiCommand(0xff); // Exit QPI Mode
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spiEnd();
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}
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spi.type = type;
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spi_set_state(SS_SINGLE);
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break;
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case ST_QUAD:
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if (spi.type == ST_QPI) {
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spiBegin();
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spiCommand(0xff); // Exit QPI Mode
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spiEnd();
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}
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// Enable QE bit
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spiWriteStatus(2, spiReadStatus(2) | (1 << 1));
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spi.type = type;
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spi_set_state(SS_QUAD_TX);
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break;
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case ST_QPI:
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// Enable QE bit
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spiWriteStatus(2, spiReadStatus(2) | (1 << 1));
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spiBegin();
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spiCommand(0x38); // Enter QPI Mode
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spiEnd();
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spi.type = type;
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spi_set_state(SS_QUAD_TX);
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break;
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default:
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return 1;
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}
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return 0;
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}
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int spiIsBusy(void) {
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return spiReadStatus(1) & (1 << 0);
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}
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void spi_wait_for_not_busy(void) {
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while (spiIsBusy())
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|
;
|
|
}
|
|
|
|
int spiBeginErase32(uint32_t erase_addr) {
|
|
// Enable Write-Enable Latch (WEL)
|
|
spiBegin();
|
|
spiCommand(0x06);
|
|
spiEnd();
|
|
|
|
spiBegin();
|
|
spiCommand(0x52);
|
|
spiCommand(erase_addr >> 16);
|
|
spiCommand(erase_addr >> 8);
|
|
spiCommand(erase_addr >> 0);
|
|
spiEnd();
|
|
return 0;
|
|
}
|
|
|
|
int spiBeginErase64(uint32_t erase_addr) {
|
|
// Enable Write-Enable Latch (WEL)
|
|
spiBegin();
|
|
spiCommand(0x06);
|
|
spiEnd();
|
|
|
|
spiBegin();
|
|
spiCommand(0xD8);
|
|
spiCommand(erase_addr >> 16);
|
|
spiCommand(erase_addr >> 8);
|
|
spiCommand(erase_addr >> 0);
|
|
spiEnd();
|
|
return 0;
|
|
}
|
|
|
|
int spiBeginWrite(uint32_t addr, const void *v_data, unsigned int count) {
|
|
const uint8_t write_cmd = 0x02;
|
|
const uint8_t *data = v_data;
|
|
unsigned int i;
|
|
|
|
// Enable Write-Enable Latch (WEL)
|
|
spiBegin();
|
|
spiCommand(0x06);
|
|
spiEnd();
|
|
|
|
// uint8_t sr1 = spiReadStatus(1);
|
|
// if (!(sr1 & (1 << 1)))
|
|
// fprintf(stderr, "error: write-enable latch (WEL) not set, write will probably fail\n");
|
|
|
|
spiBegin();
|
|
spiCommand(write_cmd);
|
|
spiCommand(addr >> 16);
|
|
spiCommand(addr >> 8);
|
|
spiCommand(addr >> 0);
|
|
for (i = 0; (i < count) && (i < 256); i++)
|
|
spiTx(*data++);
|
|
spiEnd();
|
|
|
|
return 0;
|
|
}
|
|
|
|
uint8_t spiReset(void) {
|
|
// XXX You should check the "Ready" bit before doing this!
|
|
|
|
spiSetType(ST_SINGLE);
|
|
|
|
spiBegin();
|
|
spiCommand(0x66); // "Enable Reset" command
|
|
spiEnd();
|
|
|
|
spiBegin();
|
|
spiCommand(0x99); // "Reset Device" command
|
|
spiEnd();
|
|
|
|
// msleep(30);
|
|
|
|
spiBegin();
|
|
spiCommand(0xab); // "Resume from Deep Power-Down" command
|
|
spiEnd();
|
|
|
|
return 0;
|
|
}
|
|
|
|
int spi_init(void) {
|
|
spi.state = SS_UNCONFIGURED;
|
|
spi.type = ST_UNCONFIGURED;
|
|
|
|
int i;
|
|
for (i = 0; i < 6; i++)
|
|
((uint32_t *)&spi.pins)[i] = i;
|
|
|
|
// Disable memory-mapped mode and enable bit-bang mode
|
|
picorvspi_cfg4_write(0);
|
|
|
|
// Reset the SPI flash, which will return it to SPI mode even
|
|
// if it's in QPI mode.
|
|
spiReset();
|
|
|
|
spiSetType(ST_SINGLE);
|
|
|
|
// Have the SPI flash pay attention to us
|
|
gpioWrite(spi.pins.hold, 1);
|
|
|
|
// Disable WP
|
|
gpioWrite(spi.pins.wp, 1);
|
|
|
|
gpioSetMode(spi.pins.clk, PI_OUTPUT); // CLK
|
|
gpioSetMode(spi.pins.cs, PI_OUTPUT); // CE0#
|
|
gpioSetMode(spi.pins.mosi, PI_OUTPUT); // MOSI
|
|
gpioSetMode(spi.pins.miso, PI_INPUT); // MISO
|
|
gpioSetMode(spi.pins.hold, PI_OUTPUT);
|
|
gpioSetMode(spi.pins.wp, PI_OUTPUT);
|
|
|
|
spi_get_id();
|
|
|
|
spi.quirks |= SQ_SR2_FROM_SR1;
|
|
if (spi.id.manufacturer_id == 0xef)
|
|
spi.quirks |= SQ_SKIP_SR_WEL | SQ_SECURITY_NYBBLE_SHIFT;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void spiEnableQuad(void) {
|
|
spiWriteStatus(2, spiReadStatus(2) | (1 << 1));
|
|
}
|
|
|
|
void spiSetPin(enum spi_pin pin, int val) {
|
|
switch (pin) {
|
|
case SP_MOSI: spi.pins.mosi = val; break;
|
|
case SP_MISO: spi.pins.miso = val; break;
|
|
case SP_HOLD: spi.pins.hold = val; break;
|
|
case SP_WP: spi.pins.wp = val; break;
|
|
case SP_CS: spi.pins.cs = val; break;
|
|
case SP_CLK: spi.pins.clk = val; break;
|
|
case SP_D0: spi.pins.d0 = val; break;
|
|
case SP_D1: spi.pins.d1 = val; break;
|
|
case SP_D2: spi.pins.d2 = val; break;
|
|
case SP_D3: spi.pins.d3 = val; break;
|
|
}
|
|
}
|
|
|
|
void spiHold(void) {
|
|
spiBegin();
|
|
spiCommand(0xb9);
|
|
spiEnd();
|
|
}
|
|
|
|
void spiUnhold(void) {
|
|
spiBegin();
|
|
spiCommand(0xab);
|
|
spiEnd();
|
|
}
|
|
|
|
int spiWrite(uint32_t addr, const uint8_t *data, unsigned int count) {
|
|
|
|
unsigned int i;
|
|
|
|
if (addr & 0xff) {
|
|
return 1;
|
|
}
|
|
|
|
// Erase all applicable blocks
|
|
uint32_t erase_addr;
|
|
for (erase_addr = 0; erase_addr < count; erase_addr += 32768) {
|
|
spiBegin();
|
|
spiCommand(0x06);
|
|
spiEnd();
|
|
|
|
spiBegin();
|
|
spiCommand(0x52);
|
|
spiCommand(erase_addr >> 16);
|
|
spiCommand(erase_addr >> 8);
|
|
spiCommand(erase_addr >> 0);
|
|
spiEnd();
|
|
|
|
spi_wait_for_not_busy();
|
|
}
|
|
|
|
uint8_t write_cmd;
|
|
switch (spi.type) {
|
|
case ST_SINGLE:
|
|
case ST_QPI:
|
|
write_cmd = 0x02;
|
|
break;
|
|
case ST_QUAD:
|
|
write_cmd = 0x32;
|
|
break;
|
|
default:
|
|
return 1;
|
|
}
|
|
|
|
while (count) {
|
|
spiBegin();
|
|
spiCommand(0x06);
|
|
spiEnd();
|
|
|
|
spiBegin();
|
|
spiCommand(write_cmd);
|
|
spiCommand(addr >> 16);
|
|
spiCommand(addr >> 8);
|
|
spiCommand(addr >> 0);
|
|
for (i = 0; (i < count) && (i < 256); i++)
|
|
spiTx(*data++);
|
|
spiEnd();
|
|
count -= i;
|
|
addr += i;
|
|
spi_wait_for_not_busy();
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int spiRead(uint32_t addr, uint8_t *data, unsigned int count) {
|
|
|
|
unsigned int i;
|
|
|
|
spiBegin();
|
|
switch (spi.type) {
|
|
case ST_SINGLE:
|
|
case ST_QPI:
|
|
spiCommand(0x0b);
|
|
break;
|
|
case ST_QUAD:
|
|
spiCommand(0x6b);
|
|
break;
|
|
default:
|
|
spiEnd();
|
|
return 1;
|
|
}
|
|
spiCommand(addr >> 16);
|
|
spiCommand(addr >> 8);
|
|
spiCommand(addr >> 0);
|
|
spiCommand(0x00);
|
|
for (i = 0; i < count; i++) {
|
|
data[i] = spiRx();
|
|
}
|
|
|
|
spiEnd();
|
|
return 0;
|
|
}
|
|
|
|
void spiFree(void) {
|
|
// Re-enable memory-mapped mode
|
|
picorvspi_cfg4_write(0x80);
|
|
}
|